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Figure 3 Register
Figure 4 asynchrounous reset vs synchronous
reset Register
LAB4:
1. Design 4 bit register using input name and
output name as following in Fig 4, create
the4 bit register Package and simulation.
2. Use Seg7_decorder Package in Lab 2
connect output of the 4 bit register
Package, shown in Fig 5
Figure 4. The 4 bit register
ENTITY tb_seg7_decoder_vhd IS
END tb_seg7_decoder_vhd;
COMPONENT seg7_decoder
Port ( clk :in std_logic;
rst :in std_logic;
in_en :in std_logic;
bin_in : in std_logic_vector(3 downto 0);
seg7_out : out std_logic_vector(7 downto 0));
END COMPONENT;
BEGIN
process
begin
rst <= '0';
wait for 234 ns;
rst <= '1';
wait for 123 ns;
rst <= '0';
wait;
end process;
process
begin
in_en <= '0';
wait for 10 ns;
in_en <= '1';
wait for 10 ns;
in_en <= '0';
wait for 50 ns;
in_en <= '1';
wait for 10 ns;
in_en <= '0';
wait for 50 ns;
end process;
tb : PROCESS
BEGIN
bin_in <= "0000";
wait for 500 ns;
bin_in <= "0001";
wait for 500 ns;
bin_in <= "0010";
wait for 500 ns;
bin_in <= "0011";
wait for 500 ns;
bin_in <= "0100";
wait for 500 ns;
bin_in <= "0101";
wait for 500 ns;
bin_in <= "0110";
wait for 500 ns;
bin_in <= "0111";
wait for 500 ns;
bin_in <= "1000";
wait for 500 ns;
bin_in <= "1001";
wait for 500 ns;
END PROCESS;
END;