Received 14 January 2019; revised 15 March 2019 and 12 April 2019; accepted 30 April 2019.

Date of publication 13 May 2019;

date of current version 23 August 2019. The review of this paper was arranged by Editor N. Sugii.
Digital Object Identifier 10.1109/JEDS.2019.2916460

Advanced FD-SOI and Beyond Low Temperature

SmartCutTM Enables High Density 3-D SoC
Applications
W. SCHWARZENBACH , B.-Y. NGUYEN, L. ECARNOT, S. LOUBRIAT, M. DETARD, E. CELA,
C. BERTRAND-GIULIANI, G. CHABANNE, C. MADDALON, N. DAVAL, AND C. MALEVILLE
Soitec, 38190 Bernin, France
CORRESPONDING AUTHOR: W. SCHWARZENBACH (e-mail: walter.schwarzenbach@soitec.com)
This work was supported by the Electronic Component Systems for European Leadership Joint Undertaking under Grant 692519 and Grant 662175.

ABSTRACT Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCutTM
development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX
materials developments are reported, including 4-nm SOI and 15-nm BOX layers, with performances close
to production-grade (SOI layer thickness variation at wafer and device scale, SOI layer defect density).
To support 3-D sequential integration, layer transfer at low temperature (below 500 ◦ C) with SmartCut is
demonstrated, on the path to a cost effective option. Best in class—equivalent to Epi bulk—SOI layers
thickness variability at device scale is demonstrated. Excellent SOI and BOX layers thickness uniformities
at wafer level are also highlighted while layer integrity from surface to crystalline defect density point
of view are already compliant with development grade requirements.

INDEX TERMS FD-SOI, SmartCut, 3D integration, low temperature, CMOS.

I. INTRODUCTION components, continuous footprint improvement as well as

In the post smartphone era, the Internet of Thing (IoT),
wearable electronics and automotive are big drivers for the
growth of the semiconductor market. To achieve complex,
miniaturized, ultra-low power and highly reliable circuits and
to maintain sufficient performance and cost-effective solu-
tions, planar Fully Depleted Silicon-On-Insulator (FD-SOI)
on ultra-thin Buried Oxide (BOX) demonstrates benefits
and capabilities through 28FD and 22FD technologies [1].
Recently Renesas’ FD-SOI validation of SOTBTM Energy
Harvesting Chipset (ultra-thin BOX, down to 15nm) con-
firmed extreme low power performance, including both low
active current of 20 µA/MHz and deep standby current of
150 nA [2].
In support of Moore’s Law evolution beyond such
already available 2D technologies, researchers are develop-
ing advanced Silicon-On-Insulator (SOI) processes to pursue
a digital roadmap from planar devices to 3D integration.
3D integration will help to address several challenges: inte-
gration of multiple types of devices including specialized
optimization of performance and cost [3].
Packaging and sequential integrations both represent
options to consider for 3D. Sequential integration is very
attractive to increase circuit functionality with high device
density per chip without requiring further reduction of the
single device dimensions. However, one of the most critical
challenges of 3D sequential integration is the management of
the process thermal budget [4]. The top tier device thermal
budget needs to be reduced to avoid degradation of the bot-
tom devices, the interconnects and the bonding interface [5].
In parallel, most of the reported researches propose the trans-
fer of a silicon layer to support the top tier device preparation
thanks to an SOI wafer bonding and grinding process. It
benefits from the SOI layer thin film uniformity and crystal
quality to drive the transferred silicon layer quality but with
a cost impact related to the full SOI wafer consumption. In
order to take advantage of the SmartCut process to transfer
at reduced cost a high quality, highly uniform crystalline
layers, as demonstrated on bulk as on device wafer [4], we

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 SCHWARZENBACH et al.: ADVANCED FD-SOI AND BEYOND LOW TEMPERATURE SMARTCUTTM
FIGURE 1. Soitec Digital SOI Substrate Product Portfolio.
propose the use of a new Low Temperature SmartCut process
as an alternative option for 3D integration.
II. FROM CONVENTIONAL FD-SOI TO ADVANCED SOI AND
3D INTEGRATION
Figure 1 shows how the Soitec Digital SOI product and wafer
specification portfolio enables CMOS technology scaling.
From 65FD down to 12FD technologies, this portfolio is
based on unstrained ultra-thin SOI and BOX layers with
adapted crystal orientations. BOX layer thickness varies
between 15 and 25 nm. Precise silicon thickness con-
trol requires a SOI layer thickness variation as low as
+/−5 Angstrom, already demonstrated in high volume pro-
duction mode. For advanced technologies nodes beyond
12FD, extremely thin BOX and/or SOI layers, always main-
taining a tight control of the SOI and BOX thickness
variations, are proposed in development phase. Surface
defectivity inspection threshold will need to be adjusted
according to the SOI and BOX layer thicknesses, due to
stack reflectivity sensitivity on ultra-thin layers [6]. Ultra flat
wafer characteristics help to support advanced lithography
requirements. Such advanced SOI not only applies to BOX
layer thickness down to 15nm but also to extremely thin
SOI layers in the 5 nm range. Although similar results have
recently been published [7], [8], this paper presents new
results validating substrate performances and compatibility
delivering integration-grade requirements.
Low temperature layer transfer supports 3D sequen-
tial integration. As an input, after some work consid-
ering a 600◦ C thermal limitation [9], a device prepared
with a maximum processing temperature of 525◦ C already
demonstrated performances in line with state-of-the-art,
conventional high temperature, silicon technology [5], [10].
Other works highlight a mandatory 500◦ C thermal
budget limitation for 3D Sequential Top MOSFET
fabrication [4], [11]. Therefore, we investigated the use of
low temperature layer transfer, compliant with such above
500◦ C max requirement, to deliver extremely thin, uni-
form and smooth SOI layers. This paper reports on our
findings from such transfer demonstrations on bare handle
materials.
864
FIGURE 2. SmartCut Process Flow for FD-SOI Substrate Preparation.
III. SMARTCUT ENABLES ULTRA THIN LAYERS AND 3D
INTEGRATION
The SmartCut process adapted to FD-SOI substrate prepa-
ration, as schematically shown on Figure 2, has already
been published [12]. This process is based on wafer bonding
of an implanted defect free donor substrate on a han-
dle wafer, and requires extensive optimization including
implant and thermal treatment process steps to transfer
highly uniform, extremely thin SOI layers on ultra thin
BOX. Such dedicated FD-SOI process flow considers a high
temperature smoothing option for wafer finishing, deliver-
ing ultra-thin SOI and BOX layers with ultra-low roughness
according to Mullins-Herring surface diffusion model [13].
Such surface roughness is associated to an optimal FD-SOI
thickness variability at device scale. Dedicated Differential
Reflectivity Measurement (DRM) metrology has also been
developed [14] in order to measure this SOI thickness vari-
ation at the device scale. For ultra-thin SOI and BOX layers
reported in this paper, DRM measurement wavelength has
been determined versus SOI and BOX layers reflectivity
to be more suitable than conventional surface roughness
to evaluate channel thickness (thus electrical transistor)
variability.
For 3D integration, SmartCut process is adapted (Fig. 3) in
order to transfer at low temperature ultra-thin layers compati-
ble with fully depleted requirements, in particular with excel-
lent device scale variability. This process option includes the
use of engineered, epi processed donor wafers. The epitaxy
process on conventional bulk material allows creation of
a first Silicon-Germanium layer, to be used as an etch stop
layer after SmartCut splitting. Then a subsequent Si layer,
defined accordingly to SOI film thickness target, is epitax-
ied. Implant, surface preparation, bonding (on bulk handle
material) and splitting process steps, all being compliant with
low temperature requirement, benefit from conventional FD-
SOI experience. Finishing process includes selective etching
to recover SOI layer, with an epitaxy driven final thickness
uniformity and roughness [15].
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SCHWARZENBACH et al.: ADVANCED FD-SOI AND BEYOND LOW TEMPERATURE SMARTCUTTM

FIGURE 5. TEM cross section, FD-SOI wafer with 4nm SOI layer.
FIGURE 3. SmartCut Process Flow Adapted for 3D Integration.

FIGURE 4. TEM cross section, FD-SOI wafers with 25nm (left) and
15nm (right) BOX layers.

IV. ULTRA-THIN SOI AND BOX FOR ADVANCED SOI

Thanks to process step optimization through FD-SOI process
flow, including oxide growth, cleaning, etc before splitting
and high thermal treatment during SOI finishing [16], BOX
evolution can be managed in order to deliver a wide range
of final thicknesses down to 15 nm (Transmission Electron
Microscopy [TEM] cross section on Figure 4) or less [7].
By combining process steps optimizations including implant,
splitting, smoothing and thinning, it is possible to prepare an
SOI layer with a thickness as low as 4nm. Figure 5 shows
a typical TEM cross section of such a layer with less than
10 SOI atomic crystalline lattices between native and buried FIGURE 6. (a): SOI Thickness Within Wafer Range, 22FD-SOI vs 4nm
oxide layers [8]. SOI (A). (b): 625 pts ellipsometry thickness mapping on a 4nm SOI
substrate.
Beyond layer thickness at the wafer level, SOI variation
within wafer and at device scale are known to be critical
versus transistor Vt variability [17]. Therefore, from an SOI
layer variability perspective, figures 6 and 7 confirm that Figure 6b shows ellipsometry high density thickness map-
a 4 nm thick SOI layer performs similarly to production- ping of 4nm thick SOI layer and confirms excellent product
grade 12nm thick 28FD-SOI and 22FD-SOI. Regarding uniformity on the whole 300mm wafer surface.
within wafer (WiW) SOI thickness variation, figure 6a con- DRM measurement allows for device scale thickness
firms that WiW SOI layer Range is similar on a 4nm variation consideration through 6 sigma performance.
thick sample than on a 12nm thick 22FD-SOI sample. Less Figure 7 (a) compares and validates that the same mea-
than a 1 nm WiW SOI thickness variation is measured by sure of local SOI layer thickness variability results for both
ellipsometry. a 4nm thick SOI sample and for a 22FD-SOI production

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 SCHWARZENBACH et al.: ADVANCED FD-SOI AND BEYOND LOW TEMPERATURE SMARTCUTTM

FIGURE 7. 4nm SOI DRM measurement (a) Sigma performance compared

with 22FD-SOI production (b) typical DRM 266 × 266 µm2 scan image.

sample. Figure 7(b) shows a typical DRM scan image of

a 4nm thick SOI sample.
Beyond SOI layer thickness variability, even device
yield during the development phase requires consideration
of SOI layer integrity, and therefore surface defectivity.
Figure 8 shows (a) a typical KLA Tencor SP5 @ 50nm
threshold mapping of a 4nm thick SOI layer, (b) a typ-
ical KLA Tencor SP5 @ 60nm threshold mapping (such
inspection limit being driven by SOI and BOX stack physi-
cal reflectivity) of a 3nm thick SOI layer, and (c) a typical
KLA Tencor SP2 mapping of a 4nm SOI layer after a 30min
HF decoration protocol. With the exhibited defect den-
sity below 0.05/cm2 , these results confirm how an adapted
SmartCut process delivers high integrity of ultra-thin SOI
layers.
V. LOW TEMPERATURE FD-SOI FOR 3D INTEGRATION
Thanks to engineered donor preparation, bonding and selec-
tive etch finishing, ultra-thin SOI (12nm) and BOX (20nm)
layers are prepared without need for high temperature
smoothing or sacrificial oxidation processes. As such, the
post bonding process can be restricted to typical 500◦ C.
In addition to the benefits of low temperature process-
ing for a 3D integration scheme, we demonstrate that SOI
layer thickness variability, over the full spatial wavelength
spectrum from device to wafer scale, is driven by the donor
FIGURE 8. (a) 4nm thick SOI SP5 surface defect mapping @ 50nm, (b) 3nm
thick SOI SP5 surface defect mapping @ 60nm, (c) 4nm thick SOI + HF
decoration surface defect mapping.
epitaxy performance and conforms to Fully Depleted chan-
nel device variability requirements. Figure 9 shows Atomic
Force Microscopy (AFM) roughness performance, through
30 × 30 µm2 scan (a) and Power Spectral Density (b). RMS
of 1.0 and 0.9 Å are measured on high temperature and low
temperature process options respectively.
DRM measurements on 12 nm SOI/20 nm BOX sam-
ples with both finishing options, performed to evaluate the
device scale SOI layer thickness variation, confirm excel-
lent performance of the low temperature process option
(6 sigma << 5Å).
Following a similar evaluation and development path to
one used for advanced FD-SOI, low temperature SmartCut is
also evaluated through SOI and BOX layer thickness unifor-
mities. Figure 11 shows (a) BOX and (b) SOI layers 41 points

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SCHWARZENBACH et al.: ADVANCED FD-SOI AND BEYOND LOW TEMPERATURE SMARTCUTTM
FIGURE 9. AFM meas., (a) 30 × 30 µm2 scan, (b) PSD graph, 12nm
SOI/20nm BOX, with Low or High Temperature finishing.
FIGURE 10. DRM 266 × 266 µm2 scans, 12nm SOI/20nm BOX, with Low
Temperature (left) or High Temperature (right) finishing.
ellipsometry thickness mapping, on a 12 nm SOI/20nm BOX
sample. Thanks to this low temperature process, avoiding
any high temperature influence on BOX layer, as described
in [16], BOX layer variability is primarily driven by thermal
oxide growth, thus demonstrating a within wafer uniformity
<< 10 A. Additionally, SOI layer thickness variability is
mainly driven by Epi performance on the engineered donor
wafer, thanks to this low temperature process.
Figure 12 shows typical KLA Tencor SP3 @ 65nm
threshold defect mapping, as measured on 12/20 low tem-
perature sample at the R&D stage. Defect density on this
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FIGURE 11. 41 ellipsometry thickness mapping (a) 20nm thick BOX,
(b) 12nm thick SOI normalized vs Epi profile, 12/20 Low Temperature
sample.
FIGURE 12. KLA Tencor SP3 @ 65nm threshold surface defect mapping,
12/20nm SOI with Low Temperature process.
early development product already demonstrates less than
0.1 defect/cm2 performance.
VI. CONCLUSION
On the path to advanced FD-SOI materials, ultra-thin SOI
(down to 4nm) and BOX (down to 15nm) layers are
delivered with close-to-production performances thanks to
optimized SmartCut FD-SOI process. To support 3D sequen-
tial integration, layer transfer at low temperature (< 500◦ C)
is demonstrated thanks to an adapted SmartCut process.
Next research step will confirm this capability with low
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 SCHWARZENBACH et al.: ADVANCED FD-SOI AND BEYOND LOW TEMPERATURE SMARTCUTTM
temperature layer transfer on patterned substrate for 3DS
device assessment.
ACKNOWLEDGMENT
This Joint Undertaking receives supports from the European
Union’s Horizon 2020 research and innovation programs and
from Belgium, Germany, France, The Netherlands, Poland
and United Kingdom.
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