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bq25895
SLUSC88B – MARCH 2015 – REVISED MAY 2018
bq25895 I2C Controlled Single Cell 5-A Fast Charger with MaxChargeTM for High Input
Voltage and Adjustable Voltage 3.1-A Boost Operation
1 Features Ship Mode
1• High Efficiency 5-A, 1.5-MHz Switch Mode Buck • High Accuracy
Charge – ±0.5% Charge Voltage Regulation
– 93% Charge Efficiency at 2 A and 91% Charge – ±5% Charge Current Regulation
Efficiency at 3 A Charge Current – ±7.5% Input Current Regulation
– Optimize for High Voltage Input (9 V to 12 V) • Safety
– Low Power PFM mode for Light Load – Battery Temperature Sensing for Charge and
Operations Boost Mode
• Boost Mode Operation with Adjustable Output – Thermal Regulation and Thermal Shutdown
from 4.5 V to 5.5 V
– Create a Custom Design Using the bq25895
– Selectable 500-KHz to 1.5-MHz Boost With the WEBENCH® Power Designer
Converter with up to 3.1-A Output
– 93% Boost Efficiency at 5 V at 1 A Output 2 Applications
• Integrated Control to Switch Between Charge and • Power Bank, Mobile Wi-Fi Hotspot
Boost Mode • Wireless Bluetooth Speaker
• Single Input to Support USB Input and Adjustable • Portable Internet Devices
High Voltage Adapters
– Support 3.9-V to 14-V Input Voltage Range 3 Description
– Input Current Limit (100 mA to 3.25 A with 50- The bq25895 is a highly-integrated 5-A switch-mode
mA resolution) to Support USB2.0, USB3.0 battery charge management and system power path
standard and High Voltage Adapters management device for single cell Li-Ion and Li-
– Maximum Power Tracking by Input Voltage polymer battery. The devices support high input
voltage fast charging. The low impedance power path
Limit up-to 14V for Wide Range of Adapters
optimizes switch-mode operation efficiency, reduces
– Auto Detect USB SDP, CDP, DCP, and Non- battery charging time and extends battery life during
standard Adapters discharging phase.
• Input Current Optimizer (ICO) to Maximize Input
Power without Overloading Adapters Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Resistance Compensation (IRCOMP) from
Charger Output to Cell Terminal bq25895 WQFN (24) 4.00mm x 4.00mm
• Highest Battery Discharge Efficiency with 11-mΩ (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Battery Discharge MOSFET up to 9 A
• Integrated ADC for System Monitor Simplified Schematic
(Voltage, Temperature, Charge Current) OTG
• Narrow VDC (NVDC) Power Path Management 5V at 3.1A
PMID Phone
– Instant-on Works with No Battery or Deeply Input
Discharged Battery 3.9V±14V at 3A SYS 3.5V±4.5V
USB VBUS SW
– Ideal Diode Operation in Battery Supplement
Mode SYS
Ichg = 5A
• BATFET Control to Support Ship Mode, Wake Up, BAT
and Full System Reset I2C Bus
QON
• Flexible Autonomous and I2C Mode for Optimal Host bq25895 REGN Optional
System Performance
• High Integration includes all MOSFETs, Current Host Control
TS
Sensing and Loop Compensation
• 12-µA Low Battery Leakage Current to Support
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq25895
SLUSC88B – MARCH 2015 – REVISED MAY 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Register Maps ......................................................... 32
2 Applications ........................................................... 1 9 Application and Implementation ........................ 49
3 Description ............................................................. 1 9.1 Application Information............................................ 49
4 Revision History..................................................... 3 9.2 Typical Application .................................................. 49
9.3 System Examples ................................................... 54
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 55
7 Specifications......................................................... 6 11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
7.1 Absolute Maximum Ratings ...................................... 6
11.2 Layout Example .................................................... 55
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6 12 Device and Documentation Support ................. 56
7.4 Thermal Information .................................................. 7 12.1 Development Support ........................................... 56
7.5 Electrical Characteristics........................................... 7 12.2 Receiving Notification of Documentation Updates 56
7.6 Timing Requirements .............................................. 11 12.3 Community Resources.......................................... 56
7.7 Typical Characteristics ............................................ 12 12.4 Trademarks ........................................................... 56
12.5 Electrostatic Discharge Caution ............................ 56
8 Detailed Description ............................................ 14
12.6 Glossary ................................................................ 56
8.1 Functional Block Diagram ....................................... 14
8.2 Feature Description................................................. 15 13 Mechanical, Packaging, and Orderable
8.3 Device Functional Modes........................................ 30
Information ........................................................... 56
2 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: bq25895

bq25895
www.ti.com SLUSC88B – MARCH 2015 – REVISED MAY 2018
4 Revision History
Changes from Revision A (May 216) to Revision B Page
• Added "SW (peak for 10 ns duration)" To the Absolute Maximum Rating ............................................................................ 6
• Updated the Thermal Information values ............................................................................................................................... 7
• Changed VSYS TYP value From: VBAT + 50 mV To: I(SYS) + 150 mV ...................................................................................... 7
• Changed the title of Figure 4 From: Charge Current Accuracy To: I2C Setting .................................................................. 12
• Changed axis title of Figure 8 From: BAT Voltage (V) To: Input Current Limit (mA) ........................................................... 12
• Changed VVREF to VREGN in Figure 15................................................................................................................................... 23
• Changed VVREF to VREGN in Equation 2................................................................................................................................. 23
• Changed VREF to VREGN in Figure 16 .................................................................................................................................... 24
• Added sentence to the Battery Monitor secton "In battery only mode, .."............................................................................ 24
• Changed bit 5 From: 0 To: 1 in Figure 29 ............................................................................................................................ 35
• Changed the Description values of Table 26 From: mV To: mA.......................................................................................... 47
• Changed the Type values of Bits 6 to Bit 0 in Table 28 From: R/W To: R .......................................................................... 48
• Added VREF system pullup voltage to Table 29 .................................................................................................................... 49
• Changed Figure 49............................................................................................................................................................... 52
Changes from Original (March 2015) to Revision A Page
• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1
5 Description (continued)
The I2C Serial interface with charging and system settings makes the device a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant adjustable high voltage adapter. To support fast charging using adjustable high voltage adapter,
the bq25895 provides support MaxChargeTM using D+/D– pins and DSEL pin for USB switch control. In addition,
the device includes interface to support adjustable high voltage adapter using input current pulse protocol. To set
the default input current limit, device uses the built-in USB interface. The device is compliant with USB 2.0 and
USB 3.0 power spec with input current and voltage regulation. In addition, the Input Current Optimizer (ICO)
supports the detection of maximum power point detection of the input source without overload. The device
supports battery boost operation by supplying adjustable 4.5 V to 5.5 V on PMID pin with up to 3.1 A with
integrated charge and boost mode detection
Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 3

bq25895
6 Pin Configuration and Functions
bq25895
RTW (WQFN)
Top View
REGN
DSEL
BTST
PMID
SW
SW
24 23 22 21 20 19
VBUS 1 18 PGND
D+ 2 17 PGND
D– 3 16 SYS
STAT 4 15 SYS
SCL 5 14 BAT
SDA 6 13 BAT
7 8 9 10 11 12
ILIM
TS
INT
OTG
CE
QON
Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME NO.
Charger Input Voltage.
VBUS 1 P The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on
source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
Positive line of the USB data line pair.
D+ 2 AIO D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter (MaxCharge).
Negative line of the USB data line pair.
D– 3 AIO D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter (MaxCharge).
Open drain charge status output to indicate various charger operation.
Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge
STAT 4 DO
complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz.
The STAT pin function can be disabled when STAT_DIS bit is set.
I2C Interface clock.
SCL 5 DI
Connect SCL to the logic rail through a 10-kΩ resistor.
I2C Interface data.
SDA DIO
Connect SDA to the logic rail through a 10-kΩ resistor.
Open-drain Interrupt Output.
INT 7 DO Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report
charger device status and fault.
Boost mode enable pin.
OTG 8 DI The boost mode is activated when OTG_CONFIG =1, OTG pin is high, and no input source is detected at
VBUS
Active low Charge Enable pin.
CE 9 DI
Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)

bq25895
Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NAME NO.
Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected
from ILIM pin to ground to set the maximum limit as IINMAX = KILIM/RILIM . The actual input current limit is the
lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500
ILIM 10 AI
mA is not support on ILIM pin.
ILIM pin can also be used to monitor input current when the voltage is below 0.8V. The input current is
proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8)
The ILIM pin function can be disabled when EN_ILIM bit is 0.
Temperature qualification voltage input.
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider
TS 11 AI
from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2
thermistor.
BATFET enable/reset control input.
When BATFET is in ship mode, a logic low of tSHIPMODE (typical 1sec) duration turns on BATFET to exit
shipping mode. .
QON 12 DI When VBUS is not plugged-in, a logic low of tQON_RST (typical 10sec) duration resets SYS (system power) by
turning BATFET off for tBATFET_RST (typical 0.3sec) and then re-enable BATFET to provide full system power
reset.
The pin contains an internal pull-up to maintain default high logic
Battery connection point to the positive terminal of the battery pack.
BAT 13,14 P
The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin.
System connection point.
The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system
SYS 15,16 P
voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20uF closely to the
SYS pin.
Power ground connection for high-current power converter node.
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to
PGND 17,18 P
ground connection of input and output capacitors of the charger. A single point connection is recommended
between power PGND and the analog GND near the IC PGND pin.
Switching node connecting to output inductor.
SW 19,20 P Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET.
Connect the 0.047µF bootstrap capacitor from SW to BTST.
PWM high side driver positive supply.
BTST 21 P Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047µF bootstrap
capacitor from SW to BTST.
PWM low side driver positive supply output.
Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7µF (10 V rating) ceramic
REGN 22 P
capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as
bias rail of TS pin.
Battery boost mode output.
PMID 23 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. The minimum
capacitance required on PMID to PGND is 40µF for up-to 2.4A output and 60µF for up-to 3.1A output
Open-drain D+/D- multiplexer selection control.
Connect the DSEL to a logic rail via 10-KΩ resistor. The pin is normally float and pull-up by external resistor.
DSEL 24 DO During Input Source Type Detection , the pin drives low to indicate the device D+/D- detection is in progress
and needs to take control of D+, D- signals. When detection is completed, the pin keeps low when MaxCharge
is detected. The pin returns to float and pulls high by external resistor when other input source type is detected.
Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on
PowerPAD™ P
the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.

bq25895
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX VALUE
VBUS (converter not switching) –2 22 V
PMID (converter not switching) –0.3 22 V
STAT –0.3 20 V
DSEL –0.3 20 V
BTST –0.3 20 V
SW –2 16 V
Voltage range (with respect to GND) SW (peak for 10 ns duration) –3 16 V
BAT, SYS (converter not switching) –0.3 6 V
SDA, SCL, INT, OTG, REGN, TS, CE, QON –0.3 7 V
D+, D– –0.3 7 V
BTST TO SW –0.3 7 V
PGND to GND –0.3 0.3 V
ILIM –0.3 5 V
INT, STAT 6 mA
Output sink current
DSEL 6 mA
Junction temperature –40 150 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000 V
VESD Electrostatic discharge Charged device model (CDM), per JEDEC specification
±250 V
JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 3.9 14 (1) V
IIN Input current (VBUS) 3.25 A
ISYS Output current (SW) 5 A
VBAT Battery voltage 4.608 V
Fast charging current 5 A
Up to 6 (continuos) A
IBAT
Discharging current with internal MOSFET 9 (peak)
A
(Up to 1 sec duration)
TA Operating free-air temperature range –40 85 °C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.

bq25895
7.4 Thermal Information

bq25895
THERMAL METRIC (1) RTW (WQFN) UNIT
24-PINS
RθJA Junction-to-ambient thermal resistance 31.8 °C/W
RθJC((op) Junction-to-case (top) thermal resistance 27.9 °C/W
RθJB Junction-to-board thermal resistance 8.7 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
VBAT = 4.2 V, V(VBUS) < V(UVLO), leakage
5 µA
between BAT and VBUS
High-Z mode, no VBUS, BATFET disabled
(REG09[5]=1), battery monitor disabled, TJ < 12 23 µA
IBAT Battery discharge current (BAT, SW, SYS) in buck mode
85°C
High-Z mode, no VBUS, BATFET enabled
(REG09[5]=0), battery monitor disabled, TJ < 32 60 µA
85°C
V(VBUS)= 5 V, High-Z mode, no battery, battery
15 35 µA
Input supply current (VBUS) in buck mode when High-Z mode monitor disabled
I(VBUS_HIZ)
is enabled V(VBUS)= 12 V, High-Z mode, no battery,
25 50 µA
battery monitor disabled
VBUS > V(UVLO), VBUS > VBAT, converter not
1.5 3 mA
switching
VBUS > V(UVLO), VBUS > VBAT, converter
I(VBUS) Input supply current (VBUS) in buck mode 3 mA
switching, VBAT = 3.2 V, ISYS = 0A
VBUS > V(UVLO), VBUS > VBAT, converter
3 mA
switching, VBAT = 3.8 V, ISYS = 0 A
VBAT = 4.2 V, boost mode, I(VBUS)= 0 A,
I(BOOST) Battery discharge current in boost mode 5 mA
converter switching
VBUS/BAT POWER UP
V(VBUS_OP) VBUS operating range 3.9 14 V
V(VBUS_UVLOZ) VBUS for active I2C, no battery 3.6 V
V(SLEEP) Sleep mode falling threshold 25 65 120 mV

V(SLEEPZ) Sleep mode rising threshold 130 250 370 mV
VBUS over-voltage rising threshold 14 14.6 V
V(ACOV)
VBUS over-voltage falling threshold 13.5 14 V
VBAT(UVLOZ) Battery for active I2C, no VBUS 2.3 V
VBAT(DPL) Battery depletion falling threshold 2.15 2.5 V
VBAT(DPLZ) Battery depletion rising threshold 2.35 2.7 V
V(VBUSMIN) Bad adapter detection threshold 3.8 V
I(BADSRC) Bad adapter detection current source 30 mA
POWER-PATH MANAGEMENT
I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled VBAT+
V
(REG09[5]=1) 50 mV
VSYS Typical system regulation voltage
I(SYS) = 0 A, VBAT< VSYS(MIN), BATFET Disabled VSYS(MIN) +
V
(REG09[5]=1) 150 mV
VBAT< VSYS(MIN), SYS_MIN = 3.5 V
VSYS(MIN) Minimum DC system voltage output 3.50 3.65 V
(REG03[3:1]=101), ISYS= 0 A
VBAT = 4.35 V, SYS_MIN = 3.5V
VSYS(MAX) Maximum DC system voltage output 4.40 4.42 V
(REG03[3:1]=101), ISYS= 0 A
Top reverse blocking MOSFET(RBFET) on-resistance TJ = –40°C to +85°C 27 38 mΩ

RON(RBFET)
between VBUS and PMID TJ = –40°C to +125°C 27 44 mΩ

bq25895
Electrical Characteristics (continued)

otherwise noted)
Top switching MOSFET (HSFET) on-resistance between PMID TJ = –40°C to +85°C 27 39 mΩ

RON(HSFET)
and SW TJ = –40°C to +125°C 27 47 mΩ
Bottom switching MOSFET (LSFET) on-resistance between TJ = –40°C to +85°C 16 24 mΩ

RON(LSFET)
SW and GND TJ = –40°C to +125°C 16 28 mΩ
V(FWD) BATFET forward voltage in supplement mode BAT discharge current 10 mA 30 mV
VBAT(GD) Battery good comparator rising threshold VBAT rising 3.4 3.55 3.7 V
VBAT(GD_HYST) Battery good comparator falling threshold VBAT falling 100 mV
BATTERY CHARGER
VBAT(REG_RANGE) Typical charge voltage range 3.840 4.608 V
VBAT(REG_STEP) Typical charge voltage step 16 mV
VBAT = 4.208 V (REG06[7:2]=010111) or
VBAT(REG) Charge voltage resolution accuracy VBAT = 4.352 V (REG06[7:2]=100000) -0.5% 0.5%
TJ = –40°C to +85°C
I(CHG_REG__RANGE) Typical fast charge current regulation range 0 5056 mA
I(CHG_REG_STEP) Typical fast charge current regulation step 64 mA
VBAT = 3.1 V or 3.8 V, ICHG = 128 mA
-20% 20%
TJ = –40°C to +85°C
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
I(CHG_REG_ACC) Fast charge current regulation accuracy -10% 10%
TJ = –40°C to +85°C
VBAT= 3.1 V or 3.8 V, ICHG=1792 mA
-5% 5%
TJ = –40°C to +85°C
Battery LOWV falling threshold Fast charge to precharge, BATLOWV
2.6 2.8 2.9 V
(REG06[1]) = 1
VBAT(LOWV) Battery LOWV rising threshold Precharge to fast charge, BATLOWV
(REG06[1])=1 2.8 3 3.1 V
(Typical 200-mV hysteresis)
I(PRECHG_RANGE) Precharge current range 64 1024 mA
I(PRECHG_STEP) Typical precharge current step 64 mA
I(PRECHG_ACC) Precharge current accuracy VBAT=2.6 V, IPRECHG = 256 mA –10% +10%
I(TERM_RANGE) Termination current range 64 1024 mA
I(TERM_STEP) Typical termination current step 64 mA
ITERM = 256 mA, ICHG<= 1344 mA
–12% 12%
TJ = –20°C to +85°C
I(TERM_ACC) Termination current accuracy
ITERM = 256 mA, ICHG> 1344 mA
–20% 20%
TJ = –20°C to +85°C
V(SHORT) Battery short voltage VBAT falling 2 V
V(SHORT_HYST) Battery short voltage hysteresis VBAT rising 200 mV
I(SHORT) Battery short current VBAT < 2.2 V 100 mA
VBAT falling, VRECHG (REG06[0]=0) = 0 100 mV
V(RECHG) Recharge threshold below VBATREG
VBAT falling, VRECHG (REG06[0]=0) = 1 200 mV
IBAT(LOAD) Battery discharge load current VBAT = 4.2 V 15 mA
ISYS(LOAD) System discharge load current VSYS = 4.2 V 30 mA
TJ = 25°C 11 13 mΩ
RON(BATFET) SYS-BAT MOSFET (BATFET) on-resistance
TJ = –40°C to +125°C 11 19 mΩ
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE) Typical Input voltage regulation range 3.9 15.3 V
VIN(DPM_STEP) Typical Input voltage regulation step 100 mV
VIN(DPM_ACC) Input voltage regulation accuracy VINDPM = 4.4 V, 9 V 3% 3%
IIN(DPM_RANGE) Typical Input current regulation range 100 3250 mA
IIN(DPM_STEP) Typical Input current regulation step 50 mA
IIN(DPM100_ACC) Input current 100-mA regulation accuracy IINLIM (REG00[5:0]) =100 mA
85 90 100 mA
VBAT = 5 V, current pulled from SW
USB150, IINLIM (REG00[5:0]) = 150 mA 125 135 150 mA
USB500, IINLIM (REG00[5:0]) = 500 mA 440 470 500 mA
Input current regulation accuracy
IIN(DPM_ACC) USB900, IINLIM (REG00[5:0]) = 900 mA 750 825 900 mA
VBAT = 5 V, current pulled from SW
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500
1300 1400 1500 mA
mA
IIN(START) Input current regulation during system start up VSYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA 200 mA

bq25895

otherwise noted)
KILIM IINMAX = KILIM/RILIM Input current regulation by ILIM pin = 1.5 A 320 355 390 AxΩ
D+/D- DETECTION
V(0P6_VSRC) D+/D– voltage source (0.6 V) 0.5 0.6 0.7 V
V(3p45_VSRC) D+/D– voltage source (3.45 V) 3.3 3.45 3.6 V
I(10UA_ISRC) D+ connection check current source 7 10 14 µA
I(100UA_ISINK) D+/D– current sink (100 µA) 50 100 150 µA
I(DPDM_LKG) D+/D– Leakage current D–, switch open –1 1 µA
D+, switch open –1 1 µA
I(1P6MA_ISINK) D+/D– current sink (1.6 mA) 1.45 1.60 1.75 µA
V(0P4_VTH) D+/D– low comparator threshold 250 400 mV
V(0P8_VTH) D+ low comparator threshold 0.8 V
V(2P7_VTH) D+/D– comparator threshold for non-standard adapter 2.55 2.85 V
detection (divider 1, 3, or 4)
detection (divider 1, 3)
detection (divider 2)
R(D–_DWN) D– pulldown for connection check 14.25 24.8 kΩ
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP) Battery over-voltage threshold VBAT rising, as percentage of VBAT(REG) 104%
VBAT(OVP_HYST) Battery over-voltage hysteresis VBAT falling, as percentage of VBAT(REG) 2%
IBAT(FET_OCP) System over-current threshold 9 A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy REG08[1:0] = 11 120 °C
TSHUT Thermal shutdown rising temperature Temperature rising 160 °C
TSHUT(HYS) Thermal shutdown hysteresis Temperature falling 30 °C
V(LTF) Cold temperature threshold, TS pin voltage rising threshold As percentage to V(REGN) 72.75% 73.25% 73.75%
V(LTF_HYS) Cold temperature hysteresis, TS pin voltage falling As percentage to V(REGN) 0.4%
V(HTF) Hot temperature TS pin voltage rising threshold As percentage to V(REGN) 47.75% 48.25% 48.75%
V(TCO) Cut-off temperature TS pin voltage falling threshold As percentage to V(REGN) 44.25% 44.75% 45.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
As percentage to VREGN REG01[5] = 1
V(BCOLD1) Cold temperature threshold 1, TS pin voltage rising threshold 79.5% 80% 80.5%
(Approximately –20°C w/ 103AT)
V(BCOLD1_HYS) Cold temperature threshold 1, TS pin voltage falling threshold As percentage to VREGN REG01[5] = 1 1%
As percentage to VREGN REG01[7:6] = 10
V(BHOT2) Hot temperature threshold 2, TS pin voltage falling threshold 30.75% 31.25% 31.75%
(Approx. 65°C w/ 103AT)
V(BHOT2_HYS) Hot temperature threshold 2, TS pin voltage rising threshold As percentage to VREGN REG01[7:6] =10 3%
PWM
FSW PWM switching frequency, and digital clock Oscillator frequency 1.32 1.68 MHz
DMAX Maximum PWM duty cycle 97%
BOOST MODE OPERATION
V(OTG_REG_RANGE) Typical boost mode regulation voltage range 4.55 5.55 V
V(OTG_REG_STEP) Typical boost mode regulation voltage step 64 mV
I(PMID) = 0 A, BOOSTV=5.126V (REG0A[7:4]
V(OTG_REG_ACC) Boost mode regulation voltage accuracy –3% 3%
= 1001)
V(OTG_BAT) Battery voltage exiting boost mode BAT falling 2.6 2.9 V
I(OTG) Boost mode output current range 3.1 A
V(OTG_OVP) Boost mode over-voltage threshold Rising threshold 5.8 6 V

bq25895

otherwise noted)
REGN LDO
V(REGN) REGN LDO output voltage V(VBUS) = 9 V, I(REGN) = 40 mA 5.6 6 6.4 V
V(VBUS) = 5 V, I(REGN) = 20 mA 4.7 4.8 V
I(REGN) REGN LDO current limit V(VBUS) = 9 V, V(REGN) = 3.8 V 50 mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES Resolution Rising threshold 7 bits
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
2.304 4.848 V
enabled
VBAT(RANGE) Typical battery voltage range
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
VSYS_MIN 4.848 V
disabled
V(BAT_RES) Typical battery voltage resolution 20 mV
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
2.304 4.848 V
enabled
V(SYS_RANGE) Typical system voltage range
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
VSYS_MIN 4.848 V
disabled
V(SYS_RES) Typical system voltage resolution 20 mV
V(VBUS) > VBAT + V(SLEEP) or OTG mode is 2.6 15.3 V
V(VBUS_RANGE) Typical VVBUS voltage range
enabled
V(VBUS_RES) Typical VVBUS voltage resolution 100 mV
V(VBUS) > VBAT + V(SLEEP) and VBAT >
IBAT(RANGE) Typical battery charge current range 0 6.4 A
VBAT(SHORT)
IBAT(RES) Typical battery charge current resolution 50 mA
V(TS_RANGE) Typical TS voltage range 21% 80%
V(TS_RES) Typical TS voltage resolution 0.47%
LOGIC I/O PIN (OTG, CE, PSEL, QON)
VIH Input high threshold level 1.3
VIL Input low threshold level 0.4 V
IIN(BIAS) High Level Leakage Current Pull-up rail 1.8 V 1 µA
Battery only mode BAT V
V(QON) Internal /QON pull-up V(VBUS) = 9 V 5.8 V
V(VBUS) = 5 V 4.3 V
R(QON) Internal /QON pull-up resistance 200 kΩ
LOGIC I/O PIN (INT, STAT, PG, DSEL)
VOL Output low threshold level Sink current = 5 mA, sink current 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA
I2C INTERFACE (SCL, SDA)

VIH Input high threshold level, SCL and SDA Pull-up rail 1.8 V 1.3
VIL Input low threshold level Pull-up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA, sink current 0.4 V
IBIAS High level leakage current Pull-up rail 1.8 V 1 µA

bq25895
7.6 Timing Requirements

MIN NOM MAX UNIT
VBUS/BAT POWER UP
tBADSRC Bad Adapter detection duration 30 msec
D+/D- DETECTION
tSDP_DEFAULT Charging timer with USB100 in default mode 2 mins
BAT OVER-VOLTAGE PROTECTION
Battery over-voltage deglitch time to disable
tBATOVP 1 µs
charge
BATTERY CHARGER
tRECHG Recharge deglitch time 20 ms
CURRENT PULSE CONTROL
tPUMPX_STOP Current pulse control stop pulse 430 570 ms
tPUMPX_ON1 Current pulse control long on pulse 240 360 ms
tPUMPX_ON2 Current pulse control short on pulse 70 130 ms
tPUMPX_OFF Current pulse control off pulse 70 130 ms
tPUMPX_DLY Current pulse control stop start delay 80 225 ms
BATTERY MONITOR
tCONV Conversion time CONV_RATE(REG02[6]) = 0 8 1000 ms
QON AND SHIPMODE TIMING
QON low time to turn on BATFET and exit ship
tSHIPMODE TJ = –10°C to +60°C 1.25 2.25 s
mode
tQON_RST QON low time to enable full system reset TJ = –10°C to +60°C 12 18 s
tBATFET_RST BATFET off time during full system reset TJ = –10°C to +60°C 350 550 ms
tSM_DLY Enter ship mode delay TJ = –10°C to +60°C 10 15 s
I2C INTERFACE
fSCL SCL clock frequency 400 kHz
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIG Digital low power clock REGN LDO disabled 18 30 45 kHz
fDIG Digital clock REGN LDO enabled 1320 1500 1680 kHz
WATCHDOG
(REG07[5:4])=11, REGN LDO 100 160 s
disabled
tWDT Watchdog reset time
WATCHDOG
(REG07[5:4])=11, REGN LDO 136 160 s
enabled

bq25895
7.7 Typical Characteristics
95% 95%
VBUS = 5 V
94% VBUS = 9 V 93%
93% VBUS = 12 V 91%
92% 89%
Efficiency (%)
Efficiency (%)
91% 87%
90% 85%
89% 83%
88% 81%
87% 79% VBUS = 5 V
86% 77% VBUS = 9 V
VBUS = 12 V
85% 75%
0 1 2 3 4 5 0 0.5 1 1.5 2
Charge Current (A) D001
System Load Current (A) D002
VBAT = 3.8 V DCR = 10 mΩ
Figure 1. Charge Efficiency vs Charge Current Figure 2. System Light Load Efficiency vs System Light
Load Current
100% 6%
98% 5%
4%
96%
3%
94%
2%
Efficiency (%)
92%
Error (%)
1%
90% 0
88% -1%
-2%
86%
-3%
84%
-4%
82% VBAT = 3.2 V VBAT = 3.1 V
VBAT = 3.8 V -5% VBAT = 3.8 V
80% -6%
0 1 2 3 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
PMID Load Current (A) D004
Charge Current (A) D005
VBUS = 9 V
Figure 3. Boost Mode Efficiency vs PMID Load Current Figure 4. Charge Current Accuracy vs Charge Current I2C
Setting
3.7 4.5
3.68 4.45
3.66 4.4
3.64 4.35
SYS Voltage (V)
SYS Voltage (V)
3.62 4.3
3.6 4.25
3.58 4.2
3.56 4.15
3.54 4.1
3.52 4.05
VBUS = 5 V VBUS = 5 V
3.5 4
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
VBAT = 2.9 V VBUS = 5 V SYSMIN = 3.5 V VBAT = 4.2 V
Figure 5. SYS Voltage Regulation vs System Load Current Figure 6. SYS Voltage Regulation vs System Load Current

bq25895
Typical Characteristics (continued)

4.42 1600
4.4
4.38 1400
4.36
Input Current Limit (mA)

4.34 1200
4.32
BAT Voltage (V)
4.3 1000
4.28
4.26 800
4.24
4.22 600
4.2
4.18 400
4.16 IINLM = 500 mA
4.14 VBUS = 5 V 200 IINLM = 900 mA
4.12 VBUS = 12 V IINLIM = 1.5 A
4.1 0
-50 0 50 100 150 -60 -40 -20 0 20 40 60 80 100 120 140150
Temperature (qC) D008
Temperature (qC) D009
Figure 7. BAT Voltage vs Temperature Figure 8. Input Current Limit vs Temperature

bq25895
8 Detailed Description
The device is a highly integrated 5-A siwtch-mode battery charger for single cell Li-Ion and Li-polymer battery. It
is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side siwtching FET (HSFET, Q2) ,
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap
diode for the high-side gate drive.
8.1 Functional Block Diagram
VBUS RBFET PMID
VVBUS_UVLOZ (Q1)
UVLO
Q1 Gate
VBATZ +80mV Control
SLEEP REGN
REGN
LDO
EN_HIZ
ACOV
VACOV
BTST
FBO
VBUS VBUS_OVP_BOOST
V OTG_OVP
IQ2 Q2_UCP_BOOST
VINDPM V
OTG_HSZCP
SW
IQ3
Q3_OCP_BOOST
I INDPM V
OTG_BAT
CONVERTER HSFET (Q2)
CONTROL
BAT BATOVP REGN
IC T J 104%xV BAT_REG
BAT
TREG
V BAT_REG I LSFET_UCP
UCP
LSFET (Q3) PGND
IQ2
SYS IQ3 Q2_OCP
I HSFET_OCP
VSYSMIN
ICHG_REG EN_HIZ V BTST -VSW
EN_CHARGE REFRESH
V BTST_REFRESH
EN_BOOST
SYS
I CHG
REF
DAC VCHG_REG
I BADSRC I BAT_REG Q4 Gate BATFET
BAD_SRC
ILIM IDC Control
Converter
Control State
(Q4)
DSEL
Machine IC TJ
TSHUT
TSHUT BAT
VQON
BAT
BAT_GD
Input VBATGD
D+
Source /QON
D± Detection USB I CHG
ADC Control
Adapter VBUS
V REG -VRECHG
OTG RECHRG BAT
BAT ADC
SYS
INT I CHG TS
TERMINATION
CHARGE I TERM
CONTROL
V BATLOWV
STAT STATE
MACHINE
BATLOWV
BAT bq25895
V SHORT
I2C BATSHORT
Interface BAT Battery
SUSPEND Sensing TS
Thermistor
SCL SDA CE

bq25895
8.2 Feature Description

8.2.1 Device Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.2.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods describe in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.
8.2.3 Device Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started when
AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINLIM) register and input
source type
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up
8.2.3.1 Power Up REGN Regulation (LDO)

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
3. After 220 ms delay is completed
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
8.2.3.2 Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the buck converter.
1. VBUS voltage below VACOV
2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.

bq25895
Feature Description (continued)

8.2.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection
when AUTO_DPDM_EN bit is set.
The bq25895 follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source
(SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it
initiates adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake
when MAXC_EN or HVDCP_EN is set.
After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin
are changed:
1. Input Current Limit (IINLIM) register is changed to set current limit
2. PG_STAT bit is set
3. SDP_STAT bit is updated to indicate USB100 or other input source
The host can over-write IINLIM register to change the input current limit if needed. The charger input current is
always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO) is
enable or disabled.
When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit
(IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.
8.2.3.3.1 D+/D– Detection Sets Input Current Limit

The bq25890 contains a D+/D– based input source detection to set the input current limit automatically. The
D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter
detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2
is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated
Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard
adapter detection is applied to set the input current limit.
When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge™,
etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input
source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be
disabled by clearing MAXC_EN and/or HVDCP_EN bits .
Non-Standard Adapter
(Divider 1: 2.1A)
Non-Standard
(Divider 2: 2A)
Adapter (Divider 3: 1A)
(Divider 4: 2.4A)
Adapter Plug-in
USB BC1.2 Ajustable High Voltage Adapter
or
Detection Handshake
EN_DPDM
SDP(USB100/USB500) CDP 0D[&KDUJHŒ $SDSWHU DCP

(500mA) (1.5A) (1.5A) (3.25A)
Figure 9. USB D+/D- Detection

bq25895
Table 1. Non-Standard Adapter Detection

NON-STANDARD
D+ THRESHOLD D- THRESHOLD INPUT CURRENT LIMIT
ADAPTER
Divider 1 VD+ within V2P7_VTH VD- within V2P0_VTH 2.1A
Divider 2 VD+ within V1P2_VTH VD- within V1P2_VTH 2A
Divider 3 VD+ within V2P0_VTH VD- within V2P7_VTH 1A
Divider 4 VD+ within V2P7_VTH VD- within V2P7_VTH 2.4A
Table 2. Adjustable High Voltage Adapter D+/D- Output Configurations

ADJUSTABLE HIGH VOLTAGE HANDSHAKE D+ D- OUTPUT
MaxCharge (12V) I1P6MA_ISINK V3p45_VSRC 12 V
MaxCharge (9V) V3p45_VSRC I1P6MA_ISINK 9V
After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following
registers including Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:
Table 3. bq25895 Result

INPUT CURRENT LIMIT
D+/D- DETECTION SDP_STAT VBUS_STAT
(IINLIM)
USB SDP (USB500) 500 mA 1 001
USB CDP 1.5 A 1 010
USB DCP 3.25 A 1 011
Divider 3 1A 1 110
Divider 1 2.1 A 1 110
Divider 4 2.4 A 1 110
Divider 2 2A 1 110
MaxCharge 1.5 A 1 100
Unknown Adapter 500 mA 1 101

bq25895
8.2.3.3.2 Force Input Current Limit Detection

In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed,
FORCE_DPDM bit returns to 0 by itself and Input Result is updated.
8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two
methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.
1. Absolute VINDPM (FORCE_VINDPM=1)
By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM
is writable and allows host to set the absolute threshold of VINDPM function.
2. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)
When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM
register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The
algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.
After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.
8.2.3.5 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the
device limits input current to the lower value of ILIM pin and IILIM register (ICO_EN = 0) or IDPM_LIM register
(ICO_EN = 1).
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-
tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS.
8.2.4 Input Current Optimizer (ICO)

The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without overload
the input source. The algorithm automatically identify maximum input current limit of power source without
entering VINDPM to avoid input source overload.
This feature is enabled by default (ICO_EN=1) and can be disabled by setting ICO_EN bit to 0. After DCP or
MaxCharge type input source is detected based on the procedures previously described (Input Source Type
Detection ). The algorithm runs automatically when ICO_EN bit is set. The algorithm can also be forced to
execute by setting FORCE_ICO bit regardless of input source type detected.
The actual input current limit used by the Dynamic Power Management is reported in IDPM_LIM register while
Input Current Optimizer is enabled (ICO_EN = 1) or set by IINLIM register when the algorithm is disabled
(ICO_EN = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin
function.

bq25895
8.2.5 Boost Mode Operation from Battery

The device supports boost converter operation to deliver power from the battery to other portable devices
through PMID pin. The boost mode output current rating supports maximum output current up to 3.1 A to charge
smartphone and tablet at fast charging rate. The boost operation can be enabled if the conditions are valid:
1. BAT above BATLOWV
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH and OTG_CONFIG bit =1)
4. Voltage at TS (thermistor) pin is within range configured by Boost Mode Temperature Monitor as configured
by BHOT and BCOLD bits
5. After 30 ms delay from boost mode enable
In boost mode, the device employs a 500 KHz or 1.5 MHz (selectable using BOOST_FREQ bit) step-up
switching regulator based on system requirements. To avoid frequency change during boost mode operations,
write to boost frequency configuration bit (BOOST_FREQ) is ignored when OTG_CONFIG is set.
During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5V by default
(selectable via BOOSTV register bits). The boost output is maintained when BAT is above VOTG_BAT threshold
8.2.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.2.6.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage (default 3.5 V).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the
minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the
VDS of BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage
regulation.
4.4
Minimum System Voltage
SYS (Charge Disabled)
4.2 SYS (Charge Enabled)
System Voltage (V)
3.8
3.6
3.4
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
BAT (V) D011
Figure 10. V(SYS) vs V(BAT)
8.2.6.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below
the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below
the input current limit and the input voltage rises above the input voltage limit.

bq25895
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement
Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high.
Figure 11 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V
minimum system voltage setting.
Voltage
VBUS
SYS
3.6V
3.4V
3.2V BAT
3.18V
Current
4A
3.2A ICHG
2.8A ISYS
1.2A IIN
1.0A
0.5A
-0.6A
DPM DPM
Supplement
Figure 11. DPM Response
8.2.6.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low.
This prevents oscillation from entering and exiting the Supplement Mode. As the discharge current increases, the
BATFET gate is regulated with a higher voltage to reduce RDS(ON) until the BATFET is in full conduction. At this
point onwards, the BATFET VDS linearly increases with discharge current. Figure 12 shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit Supplement Mode when the battery is below battery
depletion threshold.
5.0
4.5
4.0
3.5
Current (A)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 5 10 15 20 25 30 35 40 45 50 55
V(BAT_SYS) (mV) D010
Figure 12. BATFET V-I Curve

bq25895
8.2.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 5-A charge current for high capacity battery. The 11-mΩ
BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.2.7.1 Autonomous Charging Cycle

With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is low), the device autonomously completes
a charging cycle without host involvement. The device default charging parameters are listed in Table 4. The
host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
Table 4. Charging Parameter Default Setting

DEFAULT MODE bq25895
Charging Voltage 4.208 V
Charging Current 2.048 A
Pre-charge Current 128 mA
Termination Current 256 mA
Temperature Profile Cold/Hot
Safety Timer 12 hour
A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
• No thermistor fault on TS pin
• No safety timer fault
• BATFET is not forced to turn off (BATFET_DIS bit = 0)
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When
a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device
automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status
register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.
8.2.7.2 Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.
Table 5. Charging Current Setting

VBAT CHARGING CURRENT REG DEFAULT SETTING CHRG_STAT
<2V IBATSHORT – 01
2V–3V IPRECHG 128 mA 01
>3V ICHG 2048 mA 10

bq25895
If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less
than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is
counted at half the clock rate.
Regulation Voltage
(3.84V t 4.608V)
Battery Voltage
Fast Charge Current
(128mA-5056mA)
Charge Current
VBAT_LOWV (2.8V/3V)
VBAT_SHORT (2V)
IPRECHARGE (64mA-1024mA)
ITERMINATION (64mA-1024mA)
IBATSHORT (100mA)
Trickle Charge Pre-charge Fast Charge and Voltage Regulation Safety Timer
Expiration
Figure 13. Battery Charging Profile
8.2.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
8.2.7.4 Resistance Compensation (IRCOMP)

For high current charging system, resistance between charger output and battery cell terminal such as board
routing, connector, MOSFETs and sense resistor can force the charging process to move from constant current
to constant voltage too early and increase charge time. To speed up the charging cycle, the device provides
resistance compensation (IRCOMP) feature which can extend the constant current charge time to delivery
maximum power to battery.
The device allows the host to compensate for the resistance by increasing the voltage regulation set point based
on actual charge current and the resistance as shown below. For safe operation, the host should set the
maximum allowed regulation voltage register (VCLAMP) and the minimum resistance compensation (BATCOMP).
VREG_ACTUAL = VREG + min(ICHRG_ACTUAL x BATCOMP, VCLAMP) (1)
8.2.7.5 Thermistor Qualification
8.2.7.5.1 Cold/Hot Temperature Window in Charge Mode

The device continuously monitors battery temperature by measuring the voltage between the TS pins and
ground, typically determined by a negative temperature coefficient thermistor (NTC) and an external voltage
divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To
initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge
cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and
waits until the battery temperature is within the VLTF to VHTF range.

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REGN
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TS
RT2 RTH
103AT
Figure 14. TS Resistor Network
When the TS fault occurs, the fault register REG0C[2:0] indicates the actual condition on each TS pin and an INT
is asserted to the host. The STAT pin indicates the fault when charging is suspended.
TEMPERATURE RANGE TO TEMPERATURE RANGE
INITIATE CHARGE DURING A CHARGE CYCLE
VREGN VREF
CHARGE SUSPENDED CHARGE SUSPENDED

VLTF VLTF
VLTFH VLTFH
CHARGE at full C CHARGE at full C
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
AGND AGND
Figure 15. TS Pin Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 14, the value RT1 and RT2 can be
determined by using Equation 2: :
æ 1 1 ö
VREGN ´ RTHCOLD ´ RTHHOT ´ ç - ÷
RT2 = è VT1 VT5 ø
æ VREGN ö æ VREGN ö
RTHHOT ´ ç - 1÷ - RTHCOLD ´ ç - 1÷
è VT5 ø è VT1 ø
VREGN
-1
RT1 = VT1
1 1
+
RT2 RTHCOLD (2)
Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.91 kΩ
RT1 = 5.21 kΩ
RT2 = 29.87 kΩ

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8.2.7.5.2 Cold/Hot Temperature Window in Boost Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to
VBHOTx thresholds unless boost mode temperature is disabled by setting BHOT bits to 11. When temperature is
outside of the temperature thresholds, the boost mode and BATFET are disabled and BATFET_DIS bit is set to
reduce leakage current on PMID. Once temperature returns within thresholds, the host can clear BATFET_DIS
bit or provide logic low to high transition on QON pin to enable BATFET and boost mode.
Temperature Range to
Boost
VREGN
Boost Disable
V BCOLDx
( - 10ºC / 20ºC)
Boost Enable
V
BHOTx
(55ºC / 60ºC / 65ºC)
Boost Disable
AGND
Figure 16. TS Pin Thermistor Sense Thresholds in Boost Mode
8.2.7.6 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety
timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to
11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will
expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
8.2.8 Battery Monitor

The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system
voltage, thermistor ratio, and charging current, and charging current based on the device modes of operation.
The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be
configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second
continuous conversion.
For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the
conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The
conversion result is ready after tCONV (maximum 1 second).
For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During
active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides
conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when
CONV_RATE is cleared.
When battery monitor is active, the REGN power is enabled and can increase device quiescent current. In
battery only mode, the battery monitor is only active when V(BAT) > SYS_MIN setting in REG03.

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Table 6. Battery Monitor Modes of Operation

MODES OF OPERATION
PARAMETER REGISTER CHARGE DISABLE CHARGE BATTERY ONLY
BOOST MODE
MODE MODE MODE
Battery Voltage (VBAT) REG0E Yes Yes Yes Yes
System Voltage (VSYS) REG0F Yes Yes Yes Yes
Temperature (TS) Voltage (VTS) REG10 Yes Yes Yes Yes
VBUS Voltage (VVBUS) REG11 Yes Yes Yes NA
Charge Current (IBAT) REG12 Yes NA NA NA
8.2.9 Status Outputs (STAT, and INT)
8.2.9.1 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in
Figure 47. The STAT pin function can be disable by setting STAT_DIS bit.
Table 7. STAT Pin State

CHARGING STATE STAT INDICATOR
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (Input overvoltage, TS fault, timer fault, input or system overvoltage).
blinking at 1 Hz
Boost Mode suspend (due to TS Fault)
8.2.9.2 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate 256-µs INT pulse.
• USB/adapter source identified (through PSEL or DPDM detection, with OTG pin)
• Good input source detected
– VBUS above battery (not in sleep)
– VBUS below VACOV threshold
– VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Input removed
• Charge Complete
• Any FAULT event in REG0C
When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads
the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively.
The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.
8.2.10 BATET (Q4) Control
8.2.10.1 BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configurated
by BATFET_DLY bit.
8.2.10.2 BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
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2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping
mode
8.2.10.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged-in. By
changing the state of BATFET from off to on, system connects to SYS can be effectively have a power-on-reset.
The QON pin supports push-button interface to reset system power without host by change the state of BATFET.
When the QON pin is driven to logic low for tQON_RST (typical 15 seconds) while input source is not plugged in
and BATFET is enabled (BATFET_DIS=0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to
reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.
8.2.11 Current Pulse Control Protocol

The device provides the control to generate the VBUS current pulse protocol to communicate with adjustable
high voltage adapter in order to signal adapter to increase or decrease output voltage. To enable the interface,
the EN_PUMPX bit must be set. Then the host can select the increase/decrease voltage pulse by setting one of
the PUMPX_UP or PUMPX_DN bit (but not both) to start the VBUS current pulse sequence. During the current
pulse sequence, the PUMPX_UP and PUMPX_DN bits are set to indicate pulse sequence is in progress and the
device pulses the input current limit between current limit set forth by IINLIM or IDPM_LIM register and the
100mA current limit (IINDPM100_ACC). When the pulse sequence is completed, the input current limit is returned to
value set by IINLIM or IDPM_LIM register and the PUMPX_UP or PUMPX_DN bit is cleared. In addition, the
EN_PUMPX can be cleared during the current pulse sequence to terminate the sequence and force charger to
return to input current limit as set forth by the IINLIM or IDPM_LIM register immediately. When EN_PUMPX bit is
low, write to PUMPX_UP and PUMPX_DN bit would be ignored and have no effect on VBUS current limit.
8.2.12 Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.
The input maximum current is set by a resistor from ILIM pin to ground as:
KILIM
IINMAX =
RILIM (3)
The actual input current limit is the lower value between ILIM setting and register setting (IINLIM). For example, if
the register setting is 111111 for 3.25 A, and ILIM has a 260-Ω resistor (KILIM = 390 max.) to ground for 1.5 A,
the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings
when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters
input current regulation (Refer to Dynamic Power Management section).
The ILIM pin can also be used to monitor input current when EN_ILIM is enabled. The voltage on ILIM pin is
proportional to the input current. ILIM pin can be used to monitor the input current following Equation 4:
KILIM x VILIM
IIN =
RILIM x 0.8 V (4)
For example, if ILIM pin is set with 260-Ω resistor, and the ILIM voltage is 0.4 V, the actual input current 0.615 A
- 0.75 A (based on KILM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage
floats above 0.8 V. If ILIM pin is short, the input current limit is set by the register.
The ILIM pin function can be disabled by setting EN_ILIM bit to 0. When the pin is disabled, both input current
limit function and monitoring function are not available.
8.2.13 Thermal Regulation and Thermal Shutdown
8.2.13.1 Thermal Protection in Buck Mode

The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit
(TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC
allows the user to optimize the system thermal performance.

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During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register
THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The
BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS.
8.2.13.2 Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
surface temperature exceeds TSHUT, BATFET is turned off to disable battery discharge. When IC surface
temperature is below TSHUT_HYS, the host can use one of the method describes in section BATFET Enable (Exit
Shipping Mode) to recover.
8.2.14 Voltage and Current Monitoring in Buck and Boost Mode
8.2.14.1 Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck and boost
mode operations.
8.2.14.1.1 Input Overvoltage (ACOV)

The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops
switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT
is asserted to the host..
8.2.14.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
8.2.14.2 Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as LSFET current to ensure safe boost mode operation.
8.2.14.2.1 Boost Mode Overvoltage Protection

When PMID voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage
protection which stops switching and pauses boost mode (OTG_CONFIG bit remains set) until OVP fault is
removed. During the overvoltage, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost
operation. An INT is also asserted to the host.
8.2.15 Battery Protection
8.2.15.1 Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
8.2.15.2 Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To
recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the
BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or
precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV.
8.2.15.3 System Overcurrent Protection

When the system is shorted or significantly overloaded (IBAT > IBATOP) so that its current exceeds the overcurrent
limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET
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8.2.16 Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
8.2.16.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable; Change

Data valid of data
allowed
Figure 17. Bit Transfer on the I2C Bus
8.2.16.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA SDA
SCL SCL
START (S) STOP (P)

Figure 18. START and STOP conditions

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8.2.16.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement Acknowledgement
signal from slave signal from revceiver
MSB
P or
S or Sr 1 2 7 8 9 1 2 8 9 Sr
START or ACK ACK
STOP or
Repeated Repeated
START START
Figure 19. Data Transfer on the I2C Bus
8.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.2.16.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP
Figure 20. Complete Data Transfer
8.2.16.6 Single Read and Write
1 7 1 1 8 1 8 1 1
S Slave Address 0 ACK Reg Addr ACK Data Addr ACK P
Figure 21. Single Write

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1 7 1 1 8 1 1 7 1 1
S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK
8 1 1
Data NCK P
Figure 22. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
8.2.16.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.
Figure 23. Multi-Write
Figure 24. Multi-Read
REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the
fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault
information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and
multi-write.
8.3 Device Functional Modes

8.3.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings.

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Device Functional Modes (continued)

In default mode, the device keeps charging the battery with 12-hour fast charging safety timer. At the end of the
12-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write
command to device transitions the charger from default mode to host mode. All the device parameters can be
programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1
to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by
setting WATCHDOG bits=00.
When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all
registers are reset to default values except IINLIM, VINDPM, VINDPM_OS, BATFET_RST_EN, BATFET_DLY,
and BATFET_DIS bits.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Y Host Mode
I2C Write? Start watchdog timer
Host programs registers
Default Mode
Reset watchdog timer Y
Reset selective registers WD_RST bit = 1?
N Y N
I2C Write?
Y Watchdog Timer N
Expired?
Figure 25. Watchdog Timer Flow Chart

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8.4 Register Maps

I2C Slave Address: 6AH (1101010B + R/W)
8.4.1 REG00
Figure 26. REG00

7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. REG00
Bit Field Type Reset Description
Enable HIZ Mode
by REG_RST
7 EN_HIZ R/W 0 – Disable (default)
by Watchdog
1 – Enable
Enable ILIM Pin
by REG_RST
6 EN_ILIM R/W 0 – Disable
by Watchdog
1 – Enable (default: Enable ILIM pin (1))
5 IINLIM[5] R/W by REG_RST 1600mA Input Current Limit
Offset: 100mA
4 IINLIM[4] R/W by REG_RST 800mA
Range: 100mA (000000) – 3.25A (111111)
3 IINLIM[3] R/W by REG_RST 400mA Default:0001000 (500mA)
(Actual input current limit is the lower of I2C or ILIM pin)
2 IINLIM[2] R/W by REG_RST 200mA IINLIM bits are changed automaticallly after input source
1 IINLIM[1] R/W by REG_RST 100mA type detection is completed
USB Host SDP w/ OTG=Hi (USB500) = 500mA
USB Host SDP w/ OTG=Lo (USB100) = 500mA
USB CDP = 1.5A
0 IINLIM[0] R/W by REG_RST 50mA USB DCP = 3.25A
Adjustable High Voltage (MaxCharge) DCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2A/2.1A/2.4A

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8.4.2 REG01
Figure 27. REG01
7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 0
Table 9. REG01
by REG_RST Boost Mode Hot Temperature Monitor Threshold
7 BHOT[1] R/W
by Watchdog 00 – VBHOT1 Threshold (34.75%) (default)
01 – VBHOT0 Threshold (Typ. 37.75%)
by REG_RST 10 – VBHOT2 Threshold (Typ. 31.25%)
6 BHOT[0] R/W
by Watchdog 11 – Disable boost mode thermal protection
Boost Mode Cold Temperature Monitor Threshold
by REG_RST
5 BCOLD R/W 0 – VBCOLD0 Threshold (Typ. 77%) (default)
by Watchdog
1 – VBCOLD1 Threshold (Typ. 80%)
4 VINDPM_OS[4] R/W by REG_RST 1600mV Input Voltage Limit Offset
Default: 600mV (00110)
3 VINDPM_OS[3] R/W by REG_RST 800mV
Range: 0mV – 3100mV
2 VINDPM_OS[2] R/W by REG_RST 400mV Minimum VINDPM threshold is clamped at 3.9V
Maximum VINDPM threshold is clamped at 15.3V
1 VINDPM_OS[1] R/W by REG_RST 200mV When VBUS at noLoad is ≤ 6V, the VINDPM_OS is used
to calculate VINDPM threhold
0 VINDPM_OS[0] R/W by REG_RST 100mV When VBUS at noLoad is > 6V, the VINDPM_OS multiple
by 2 is used to calculate VINDPM threshold.

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8.4.3 REG02
Figure 28. REG02
7 6 5 4 3 2 1 0
Table 10. REG02

ADC Conversion Start Control
0 – ADC conversion not active (default).
by REG_RST
7 CONV_START R/W 1 – Start ADC Conversion
by Watchdog
This bit is read-only when CONV_RATE = 1. The bit stays high during
ADC conversion and during input source detection.
ADC Conversion Rate Selection
by REG_RST
6 CONV_RATE R/W 0 – One shot ADC conversion (default)
by Watchdog
1 – Start 1s Continuous Conversion
Boost Mode Frequency Selection
by REG_RST 0 – 1.5MHz
5 BOOST_FREQ R/W
by Watchdog 1 – 500KHz (default)
Note: Write to this bit is ignored when OTG_CONFIG is enabled.
Input Current Optimizer (ICO) Enable
4 ICO_EN R/W by REG_RST 0 – Disable ICO Algorithm
1 – Enable ICO Algorithm (default)
High Voltage DCP Enable
3 HVDCP_EN R/W by REG_RST 0 – Disable HVDCP handshake
1 – Enable HVDCP handshake (default)
MaxCharge Adapter Enable
2 MAXC_EN R/W by REG_RST 0 – Disable MaxCharge handshake
1 – Enable MaxCharge handshake (default)
Force D+/D- Detection
by REG_RST
1 FORCE_DPDM R/W 0 – Not in D+/D- or PSEL detection (default)
by Watchdog
1 – Force D+/D- detection
Automatic D+/D- Detection Enable
0 AUTO_DPDM_EN R/W by REG_RST 0 –Disable D+/D- or PSEL detection when VBUS is plugged-in
1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default)

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8.4.4 REG03
Figure 29. REG03

7 6 5 4 3 2 1 0
0 0 1 1 1 0 1 0
R/W R/W R/W R/W R/W R/W R/W RW
Table 11. REG03

Battery Load (IBATLOAD) Enable
by REG_RST
7 BAT_LOADEN R/W 0 – Disabled (default)
by Watchdog
1 – Enabled
I2C Watchdog Timer Reset
by REG_RST
6 WD_RST R/W 0 – Normal (default)
by Watchdog
1 – Reset (Back to 0 after timer reset)
Boost (OTG) Mode Configuration
by REG_RST
5 OTG_CONFIG R/W 0 – OTG Disable
by Watchdog
1 – OTG Enable (default)
Charge Enable Configuration
by REG_RST
4 CHG_CONFIG R/W 0 - Charge Disable
by Watchdog
1- Charge Enable (default)
3 SYS_MIN[2] R/W by REG_RST 0.4V Minimum System Voltage Limit
Offset: 3.0V
2 SYS_MIN[1] R/W by REG_RST 0.2V
Range 3.0V-3.7V
1 SYS_MIN[02] R/W by REG_RST 0.1V Default: 3.5V (101)
by REG_RST
0 Reserved R/W Reserved (default = 0)
by Watchdog

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8.4.5 REG04
Figure 30. REG04
7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0
Table 12. REG04

Current pulse control Enable
by Softwareby
7 EN_PUMPX R/W 0 - Disable Current pulse control (default)
by Watchdog
1- Enable Current pulse control (PUMPX_UP and PUMPX_DN)
by Softwareby
6 ICHG[6] R/W 4096mA
by Watchdog
by Softwareby
5 ICHG[5] R/W 2048mA
by Watchdog
Fast Charge Current Limit
by Softwareby
4 ICHG[4] R/W 1024mA Offset: 0mA
by Watchdog
Range: 0mA (0000000) – 5056mA (1001111)
by Softwareby Default: 2048mA (0100000)
3 ICHG[3] R/W 512mA
by Watchdog Note:
ICHG=000000 (0mA) disables charge
by Softwareby
2 ICHG[2] R/W 256mA ICHG > 1001111 (5056mA) is clamped to register value
by Watchdog
1001111 (5056mA)
by Softwareby
1 ICHG[1] R/W 128mA
by Watchdog
by Softwareby
0 ICHG[0] R/W 64mA
by Watchdog

bq25895
8.4.6 REG05
Figure 31. REG05
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 1
Table 13. REG05

by Softwareby
7 IPRECHG[3] R/W 512mA
by Watchdog
by Softwareby Precharge Current Limit
by Watchdog Offset: 64mA
by Softwareby Range: 64mA – 1024mA
5 IPRECHG[1] R/W 128mA Default: 128mA (0001)
by Watchdog
by Softwareby
by Watchdog
by Softwareby
3 ITERM[3] R/W 512mA
by Watchdog
by Softwareby Termination Current Limit
2 ITERM[2] R/W 256mA
by Watchdog Offset: 64mA
by Softwareby Range: 64mA – 1024mA
1 ITERM[1] R/W 128mA Default: 256mA (0011)
by Watchdog
by Softwareby
0 ITERM[0] R/W 64mA
by Watchdog

bq25895
8.4.7 REG06
Figure 32. REG06
7 6 5 4 3 2 1 0
0 1 0 1 1 1 1 0
Table 14. REG06

by Softwareby
7 VREG[5] R/W 512mV
by Watchdog
by Softwareby
6 VREG[4] R/W 256mV
by Watchdog Charge Voltage Limit
by Softwareby Offset: 3.840V
5 VREG[3] R/W 128mV Range: 3.840V – 4.608V (110000)
by Watchdog
Default: 4.208V (010111)
by Softwareby Note:
4 VREG[2] R/W 64mV
by Watchdog VREG > 110000 (4.608V) is clamped to register value
by Softwareby 110000 (4.608V)
3 VREG[1] R/W 32mV
by Watchdog
by Softwareby
2 VREG[0] R/W 16mV
by Watchdog
Battery Precharge to Fast Charge Threshold
by Softwareby
1 BATLOWV R/W 0 – 2.8V
by Watchdog
1 – 3.0V (default)
Battery Recharge Threshold Offset
by Softwareby (below Charge Voltage Limit)
0 VRECHG R/W
by Watchdog 0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])

bq25895
8.4.8 REG07
Figure 33. REG07
7 6 5 4 3 2 1 0
1 0 0 1 1 1 0 1
Table 15. REG07

Charging Termination Enable
by Softwareby
7 EN_TERM R/W 0 – Disable
by Watchdog
1 – Enable (default)
STAT Pin Disable
by Softwareby
6 STAT_DIS R/W 0 – Enable STAT pin function (default)
by Watchdog
1 – Disable STAT pin function
by Softwareby I2C Watchdog Timer Setting
5 WATCHDOG[1] R/W
by Watchdog 00 – Disable watchdog timer
01 – 40s (default)
by Softwareby 10 – 80s
4 WATCHDOG[0] R/W
by Watchdog 11 – 160s
Charging Safety Timer Enable
by Softwareby
3 EN_TIMER R/W 0 – Disable
by Watchdog
1 – Enable (default)
by Softwareby Fast Charge Timer Setting
2 CHG_TIMER[1] R/W
by Watchdog 00 – 5 hrs
01 – 8 hrs
by Softwareby 10 – 12 hrs (default)
1 CHG_TIMER[0] R/W
by Watchdog 11 – 20 hrs
0 Reserved R/W Reserved (Default = 1)

bq25895
8.4.9 REG08
Figure 34. REG08
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
Table 16. REG08

by Softwareby
7 BAT_COMP[2] R/W 80mΩ
by Watchdog
IR Compensation Resistor Setting
by Softwareby
6 BAT_COMP[1] R/W 40mΩ Range: 0 – 140mΩ
by Watchdog
Default: 0Ω (000) (i.e. Disable IRComp)
by Softwareby
5 BAT_COMP[0] R/W 20mΩ
by Watchdog
by Softwareby
4 VCLAMP[2] R/W 128mV
by Watchdog IR Compensation Voltage Clamp
above VREG (REG06[7:2])
by Softwareby
3 VCLAMP[1] R/W 64mV Offset: 0mV
by Watchdog
Range: 0-224mV
by Softwareby Default: 0mV (000)
2 VCLAMP[0] R/W 32mV
by Watchdog
by Softwareby Thermal Regulation Threshold
1 TREG[1] R/W
by Watchdog 00 – 60°C
01 – 80°C
by Softwareby 10 – 100°C
0 TREG[0] R/W
by Watchdog 11 – 120°C (default)

bq25895
8.4.10 REG09
Figure 35. REG09
7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
Table 17. REG09

Force Start Input Current Optimizer (ICO)
0 – Do not force ICO (default)
by Softwareby
7 FORCE_ICO R/W 1 – Force ICO
by Watchdog
Note:
This bit is can only be set only and always returns to 0 after ICO starts
Safety Timer Setting during DPM or Thermal Regulation
0 – Safety timer not slowed by 2X during input DPM or thermal
by Softwareby
6 TMR2X_EN R/W regulation
by Watchdog
1 – Safety timer slowed by 2X during input DPM or thermal regulation
(default)
Force BATFET off to enable ship mode
5 BATFET_DIS R/W by Softwareby 0 – Allow BATFET turn on (default)
1 – Force BATFET off
4 Reserved R/W Reserved (Default = 0)
BATFET turn off delay control
3 BATFET_DLY R/W by Softwareby 0 – BATFET turn off immediately when BATFET_DIS bit is set (default)
1 – BATFET turn off delay by tSM_DLY when BATFET_DIS bit is set
BATFET full system reset enable
2 BATFET_RST_EN R/W by Softwareby 0 – Disable BATFET full system reset
1 – Enable BATFET full system reset (default)
Current pulse control voltage up enable
0 – Disable (default)
by Softwareby 1 – Enable
1 PUMPX_UP R/W
by Watchdog Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed
Current pulse control voltage down enable
0 – Disable (default)
by Softwareby 1 – Enable
0 PUMPX_DN R/W
by Watchdog Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed

bq25895
8.4.11 REG0A
Figure 36. REG0A
7 6 5 4 3 2 1 0
1 0 0 1 0 0 1 1
Table 18. REG0A

by Softwareby
7 BOOSTV[3] R/W 512mV
by Watchdog
by Softwareby Boost Mode Voltage Regulation
6 BOOSTV[2] R/W 256mV Offset: 4.55V
by Watchdog
Range: 4.55V – 5.51V
5 BOOSTV[1] R/W by Softwareby 128mV Default: 5.126V (1001)
by Softwareby
4 BOOSTV[0] R/W 64mV
by Watchdog
by Software
by Watchdog
by Software
by Watchdog
by Software
by Watchdog
by Software
by Watchdog

bq25895
8.4.12 REG0B
Figure 37. REG0B
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
Table 19. REG0B

7 VBUS_STAT[2] R N/A VBUS Status register
bq25895
6 VBUS_STAT[1] R N/A
000: No Input 001: USB Host SDP
010: USB CDP (1.5A)
011: USB DCP (3.25A)
100: Adjustable High Voltage DCP (MaxCharge) (1.5A)
5 VBUS_STAT[0] R N/A 101: Unknown Adapter (500mA)
110: Non-Standard Adapter (1A/2A/2.1A/2.4A)
111: OTG
Note: Software current limit is reported in IINLIM register
4 CHRG_STAT[1] R N/A Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV)
3 CHRG_STAT[0] R N/A 10 – Fast Charging
11 – Charge Termination Done
Power Good Status
2 PG_STAT R N/A 0 – Not Power Good
1 – Power Good
USB Input Status
0 – USB100 input is detected
1 SDP_STAT R N/A
1 – USB500 input is detected
Note: This bit always read 1 when VBUS_STAT is not 001
VSYS Regulation Status
0 VSYS_STAT R N/A 0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)

bq25895
8.4.13 REG0C
Figure 38. REG0C
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
Table 20. REG0C

Watchdog Fault Status
7 WATCHDOG_FAULT R N/A Status 0 – Normal
1- Watchdog timer expiration
Boost Mode Fault Status
0 – Normal
6 BOOST_FAULT R N/A
1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low in
boost mode
5 CHRG_FAULT[1] R N/A Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V)
4 CHRG_FAULT[0] R N/A )
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
Battery Fault Status
3 BAT_FAULT R N/A 0 – Normal
1 – BATOVP (VBAT > VBATOVP)
2 NTC_FAULT[2] R N/A NTC Fault Status
Buck Mode:
1 NTC_FAULT[1] R N/A
000 – Normal
001 – TS Cold
010 – TS Hot
Boost Mode:
0 NTC_FAULT[0] R N/A
000 – Normal
101 – TS Cold
110 – TS Hot

bq25895
8.4.14 REG0D
Figure 39. REG0D
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0
Table 21. REG0D

VINDPM Threshold Setting Method
7 FORCE_VINDPM R/W by Softwareby 0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
6 VINDPM[6] R/W by Softwareby 6400mV Absolute VINDPM Threshold
Offset: 2.6V
5 VINDPM[5] R/W by Softwareby 3200mV
Range: 3.9V (0001101) – 15.3V (1111111)
4 VINDPM[4] R/W by Softwareby 1600mV Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
2 VINDPM[2] R/W by Softwareby 400mV Register is read only when FORCE_VINDPM=0 and can
be written by internal control based on relative VINDPM
threshold setting
0 VINDPM[0] R/W by Softwareby 100mV Register can be read/write when FORCE_VINDPM = 1
8.4.15 REG0E
Figure 40. REG0E
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 22. REG0E

Thermal Regulation Status
7 THERM_STAT R N/A 0 – Normal
1 – In Thermal Regulation
6 BATV[6] R N/A 1280mV
4 BATV[4] R N/A 320mV ADC conversion of Battery Voltage (VBAT)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
2 BATV[2] R N/A 80mV Default: 2.304V (0000000)

bq25895
8.4.16 REG0F
Figure 41. REG0F
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 23. REG0F

7 Reserved R N/A Reserved: Always reads 0
6 SYSV[6] R N/A 1280mV
4 SYSV[4] R N/A 320mV ADDC conversion of System Voltage (VSYS)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
2 SYSV[2] R N/A 80mV Default: 2.304V (0000000)
8.4.17 REG10
Figure 42. REG10
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 24. REG10

7 Reserved R N/A Reserved: Always reads 0
6 TSPCT[6] R N/A 29.76%
5 TSPCT[5] R N/A 14.88%
4 TSPCT[4] R N/A 7.44% ADC conversion of TS Voltage (TS) as percentage of REGN
Offset: 21%
3 TSPCT[3] R N/A 3.72%
Range 21% (0000000) – 80% (1111111)
2 TSPCT[2] R N/A 1.86% Default: 21% (0000000)
1 TSPCT[1] R N/A 0.93%
0 TSPCT[0] R N/A 0.465%

bq25895
8.4.18 REG11
Figure 43. REG11
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 25. REG11

VBUS Good Status
7 VBUS_GD R N/A 0 – Not VBUS attached
1 – VBUS Attached
6 VBUSV[6] R N/A 6400mV
4 VBUSV[4] R N/A 1600mV ADC conversion of VBUS voltage (VBUS)
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
2 VBUSV[2] R N/A 400mV Default: 2.6V (0000000)
8.4.19 REG12
Figure 44. REG12
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 26. REG12

7 Unused R N/A Always reads 0
6 ICHGR[6] R N/A 3200mA
5 ICHGR[5] R N/A 1600mA ADC conversion of Charge Current (IBAT) when VBAT >
VBATSHORT
Offset: 0mA
3 ICHGR[3] R N/A 400mA Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
Note:
1 ICHGR[1] R N/A 100mA This register returns 0000000 for VBAT < VBATSHORT

bq25895
8.4.20 REG13
Figure 45. REG13
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
Table 27. REG13

VINDPM Status
7 VDPM_STAT R N/A 0 – Not in VINDPM
1 – VINDPM
IINDPM Status
6 IDPM_STAT R N/A 0 – Not in IINDPM
1 – IINDPM
5 IDPM_LIM[5] R N/A 1600mA
Input Current Limit in effect while Input Current Optimizer
3 IDPM_LIM[3] R N/A 400mA (ICO) is enabled
2 IDPM_LIM[2] R N/A 200mA Offset: 100mA (default)
Range 100mA (0000000) – 3.25mA (1111111)
8.4.21 REG14
Figure 46. REG14
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R R R R R R
Table 28. REG14

Register Reset
0 – Keep current register setting (default)
7 REG_RST R/W N/A 1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
Input Current Optimizer (ICO) Status
6 ICO_OPTIMIZED R N/A 0 – Optimization is in progress
1 – Maximum Input Current Detected
5 PN[2] R N/A
Device Configuration
4 PN[1] R N/A
111: bq25895
3 PN[0] R N/A
Temperature Profile
2 TS_PROFILE R N/A
0 – Cold/Hot (default)
1 DEV_REV[1] R N/A
Device Revision: 01
0 DEV_REV[0] R N/A

bq25895
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

A typical application consists of the device configured as an I2C controlled power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also
integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application

5V at 2.4A OTG
Phone PMID 2.2 H SYS 3.5V±4.5V

Input SW
3.9V±14V at 3A 40 F
VBUS 47nF 10 F 10 F
1 F BTST
REGN
USB D+ 4.7 F
D-
PGND
260Q
ILIM
SYS
SYS Ichg=5A
BAT
10uF
VREF QON
2.2<Q
STAT
10<Q 10<Q 10<Q
Host SDA REGN Optional
SCL
5.23<Q
INT
OTG TS
/CE
30.1<Q 10<Q
bq25895
Figure 47. bq25895 with D+/D- Interface and 2.4 A Boost Mode Output
9.2.1 Design Requirements

For this design example, use the parameters shown in Table 29.
Table 29. Design Parameter

PARAMETERS VALUES
Input voltage range 3.9 V to 14 V
Input current limit 1.5 A
Fast charge current 5000 mA
Output voltage 4.352 V
VREF system pullup voltage 1.8 V - 3.3 V

bq25895
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the bq25895 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
IBAT ³ ICHG + (1/2) IRIPPLE (5)
The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs)
and inductance (L):
VBUS x D x (1-D)
IRIPPLE =
fs xL (6)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a
practical design.
9.2.2.3 Buck Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50%
and can be estimated by Equation 7:
IPMID = ICHG x D x (1 - D) (7)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred
for up to 14-V input voltage. 8.2-μF capacitance is suggested for typical of 3 A – 5 A charging current.

bq25895
9.2.2.4 System Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
ICSYS = RIPPLE » 0.29 x IRIPPLE
2x 3 (8)
The output capacitor voltage ripple can be calculated as follows:

VSYS æ V ö
DVO = çç1- SYS ÷÷÷
ç
8 LCSYS f s2 çè VBUS ø÷
(9)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum
of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.

bq25895
9.2.3 Application Curves
VBAT = 3.2 V IILIM = 500 mA VBAT = 3.2 V
Figure 48. Power Up from USB100 Figure 49. Power Up with Charge Disabled
VBAT = 3.2 V
Figure 50. Power Up with Charge Disabled Figure 51. Power Up with Charge Enabled
VBUS = 5 V VBUS = 12 V
Figure 52. Charge Enable Figure 53. Charge Disable

bq25895
VBUS = 5 V IIN = 3 A Charge Disable VBUS = 9 V IIN = 1.5 A VBAT = 3.8 V

ICHG = 2 A ISYS = 0 A - 4 A
Figure 54. Input Current DPM Response without Battery Figure 55. Load Transient During Supplement Mode
VBUS = 12 V VBAT = 3.8 V ICHG = 3 A VBUS = 9V ISYS = 10 mA, Charge Disable

No Battery
Figure 56. PWM Switching Waveform Figure 57. PFM Switching Waveform
VBAT = 3.8 V ILOAD = 1 A VBAT = 3.8 V ILOAD = 0 A - 1 A
Figure 58. Boost Mode Switching Waveform Figure 59. Boost Mode Load Transient

bq25895
9.3 System Examples

NSR10F20NXT5G
5V at 3.1A OTG
Phone PMID 2.2 H SYS 3.5V±4.5V

Input SW
3.9V±14V at 3A 60 F
VBUS 47nF 10 F 10 F
1 F BTST
REGN
USB D+ 4.7 F
D-
PGND
260Q
ILIM
SYS
SYS Ichg=5A
BAT
10uF
VREF QON
2.2<Q
STAT
10<Q 10<Q 10<Q
Host SDA REGN Optional
SCL
10<Q
INT
OTG TS
/CE
10<Q
bq25895
Figure 60. bq25895 with D+/D- Interface, 3.1 A Boost Mode Output, and no Thermistor Connections

bq25895
10 Power Supply Recommendations

In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 14 V input
with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage > VBATUVLO
connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 61) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground
with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.
Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the VQFN
information, refer to SCBA017 and SLUA271.
11.2 Layout Example
Figure 61. High Frequency Current Path

bq25895
12 Device and Documentation Support
12.1 Development Support

12.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the bq25895 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ25895RTWR ACTIVE WQFN RTW 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ25895
& no Sb/Br)
BQ25895RTWT ACTIVE WQFN RTW 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ25895
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25895RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ25895RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ25895RTWT WQFN RTW 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ25895RTWT WQFN RTW 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Dec-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ25895RTWR WQFN RTW 24 3000 367.0 367.0 35.0
BQ25895RTWR WQFN RTW 24 3000 367.0 367.0 35.0
BQ25895RTWT WQFN RTW 24 250 210.0 185.0 35.0
BQ25895RTWT WQFN RTW 24 250 210.0 185.0 35.0
Pack Materials-Page 2
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PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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Product Order Technical Tools & Support &

Folder Now Documents Software Community

2 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: bq25895

Changes from Original (March 2015) to Revision A Page

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6 Pin Configuration and Functions

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Pin Functions (continued)

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 5

7.2 ESD Ratings

7.3 Recommended Operating Conditions

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7.4 Thermal Information

7.5 Electrical Characteristics

V(VBUS_UVLOZ) VBUS for active I2C, no battery 3.6 V

V(SLEEP) Sleep mode falling threshold 25 65 120 mV

Top reverse blocking MOSFET(RBFET) on-resistance TJ = –40°C to +85°C 27 38 mΩ

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (continued)

Top switching MOSFET (HSFET) on-resistance between PMID TJ = –40°C to +85°C 27 39 mΩ

Bottom switching MOSFET (LSFET) on-resistance between TJ = –40°C to +85°C 16 24 mΩ

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Electrical Characteristics (continued)

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 9

Electrical Characteristics (continued)

I2C INTERFACE (SCL, SDA)

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7.6 Timing Requirements

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7.7 Typical Characteristics

SYS Voltage (V)

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Typical Characteristics (continued)

Input Current Limit (mA)

Figure 7. BAT Voltage vs Temperature Figure 8. Input Current Limit vs Temperature

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8.1 Functional Block Diagram

VBUS RBFET PMID

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8.2 Feature Description

8.2.2 Device Power Up from Battery without Input Source

8.2.3 Device Power Up from Input Source

8.2.3.1 Power Up REGN Regulation (LDO)

8.2.3.2 Poor Source Qualification

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 15

Feature Description (continued)

8.2.3.3.1 D+/D– Detection Sets Input Current Limit

SDP(USB100/USB500) CDP 0D[&KDUJHŒ $SDSWHU DCP

Figure 9. USB D+/D- Detection

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Table 1. Non-Standard Adapter Detection

Table 2. Adjustable High Voltage Adapter D+/D- Output Configurations

Table 3. bq25895 Result

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 17

8.2.3.3.2 Force Input Current Limit Detection

8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)