Course: Electronics – for Complete Beginners

Section 8: Monolithic Integrated Circuits

Lecture 3: Flip-Flops and Clocks

Flip-Flops
Continuing our conversation from the
previous lecture, we were wondering what
all this flip-flop stuff was about anyway. It’s
not about politics, sandals, or sex.
The basic SR Flip-Flop, also called a Bi-
Stable Latch, can be implemented with
either NAND or NOR gates, although
NANDs are more commonly used.

For the NAND case, the S and R inputs are

normally at logical “1” (high). Taking the S
input to logical “0” results in Q going high.
This is an active-low situation, meaning that
the state changes are caused by inputs going
low, or to logical “0”. By virtue of the cross-
coupled connection, and the fact that R is
high, Q̄ will go to logical “0” (low).
Since that output is coupled to the input of
the “Q” gate, Q will then remain high no
matter what happens at the S input. The flip-
flop is therefore “set”.
Taking R low causes Q̄ to go high, and
assuming that S is then once again in its
normally high state, this results in Q
returning to the logical “0” condition. The
latch is then said to have been “reset”.
The bi-stable latch will remain in whatever
condition it’s in, set or reset, until toggled by
an appropriate S or R input, or until the
power is removed.
Contact De-bouncing
Mechanical switches and relay contacts do
not mix with fast digital circuitry because of
contact bounce. The contacts of switches
and relays do not usually close cleanly,
momentarily producing some chatter before
coming to rest in the new position. In purely
electrical applications, this is usually
irrelevant, but when part of fast electronic
circuitry, the bounces are seen as a series of
openings and closings.
As an example, consider a simple counting
device used at the gate of a public event to
tally attendance. The gate attendant pushes a
button for each person admitted, and the
counter increments by one each time. But
because of switch bounce, the count is apt to
sometimes increment by two, or three, or
four, instead of just one. The simple flip-
flop can fix this …
 Pull-up resistors ensure that the S and R
inputs are never open while the switch is
operated. With R grounded (logical “0”),
output Q will be low. When the button is
pressed, R goes high, and the first instant
that S is touched by the switch’s armature, Q
will go high, forcing Q̄ to go low. The
switch’s armature can then bounce against
the S contact all it wants to, but the output
will not change. When the pushbutton is
released, the opposite occurs, resulting in a
single, clean positive pulse at Q for each
time the attendant pushes the button.
Clocking
In all but the simplest digital applications,
it’s usually advisable, or essential, to control
switching times and sequencing. In the case
of the bi-stable latch, this involves a third
input, called CLK, or sometimes EN — a
“clock” or an “enable” input.
 The two terms are not always
interchangeable. Clock signals usually take
the form of a train of pulses provided by
crystal-controlled multivibrator circuit
operating as “system clock”. Enable signals
may be conditional, generated by some sort
of controller elsewhere in the system. A
simple implementation looks like this …

This is now an active-high bi-stable. When

S goes high, nothing happens until the CLK
input also goes to logical “1”. Then (x) goes
low, causing Q to go high. Since R is low,
(y) will also be high, so Q̄ will go low,
latching Q at logical “1”.
The reset function operates in the same
way; R going high, and (y) then going low
when CLK also goes high. That drives Q̄
high, and since (x) will also be high, Q is
reset to logical “0”.
But there’s a problem with these basic
flip-flops. The simple NAND version is an
active low configuration, meaning that the
static input state is high, with toggling
occurring when one input or the other goes
to logical “0”. What if both inputs happen to
go to logical “0” at the same time?
Obviously, that’ll force both Q and Q̄ to go
high, an illegal situation since these outputs
are supposed to be complimentary.
The same situation occurs with the active-
high clocked version if both S and R
somehow become high during a clock pulse.
Another problem with this clocking scheme
is that the S and R inputs remain active for
the whole duration of the CLK pulse when
that input is raised to logical “1”.
Electrical interference, or “noise”, is the
curse of fast digital circuitry. Noise can
come from a variety of sources — line
voltage spikes, caused by the start-up or
shut-down of other equipment on the power
lines, that are communicated through the
system’s power supply, RFI (radio
frequency interference) from other nearby
equipment that gets conducted into the
circuitry though the air and/or through the
shared power line connection, or even
uncontained signals from other circuitry in
the same system. One of the important
purposes of clocking is to activate the inputs
only briefly, in order to help make them
immune to spurious impulses, so it’s a good
idea to make the duration of the CLK pulses
very short.
But there’s an even better way; it’s called
edge triggering.
 The J-K Flip-Flop
The “J-K” might stand for Jack Kilby, or
maybe it was the Canadian engineer John
Kardash, who actually did patent such a
circuit. Whatever the case, the Set input of
these circuits is labeled J, and the Reset
input, K.

This is obviously like the simple active-

high clocked flip-flop, except that the Q
output is fed back to the Q̄ clocking gate,
and vice versa.
When J is set high, (x) goes low just as
soon as CLK goes high. That causes Q to go
to logical “1”.
With K in its normally low state, (y) will
be high, so Q̄ now goes low. Since Q̄ is fed
back to the Q clocking gate, (x) then goes
high, latching Q at logical “1”.
This all happens instantly, restrained only
by the switching times of the gates, with the
result that the circuit changes state and
latches just as soon as the CLK signal
crosses the switching threshold of the three-
input clocking gates — on the positive-
going transition, or edge, of the CLK signal,
in other words. Hence, the J-K flip-flop acts
like an edge-triggered bi-stable.
The J-K flip-flop is the most widely used,
but there is another popular version …
The D-Type Flip-Flop
Nobody seems to know who originally
designed the type D flip-flop; it might have
been Montgomery “Monty” Phister, a highly
talented computer engineer at Hughes
Aircraft in Glendale, California. The “D”
apparently stands for the circuits single
“Data” input …
 This configuration solves the problem of
an indeterminate state resulting if S and R
should somehow wind up at the same logic
level in a rather obvious way — by deriving
the R input by inverting the S input — which
in this case is called the D (or Data) input.
The D-type flip-flop, sometimes also
called a data latch, is also an active-high
edge-triggered circuit.
With D high, (R) will be low, and (y) will
therefore be at logical “1”. When CLK goes
high, (x) will go low, and Q will go to
logical “1”.
This forces Q̄ to go low which, in turn,
latches Q in the logical “1” state. All this
occurs very rapidly as the leading edge of
the positive-going CLK input crosses the
switching threshold of the gate, with the Q
output latched by the time it reaches its peak
positive level. Hence, the circuit is also
obviously edge-triggered.
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There are other types of flip-flops, and
other versions of these two most-popular
designs. Our interest in bi-stables at this
point arises from the fact that they are used
to make the various kinds of monolithic
binary counters, which we’ll soon be talking
about.
Multivibrators
Speaking of clock pulses, you might
wonder where they come from. The first
known mention of the multivibrator circuit
was in a publication of the French Ministry
of War, written by physicists Henri
Abraham and Eugene Bloch in 1918, so it is
assumed that they were its inventers. Both
died in the Auschwitz concentration camp
during WW-II.
As late as 1958, a common method of
converting DC to AC in portable equipment,
such as automobile radios or aircraft
equipment, was the vibrator — a device that
operated like a buzzer, but with a contact
armature that alternated back and forth
between two stationary contacts, one
connected to whatever the DC voltage was,
and the other to ground. This provided a
pulsating DC output from the vibrating
armature, and that was passed through a
transformer to provide a floating AC
voltage. Believe it or not, even the B-52
bombers and KC-135 tankers that I worked
on had one of these very low-tech devices
onboard … in the ARN-14 Omni-Range
Radio receiver, now more commonly known
as a VOR (visual omni-range) system.
I’m assuming that’s why Abraham and
Bloch called their circuit a vibrator. The
“multi” part was probably due to the fact
that it could be configured to act as a
monostable, bi-stable, or astable pulse
generator.
When I went through tech school, the
multivibrator was sort of a big deal. I can’t
remember exactly why, except that there
were several different versions of the circuit,
all of which used vacuum tubes. It all
seemed very complicated.
Nowadays, it’s just a piece of cake. It’s so
easy to generate square-wave signals and
pulse waveforms with simple logic circuits
or monolithic ICs designed for that purpose,
that the term “multivibrator” is actually
obsolete, these newer schemes not having
much in common with what Abraham and
Bloch described about 100-years ago.
 Here’s what is perhaps the most modern
version of their circuit …

The circuit depends on slight component

imbalances to make sure that it starts up. For
example, assume that Q1 switches on first.
That connects capacitor C1 to ground (0V)
which ensures that Q2 cannot turn on.
The capacitor C1 begins to charge up
through resistor R2, and when it reaches
about 0.7V, Q2 will begin to turn on. How
long that takes is established by the values
chosen for C1 and R2.
When Q2 turns on, the voltage drop across
capacitor C2 will be about zero, so the base
of Q1 is then essentially grounded, and it
turns off … until the charge on C2 begins to
exceed the base turn-on voltage of Q1
(probably about 0.7V) and that transistor
begins to conduct again.
So you can see that this sequencing will go
on forever — that this is an astable
multivibrator. If the values on either side of
the circuit are balanced, the output will be a
continuous square wave, and may be taken
from either collector.
For clocking purposes, it might be
desirable to have short-duration CLK pluses,
with long-duration intervals. That’s easily
accomplished by just varying the RC values
to provide a short time constant on one side
of the circuit, and a long time constant on
the other, then taking the output from the
side with the shorter time constant.
The square wave output otherwise looks
like this; please notice the terminology.
 So much for the antiquated multivibrator
approach.
There are now many better ways to
generate CLK signals. In the interest of
brevity, here’s the simplest …

Life doesn’t get much easier than this! The

CD40106B is a CMOS inverter with a
Schmitt-type input. That means that the
switching points for positive-going and
negative-going inputs are different. They’re
called the upper trip point (UTP or VTH+)
and the lower trip point (LTP or VTH−), and
the difference between them is called
hysteresis (VH). With a 5-volt supply, VH
will be about 1-volt, with VTH+≈3Vand
VTH−≈2V.
What’s the purpose of this scheme?
 Logic gates normally have a single
switching threshold for positive-going and
negative-going inputs. That’s fine for input
pulses with sharp leading and lagging edges.
For more slowly changing inputs, these
circuits are likely to go into a linear mode
momentarily as the input leisurely crosses
through the threshold, or momentarily
switch erratically between their output
extremes if the input is a little noisy.
NANDs, NORs and NOTs (inverters) are
also available with Schmitt inputs, which
provides a means of accommodating slowly
changing or noisy inputs.
In the “for what it’s worth” department,
this scheme was originally devised in 1934
as part of a circuit called a Schmitt trigger,
invented by American inventor, engineer
and biophysicist Otto H Schmitt, hence the
nomenclature.
Getting back to our simple oscillator with
a Schmitt input, once the leading edge of the
input exceeds VTH+, the gate switches to
logical “0”, which causes the switching
threshold to drop down to VTH−, thus
ensuring a clean, single output transition.
For falling input transitions, the opposite
occurs.
The capacitor C charges and discharges
between these two levels, causing the output
to alternately swing between 5V and ground
(actually about 4.95V and 0.05V).
The duration of the output is …
−
=
−
The term “ln” means “natural logarithm”.
In other words, the duration is equal to the
product of R and C and the natural logarithm
of the parenthetic expression. We don’t need
to get into a discussion about logarithms,
common and natural, because our handy
calculator’s “Ln” function will provide the
necessary conversion at the click of a button.
 Let’s assume a situation where VCC is 5V,
VTH+ is 3V and VTH− is 2V. What if R is 47K
and C is 0.001µF? The square wave
frequency can be calculated as follows …
3 5−2
= = ×2.25
2 5−3
Using the calculator, enter 2.25 and click
the “Ln” button to find the natural logarithm
of 2.25, which is 0.81093. So …
= 47 ×0.001 ×0.81093
= 38.113
Since the signal’s frequency is calculated
simply as the reciprocal of its period …
1
= = 26.237
38.113
This is a very easy solution for
applications not requiring a great deal of
precision and stability. Otherwise, the
Pierce-gate oscillator is more often
employed.
 This scheme is attributed to George W
Pierce, who grew up in Texas working on
his father’s cattle ranch, to become a physics
professor at Harvard University. He patented
the idea in 1923.
With the development of monolithic
microcontrollers and microprocessors, this
became the standard method of generating
clock signals, because of its very low cost
and outstanding frequency stability.
The part of the circuit that’s enclosed in
the dashed box is typically built into the
chip. System designers may then select a
crystal resonator to provide the clocking
frequency of their choice. The recommended
size of the capacitors Ca and Cb are specified
by the manufacturer of the crystal, and the
value of RS is whatever matches the XC of
capacitor Cb at the resonate frequency.
The inverter part of the circuit is usually a
simple unbuffered CMOS inverter, as
opposed to the buffered types in general
purpose gates. The feedback resistor, RFB,
causes the inverter to operate in the linear
mode, rather than as a switch, with its output
and input settling at about half of whatever
the supply voltage is.
The crystal with its two small capacitors
forms a highly selective pi-type filter, with
the crystal acting like an inductor at the
resonant frequency. This provides a phase
shift of about 180-degrees which, when
added to the 180-degree phase shift at the
inverter/amplifier, guarantees sustained
oscillation.
 The function of the series resistor, RS, is
mainly to help prevent spurious high-
frequency oscillations, and to isolate the
output of the inverter from the crystal
network in order to provide a clean, well-
formed square wave output.
Fairchild Semiconductor published a very
nice application note dealing with this
circuit in 1983. If you’d like to delve deeper
into the details with a discussion that’s not
over the top with engineering-speak, their
AN-340 is available in the resources section
of the course.
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We’ve already seen what a ripple counter
looks like, perhaps a bit prematurely. Before
going any further in that direction, we need
to talk about the various systems of binary
numbers used in digital electronics.
That’s the subject of the next lecture.
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