PRACTICAL LOW POWER

DIGITAL VLSI DESIGN

PRACTICAL LOW POWER
DIGITAL VLSI DESIGN

by

Gary Yeap
Motorola

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

ISBN 978-1-4613-7778-8 ISBN 978-1-4615-6065-4 (eBook)
DOI 10.1007/978-1-4615-6065-4

Library of Congress Cataloging-in-Publication Data

A C.I.P. Catalogue record for this book is available

from the Library of Congress.

Copyright © 1998 by Springer Science+Business Media New York

Originally published by Kluwer Academic Publishers in 1998
Softcover reprint of the hardcover 1st edition 1998
AII rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo-
copying, record ing, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC.

Printed an acid-free paper.

 Preface

Low power VLSI design has been a subject of interest in recent years as evident from
the surge of related activities in the engineering and research community. The topic
has been very much left isolated since the invention of integrated circuits. For long, it
was only practiced by a few elite designers in specific areas such as medical elec-
tronic implant. It is not until the proliferation of portable consumer electronics that
the low power challenges emerge in the mass market digital design. Besides the busi-
ness demand, the evolution of semiconductor process technology has led to the steady
increase in per chip power consumption. For someone who was once an electronic
hobbyist like me, the declaration that some commercial microprocessor power dissi-
pation is more than that of a hand held soldering iron certainly wakens the memories
of blistered finger burnt. With the Moore's Law showing no signs of deceleration, the
power consumption of a VLSI chip is expected to rise beyond the current status. Last
but not least, the environmental concerns about the energy consumption of office
computing equipment have also fueled the low power needs on the techno-political
front.
This book was written for VLSI design engineers and students who have had a funda-
mental knowledge in CMOS digital design. Part of the contents of this book was con-
ceived when I developed a company wide training class "Tutorial on Low Power
Digital VLSI Design" for designers in Motorola. The feedback from the tutorial
attendees helps to establish the themes and tone of this book. This book covers the
practical low power design techniques and their analysis method at various levels of
design abstraction. There is no universal technique that can solve the power dissipa-

v
Preface

tion problem in all application areas. It is also my observation that power efficiency
cannot be achieved without affecting the other figures of merits of the design. This
book emphasizes the optimization and trade-off techniques that involve power dissi-
pation, in the hope that the readers are better prepared the next time they are presented
with a low power design problem. It does not document particular results collected
from some low power design projects. Rather, it highlights the basic principles, meth-
odologies and techniques that are common to most CMOS digital designs. The advan-
tages and disadvantages of a particular low power technique will be discussed.
Besides the classical area-performance trade-off, the impact to design cycle time,
complexity, risk, testability, reusability will be discussed. The wide impacts to all
aspects of design are what make the low power problems challenging and interesting.
Heavy emphasis will be given to top-down structured design style with occasion cov-
erage in the semicustom design methodology. The examples and design techniques
cited have been known to be applied to production scale designs or laboratory set-
tings. The goal is to permit the readers to practice the low power techniques using
current generation design style and process technology.
Today, the VLSI design task is so huge that specialization is a must. As a result, most
designers are experienced in their corresponding focused areas. However, the low
power problem is one that calls for total solution at all levels of design abstraction to
achieve the highest impact. A design decision made at one level of abstraction can
hamper or aid the low power goal in the downstream design process. A breadth of
knowledge from all aspects of the design from specification to mass production is
required. Hopefully, this book can provide a comprehensive coverage in all areas of
the digital design domain. Some analysis techniques have been so mature that com-
mercial Computer-Aided Design software packages have routinely been used in the
design process. This book will illuminate the application and the potential role of the
software in solving low power problems.
The book is intended to cover wide ranges of design abstraction levels spanning cir-
cuit, logic, architecture and system. The art of chip design demands solid intuition,
skill and experience. If the craftsmanship of chip design can be acquired through hard
work, I believe the basic drill is in the qualitative and quantitative analysis at the vari-
ous levels of design abstraction. The first three chapters provide enough basic knowl-
edge to cover the qualitative and quantitative analysis at the different design
abstraction levels. It is recommended that Chapter 1 thorough 3 be read, in succes-
sion, before the later chapters. Subsequent chapters present the low power techniques
at the circuit, logic, architecture and system levels. Chapter 6 includes special tech-
niques that are specific to some key areas of digital chip design. The last chapter pro-
vides a glimpse of the low power techniques appearing on the horizon.

vi
Preface

I would like to thank Prof. Majid Sarrafzadeh of Northwestern University for his
encouragement and support during the writing of this book. I would also like to
express my sincere gratitude to my friends and colleagues who helped to review the
manuscript of this book: Dr. Chih-Tung Chen, Dr. Jenny Gong, Dr. Weiliang Lin,
Alberto Reyes, Hongyu Xie.

Gary K. Yeap, Ph.D.

Gilbert, Arizona

vii
 Contents

Preface .............................................................................. v

Contents .......................................................................... ix

1 Introduction ................................................................... 1
1.1 Needs for Low Power VLSI Chips ................................................................ 2
1.2 Charging and Discharging Capacitance .........................................................4
1.3 Short-circuit Current in CMOS Circuit.. ........................................................ 8
1.3.1 Short-circuit Current of an Inverter .................................................... 8
1.3.2 Short-circuit Current Variation with Output Load ............................ l0
1.3.3 Short-circuit Current Variation with Input Signal Slope .................. 13
1.4 CMOS Leakage Current ............................................................................... 15
1.4.1 Reverse Biased PN-junction ............................................................. 15
1.4.2 Subthreshold Channel Leakage ........................................................ 16
1.4.3 Leakage Current in Digital Design ................................................... 19
1.5 Static Current ................................................................................................ 19
1.6 Basic Principles of Low Power Design ........................................................20
1.6.1 Reduce Switching Voltage ................................................................ 21

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Contents

1.6.2 Reduce Capacitance .......................................................................... 21

1.6.3 Reduce Switching Frequency ........................................................... 22
1.6.4 Reduce Leakage and Static Current .................................................. 22
1.7 Low Power Figure of Merits ........................................................................ 23

2 Simulation Power Analysis ......................................... 27

2.1 SPICE Circuit Simulation ............................................................................ 29
2.1.1 SPICE Basics .................................................................................... 29
2.1.2 SPICE Power Analysis .................................................................... .30
2.2 Discrete Transistor Modeling and Analysis ................................................. 31
2.2.1 Tabular Transistor Model ................................................................. .31
2.2.2 Switch Level Analysis ..................................................................... .32
2.3 Gate-level Logic Simulation ........................................................................ 33
2.3.1 Basics of Gate-level Analysis ........................................................... 33
2.3.2 Capaciti ve Power Dissipation ........................................................... 34
2.3.3 Internal Switching Energy ................................................................ 35
2.3.4 Static State Power ............................................................................. 36
2.3.5 Gate-level Capacitance Estimation ................................................... 37
2.3.6 Gate-level Power Analysis ............................................................... .39
2.4 Architecture-level Analysis ......................................................................... .40
2.4.1 Power Models Based on Activities .................................................. .41
2.4.2 Power Model Based on Component Operations .............................. .42
2.4.3 Abstract Statistical Power Models ....................................................43
2.5 Data Correlation Analysis in DSP Systems ................................................ .44
2.5.1 Dual Bit Type Signal Model ............................................................ .45
2.5.2 Datapath Module Characterization and Power Analysis ..................46
2.6 Monte Carlo Simulation ............................................................................... 50
2.6.1 Statistical Estimation of Mean .......................................................... 51
2.6.2 Monte Carlo Power Simulation ........................................................ 54

3 Probabilistic Power Analysis ...................................... 59

3.1 Random Logic Signals .................................................................................60
3.1.1 Characterization of Logic Signals .....................................................60
3.1.2 Continuous and Discrete Random Signals ....................................... 62

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3.2 Probability and Frequency ...........................................................................62

3.2.1 Static Probability and Frequency ......................................................63
3.2.2 Conditional Probability and Frequency ............................................ 65
3.2.3 Word-level and Bit-level Statistics ................................................... 67
3.3 Probabilistic Power Analysis Techniques .................................................... 69
3.3.1 Propagation of Static Probability in Logic Circuits ..........................70
3.3.2 Transition Density Signal Model ......................................................72
3.3.3 Propagation of Transition Density ....................................................72
3.3.4 Gate Level Power Analysis Using Transition Density ..................... 75
3.4 Signal Entropy .............................................................................................. 77
3.4.1 Basics of Entropy ..............................................................................77
3.4.2 Power Estimation Using Entropy .....................................................78

4 Circuit .......................................................................... 85
4.1 Transistor and Gate Sizing ........................................................................... 86
4.1.1 Sizing an Inverter Chain ................................................................... 87
4.1.2 Transistor and Gate Sizing for Dynamic Power Reduction .............. 90
4.1.3 Transistor Sizing for Leakage Power Reduction .............................. 91
4.2 Equivalent Pin Ordering ............................................................................... 92
4.3 Network Restructuring and Reorganization .................................................95
4.3.1 Transistor Network Restructuring ..................................................... 95
4.3.2 Transistor Network Partitioning and Reorganization ....................... 97
4.4 Special Latches and Flip-flops ..................................................................... 99
4.4.1 Flip-Flop and Latch Circuits ........................................................... 100
4.4.2 Self-gating Flip-flop ........................................................................ l02
4.4.3 Combinational Flip-flop .................................................................. l04
4.4.4 Double Edge Triggered Flip-flop .................................................... 104
4.5 Low Power Digital Cell Library ................................................................. 107
4.5.1 Cell Sizes and Spacing .................................................................... 107
4.5.2 Varieties of Boolean Functions ....................................................... 108
4.6 Adjustable Device Threshold Voltage ........................................................ 110

5 Logic ........................................................................... 117

5.1 Gate Reorganization ................................................................................... 118

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5.1.1 Local Restructuring ........................................................................ 118

5.2 Signal Gating .............................................................................................. 120
5.3 Logic Encoding .......................................................................................... 121
5.3.1 Binary versus Gray Code Counting ................................................ 121
5.3.2 Bus Invert Encoding ....................................................................... 123
5.4 State Machine Encoding ............................................................................. 126
5.4.1 Transition Analysis of State Encoding ........................................... 127
5.4.2 Output Don't-care Encoding ........................................................... 129
5.4.3 Design Trade-offs in State Machine Encoding ............................... 129
5.5 Precomputation Logic ................................................................................ 130
5.5.1 Basics of Precomputation Logic ..................................................... 130
5.5.2 Precomputation Condition .............................................................. 132
5.5.3 Alternate Precomputation Architectures ......................................... 134
5.5.4 Design Issues in Precomputation Logic Technique ........................ 134

6 Special Techniques .................................................... 139

6.1 Power Reduction in Clock Networks ......................................................... 139
6.1.1 Clock Gating ................................................................................... 140
6.1.2 Reduced Swing Clock ..................................................................... 141
6.1.3 Oscillator Circuit for Clock Generation .......................................... 144
6.1.4 Frequency Division and Multiplication .......................................... 145
6.1.5 Other Clock Power Reduction Techniques ..................................... 145
6.2 CMOS Floating Node ................................................................................. 146
6.2.1 Tristate Keeper Circuit.. .................................................................. 146
6.2.2 Blocking Gate ................................................................................. 147
6.3 Low Power Bus .......................................................................................... 148
6.3.1 Low Swing Bus ............................................................................... 148
6.3.2 Charge Recycling Bus .................................................................... 151
6.4 Delay Balancing ......................................................................................... 155
6.5 Low Power Techniques for SRAM ............................................................ 158
6.5.1 SRAM Cell ..................................................................................... 159
6.5.2 Memory Bank Partitioning ............................................................. 160
6.5.3 Pulsed Wordline and Reduced BitIine Swing ................................. 160
6.5.4 Case Study: Design of an FIFO Buffer ........................................... 162

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7 Architecture and System .......................................... 167

7.1 Power and Perfonnance Management........................................................ 168
7.1.1 Microprocessor Sleep Modes .......................................................... 168
7.1.2 Perfonnance Management .............................................................. 169
7.1.3 Adaptive Filtering ........................................................................... 171
7.2 Switching Activity Reduction .................................................................... 175
7.2.1 Guarded Evaluation ........................................................................ 175
7.2.2 Bus Multiplexing ............................................................................ 176
7.2.3 Glitch Reduction by Pipelining ...................................................... 177
7.3 Parallel Architecture with Voltage Reduction ............................................ 178
7.4 Flow Graph Transfonnation ....................................................................... 181
7.4.1 Operator Reduction ......................................................................... 182
7.4.2 Loop Unrolling ............................................................................... 185

8 Advanced Techniques ............................................... 189

8.1 Adiabatic Computation .............................................................................. 190
8.1.1 Complementary Adiabatic Logic .................................................... 190
8.1.2 Power Efficiency of Adiabatic Logic .............................................. 192
8.2 Pass Transistor Logic Synthesis ................................................................. 196
8.2.1 Basics of Pass Transistor Logic ...................................................... 197
8.2.2 Boolean Decision Diagram and Pass Transistor Logic ................... 198
8.2.3 Pass Transistor Logic Synthesis System .........................................201
8.3 Asynchronous Circuits ............................................................................... 202
8.3.1 Asynchronous System Basics ......................................................... 203
8.3.2 Prospects of Asynchronous Computation .......................................205

Index ............................................................................. 209

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