The F-LDPC Family: High-Performance Flexible
Modern Codes for Flexible Radio
Thomas R. Halford, Metin Bayram, Cenk Kose
TrellisWare Technologies, Inc.
San Diego, CA, USA
{thalford,mbayram,ckose}@trellisware.com
Abstract—Flexibility is an increasingly important aspect of
radio modem design. In this paper, flexibility within the physical
(PHY) layer in general, and the forward error correction (FEC)
component in particular, is examined in detail. Following a
discussion of the need for flexible modern code designs that
exhibit universally good performance across a wide range of op-
erational scenarios (i.e., input block size, code rate, modulation),
TrellisWare Technologies, Inc.’s Flexible Low-Density Parity-
Check (F-LDPC) codes are offered as an example of a high-
performance modern coding solution for flexible radio designs.
Specifically, the F-LDPC family offers performance within 0.8 dB
of theoretical bounds across a wide range of operational scenarios
with a design that is especially amenable to low-complexity, high-
thoughput reconfigurable hardware implementation.
I. I NTRODUCTION
Flexibility, adaptability, and reconfigurability are three as-
pects of radio design receiving ever more attention from
industry, government, and the academe (cf., [1], and the
references therein). This focus comprises such technological
frameworks as software radio (SR) (cf., [2]), software defined
radio (SDR) (cf., [3]), reconfigurable radio (cf., [4]), and
cognitive/intelligent/smart radio (cf., [5]). European research
efforts in this field were reviewed in [6]. At a high level, a
flexible radio receiver is capable of processing signals defined
by a plurality of modes. These different modes may be defined
by distinct communication standards (e.g., the co-existence
of UMTS and WLAN receiver processing chains in a single
handset [7]), or within a single standard (e.g., the different
modulations and code rates used to define different modes in
the HiperLAN/2 standard). A flexible receiver may adaptively
choose a specific operating mode in order to, e.g., achieve
some quality of service (QoS) target (cf., [8]). Furthermore,
a receiver may be reconfigured in order to process some new
mode defined by, e.g., an over-the-air download (cf., [9]).
In this paper, a particular aspect of the flexible radio
concept is considered: flexibility in the FEC component of
the PHY-layer. Modern flexible receivers must support modes
corresponding a wide range of FEC operational scenarios. For
example, the efficient transmission of control packets typically
requires short block lengths, while the robust transmission
of data packets typically requires long block lengths and
code rates that adapt to changing channel conditions. A
conceptually simple solution to offering such flexibility is to
design a specific code for each mode, and to then implement
978-1-4244-2204-3/08/$25.00 ©2008 IEEE
Keith M. Chugg Andreas Polydoros
Univ. of Southern California Univ. of Athens
Los Angeles, CA, USA Athens, Greece
chugg@usc.edu polydoros@phys.uoa.gr
separate, mode-specific decoders (in software or software-
reconfigurable hardware). Such an approach is clearly inef-
ficient - and possibly intractable - from an implementation
complexity perspective. Furthermore, this approach is brittle
with respect to reconfigurability in that any future modes to be
supported by such a radio must employ one these pre-defined
codes. A more pragmatic approach is to choose a family of
codes that can be decoded by a single flexible architecture.
While some loss in performance with respect to specific point
designs is inevitably incurred by such a scheme, the gains
in implementation complexity, flexibility, adaptability, and
reconfigurability can vastly outstrip this performance penalty,
provided the code family is properly designed.
TrellisWare Technologies, Inc. (TWT) recently proposed a
family of codes that offer the flexibility, high-performance, and
high-throughput implementation architectures demanded by
modern flexible radio receivers [10]. The F-LDPC family of-
fers performance within 0.8 dB of theoretical bounds (cf., [11])
across a wide range of operational scenarios with a design
that is especially amenable to low-complexity, high-throughput
reconfigurable-hardware implementation. For example, TWT
has implemented F-LDPC decoders in field-programmable
gate arrays (FPGAs) - a core enabling technology for SDR
[12] - which achieve throughput at and beyond 1 Gbps with
full decoder convergence. Xilinx, Inc. featured such a decoder
in its booth at MILCOM’06 in Washington, DC. A high-speed
F-LDPC FPGA-based decoder was also featured at Altera
Corp.’s MILCOM’07 in Orlando, FL. Finally, TWT recently
announced the F-LDPC Chameleon ASIC encoder/decoder
which achieves 1 Gbps throughput.
This paper discusses the F-LDPC in the context of flexible
radio design and is organized as follows. Section II briefly re-
views modern codes and discusses existing popular designs in
the context of flexible radios. The design and performance of
the F-LDPC are discussed in Sections III and IV, respectively.
Concluding remarks are given in Section V.
II. F LEXIBLE M ODERN C ODES FOR F LEXIBLE R ADIOS
A. Review of Modern Codes
The introduction of turbo codes in 1993 [13] and the
subsequent rediscovery of Gallager’s low-density parity-check
(LDPC) codes [14], [15], revolutionalized coding theory and
practice. In the ensuing years, there has been an explosion
 Waterfall Region
Block / Bit Error Rate
Error Floor Region
Classical
Modern
Eb/No (dB)
Fig. 1. Typical error performance for modern and classical codes.
of interest in the design of such modern codes (in contrast to
classical codes such as Reed-Solomon (RS) and convolutional
codes [16]). Modern codes are characterized by the concate-
nation of two or more relatively simple codes separated by an
interleaver, combined with a decoding strategy that operates by
passing messages between decoders for the simple constituent
codes. To date, the most popular modern code designs include
parallel concatenated convolutional codes (PCCCs) [13], se-
rially concatenated convolutional codes (SCCCs) [17], turbo
product codes (TPCs) [18], and the large family of LDPC
codes that includes both unstructured LDPCs (e.g., Gallager’s
codes [14]), which are defined by optimizing the sparse parity-
check matrix that defines the code, and structured LDPCs
(e.g., repeat-accumulate codes [19]), which are designed in
a manner more akin to PCCCs and SCCCs.
Figure 1 illustrates typical error probability performance
curves for modern and classical codes. Observe that the perfor-
mance curve for the modern code is characterized by an initial
steep reduction in error probability as Eb /N0 is increased - the
waterfall region - followed by a region of shallower reduction
in the floor region. Performance is a function of the code’s
minimum distance and distance spectrum in the floor and
waterfall regions, respectively. Observe that the performance
curve for the classical code is characterized by a shallow
reduction in error probability throughout. Classical codes thus
operate in the floor (i.e., minimum distance dominated) region
for all Eb /N0 values. In terms of performance, it is the
presence of the waterfall region that distinguishes modern and
classical codes. The initial steep reduction at some Eb /N0
threshold allows systems employing modern codes to function
reliably at lower signal-to-noise ratios (SNRs).
From a performance perspective, the key challenge of
modern coding is the construction of codes which excel in
both the waterfall and floor regions for a given operational
scenario. This is particularly difficult as it is often observed
that floor and threshold performance can be improved at each
others expense. From an implementation complexity perspec-
tive, the key challenge of modern coding is the construction
of codes which afford low-complexity decoding algorithms
that are particularly amenable to high-throughput hardware
implementation. Practical modern code point designs must
consider both performance and implementation complexity.
B. Existing Code Designs: A Flexible Radio Perspective
While initially demonstrated for relatively low rates and
large input block sizes [13], modern codes have been shown
to be capable of near-optimal performance for nearly all
practical operational scenarios. However, no single design to-
date has offered the necessary flexibility and performance
required for practical flexible radio design. This situation
is mirrored when implementation is considered: while low-
complexity codes have been successfully design for specific
operational scenarios, no single design to-date has offered low-
complexity implementations across all operational scenarios
of practical interest. What has been lacking in modern coding
theory and practice is a single design that can simultaneously
offer excellent performance and low decoding complexities
across a wide range of operational scenarios. Before beginning
a discussion of a modern code family that does just this -
TWT’s F-LDPC - the prevelant existing modern code designs
are briefly viewed through the lens of flexible radio systems.
1) PCCCs: While offering good threshold performance,
practically realizable PCCCs tend to suffer from poor floor
performance. The block size of PCCCs can trivially be
changed by modifying the interleaver size; however, PCCCs
exhibit only modest code rate flexibility. Specifically, code
rate flexibility is achieved by puncturing the output of the
constituent codes. For very high code rates, the amount of
puncturing required results in degraded performance.
2) SCCCs: The threshold performance of SCCCs are worse
than PCCCs (typically by ∼ 0.3 dB), but they exhibit among
the best floors of all modern code designs. For similar reasons
to PCCCs, SCCCs exhibit good block size but poor code rate
flexibility. However, block size and code rate flexibility are
coupled in SCCCs which can complicate reconfigurability.
3) TPCs: TPCs have the worst threshold performance
among all modern code designs (except for very high code
rates and very large block sizes), and floor performance that is
a compromise between PCCCs and SCCCs. Since the overall
rate and block size of a TPC is determined by its constituent
codes, arbitrary rates and block sizes cannot be supported.
4) Unstructured LDPCs: Although LDPCs have been re-
ported with threshold performance within a tiny fraction of a
dB of theoretical limits (e.g., [20]), practically implementable
LDPC codes have thresholds that are typically comparable to
PCCCs. Many unstructured LDPCs are prone to early flooring
due to non minimum-distance error events. Most importantly,
unstructured LDPCs exhibit poor flexibility. Block size flexi-
bility can only be achieved by changing the matrix that defines
the code. While some rate flexibility can be achieved via
puncturing, the code that results from a puncturing a good
low-rate design does not generally a good high-rate code.
III. T HE F-LDPC FAMILY
In light of the above discussion, a modern code design
should be sought that exhibits the threshold performance and
block size flexibility of PCCCs, floor performance similar to
that of SCCCs, the low implementation complexity of LDPCs,
and a rate flexibility exceeding all existing popular designs.
To this end, a number of authors have studied structured
LDPCs, e.g., protograph (cf., [21]) and generalized repeat-
accumulate1 (GRA) codes [19]. The F-LDPC constitutes an
especially flexible structured LDPC design that is particularly
amenable to high-throuput hardware implementation.
A. Encoder Structure
IPG = Punctured Accumulator
Example 2-state Ir-S-SCP
b P/S dj P = kQ/J p
i parity bits m
1+D = I 1/(1+D) J:1
Puncture
Q(i)
k systematic bits bi
Fig. 2. F-LDPC encoder structure.
Figure 2 illustrates an encoder for a typical member of
the F-LDPC family. A block of K input bits feeds an outer
code, the output of which is interleaved and then fed to an
inner parity generator (IPG), which generates a parity bit
stream. The parity bit stream is then transmitted along with the
systematic bit stream so that the resulting code is systematic.
The outer code is formed by the serial concatenation of a
2-state convolutional code (1 + D) and a repetition code
(=). Observe that the ith output of this convolutional code
is repeated Q(i) times. The IPG comprises an accumulator
(1/(1 + D)) followed by a J : 1 puncture. This inner block
is denoted an IPG rather than an inner code to highlight the
fact that the IPG produces 1 output bit for every J inputs and
thus has rate greater than unity. The input and output block
sizes of the F-LDPC are K and K(1 + Q̄(i)/J), respectively
(where Q̄(i) is the average value of Q(i)). If Q(i) is constant
over all i, then the resulting F-LDPC code is regular. Irregular
variants of the F-LDPC are formed by varying Q(i) over i. The
standard regular F-LDPC uses Q = 2 and thus has a (coarse)
J
code rate that depends only on J: Rc = J+2 . Rate refinement
can be achieved by further periodic puncturing of the parity
bits. When a fraction p of the parity bits are transmitted, the
J
refined code rate is Rp = J+2p . with decreasing input block size.
B. Flexibility Without Sacrificing Throughput
That the F-LDPC code family does not sacrifice perfor-
mance for flexibility will be detailed in Section IV. In this
section, the decoding complexity of the F-LDPC is highlighted
in the context of input block size and code rate flexibility. A
deeper discussion of hardware architectures for the F-LDPC
family can be found in [23], [10], [22].
TWT utilizes segment-based techniques (cf., [24]) for pro-
cessing the constituent inner and outer code trellises thus
enabling parallel architectures that achieve very high through-
puts. As the degree of parallelism employed becomes large,
1 Indeed, the design of the F-LDPC is closely related to that of GRA codes.
As discussed in detail in [10] and [22], the main advantage of F-LDPC codes
over GRA codes lies in implementation complexity. For example, a GRA code
with the same performance as a regular Q = 2 F-LDPC typically requires
33%-50% more memory and suffers a 25% penalty in decoder throughput.
memory design and routing become the primal challenge. To
this end, dithered relative-prime (DRP) interleavers [25] are
used to ensure low-overhead addressing and contention-free
memory access. The interleaver length of a Q = 2 regular
F-LDPC code is simply 2K and, therefore, depends only on
the input block size. Since DRP interleavers are compactly
described by a small parameter set - rather than storing the
entire permuation - interleavers corresponding to an enormous
range of block sizes (e.g., 32 bits - 16K) can be implemented
efficiently on a single chip.2 Finally, as will be seen in Section
IV, the F-LDPC offers unparalleled code rate flexibility. Since
rate flexibility for regular designs is achieved via puncturing,
overall hardware throughput is minimally affected. Note that
the design of rate compatible Q(i) distributions for efficient
irregular F-LDPC decoder architectures was discussed in [22].
IV. F-LDPC P ERFORMANCE E XAMPLES
A. Flexibility Across Rate and Block Length
In this section, the uniformly good performance of the
regular (Q = 2) F-LDPC family is demonstrated across a
wide range of rates, block lengths, and modulations on the
additive white Gaussian noise channel (AWGNC). The specific
F-LDPC modes studied in this section were initially proposed
as a potential coding solution for 802.11n MIMO systems
[23]. Input block sizes from 3-1024 bytes in single byte
increments are considered. Five coarse rates of Rc = 1/2,
2/3, 4/5, 8/9, and 16/17 are considered along with 8 fine
rates using p = 16/16, 15/16, . . . , 9/16, for a total of 40
overall codes rates from Rp = 1/2 to 32/33. Finally, 5 Gray-
mapped modulations are supported: BPSK, QPSK, 16QAM,
64QAM, and 256QAM. Figure 3 illustrates packet error rate
(PER) versus receiver SNR curves for a range of code rates and
modulation orders using min-sum decoding. Observe that a 1%
PER can be achieved from −2 dB to 27 dB SNR in increments
of approximately 0.25 dB by varying the rate and modulation.
Figure 4 illustrates PER vs. SNR curves for a range of input
block block sizes (8 to 1000 bytes) with fixed rate (4/5) and
modulation (16QAM). As expected, the performance degrades
B. F-LDPC Performance for Short Block Sizes
It is now well-known that modern codes offer excellent
performance with respect to classical codes when input block
sizes are long. However, many modern code designs perform
poorly at short block lengths and there remains a considerable
gap between the performance of these codes and theoretical
limits. In order to demonstrate the efficacy of the F-LDPC for
short block lengths, Figure 5 compares the performance of the
binary image of a rate 1/3 RS code with input block size 126
bits to that of a similar irregular F-LDPC with Q̄(i) = 4.
The RS code is decoded using classical hard-in algebraic
techniques (cf., [26]). The performance of this F-LDPC code is
strictly better than that of the CCSDS turbo code with identical
2 Note that similar block length flexibility can be achieved for PCCC and
SCCC designs by using DRP interleavers.
 1
F-LDPC
10-1
Reed-Solomon

10-2

0.1

Bit Error Rate

PER

10-3

0.01
10-4

10-5

0.001
0 5 10 15 20 25 30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SNR (dB) Eb/No (dB)

Fig. 3. Flexibility in rate and modulation of the F-LDPC. The rates and Fig. 5. Performance comparison of K = 126 bit, R = 1/3 F-LDPC and
modulations range from R=1/2 BPSK (left) to R=32/33 256QAM (right). Reed-Solomon codes. Fifteen F-LDPC decoding iterations were performed.

1
100

10-1

10-2

0.1 10-3

10-4

Block/Bit Error Rate

PER

10-5

10-6

0.01
10-7

10-8

1000 bytes 8 bytes 10-9

Frame Size

0.001 10-10 Block Error Rate

10.5 11 11.5 12 12.5 13 13.5 14 Bit Error Rate

0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
SNR (dB)
Eb/No (dB)

Fig. 4. Flexibility in block length of the F-LDPC. All curves correspond to Fig. 6. Hardware performance of a K = 4096 bit, R = 1/2 regular
rate R=4/5, 16QAM-modulated codes. F-LDPC. Twelve F-LDPC decoding iterations were performed.

parameters and approximately 0.8 dB from the sphere packing 4096, regular rate 1/2 F-LDPC on the AWGNC with BPSK
bound (as extrapolated from curves in [11]). Observe that at modulation. These curves were produced via hardware simu-
this low rate and short block length, the F-LDPC outperforms lation in order to simulate such low error rates with statistical
the RS code by approximately 4.5 dB. Some of this difference confidence. Observe that no error flooring was observed to
can be accounted for by the fact that the RS decoder employing occur at a bit error rate (BER) of 10−10 . When complexity is
a hard-in algorithm that discards available soft information considered, the performance of this particular F-LDPC code
from the channel. Soft algebraic (e.g., [27]) and novel iterative compares favorably to highly optimized point designs that
(e.g., [28]) decoding algorithms can improve performance by have been reported in the literature. In particular, Divsalar
1-2 dB; however, the complexity of these algorithms vastly and Jones reported performance results of a protograph-based
outstrip that of decoding the F-LDPC. code with the same parameters that also does not floor by
10−10 BER and noted that the threshold of their code, which
C. Comparisons to Optimized Point Designs
is approximately 0.25 dB better that this regular F-LDPC
A flexible code design generally incurs some performance code,3 outperforms those of the best known unstructured
penalty with repsect to a highly optimized point solution. irregular LDPC codes [21]. The protograph used to construct
While the F-LDPC family is no exception to this trend, it this code, however, contains degree-6 repetition constraints in
is remarkable in that this loss is minimal and can be traded- contrast to the degree-3 constraints used to define the regualr
off favorably with flexibility. For example, maximally flexible F-LDPC. As detailed in [22], the use of such high-degree
regular F-LDPC codes typically perform within 0.3 dB of the repetition constraints can impede the design of high-speed
best point designs over a wide range of operational scenarios. decoder architectures (e.g., Gbps and higher throughput) for
This gap can be closed with a modest reduction in flexibility such codes. Furthermore, the irregular profile used to define
via irregular design. For high rates and small block sizes, the
F-LDPC provides the best performance known to the authors. 3 Note that this 0.25 dB threshold gap can be readily closed by careful
Figure 6 illustrates the performance of an input block size construction of an irregular F-LDPC.
the protograph code results in increased decoder complexity.
Figure 7 compares the performance of four K = 1944
codes drawn from the 802.11n standard with F-LDPC codes
of identical input block size and rate. For each rate (1/2, 2/3,
3/4, and 5/6), the performance of the F-LDPC is compared
to the of the corresponding 802.11n code at convergence
(50 iterations) and with a practical number of iterations (7
for the rate 5/6 802.11n code, 10 for the other 802.11n
codes, and 12 for the F-LDPC codes).4 The F-LDPC codes
considered in this example lose at most 0.25 dB compared to
the 802.11n codes. Note that each 802.11n code constitutes
a highly optimized point design that was designed without
respect to implementation compatibility with the other modes.
Note also that the 802.11n codes have been optimized for
performance using infinite precision sum-product decoding
(shown in Figure 7). When a more realistic decoding archi-
tecture is used (e.g., fixed-point scaled min-sum decoding),
the F-LDPC codes, whose interleavers are optimized for such
operation, the performance gap is less pronounced.
r=2/3
1e0
1e-1
Block Error Rate
1e-2
r=1/2
1e-3 F-LDPC (50)
F-LDPC (12)
802.11n (50)
802.11n (7-10)
0.25 0.50 0.75 1.00 1.25 1.50
Fig. 7. Comparison of F-LDPC and 802.11n standard codes.
V. C ONCLUSION
Flexible codes designs offering excellent performance and
high throughput are a key component of future flexible ra-
dio designs. This paper highlighted TrellisWare Technolo-
gies Inc.’s Flexible Low-Density Parity-Check (F-LDPC) code
family and demonstrated that it indeed exhibits the crucial
performance and low-complexity decoding architectures re-
quired for use in flexible, adaptable, and reconfigurable radios.
TWT supplies ASIC and FPGA F-LDPC encoder/decoder
cores - both off-the-shelf and tailored to specific application
requirements (e.g., higher throughput, lower complexity, better
threshold performance, lower floors, and greater flexibility).
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