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I express my heartfelt gratitude to Almighty the supreme guide for bestowing his blessings in my
entire endeavour.

I am deeply grateful to c , Head of the Department, Applied Electronics and
Instrumentation, M.E.S College of Engineering, Kuttipuram for his support and encouragement in
carrying out this seminar and also the facilities provided to me.

I am deeply indebted to my Seminar Guide,

 c Lecturer, Department of AEI and
Seminar Coordinator,
c  c Lecturer in AEI, M.E.S College Of Engineering, Kuttippuram
and
c  Lecturer in AEI, M.E.S College Of Engineering, Kuttippuram for their
guidance and support in realizing this seminar without their valuable advice and whole-hearted
cooperation, this seminar would not have seen the light of the day.

I express my sincere gratitude to all the faculty of the Department of AEI for their valuable advice and
their encouragement.

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The ability to monitor the simultaneous electrical activity of multiple neurons in the brain
enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature
multi-electrode neural recording arrays with integrated electronics have revealed significant
circuit design challenges. Weak neural signals must be amplified and filtered using low-noise
circuits placed close to the electrodes themselves, but power dissipation must strictly be
limited to prevent tissue damage due to local heating. In modern recording systems with 100
or more electrodes, raw data rates of 15 Mb/s or more are easily produced. Micropower
wireless telemetry circuits cannot transmit information at such high rates, so data reduction
must be performed in the implanted device. This paper explains about the integrated circuits
and design techniques that address the twin problems of neural signal amplification and data
reduction for this severely size- and power-limited application.

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ccTITLE PAGE NO

CERTIFICATE I

ACKNOWLEDGEMENTS II

ABSTRACT III
CONTENTS IV

1. INTRODUCTION 1

2. NEURAL SIGNALS 3

3. NEURAL SIGNAL AMPLIFICATION 6

3.1 DESIGN REQUIREMENTS 6

3.2 ARCHITECTURE AND DESIGN OF CIRCUIT 7

3.3 SIGNAL DIGITIZATION 11

4. NEURAL SPIKE DETECTION 14

4.1 DESIGN AND IMPLEMENTATION OF CIRCUIT 16

4.2 CIRCUIT TESTING 17

5. LOCAL FIELD POTENTIAL ENERGY DETECTION 19

5.1 LFP ENERGY DETECTION ALGORITHM 19

5.2 CIRCUIT DESIGN AND IMPLEMENTATION 20

5.3 CIRCUIT TESTING 21

6. CONCLUSION 22

BIBLIOGRAPHY 23

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DEPT OF AEI V MESCE KUTTIPPURAM