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TPS2120, TPS2121
SLVSEA3 – AUGUST 2018

TPS212x 2.8-V to 22-V Priority Power MUX with Seamless Switchover


1 Features 3 Description

1 Wide Operating Range: 2.8 V to 22 V The TPS212x devices are Dual-Input, Single-Output
(DISO) Power Multiplexer (MUX) that are well suited
• Low RON Resistance: for a variety of systems having multiple power
– TPS2120: 62 mΩ (Typical) sources. The devices will Automatically Detect,
– TPS2121: 56 mΩ (Typical) Select, and Seamlessly Transition between available
inputs.
• Adjustable Overvoltage Supervisor (OVx): ±5%
• Adjustable Priority Supervisor (PR1): ±5% Priority can be automatically given to the highest
input voltage or manually assigned to a lower voltage
• TPS2121 Supports External Voltage Reference
input to support both ORing and Source Selection
(CP2): <1% operations. A priority voltage supervisor is used to
• Output Current Limit (ILM): select an input source.
– TPS2120: 1 A – 3 A An Ideal Diode operation is used to seamlessly
– TPS2121: 1 A – 4.5 A transition between input sources. During switchover,
• Channel Status Indication (ST) the voltage drop is controlled to block reverse current
before it happens and provide uninterrupted power to

ADVANCE INFORMATION
• Adjustable Input Settling Time (SS) the load with minimal hold-up capacitance.
• Adjustable Output Soft Start Time (SS)
Current limiting is used during startup and switchover
• TPS2121 Fast Output Switchover (tSW): 5 µs to protect against overcurrent. The output current
(Typical) limit can be adjusted with a single external resistor.
• Low Iq from Enabled Input: 200 µA (Typical)
The TPS212x devices are available in WCSP and
• Low Iq from Disabled Input: 10 µA (Typical) small VQFN-HR package options characterized for
• Manual Input Source Selection (OVx) operation for a temperature range of –40°C to 125°C.
• Over Temperature Protection (OTP)
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
TPS2120 WCSP (20) 1.5 mm x 2.0 mm
• Backup and Standby Power
TPS2121 VQFN-HR (12) 2.0 mm x 2.5 mm
• Input Source Selection
(1) For all available packages, see the orderable addendum at
• Multiple Battery Management the end of the data sheet.
• EPOS and Barcode Scanners
• Building Automation and Surveillance Typical Application
• Tracking and Telematics

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
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Table of Contents
1 Features .................................................................. 1 10.2 Typical Application ............................................... 17
2 Applications ........................................................... 1 10.3 Internal Voltage Reference Control Scheme
(VREF) ..................................................................... 19
3 Description ............................................................. 1
10.4 External Comparator Control Scheme (XCOMP) . 20
4 Revision History..................................................... 2
10.5 External Voltage Reference Control Scheme
5 Device Comparison Table..................................... 3 (XREF) ..................................................................... 20
6 Pin Configuration and Functions ......................... 4 10.6 Application Limitations .......................................... 21
7 Specifications......................................................... 6 11 Power Supply Recommendations ..................... 22
7.1 Absolute Maximum Ratings ...................................... 6 12 Layout................................................................... 22
7.2 ESD Ratings.............................................................. 6 12.1 Layout Guidelines ................................................. 22
7.3 Recommended Operating Conditions....................... 6 12.2 Layout Example .................................................... 22
7.4 Thermal Information .................................................. 6 13 Device and Documentation Support ................. 23
7.5 Electrical Characteristics........................................... 7 13.1 Documentation Support ....................................... 23
8 Parameter Measurement Information .................. 8 13.2 Receiving Notification of Documentation Updates 23
9 Detailed Description .............................................. 9 13.3 Community Resources.......................................... 23
9.1 Overview ................................................................... 9 13.4 Trademarks ........................................................... 23
9.2 Functional Block Diagram ......................................... 9 13.5 Electrostatic Discharge Caution ............................ 23
9.3 Feature Description................................................. 10 13.6 Glossary ................................................................ 23
ADVANCE INFORMATION

9.4 TPS2120 Device Functional Modes........................ 16 14 Mechanical, Packaging, and Orderable


9.5 TPS2121 Device Functional Modes........................ 16 Information ........................................................... 23
10 Application and Implementation........................ 17 14.1 Package Option Addendum .................................. 24
10.1 Application Information.......................................... 17

4 Revision History
DATE REVISION NOTES
August 2018 * Initial release.

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5 Device Comparison Table

Part Number Package On-Resistance Maximum Current Fastest Switchover


TPS2120 WCSP (20) 62 mΩ 3A 100 us
TPS2121 VQFN-HR (12) 56 mΩ 4.5 A 5 us

ADVANCE INFORMATION

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6 Pin Configuration and Functions

TPS2120 (YFP) Package


20-Pin WCSP
Bottom View
ADVANCE INFORMATION

TPS2121 (RUX) Package


12-Pin VQFN-HR
Bottom View

Pin Functions
PIN
TPS2120 TPS2121 I/O DESCRIPTION
NAME
WCSP VQFN-HR
IN1 B1, B2, C1 7 I Power Input for Source 1
IN2 B3, B4, C4 2 I Power Input for Source 2
C2, C3, D1,
OUT 1, 8 I Power Output
D2, D3, D4
ST E1 9 O Status output indicating which channel is selected.
ILIM E2 10 O Output Current Limiting for both channels.
SS E3 11 O Adjusts Input Setting Delay Time and Output Soft Start Time
GND E4 12 — Device Ground
PR1 A1 6 I Enables Priority Operation. Connect to IN1 to set switchover voltage.
OV1 A2 5 I Active Low Enable Supervisor for IN1 Overvoltage Protection
OV2 A3 4 I Active Low Enable Supervisor for IN2 Overvoltage Protection

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Pin Functions (continued)


PIN
TPS2120 TPS2121 I/O DESCRIPTION
NAME
WCSP VQFN-HR
Active low Enable for IN1. Allows GPIO to override priority operation and manually
SEL A4 — I
select IN2. TPS2120 only.
Enables Comparator Operation and is compared to PR1 to set switchover voltage.
CP2 — 3 I
TPS2121 only.

ADVANCE INFORMATION

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Pins MIN MAX UNIT
VIN1 , IN1, IN2,
Maximum Power Pin Voltage -0.3 24 V
VIN2 , VOUT OUT
VOV1 ,
Maximum Overvoltage Pin Voltage OV1, OV2 -0.3 6 V
VOV2
VPRI , VSEL Maximum Control Pin Voltage PRI, SEL -0.3 6 V
VST Maximum Control Pin Voltage ST -0.3 6 V
IOUT Maximum Output Current OUT Internally Limited
TJ, MAX Maximum Junction Temperature Internally Limited
TSTG Storage temperature -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ADVANCE INFORMATION

7.2 ESD Ratings


Pins VALUE UNIT
Human body model (HBM), per
All ±2000
ANSI/ESDA/JEDEC JS-001, (1)
VESD Electrostatic discharge V
Charged device model (CDM), per JEDEC
All ±500
specification JESD22-C101, (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions


over operating free-air temperature range (unless otherwise noted)
Pins MIN MAX UNIT
VIN1 , VIN2 Input Voltage Range (1) IN1, IN2 2.7 22 V
VOUT Output Voltage Range OUT 0 22 V
VOV1 ,
Overvoltage Pin Voltage OV1, OV2 0 5.5 V
VOV2
VPRI , VSEL Control Pin Voltage PRI, SEL 0 5.5 V
VST Control Pin Voltage ST 0 5.5 V
RST Status Pin Pull Up Resistance ST 6 20 kΩ
RILM Current Sense Resistance ILM 10 100 kΩ
CSS Soft-start Capacitor Voltage Rating SS 4 V
TJ Junction temperature °C -40 125 °C

(1) See Power Supply Recommendations Section for more Details

7.4 Thermal Information


TPS2120 TPS2121
THERMAL METRIC (1) YFP (WCSP) RUX (VQFN-HR) UNIT
20 PINS 11 PINS
RθJA Junction-to-ambient thermal resistance 72.5 (2) 72.2 (2) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.5 38.5 °C/W
RθJB Junction-to-board thermal resistance 16.4 15.4 °C/W
ΨJT Junction-to-top characterization parameter 0.3 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Estimates Subject to Change
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Thermal Information (continued)


TPS2120 TPS2121
THERMAL METRIC (1) YFP (WCSP) RUX (VQFN-HR) UNIT
20 PINS 11 PINS
ΨJB Junction-to-board characterization parameter 16.6 15.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance TBD - °C/W

7.5 Electrical Characteristics


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT
INPUT SOURCE (IN1, IN2)
Quiescent Current 25°C 200 300 µA
IQ, INx (1) OUT = Open
(INx Powering OUT -40°C to 125°C 400 µA
Standby Current
ISBY, INx VOUT = VINx -40°C to 125°C 10 20 µA
(INx not powering OUT (1)
VINx Rising -40°C to 125°C 2.5 2.65 2.8 V
VUV, INx Undervoltage Lockout
VINx Falling -40°C to 125°C 2.4 2.55 2.7 V

ADVANCE INFORMATION
OUTPUT SWITCHOVER (OUT)
VOUT < VINx
tSW Switchover Time -40°C to 125°C 100 250 µs
CP2 < VREF
Fast Switchover Time VOUT < VINx
tFSW -40°C to 125°C 5 10 µs
(TPS2121 only) CP2 ≥ VREF
Input Voltage Comparator VIN1 ≥ VIN2 -40°C to 125°C 0 300 600 mV
VCOMP
(VIN2 referenced to VIN1) VIN1 > VIN2, Falling Hysteresis -40°C to 125°C 3 3.5 4 %
ON-RESISTANCE (INx to OUT)
25°C 62 75 mΩ
IOUT = -200 mA -40°C to 85°C 90 mΩ
ON-State Resistance (TPS2120) VPRI > VREF
VIN = 5V to 22V -40°C to 105°C 100 mΩ
-40°C to 125°C 120 mΩ
RON
25°C 56 65 mΩ
IOUT = -200 mA -40°C to 85°C 75 mΩ
ON-State Resistance (TPS2121) VPRI > VREF
VIN = 5V to 22V -40°C to 105°C 85 mΩ
-40°C to 125°C 100 mΩ
CURRENT LIMIT AND MONITOR (ILM)
RILM = 21.5kΩ -40°C to 125°C 4 4.5 5 A
RILM = 28kΩ -40°C to 125°C 3 3.5 4 A
ILM Output Current Limit RILM = 40.2kΩ -40°C to 125°C 2 2.5 3 A
RILM = 71.5kΩ -40°C to 125°C 1 1.5 2 A
RILM < 1kΩ -40°C to 125°C 2.5 3.5 4.5 A
tLM Current Limit Response Time Output Steady State -40°C to 125°C 250 500 µs
CONTROL PINS (PRI, SEL, OV1, OV2)
VPR1, VCP2, VOV1, VOV2 Rising -40°C to 125°C 1.01 1.06 1.1 V
VREF, x Internal Voltage Reference
VPR1, VCP2, VOV1, VOV2 Falling -40°C to 125°C 0.99 1.04 1.09 V
VPR1 > VREF
VOFST Comparator Offset Voltage -40°C to 125°C 5 20 35 mV
VCP2 > VREF
VPR1, VCP2, VOV1, VOV2 = 0 V to 5.5
ILK, x Pin Leakage Current -40°C to 125°C -0.1 0.1 µA
V
STATUS INDICATION PIN (ST)
ILK, ST Pin Leakage VST = 0 V to 5.5 V -40°C to 125°C -0.1 0.1 µA

(1) When PR1 < VREF, CP2 < VREF, and |VIN1-VIN2| < 1V, Quiescent current can be drawn from both IN1 and IN2 with combined current not
to exceed IQ,INx.
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Electrical Characteristics (continued)


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT
tST Status Delay L to H -40°C to 125°C 1 µs
FAST REVERSE CURRENT BLOCKING (RCB)
Fast Reverse Current Detection
IRCB VOUT > VINx 25°C to 125°C 0.25 1 2 A
Threshold
VRCB RCB Release Voltage VOUT > VINx -40°C to 125°C 0 25 50 mV
Fast Reverse Current Blocking
tRCB -40°C to 125°C 2 µs
Response Time
THERMAL SHUTDOWN (TSD)
Shutdown Rising 150 170 190 °C
TSD Thermal Shutdown
Recovery Falling 140 160 180 °C

8 Parameter Measurement Information


ADVANCE INFORMATION

Figure 1. Timing Parameter Diagram

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9 Detailed Description

9.1 Overview
The TPS212x devices are Dual-Input, Single-Output (DISO) Power Multiplexer (MUX) that are well suited for a
variety of systems having multiple power sources. The devices will Automatically Detect, Select, and Seamlessly
Transition between available inputs. Priority can be automatically given to the highest input voltage or manually
assigned to a lower voltage input to support both ORing and Source Selection operations. A priority voltage
supervisor is used to select an input source.
An Ideal Diode operation is used to seamlessly transition between input sources. During switchover, the voltage
drop is controlled to block reverse current before it happens and provide uninterrupted power to the load with
minimal hold-up capacitance. Active current limiting is used during startup and switchover to protect against
overcurrent. The output current limit can be adjusted with a single external resistor.

9.2 Functional Block Diagram

Figure 2. TPS2120 Functional Block Diagram ADVANCE INFORMATION

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Functional Block Diagram (continued)


ADVANCE INFORMATION

Figure 3. TPS2121 Functional Block Diagram

9.3 Feature Description


This section describes the different features of the TPS212x power mux device.

9.3.1 Input Settling Time and Output Soft Start Control (SS)
The TPS212x will automatically select the first source to become valid (INx >UV and INx <OV). The external
capacitor (CSS) will then be used as a timer to wait for the input to finish setting (tSETx). When the settling timer
has expired, CSS will be reused to set the output slew rate (SRON) for a soft start. The total turn on time (tONx)
from becoming valid to finishing soft start, including the settle time, will be double the settling time (tSETx). After
tONx, soft start will not be used again for INx until it ceases to be valid (INx <UV or INx >OV).
When the second source becomes valid (INy >UV and INy <OV), the external capacitor (Css) will be used again
for a second settling time (tSETy). After tSETy, the TPS212x will decide whether to continue sourcing the first
source, or switchover to the second source. If the second source is selected at the end of tSETy, then CSS will
be reused to set the output slew rate (SRON) for a second soft start. The total turn on time (tONy) from the
second source becoming valid to finishing soft start, including the settle time, will be double the settling time
(tSETy). After tONy, soft start will not be used again for INy until it ceases to be valid (INy <UV or INy >OV).
Since the same external capacitor is used for both inputs, the settling and total turn on time for both sources will
be the same (tSETx = tSETy) (tONx = tONy).

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Feature Description (continued)

Figure 4. Settling and Soft Start Timing

ADVANCE INFORMATION
If INy becomes valid before the end of tONx, tSETy will be delayed and start after tONx has ended.
If INy is not selected during tSETy, a second soft start will not take place, skipping tONy, and CSS will be retired
until one of the inputs ceases to be valid.

9.3.1.1 Slew Rate vs. CSS Capacitor


Table 1 shows the estimated slew rate across CSS capacitance and VIN.

Table 1. Slew Rate vs. CSS Capacitor


CSS CAPACITOR VIN = 5 V VIN = 12 V VIN = 20 V UNITS
100 nF 780 800 880 V/s
1 uF 88 92 92 V/s
10 uF 8.8 9.6 10.4 V/s

9.3.2 Active Current Limiting (ILM)


The load current is monitored at all times. When the load current exceed the current limit trip point ILM
programmed by RILM resistor, the device regulates the current within tILM. The following equations can be used
to find the RILM value for a desired current limit, where RILM is in kΩ and between 17kΩ to 80kΩ.

TPS2120:
I LM 70.5 R ILM ^ 0.91 (1)

TPS2121:
I LM 71.5 R ILM ^ 0.9 (2)
During current regulation, the output voltage will drop resulting in increased device power dissipation. If the
device junction temperature (TJ) reaches the thermal shutdown threshold (TSD) the internal FETs are turned off.
After cooling down, the device will automatically restart.

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ADVANCE INFORMATION

Figure 5. Current Limiting Behavior

9.3.3 Short-Circuit Protection


During a transient short circuit event, the current through the device increases very rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip over
current protection (OCP) comparator, with a threshold IOCP. This comparator shuts down the pass device within 1
µs, when the current through internal FET IOUT exceeds IOCP (IOUT> IOCP). The trip threshold is set to about 2.4x
of the programmed current limit IOCP = 2.4 × ILM. The OCP circuit holds the internal FET off for about 25 ms, after
which the device turns back on. If the short is still present then the current-limit loop will regulate the output
current to ILM and behave in a manner similar to a power up into a short.

9.3.4 Thermal Protection (TSD)


The TPS212x devices have built-in absolute thermal shutdown and relative thermal shutdown to ensure
maximum reliability of the power mux. The absolute thermal shutdown is designed to disable the power FETs, if
the junction temperature exceeds 170°C (typical). The device auto recovers about 25 ms after TJ < [T (TSD) –
10°C]. The relative thermal shutdown protects the device by turning off when the temperature of the power FETs
increases sharply such that the FET temperature rises about 60°C above the rest of the die. The device auto
recovers about 25 ms after the FETs cools down by 20°C. The relative thermal shutdown is critical for protecting
the device against faults such as a power up into a short which causes the FET temperature to increase sharply.

9.3.5 Overvoltage Protection (OVx)


Output Overvoltage Protection is available for both IN1 and IN2 in case either applied voltage is greater than the
maximum supported load voltage. The VREF comparator on the OVx pins allow for the Overvoltage Protection
threshold to be adjusted independently for each input. When overvoltage is engaged, the corresponding channel
with turn off immediately. Fast switchover to the other input is supported if it is a valid voltage.

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VSUPPLY

R1

OVx

R1

VOVx = VINx x R2/(R1+R2)

Figure 6. OVP Resistor Configuration

9.3.6 Fast Reverse Current Blocking (RCB)


Each channel has always on reverse current blocking. If the output is forced above the selected input by VIRCB,
the channel will switch off to stop the reverse current IRCB within tRCB. As the output falls to within VRCB of VIN, the
selected channel will quickly turn back on to avoid unnecessary voltage drops during fast switchover (tSW).

ADVANCE INFORMATION
Figure 7. Reverse Current Blocking Behavior

9.3.7 Output Voltage Dip and Fast Switchover Control (TPS2121 only)
After input settling and soft start time, the TPS2121 utilizes a fast switchover to minimize output voltage drop.
Where VSW is the output voltage when the switchover is triggered and tSW is the time until the output voltage
stops dipping. The amount of voltage dip during the switchover time is a function of output load current (IOUT)
and load capacitance (COUT) The minimum output voltage during switchover can be found using the following
equations:
V OUT,MIN V SW V DIP (3)
Where:
V DIP t SW u I OUT C OUT (4)

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Figure 8. Minimum Output Voltage During Fast Switchover

If switching from a lower to a higher voltage, the selected channel will not detect reverse voltage and shall turn
on immediately using the current monitor to limit the output current to a safe level. If the output current reaches
the current limit during fast switchover, this will increase the total time until the output reaches steady state.

VIN2
ADVANCE INFORMATION

Input VIN1
Voltages
0V

H
PRI VREF
L
VIN2

VOUT tSW
VIN1
VSW
VOUT,MIN
SROUT
Current Limited
IOUT
IIN2
0

Time
VOUT,MIN = VSW - (tSWxSROUT) where SROUT = IOUT/COUT

VOUT,MIN = 3.5 V - (5µs x 30mV/µs) = 3.35 V

VOUT,MIN = 3.5 V - (5µs x 1A/10µF) = 3 V

VOUT,MIN = 3.5 V - (5µs x 1A/100µF) = 3.45 V

Figure 9. Fast Switchover from Lower to Higher Voltage

If an input is selected while the output voltage is still a higher voltage, that channel will continue to block reverse
current by waiting to fast turn on until the output drops below the VRCB threshold.

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VIN2
Input VIN1
Voltages
0V
1
OV2
0

VIN2

VOUT tSW
SROUT
VRCB
VIN1
VOUT,MIN

IOUT No Spikes
IIN1
0

Time
VOUT,MIN = VIN1 + VRCB - (tSW x SROUT) where SROUT = IOUT/COUT

VOUT,MIN = 4.25 V + 50 mV - (5µs x 30mV/µs) = 4.15 V

ADVANCE INFORMATION
VOUT,MIN = 4.25 V + 50 mV - (5µs x 1A/10µF) = 3.8 V

VOUT,MIN = 4.25 V + 50 mV (5µs x 1A/100µF) = 4.25 V

Figure 10. Fast Switchover from Higher to Lower Voltage

9.3.8 Input Voltage Comparator (VCOMP)


If both PR1 and CP2 are < VREF, the device will use an internal comparator between the two inputs to
determine the priority source. VCOMP is configured to ensure IN2 will take priority if the input voltages are equal. If
IN2 falls below the VCOMP Hysteresis, then IN1 will have priority.

Figure 11. VCOMP Priority Source Selection

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9.4 TPS2120 Device Functional Modes


Table 2 shows the TPS2120 functional behavior.

Table 2. TPS2120 Output Source Selection Table


IN1 ≥ UV OR
IN2 ≤ UV OR
OV1 ≥ VREF OR PR1 ≥ VREF VCOMP OUT ST
OV2 ≥ VREF
SEL ≥VREF
0 0 0 IN2 < IN1 IN1 H
0 0 0 IN2 ≥ IN1 IN2 L
0 0 1 X IN1 H
0 1 X X IN1 H
1 0 X X IN2 L
1 1 X X Hi-Z H

A summary of the operation of the TPS2120 device can be found below:


• If only one input voltage is valid (above UV and below OV) then that input will power the output.
• If both inputs are not valid, then the output is Hi-Z.
• ST is pulled high when the output is Hi-Z or IN1. It is pulled low when IN2 is powering the output.
ADVANCE INFORMATION

• If both inputs are valid and PR1 is pulled high, then IN1 is used.
• If both inputs are valid and PR1 is pulled low, then the highest voltage input is used.

9.5 TPS2121 Device Functional Modes


Table 3 shows the TPS2121 functional behavior.

Table 3. TPS2121 Output Source Selection Table


IN1 ≤ UV OR IN2 ≤ UV OR CP2 ≥ PR1 ≥
VCOMP XCOMP OUT ST
OV1 ≥ VRFEF OV2 ≥ VREF VREF VREF
0 X 0 0 IN2 < IN1 X IN1 H
X 0 0 0 IN2 ≥ IN1 X IN2 L
0 X 0 1 X X IN1 H
X 0 1 0 X X IN2 L
0 X 1 1 X PR1 > CP2 IN1 H
X 0 1 1 X PR1 ≤ CP2 IN2 L
0 1 X X X X IN1 H
1 0 X X X X IN2 L
1 1 X X X X Hi-Z H

A summary of the operation of the TPS2121 device can be found below:


• If only one input voltage is valid (above UV and below OV) then that input will power the output.
• If both inputs are not valid, then the output is Hi-Z.
• ST is pulled high when the output is Hi-Z or IN1. It is pulled low when IN2 is powering the output.
• If CP2 is pulled low, then the TPS2121 ignores this pin.
• When CP2 is pulled high, it is compared to PR1. If PR1 > CP2 then IN1 is used, and if PR1 < CP2 then IN2
is used.
• If both inputs are valid, CP2 is low, and PR1 is pulled high, then IN1 is used.
• If both inputs are valid, CP2 is low, and PR1 is pulled low, then the highest voltage input is used.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information


This section highlights some of the design considerations when implementing this device in various applications.

10.2 Typical Application

ADVANCE INFORMATION
Figure 12. TPS212x Typical Application

10.2.1 Design Requirements


For this design example, use the values listed in Table 4 as the design parameters:

Table 4. Design Requirements Table


DESIGN PARAMETER EXAMPLE VALUE
IN1 Voltage (VIN1) 5V
IN2 Voltage (VIN2) 0V
Load Capacitance (CL) 100 uF
Maximum Inrush Current 100 mA

10.2.2 Detailed Design Procedure

10.2.2.1 Managing Inrush Current


To calculate the slew rate needed to limit the inrush current to 100 mA, the following equation can be used:

Slew Rate
SR ON C L I INRUSH
Where:
• SRON = Slew Rate
• CL = Load Capacitance

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• IINRUSH = Inrush Current (5)


Using the above equation, the slew rate must be limited to 1000V/s or below to keep the inrush current below
100 mA. At 5 V, a CSS capacitance of 100 nF will provide a slew rate of about 780V/s, and this is well below the
calculated value of 100V/s.

10.2.3 Application Curves


The below oscilloscope capture shows the inrush current being limited to below 100 mA with a CSS capacitor of
100 nF.
ADVANCE INFORMATION

VIN1 = 5 V CL = 100 uF VIN2 = 0 V

10.2.4 Internal Comparator Control Scheme (VCOMP)


In ideal diode operation both channels will be enables and the highest input voltage will be sourced to the load. If
both inputs are equal, then current will be shared between the channels.

Figure 13. VCOMP Control Circuit

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Table 5. VCOMP Output Source Selection Table


Priority Source
CP2 ≥ VREF PR1 ≥ VREF VCOMP XCOMP
Selection
0 0 IN2 < IN1 X IN1
0 0 IN2 ≥ IN1 X IN2

10.3 Internal Voltage Reference Control Scheme (VREF)


For priority operation using the internal voltage reference VREF, connect PR1 to IN1 through a resistor divider to
set the switchover voltage (VSW). SEL or OV1 can also be used to override the automatic priority selection and
manually select IN2 to power the load.

ADVANCE INFORMATION
Figure 14. VREF Control Circuit

Table 6. VREF Output Source Selection Table


Priority Source
CP2 ≥ VREF PR1 ≥ VREF VCOMP XCOMP
Selection
0 0 IN2 < IN1 X IN1
0 0 IN2 ≥ IN1 X IN2
0 1 X X INI

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10.4 External Comparator Control Scheme (XCOMP)


The comparator breakout allows the two input sources to be directly compared to each other with the ST pin
providing an adjustable hysteresis.
ADVANCE INFORMATION

Figure 15. XCOMP Control Circuit

Table 7. XCOMP Output Source Selection Table


Priority Source
CP2 ≥ VREF PR1 ≥ VREF VCOMP XCOMP
Selection
0 0 IN2 < IN1 X IN1
0 0 IN2 ≥ IN1 X IN2
0 1 X X IN1
1 0 X X IN2
1 1 X PR1 > CP2 IN1
1 1 X PR1 ≤ CP2 IN2

10.5 External Voltage Reference Control Scheme (XREF)


A comparator breakout operation can be used to reduce the switchover voltage error to only VOFST for a more
seamless switchover. An external precision voltage reference (XREF) can be connected to the CP2 pin for
comparison to the Priority Power Source 1 being sensed on the PR1 pin. The XREF can be generated from
either input source or even the output because the other operating modes support startup even without this
voltage present. The ST pin can also be used for a precise adjustable hysteresis for the Priority Power Source 1.

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External Voltage Reference Control Scheme (XREF) (continued)

ADVANCE INFORMATION
Figure 16. XREF Control Circuit

Table 8. XREF Output Source Selection Table


Priority Source
CP2 ≥ VREF PR1 ≥ VREF VCOMP XCOMP
Selection
0 0 IN2 < IN1 X IN1
0 0 IN2 ≥ IN1 X IN2
0 1 X X IN1
1 0 X X IN2
1 1 X PR1 > CP2 IN1
1 1 X PR1 ≤ CP2 IN2

10.6 Application Limitations


This section highlights some limitations in the application which were identified during bench evaluation of the
existing TPS212x silicon on the evaluation module (EVM). Removal of this section in future datasheet revisions
confirms that these limitations have been resolved.

10.6.1 Thermal Shutdown


The thermal shutdown threshold does not match the specified value of 170°C. Testing has shown that the actual
thermal shutdown threshold is approximately 135°C.
A design fix will be included in the next version of the IC.

10.6.2 Switchover Time (TPS2120)


When the SEL pin is pulled low in the TPS2120, the switchover time matches the specified value of 100μs. When
the SEL pin is pulled high, then the switchover time is reduced to 5μs.
A design change will be included in the next version of the IC so that the switchover time is always 100μs.

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11 Power Supply Recommendations


IN1, IN2, and OUT traces should all be wide enough to accomodate the amount of current passing through the
device. Bypass capacitors on these pins should be placed as close to the device as possible. Low ESR ceramic
capacitors with X5R or X7R dielectric are recommended.
To avoid output voltage drop, the capacitance on OUT can be increased. If the power supply cannot handle the
inrush current transients due to the output capacitance, a higher input capacitance can be used.

12 Layout

12.1 Layout Guidelines


Use short wide traces for input and output planes. For high current applications place vias under input and output
pins to avoid current density and thermal resistance bottlenecks.

12.2 Layout Example


ADVANCE INFORMATION

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13 Device and Documentation Support

13.1 Documentation Support


13.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.

Table 9. Related Links


TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TPS2120 Click here Click here Click here Click here Click here
TPS2121 Click here Click here Click here Click here Click here

13.2 Receiving Notification of Documentation Updates


To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

ADVANCE INFORMATION
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.4 Trademarks
E2E is a trademark of Texas Instruments.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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14.1 Package Option Addendum


14.1.1 Packaging Information

(1) Package Package Package (2) Lead/Ball (4)


Orderable Device Status Pins Eco Plan MSL Peak Temp Op Temp (°C) Device Marking (5) (6)
Type Drawing Qty Finish (3)
PTPS2120YFPR ACTIVE DSBGA YFP 20 3000 TBD Call TI Call TI –40 to 125 P0
PTPS2121RUXR ACTIVE VQFN-HR RUX 12 3000 TBD Call TI Call TI –40 to 125
TPS2120YFPR PREVIEW DSBGA YFP 20 3000 TBD Call TI Call TI –40 to 125
TPS2120YFPT PREVIEW DSBGA YFP 20 250 TBD Call TI Call TI –40 to 125
TPS2121RUXR PREVIEW VQFN-HR RUX 12 3000 TBD Call TI Call TI –40 to 125
ADVANCE INFORMATION

(1) The marketing status values are defined as follows:


ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

24 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

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14.1.1.1 Tape and Reel Information


REEL DIMENSIONS TAPE DIMENSIONS
K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

ADVANCE INFORMATION
Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
PTPS2120YFPR DSBGA YFP 20 3000 180.0 8.4 1.66 2.06 0.56 4.0 8.0 Q1
PTPS2121RUXR VQFN-HR RUX 12 3000 180.0 8.4 2.25 2.8 1.10 4.0 8.0 Q1
TPS2120YFPR DSBGA YFP 20 3000 180.0 8.4 1.66 2.06 0.56 4.0 8.0 Q1
TPS2120YFPT DSBGA YFP 20 3000 180.0 8.4 1.66 2.06 0.56 4.0 8.0 Q1
TPS2121RUXR VQFN-HR RUX 12 3000 180.0 8.4 2.25 2.8 1.10 4.0 8.0 Q1

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
ADVANCE INFORMATION

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PTPS2120YFPR DSBGA YFP 20 3000 182.0 182.0 20.0
PTPS2121RUXR VQFN-HR RUX 12 3000 2.0 2.5 1.0
TPS2120YFPR DSBGA YFP 20 3000 182.0 182.0 20.0
TPS2120YFPT DSBGA YFP 20 3000 182.0 182.0 20.0
TPS2121RUXR VQFN-HR RUX 12 3000 2.0 2.5 1.0

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PACKAGE OUTLINE
YFP0020 SCALE 7.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER
D: 1958μm +/- 30µm
D E: 1558µm +/- 30µm

ADVANCE INFORMATION
C
0.5 MAX
SEATING PLANE

0.19 BALL TYP


0.05 C
0.13

1.2 TYP

SYMM

D
SYMM
1.6 C
TYP

A
0.4 TYP 1 2 3 4
0.25
20X
0.21 0.4 TYP
0.015 C A B

4222895/A 04/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS2120 TPS2121
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EXAMPLE BOARD LAYOUT


YFP0020 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP
20X ( 0.23)
1 2 3 4

A
(0.4) TYP

B
SYMM
C
ADVANCE INFORMATION

SYMM

LAND PATTERN EXAMPLE


SCALE:25X

( 0.23) 0.05 MAX 0.05 MIN METAL UNDER


METAL SOLDER MASK

SOLDER MASK ( 0.23)


OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS


NOT TO SCALE

4222895/A 04/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
28 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

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EXAMPLE STENCIL DESIGN


YFP0020 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

20X ( 0.25) (R0.05) TYP

1 2 3 4
A

(0.4) TYP

ADVANCE INFORMATION
B

METAL
TYP SYMM
C

SYMM

SOLDER PASTE EXAMPLE


BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4222895/A 04/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS2120 TPS2121
PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

PTPS2120YFPR ACTIVE DSBGA YFP 20 3000 TBD Call TI Call TI -40 to 125 P0

PTPS2121RUXR ACTIVE VQFN-HR RUX 12 3000 TBD Call TI Call TI -40 to 125

TPS2120YFPR PREVIEW DSBGA YFP 20 3000 TBD Call TI Call TI -40 to 125
TPS2120YFPT PREVIEW DSBGA YFP 20 250 TBD Call TI Call TI -40 to 125
TPS2121RUXR PREVIEW VQFN-HR RUX 12 3000 TBD Call TI Call TI -40 to 125

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2018

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE OUTLINE
YFP0020 SCALE 7.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX
SEATING PLANE

0.19 BALL TYP


0.05 C
0.13

1.2 TYP

SYMM

D
SYMM
1.6 C
TYP

A
0.4 TYP 1 2 3 4
0.25
20X
0.21 0.4 TYP
0.015 C A B

4222895/A 04/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
EXAMPLE BOARD LAYOUT
YFP0020 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP
20X ( 0.23)
1 2 3 4

A
(0.4) TYP

B
SYMM
C

SYMM

LAND PATTERN EXAMPLE


SCALE:25X

( 0.23) 0.05 MAX 0.05 MIN METAL UNDER


METAL SOLDER MASK

SOLDER MASK ( 0.23)


OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS


NOT TO SCALE

4222895/A 04/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
EXAMPLE STENCIL DESIGN
YFP0020 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

20X ( 0.25) (R0.05) TYP

1 2 3 4
A

(0.4) TYP
B

METAL
TYP SYMM
C

SYMM

SOLDER PASTE EXAMPLE


BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4222895/A 04/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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