PIC Microcontrollers: Chapter 4: Pic Architecture & Assembly

PIC Microcontrollers
Chapter 4: PIC ARCHITECTURE & ASSEMBLY

LANGUAGE PROGRAMMING
Gaby Abou Haidar M.S. Fall 2017 - 2018

• PIC microcontrollers have many registers for arithmetic and logic
operations. Among them is the WREG register.
• In the PIC there is only one data type: 8-bit.
• any data larger than 8 bits must be broken into 8-bit chunks
before it is processed.
• WREG stands for working register, as there is only one.
• The WREG register is used for all arithmetic and logic
instructions.

• MOVLW: moves 8-bit data into the WREG register.
MOVLW K ;move literal value K into WREG
▫ K is an 8-bit value that can range from 0-255 in decimal, or 00-FF in hex.
▫ The L stands for literal, which means, literally, a number must be used.
▫ The word literal in any instruction: a value must be provided. This is
similar to the immediate addressing in microprocessors.
MOVLW 25H ;move value 25H into WREG (WREG = 25H)
• ADDLW
ADDLW K ;ADD literal value K to WREG
▫ The ADD instruction tells the CPU to add the literal value K to register
WREG and put the result back in the WREG register.
MOVLW 25H ;load 25H into WREG
ADDLW 34H ;add value 34 to W (W = W + 34H)
• Example:
MOVLW 12H ;load value 12H into WREG (WREG = 12H)
ADDLW 16H ;add 16 to WREG (WREG 28H)
ADDLW 11H ;add 11 to WREG (WREG 39H)
ADDLW 43H ;add 43 to WREG (WREG 7CH)
• Example:
MOVLW 7F2H ;ILLEGAL 7F2H > 8 bits, becomes F2H
MOVLW 456H ;ILLEGAL 456H > FFH, becomes 56H
MOVLW 60A5H ;ILLEGAL but becomes ASH

• The PIC microcontroller has many other registers than WREG.
▫ They are called data memory space to distinguish them from program
(code) memory space.
▫ The data memory space in PIC is a read/write (static RAM) memory.
▫ In the PIC microcontroller literature, the data memory is also called the
file register.
• File register (data RAM) space allocation in PIC:
▫ The PIC microcontrollers' file register size ranges from 32 bytes to
several thousand bytes depending on the chip.
▫ The file register data RAM in PIC is divided into two sections:
 Special Function Registers (SFR),
 General Purpose Registers (GPR).
▫ The GPR is also referred to as General-Purpose RAM (GP RAM).
• SFRs (Special Function Registers)
▫ The Special Function Registers (SFRs) are dedicated to specific functions
such as ALU status, timers, serial communication, 1/0 ports, ADC, ….
▫ The function of each SFR is fixed by the CPU designer at the time of
design because it is used for control of the microcontroller or peripheral.
▫ The PIC SFRs are 8-bit registers.
• GPR (General-Purpose Registers or RAM)

▫ The general-purpose registers are a group of RAM locations in the file
register that are used for data storage and scratch pad.
▫ Each location is 8 bits wide and can be used to store any data we want as
long as it is 8-bit.

• GP RAM vs. EEPROM in PIC chips
▫ There are two RAM columns in the chip information section of The
Microchip web site.
▫ One refers to the general-purpose registers (GP RAM) size, and the other
is the EEPROM size.
▫ GP RAM (which constitutes most of the file register) must not be
confused with the EEPROM data memory.
▫ The GPRs are used by the CPU for internal data storage, whereas the
EEPROMs are considered as an add-on memory that one can also add
externally to the chip.

• The file register of the PIC18 can have a maximum of 4096 (4K) bytes.
▫ With 4096 bytes, the file register has addresses of 000-FFFH.
▫ The file register in the PIC 18 is divided into 256-byte banks.
▫ Therefore, we can have up to a maximum of 16 banks (16 x 256 = 4096).
▫ Although not all members of the PIC18 family have that many banks, every PIC
18 family member has at least one bank for the file register.
▫ It is called the access bank: the default bank when we power up the PIC 18 chip.
▫ The 256-byte access bank is divided into two equal sections of 128 bytes.
▫ These 128-byte sections are given to the GPR and SFR.
▫ The 128 bytes from locations 00H to 7FH are set aside GPR and are used for
read/write (scratch pad).
▫ These 128 locations of RAM are widely used for storing data and parameters.
▫ Each location of the 128-byte RAM of GPR can be accessed by its address.

• A file register of more than 256 bytes will necessitate bank switching.
• Bank switching is a method used to access all the banks of the file
register for PIC 18 family members that have more than the minimum
access bank.

• MOVWF:
▫ The term file register must be emphasized because the instructions have
the letter F in their mnemonics.
▫ MOVWF instruction tells the CPU to move (copy) the source register of
WREG to a destination in the file register (F).
▫ The location in the file register can be one of the SFRs or a location in the
general purpose registers region.

• ADDWF:
▫ adds together the contents of WREG and a file register location.
▫ The file register location can be one of the SFRs or a general-purpose
register.
▫ The destination for the result can be the WREG or the file register.
ADDWF fileReg, D
▫ fileReg is the file register location and D indicates the destination bit.
▫ If D = 0 → the destination is WREG
▫ If D = 1 → the result will be placed in the file register.
MOVLW 22H ;WREG = 22H
MOVWF 5H ;move(copy) WREG contents to location 5H
MOVWF 6H ;move(copy) WREG contents to location 6H
ADDWF 5H, 0 ;add w and loc 5, result in WREG (W 44H)
ADDWF 6H, 0 ;add w and loc 6, result in WREG (W 66H)
• To make things less confusing, the PIC assembler allows us to use the
letters W or F instead of 0 or 1 to indicate the destination.
ADDWF fileReg, w ; WREG=the result
ADDWF fileReg, f ;fileReg =the result
• Example: State the contents of file register RAM locations 12H and
WREG after the following program:
MOVLW 0 ;move 0 WREG to clear it (WREG = 0)
MOVWF 12H ;move WREG to location 12 to clear it
MOVLW 22H ;load WREG with value 22H
ADDWF 12H, F ;add WREG to loc 12H, loc 12 sum
• Instruction
▫ ADDWF fileReg, d ;ADD WREG and fileReg
▫ ADDWFC fileReg, d ;ADD WREG and fileReg with Carry
▫ ANDWF fileReg, d ;AND WREG with fileReg
▫ IORWF fileReg, d ;OR WREG with fileReg
▫ SUBFWB fileReg, d ;Subtract fileReg from WREG with borrow
▫ SUBWF fileReg, d ;Subtract WREG from fileReg
▫ SUBWFB fileReg, d ;Subtract WREG from fileReg with borrow
▫ XORWF fileReg, d ;Exclusive-OR WREG with fileReg
▫ The d bit selects the destination for the operation. If d = w; the result is
stored in WREG (d = 0). If d = F; the result is stored in the fileReg (d =1 ).
The default is F.
• Instruction
▫ COMF fileReg, d ;Complement fileReg
▫ DECF fileReg, d ;Decrement fileReg
▫ DECFSZ fileReg, d ;Decrement file Reg and skip if zero
▫ DECFSNZ fileReg, d ;Decrement fileReg and skip if not zero
▫ INCF fileReg, d ;Increment fileReg
▫ INCFSZ fileReg, d ;Increment fileReg and skip if zero
▫ INCSNZ fileReg, d ;Increment fileReg and skip if not zero
▫ MOVF fileReg, d ;Move fileReg
▫ NEGF fileReg, d ;Negative fileReg
▫ RLCF fileReg, d ;Rotate left fileReg through carry
▫ RLNCF fileReg, d ;Rotate left fileR eg (No carry)
▫ RRCF fileReg, d ;Rotate right fileReg through carry
▫ RRNCF fileReg, d ;Rotate right fileReg (No carry)
▫ SWAPP fileReg, d ;Swap nibbles in fileReg
▫ BTG fileReg, d
Gaby Abou Haidar M.S.
;Bit Toggle fileReg
Fall 2017 - 2018
• COMF
▫ complements (inverts) the contents of fileReg and places the result in
WREG or fileReg.
MOVLW 55H ;WREG = 55h
MOVWF PORTE ;Move WREG to Port B SFR (PB= 55h)
COMF PORTE, F ;complement Port B (PB= AAh)
• DECF
▫ decrements the contents of fileReg, the result in WREG or fileReg.
MOVLW 3 ;WREG = 3
MOVWF 20H ;move WREG to loc 20H (loc 20H = 3)
DECF 0x20, F ;loc 20H has 2
DECF 0x20, F ;loc 20H has 1
DECF 0x20, F ;loc 20H has 0 and WREG = 3
• MOVF
MOVF fileReg, D
▫ If D = 0, it copies the content of fileReg to WREG.
▫ If D = 1, the content of fileReg is copied to itself.
▫ we use the MOVF instruction to bring data into WREG from I/0 pins
▫ we sometimes use it to copy fileReg to itself for the purpose of testing
fileReg contents.
▫ the MOVF instruction is used to bring data from I/0 ports e.g. Port B into
the CPU.
▫ We also use the MOVF instruction to bring data into WREG from any
SFRs or from any location in the GP RAM in order to perform arithmetic
and operations on them.

• Example: Write a program to get data from the SFRs of Port B and
send it to the SFRs of PORT C continuously.
AGAIN MOVF PORTB, W ;bring data from PortB into WREG
MOVWF PORTC ;send it to Port C
GOTO AGAIN ;keep doing it forever
• Example: Write a program to get data from the SFRs of Port B. Add
the value 5 to it and send it to the SFRs of Port C.
MOVF PORTB,W ;bring data from Port B into WREG
ADDLW 05H ;add 5 to WREG
MOVWF PORTC ;copy WREG to Port C

• MOVFF
▫ copies data from one location in fileReg to another location in fileReg.
▫ The fileReg location for source and destination can be any of the 4096
locations in the data RAM space of the PIC 18, without going through the
WREG register.

• Example: Write a program to get data from the SFRs of Port B and
send it to the SFRs of PORT C continuously using MOVFF.
AGAIN MOVFF PORTB, PORTC ;copy data from Port B to Port C
GOTO AGAIN ;keep doing it forever

• The status register is an 8-bit register. It is also referred to as the flag
register.
▫ Although the status register is 8 bits wide, only 5 bits of it are used by the
PIC 18. The three unused bits are unimplemented and read as 0.
▫ The five flags are called conditional flags, meaning that they indicate
some conditions that result after an instruction is executed.

• C, the carry flag
▫ This flag is set whenever there is a carry out from the D7 bit. This flag bit is
affected after an 8-bit addition or subtraction.
• DC, the digital carry flag
▫ If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is set;
otherwise, it is cleared. This flag bit is used by instructions that perform BCD
arithmetic.
• Z, the zero flag
▫ If the result of an arithmetic or logic operation is zero, then Z = 1 (Z=0 if the
result is not zero).
• OV, the overflow flag
▫ This flag is set whenever the result of a signed number operation is too large,
causing the high-order bit to overflow into the sign bit.
• N, the negative flag
▫ Binary representation of signed numbers uses D7 as the sign bit. If the D7 bit of
the result is zero, then N = 0 and the result is positive. If the D7 bit is one, then N
= 1 and the result is negative.

• Example: Show the status of the C, DC, and Z flags after the addition of
38H and 2FH in the following instructions:
MOVLW 38H ;add 2FH to WREG
ADDLW 2FH
38H 0011 1000
+2FH 0010 1111
67H 0110 0111 WREG = 67H
▫ C = 0 because there is no carry beyond the D7 bit.
▫ DC = 1 because there is a carry from the D3 to the D4 bit.
▫ Z = 0 because the WREG has a value other than 0 after the addition.
▫ Some instructions affect all the five flag bits (e.g., ADDWL). But some
instructions affect no flag bits at all. The move instructions are in this category
(except MOVF). And some instructions affect only the Z or N flag bits, or both.
The logic instructions are in this category (e.g., ANDWL).
• PIC18 Branch (Jump) Instructions Using Flag Bits
Instruction Action
▫ BC Branch if C = 1
▫ BNC Branch if C  0
▫ BZ Branch if Z = 1
▫ BNZ Branch if Z  0
▫ BN Branch if N = 1
▫ BNC Branch if N  0
▫ BOV Branch if OV = 1
▫ BNOV Branch if OV  0

• PIC data type
▫ The PIC microcontroller has only one data type. It is 8 bits, and the size
of each register is also 8 bits. It is the job of the programmer to break
down data larger than 8 bits (00 to FFH, or 0 to 255 in decimal) to be
processed by the CPU.
• Data format representation
▫ Hex numbers:
▫ We can use h (or H) : MOVLW 99H
▫ Put 0x in front of the number: MOVLW 0x99
▫ Put nothing in front or back: MOVLW 99
▫ Put h in front with single quotes: MOVLW h ‘99‘
▫ Binary numbers: MOVLW B'10011001' ;WREG = 10011001 or 99 in hex
▫ Decimal numbers: MOVLW D'12' ;WREG = 00001100 or 0C in hex
▫ ASCII character: MOVLW A'2' ;WREG = 00110010 or 32 in hex

• EQU (equate)
▫ This is used to define a constant value or a fixed address.
COUNT EQU 0x25
MOVLW COUNT ;WREG = 25H
• SET
▫ This directive is used to define a constant value or a fixed address.
▫ In this regard, the SET and EQU directives are identical. The only difference is
the value assigned by the SET may be reassigned later.
• Using EQU for fixed data assignment

DATA1 EQU 39 ;hex data is the default
DATA2 EQU 0x39 ;another way for hex
DATA3 EQU 39H ;another way for hex (redundant)
DATA6 EQU b ' 00110101' ;binary ( 35 in hex)
DATA7 EQU D'28' ;decimal numbers (lC in hex)
DATA8 EQU A' 2 ' ;ASCII characters
• Program counter in the PIC
▫ Another important register in the PIC microcontroller is the PC.
▫ The program counter is used by the CPU to point to the address of the
next instruction to be executed.
▫ As the CPU fetches the opcode from the program ROM, the PC is
incremented automatically to point to the next instruction.
▫ The wider the program counter, more the memory locations a CPU can
access.
▫ The program counter in the PIC 18 family is 21-bit.
▫ This means that the PIC18 family can access program addresses 000000
to 1FFFFFH, a total of 2M of code.
• ROM memory map in the PIC18 family
▫ The point to remember is that no member of the PIC family can access
more than 2M of opcode.

• Example: Find the ROM memory address of each of the following
PIC chips:
a. PIC18F2220 with 4 KB
b. PIC18F2410 with 16 KB
c. PIC18F458 with 32 KB
• Solution:
a. With 4K of on-chip ROM memory space, we have 4096 bytes (4 x 1024
= 4096). This maps to address locations of 0000 to 0FFFH. Notice that 0 is
always the first location.
b. With 16K of on-chip ROM memory space, we have 16,384 bytes (16 x
1024 = 16,384),which gives 0000-3FFFH.
c. With 32K we have 32,768 bytes (32 x 1024 = 32,768). Converting 32,768
to hex, we get 8000H; therefore, the memory space is 0000 to 7FFFH.
• the PIC 18 program memory is byte-addressable, and the instructions
are either 2-byte or 4-byte. Almost all the instructions are 2-byte
instructions. The exceptions are MOVFF, GOTO, and a few others.
• MOVLW instruction formation
 The MOVLW is a 2-byte instruction. Of the 16 bits, the first 8 bits are set aside
for the opcode and the other 8 bits are used for the literal value of 00 to FFH.
• ADDLW instruction formation

• MOVWF instruction formation
▫ The LSB bit of the opcode is designated by the letter a to signify the
access from the access bank or the other bank in the 4096 location.
▫ If a= 0, the fileReg is in the access bank. If a= 1, then we have to use
bank switching.
• MOVFF instruction formation

▫ The MOVFF is a 4-byte instruction. Of the 32 bits, the first 16 bits are set
aside for the opcode and the address of the source fileReg and the other
16 bits are used for the opcode and the address of the destination.
▫ Notice that for both the source and destination parts of the instruction, 12
bits are used for the file register address of the PIC18. The 12 bits cover
the entire range of the addresses 000-FFFH for the file register, which has
4096 bytes (4K) of data RAM space.

• GOTO instruction formation
▫ The GOTO is a 4-byte (32-bit) instruction. Of the 32 bits, only 12 bits are
set aside for the opcode and the rest (20 bits) are used for the target
address of the GOTO.

• However, the 20-bit address gives us only 1 M of address space and
the PIC 18 has 2M of ROM space. This is solved by making the least-
significant bit (LSB) of the GOTO instruction 0.
• Setting the LSB of the target address to zero will make sure that the
target address is an even address. As we saw in the last section, that is
exactly what we want because all the instructions are either 2-byte or
4-byte.

PIC Microcontrollers: Chapter 4: Pic Architecture & Assembly

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PIC Microcontrollers

Chapter 4: PIC ARCHITECTURE & ASSEMBLY

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

• GPR (General-Purpose Registers or RAM)

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

• Using EQU for fixed data assignment

Gaby Abou Haidar M.S. Fall 2017 - 2018

• ADDLW instruction formation

Gaby Abou Haidar M.S. Fall 2017 - 2018

• MOVFF instruction formation

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

Gaby Abou Haidar M.S. Fall 2017 - 2018

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