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4 Semester CSE Computer Architecture (CS403)

Assignment–04(Individual) [Memory]
Last date of submission: 08/05/2019
NB:- Write the answers in your own way and do not copy from other

Write all answer [Mandatory for all]

1) Briefly describe cache coherence problem with an example. Suggest one software protocol for this.
2) Briefly explain the two write policies: write through and write back with advantages and
disadvantages
3) What is the objective of OPT page replacement algorithm policy of virtual memory? Using FIFO,
LRU and OPT show the page-fault rate for the reference string with three frames.
70120304230321201701
4) What is meant by the cache miss penalty? Briefly discuss “early restart” technique to reduce miss
penalty.
5) Let us consider a memory system consisting of main memory and cache ' memory. In case of a cache
miss, assume the performance of the basic memory organization as:
4 clock cycles to send the address. 24 clock cycles for the access time per word. 4 clock
cycles to send a word of data. (i) What will be the miss penalty, given a cache block of four words?
(ii) What will be the memory bandwidth?
6) You are asked to perform capacity planning for a two-level memory system, M 1 (cache) has three
choices: 64 KB, 128 KB and 256 KB, M 2 (Main memory) has 4 KB respectively. Given that C 1=20C2
and t2=10t1, Cache hit ratios are 0.7, 0.9 and 0.98 respectively for above three choices of M 1 a) Find
taverage in term of t1=20ns b) Find average cost of entire system of c 2 =$0.2/KB c) Compare the three
memory design.
7) A block set associative cache memory consists of 128 blocks divided into four block sets. The main
memory consists of 16384 blocks and each block contains 256 eight-bit words. i) How many bits are
required for addressing the main memory? ii) How many bits are needed to represents the TAG, SET
and WORD fields?
8) Consider a cache (M1) and memory (M2) hierarchy with the following characteristics: M1: 16K
words, 50 ns access time; M2: 1M words, 400 ns access time. Assume 8-word cache blocks and a set
size of 256 words with set-associative mapping. i) Show the mapping between M 2 and M1. ii)
Calculate the effective memory access time with a cache hit of h=0.95?

Course outcome: Learn the concept of memory hierarchy, performance and bridge speed mismatch with processor
and main memory.

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