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Fig. 4. Layout of 1-bit register implemented using D flip-flop Fig. 7. above shows that the Shift-3 Register 4-bit has
been implemented properly. The setup time needed is 118 ps,
Layout on the Fig. 4. above is implemented using CMOS rising latency is 24 ps (from falling-edge clock to rising-edge
0.12 μm technology. The total area needed is 142 lambda x QY0) and falling latency is 47 ps (from falling-edge clock to
64 lambda = 8.52 μm x 3.84 μm = 32.7168 μm2. There is no falling-edge QY0).
DRC (design rule check) error at all. The design uses 3 metal
layers. C. Booth Decoder
Fig. 11. above shows that the 4-bit Multiplexer has been
implemented properly. The setup time needed is roughly 0 ps,
rising latency is 12 ps (from 2y1_0 to rising-edge mux2_0)
and falling latency is 11 ps (from 2y1_0 to falling-edge
mux2_0).
Fig. 13. above shows that the 4-bit full adder has been
implemented properly. The setup time needed is 265 ps,
rising latency is 38 ps (from A[3] to rising-edge OUT[3]) and
falling latency is 140 ps (from A[3] to falling-edge OUT[3]).
F. 4-bit Register G. Final and Complete Design