CMOS

Digital Integrated
Circuits
Analysis and Design

Chapter 7
Combinational MOS
Logic Circuits

1
Introduction
• Combination logic circuit
– Performing Boolean operations between input and output
– Static and dynamic characteristics
• MOS depletion-load gates
– Emphasize the load concept
– NAND, NOR
• CMOS logic circuit
• CMOS transmission gates
• Transmission gate (TG) logic circuits
• In most general form
– A multiple-input, single-output system
– Using positive logic convention

2
MOS logic circuits with depletion nMOS loads

• Two-input NOR gate

– Calculation of VOH
– Calculation of VOL
– General NOR structure with multiple inputs
– Transient analysis of NOR gate
• Two-input NAND gate
– General NAND structure with multiple inputs
– Transient analysis of NOR gate

3
Two-input NOR gate

4
 Calculation of VOH, VOL
Calculation of VOH
When VA and VB are lower than threshold voltage ⇒ both off

I D ,load =
2
k n ,load
[ ]
⋅ 2 VT ,load (VOH ) ⋅ (VDD − VOH ) − (VDD − VOH ) = 0 than VOH = VDD
2

Calculation of VOL
Three case : (i)VA = VOH VB = VOL (ii)VA = VOL VB = VOH (iii)VA = VOH VB = VOH
⎛W ⎞ ⎛W ⎞
k n′ ,driver ⎜ ⎟ k n′ ,driver ⎜ ⎟
For the first two case : in case (i) k R =
k driver , A ⎝ L ⎠ A in case (ii) k = k driver , B = ⎝ L ⎠B
=
⎛W ⎞ ⎛W ⎞
R
kload kload
k n′ ,load ⎜ ⎟ k n′ ,load ⎜ ⎟
⎝ L ⎠ load ⎝ L ⎠load
⎞ ⎛
(VOH − VT 0 )2 − ⎜⎜ kload
⎟⎟ ⋅ VT ,load (VOL ) (7.4)
2
VOL = VOH − VT 0 −
⎝ k driver ⎠
If the (W/L) ratios of both drivers are identical, the two VOL will identical. In case (iii) both transistors are
turned on, the saturated load current is the sum of the two linear - mode driver currents
k
2
k
2
[
I D ,load = I D ,driverA + I D ,driverB ⇒ load VT ,load (VOL ) 2 = driver , A 2(VA − VT 0 )VOL − VOL
2 k
] [
+ driver , B 2(VB − VT 0 )VOL − VOL
2
2
]
Since the gate voltages of both driver transistors are equal, we can devise an equivalent driver - to - load ratio for the NOR structure
⎡⎛ W ⎞ ⎛ W ⎞ ⎤
k n′ ,driver ⎢⎜ ⎟ + ⎜ ⎟ ⎥
k +k ⎣⎝ L ⎠ A ⎝ L ⎠ B ⎦ V = V − V − ⎛ ⎞
(VOH − VT 0 )2 − ⎜⎜ kload ⎟ ⋅ VT ,load (VOL ) (7.8)
2
k R = driver , A driver , B = ⎟
⎛W ⎞ ⎝ k driver , A + k driver , B ⎠
OL OH T0
kload
k n′ ,load ⎜ ⎟
⎝ L ⎠ load
The VOL given by (7.8) is lower than the VOL by (7.4)
We usually set k driver , A = k driver , B = k R kload
5
Generalized NOR structure with multiple inputs
µn C ox ⎛ W ⎞
⎧
[ ]
⎪ ∑ 2 ⎜ L ⎟ 2(VGS ,k − VT 0 )Vout − Vout
2
linear
⎪ k (on ) ⎝ ⎠k
ID = ∑I =⎨
⎪ ∑ µn C ox ⎛⎜ W ⎞⎟ (VGS ,k − VT 0 )2
D ,k
k (on )
saturation
⎪⎩k (on ) 2 ⎝ L ⎠ k
VGS ,k = VGS for k = 1,2,K , n
⎧ µnCox ⎛ ⎛ W ⎞ ⎞
⎪ ⎜ ⎟
[
⎜ ∑ ⎜ ⎟ ⎟ 2(VGS − VT 0 )Vout − Vout
2
]
linear
⎪ 2 ⎝ ( )⎝ L ⎠ k ⎠
ID = ⎨
k on

⎪ µnCox ⎛⎜ ⎛⎜ W ⎞⎟ ⎞⎟(V − V )2
⎪ 2 ⎜ k∑ ⎟ GS T0 saturation
⎩ ⎝ ( on )⎝ L ⎠ k ⎠

⎛W ⎞ ⎛W ⎞
⎜ ⎟ = ∑⎜ ⎟
⎝ L ⎠ equivalent k (on )⎝ L ⎠ k

The driver: no substrate bias effect

The load: suffered substrate biased effect, VSB=Vout

6
Transient analysis of NOR gate
• The output load
capacitance
– Being valid for
simultaneous as well
as for single-input
switching
– The load capacitance
Cload will be present at
the output node even if
only one input is active
and all other input are
low
– Cload = C gd , A + C gd , B + C gd ,load + C db, A + C sb,load + C wire
7
Two-input NAND gate

8
Calculation of VOH, VOL
When both input equal to VOH ⇒ I D ,load = I D ,driverA = I D ,driverB
kload
2
2

2
[
VT ,load (VOL ) = driver , A 2(VGS , A − VT , A )VDS , A − VDS
k 2
,A = ]
k driver , B
2
[
2(VGS , B − VT , B )VDS , B − VDS
2
,B ]
Assume VT, A = VT, B = VT0
⎛ kload ⎞
(VOH − VT 0 )2 − ⎜⎜ ⎟ ⋅ VT ,load (VOL )
2
VDS , A = VOH − VT 0 − ⎟
⎝ k driver , A ⎠
⎛ kload ⎞
(VOH − VT 0 )2 − ⎜⎜ ⎟ ⋅ VT ,load (VOL )
2
VDS , B = VOH − VT 0 − ⎟
⎝ k driver , B ⎠
⎛ ⎛ kload ⎞ ⎞
⎜
VOL ≈ 2 VOH − VT 0 − (VOH − VT 0 ) − ⎜⎜
2
⎟⎟ ⋅ VT ,load (VOL ) ⎟
2

⎜ ⎝ k driver ⎠ ⎟
⎝ ⎠

2
[
I D , A = driver 2(VGS , A − VT 0 )VDS , A − VDS
k 2
,A ] k
2
[
I D , A = driver 2(VGS , B − VT 0 )VDS , B − VDS
2
,B]
I +I
I D = I D, A = I D,B = D, A D,B
2
k
4
[
I D = driver 2(VGS , B − VT 0 )(VDS , A + VDS , B ) − (VDS , A + VDS , B )
2
]
k
4
[
I D = driver 2(VGS − VT 0 )VDS − VDS 2
]
Two nMOS transistors connected in series and with the same gate voltage behave like
one nMOS transistor with keq = 0.5k driver 9
Generalized NAND structure with Multiple inputs

⎛ ⎞
⎜ ⎟
⎜ ⎟
ID =
µ nCox ⎜ 1
⋅
[ 2
]
⎟ ⎧ 2(Vin − VT 0 )Vout − Vout linear
⎨
2 ⎜⎜ 1 ⎟
⎟ ⎩(Vin − VT 0 )
2

∑
⎜ k (on )⎛⎜ W ⎞⎟
saturation

⎜ ⎟⎟
⎝ ⎝L ⎠⎠
⎛W ⎞ 1
⎜ ⎟ =
⎝ L ⎠ equivalent 1
∑
( )⎛ W ⎞
⎜ ⎟
k on

⎝ L ⎠k
⎛W ⎞ 1 ⎛W ⎞
⎜ ⎟ = ⎜ ⎟
⎝ L ⎠ equivalent n⎝ L ⎠

10
Transient analysis of NAND gate
VA = VOH and other input VB is switching from VOH to VOL
both the output voltage Vout and the internal node voltage Vx will rise
Cload = C gd ,load + C gd , A + C gd , B + C gs , A + Cdb , A + Cdb , B + Csb , A + Csb ,load + Cwire

VB is equal to VOH and VA switches from VOH to VOL

the output voltage Vout will rise, but the internal node voltage Vx will remain low
because the bottom driver transistor is on
Cload = C gd ,load + C gd , A + Cdb , A + Csb ,load + Cwire

11
Example 7.1

12
CMOS logic circuits

• CMOS NOR2 gate

• CMOS NAND2 gate
• Layout of simple CMOS logic gates

13
CMOS NOR2 gate
• Consisting
– A parallel-connected n-net
– A series-connected complementary p-net
• Operation
– Either one or both input are high
• The n-net creates a conduction path between the output node
• The p-net is cut off
• Output low, VOL=0
– Both input are low
• The n-net is cut off
• The p-net creates a conduction path between the output node and VDD
• Output high, VOH=VDD

14
The switching threshold voltage

By definition, the output voltage is equal the input voltage at the switching
threshold : VA = VB = Vout = Vth
Both transistors are saturated at this point, because VGS = VDS

then I D = k n (Vth − VT ,n ) ⇒ Vth = VT ,n +

2 ID
(7.32)
kn
At Vin = Vout , M3 in linear region, M4 in saturation region

I D3 =
kp
2
[2(V DD )
− Vth − VT , p VSD 3 − VSD
2
]
3 , I D4 =
kp
2
(V DD − Vth − VT , p − VSD 3 ) 2

ID
I D 3 = I D 4 ⇒ VDD − Vth − VT , p = 2 (7.35), Conbining (7.32) and (7.35)
kp

VT ,n +
1 kp
2 kn
(
VDD − VT , p ) VT ,n +
kp
kn
(V DD − VT , p )
Vth ( NOR 2 ) = (7.36), Vth (INR ) = (CMOS inverter)
1 kp kp
1+ 1+
2 kn kn
VDD + VT ,n
If k n = k p and VT,n = VT,p , Vth(CMOS inverter) = VDD / 2 , Vth ( NOR 2 ) = , not equal to VDD /2
3
For example : VDd = 5V, VT,n = VT,p = 1V , Vth ( NOR 2) = 2V , Vth ( INR) = 2.5V

15
The switching threshold voltage

• When both inputs are identical

– The parallel-connected nMOS transistors can be represented by a
single nMOS transistor with 2kn
– The series-connected pMOS transistors are represented by a single
pMOS transistor with kp/2
– Using the inverter switching threshold expression (7.37) for the
equivalent inverter circuit
•
VT ,n +
kp
4k n
(
VDD − VT , p )
Vth (NOR 2 ) =
kp
1+
4k n
• In order to achieve Vth=VDD/2, we have to set VT,n=|VT,p| and kp=4kn
16
CMOS NAND2 gate
• The n-net in series,
the p-net in parallel.

17
NAND2’s inverter equivalent
• Assuming (W/L)n,A=(W/L)n,B and (W/L)p,A=(W/L)p,B
– The switching threshold
•
VT ,n +
kp
kn
(V
DD − VT , p )
Vth ( NAND 2 ) =
kp
1+ 2
kn

• A threshold voltage of VDD/2 is achieved by setting VT,n=|VT,p| and

kn=4kp

18
Layout of simple CMOS logic gates

19
Stick-diagram layout of the CMOS NOR2 gate
• The stick-diagram does not carry out any information on the actual
geometry relations of the individual features, but it conveys valuable
information on the relative placement of the transistors and their
interconnections

20
Complex logic circuits
• The simple design principle of
the pull-down network
– OR operations are performed
by parallel-connected drivers
– AND operations are performed
by series-connected drivers
– Inversion is provided by the
nature of MOS circuit
operation
• If all input variables are logic
high, the equivalent-driver
(W/L) ratio of the pull-down
network
– Z = A(D + E ) + BC

⎛W ⎞ 1 1
⎜ ⎟ = +
⎝ L ⎠ equivalent 1
+
1 1
+
1
⎛W ⎞ ⎛W ⎞ ⎛W ⎞ ⎛W ⎞ ⎛W ⎞
⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ +⎜ ⎟
⎝ L ⎠ B ⎝ L ⎠C ⎝ L ⎠ A ⎝ L ⎠D ⎝ L ⎠E

21
Complex logic circuits
• For calculating the logic-low • The design objective⇒ determine
voltage level VOL the driver and load transistor
– The value of VOL depends on the size→ achieves the specified VOL
number and the configuration of value even in the worst case
the conducting nMOS transistors • Three worst-case paths
– Assigning a class number which – ⎛W ⎞ ⎛W ⎞ ⎛W ⎞
reflects the total resistance of the ⎜ ⎟ = ⎜ ⎟ = 2⎜ ⎟
⎝L ⎠ A ⎝ L ⎠D ⎝ L ⎠ driver
current path from Vout node to
ground ⎛W ⎞ ⎛W ⎞ ⎛W ⎞
⎜ ⎟ = ⎜ ⎟ = 2⎜ ⎟
• A-D ⇒ class 1 ⇒ highest series ⎝L ⎠ A ⎝ L ⎠E ⎝ L ⎠ driver
resistance ⎛W ⎞ ⎛W ⎞ ⎛W ⎞
⎜ ⎟ = ⎜ ⎟ = 2⎜ ⎟
• A-E ⇒ class 1⇒ highest series ⎝ L ⎠ B ⎝ L ⎠C ⎝ L ⎠ driver
resistance
• B-C ⇒ class 1⇒ highest series – Guarantee all other input ⇒
resistance output low will less than VOL
• A-D-E ⇒ class 2
• A-D-B-C ⇒ class 3
• A-E-B-C ⇒ class 3
• A-D-E-B-C ⇒ class 4
• VOL1>VOL2>VOL3>VOL4
• We usually start by specifying a
maximum VOL value

22
Complex CMOS logic gates
• The pMOS pull-up network
– Must be the dual network of the n-net
• nMOS parallel ⇒ pMOS series
• nMOS series ⇒ pMOS parallel

23
Stick-diagram, with arbitrary ordering of poly-Si
• The stick diagram layout ⇒ a “first attempt”
• An arbitrary ordering of the polysilicon gate column
– The separation between polysilicon must be allow
• One diffusion-to-diffusion separation
• Two metal-to-diffusion contacts
– Consuming area

24
Stick-diagram, Euler path approach

• Find a Euler-path in the pull-down graph and a Euler path in the pull-up graph with
identical ordering of input labels
• The Euler path is defined as an uninterrupted path that traverses each edge (branch)
of the graph exactly once
– E-D-A-B-C
• The polysilicon column separation has to allow
– Only metal-to-diffusion contact
• More compact layout area, simple routing of signals, less parasitic capacitance

25
Full CMOS implementation of XOR

• Two additional inverter are needed

• Total 12 transistors

26
AOI and OAI gates

• The AOI gates

– Enable the sum-of-products realization of a Boolean function in
one logic stage
• The OAI gates
– Enable the product-of-sums realization of a Boolean function in
one logic stage

27
Psuedo-nMOS gates
• CMOS gates ⇒ large area
• Pseudo-nMOS
– To reduce the number of
transistors
– To use a single pMOS transistor
as the load device
• with its gate terminal connected to
ground
– Disadvantage
• Nonzero static power dissipation
– As the Vout is lower than VDD ⇒ the always-on pMOS load
device conducts a steady state current
• The value of VOL and the noise margins
– Determining by the ratio of pMOS transconductance load to
driver transconductance

28
Example 7.2

29
CMOS full-adder circuit_gate level
• The carry_out signal to generate the sum output
– Reduce the circuit complexity
– Save chip area
sum _ out = A ⊕ B ⊕ C
= ABC + A B C + A BC + AC B
carry _ out = AB + AC + BC

30
CMOS full-adder circuit

31
CMOS transmission gates (pass gates)
• Consisting of one nMOS and one pMOS transistor, connected in parallel
• The gate voltage applied to these two transistors are also set to be
complementary signals
• A bidirectional switch between nodes A and B which is controlled by signal
C
– If signal C is logic high
• Low-resistance current path between the nodes A and B
– If the signal C is low
• Both transistors will be off
• Both transistors must take into account the substrate-bias effect

32
Carry ripple adder
• N-bit binary adder
– The full adder as the basic building block
– Two n-bit binary numbers as input and produces the binary sum
at the output
– The overall speed of the carry ripple adder is obviously limited by
• The delay of the carry bits rippling through the carry chain
• A fast carry_out response become essential
• Critical path

33
CMOS transmission gates (pass gates)
• Consisting of one nMOS and
one pMOS transistor,
connected in parallel
• The gate voltage
– Complementary signal to the
two transistors
• Bidirectional switch between A
and B, controlled by C
– Signal C is logic-high
• Both transistors turn on, low
resistance current path
– Signal C is logic-low
• Both transistors turn off, open,
high-impedance state
– Substrate terminal
• nMOS⇒ ground, pMOS ⇒
VDD
• Must consider body effect

34
 CMOS transmission gates (pass gates)

Vin = VDD , The control signal is logic - high, the output node may be connected to a capacitor
For nMOS transistor ⇒ VDS,n = VDD -Vout , VGSn = VDD -Vout
The nMOS will turn off for Vout > VDD -VT,n and operate in the saturation for Vout < VDD -VT,n
For pMOS transistor ⇒ VDS,p = Vout -VDD , VGS,p = -VDD
The pMOS is in saturation for Vout < VT,p , in linear region for Vout > VT,p ,pMOS remains turn on, regardless of the Vout
The total current : I D = I DS,n + I SD,p
VDD -Vout V -V
equivalent resistance : Req,n = , Req,p = DD out , The total resistance = Req,n Req,p
I DS,n I SD,p

Region 1
2(VDD -Vout ) 2(VDD -Vout )
Vout < VT,p ⇒ both transistor in saturation, Req,n = , Req,p =
k n (VDD − Vout − VT ,n )
2
(
k p VDD − VT , p )2

note that VSB,n = Vout , VSB,p = 0 ⇒ nMOS should take into account the sbustrate - bias effect

Region 2
VT, p < Vout < (VDD − VT ,n ) ⇒ pMOS linear region, nMOS saturation region
2(VDD -Vout ) 2(VDD -Vout ) 2
Req,n =
k n (VDD − Vout − VT ,n )
2
, Req,p =
[( ) (
k p 2 VDD − VT , p (VDD -Vout ) − VDD − VT , p )]
2
=
[( ) ]
k p 2 VDD − VT , p − (VDD − Vout )

Region 3
Vout > (VDD − VT ,n ) ⇒ pMOS linear region, nMOS off
2
Req,p =
[( )
k p 2 VDD − VT , p − (VDD − Vout ) ]
35
Replacing the CMOS TG with its resistor equivalent
• The total equivalent resistance of the TG
remains relatively constant
– Its value is almost independent of the output voltage
• Whereas the individual equivalent resistances are strongly
dependent on Vout
– A CMOS TG can be replaced by its simple equivalent
resistance for dynamic analysis

36
Two input multiplexer
• The implement of CMOS transmission gates in logic circuit design
– Compact circuit structures, requires a smaller number of transistors
– The control signal and its complement must be available simultaneously
for TG applications
• Two input multiplexer
– If the control input S is logic high
• The bottom TG conduct ⇒ output equal to the input B
– If the control input S is logic low
• The top TG conduct ⇒ output equal to the input A

37
XOR

38
CMOS TG realization of a three-variable Boolean
function

39
Complementary pass-transistor logic (CPL)
• The main idea behind CPL is to use a purely nMOS pass-transistor
network for the logic operations, instead of a CMOS TG network
– All input are applied in complementary form
– The circuit also produces complementary outputs, to be used by
subsequent CPL stage
– The CPL circuit consisting
• Complementary input
• An nMOS pass transistor logic network to generate complementary outputs
• CMOS output inverter to restore the output signal

40
Complementary pass-transistor logic
• The elimination of pMOS transistors from
the pass-gate network
– Reducing the parasitic capacitances
– Higher operation speed
– Process complexity
• The Vt,n must be reduced to about 0V through
threshold-adjustment implants
– Reducing the overall noise immunity
– Making the transistors more susceptible to subthreshold
conduction in the off-mode
– The CPL design style is highly modular
• A wide range of functions can be realized by using
the same basic pass-transistor structures
41
Regarding the transistor count
• CPL circuits do not always offer a marked advantage over conventional
CMOS
• NAND2, NOR2⇒8 transistors
• XOR, XNOR functions realized with CPL have a similar complexity as
CMOS realizations
– The cross-coupled pMOS pull-up transistors are used to speed up the output
response
• Full adder
– The same observation is true for the realization with CPL
– consisting of 32 transistors

42