Dr. Vikas Maheshwari, Ph.D.

Associate Professor, Dept of ECE

Bharat Institute of Engineering and Technology
Ibrahimpatnam, Dist Ranga-Reddy, Telangana State
maheshwarivikas1982@gmail.com, mob:9818467308

Statement of Research
My research interest includes Analog VLSI Design, VLSI interconnect modeling and
optimization, and Antenna Design & optimization. During my M.Tech. program, I was
introduced the fundamental and conceptual study about VLSI design domain thoroughly. As
I had done APGD in VLSI from semi-conductor laboratory, mohali, so I have a great desire
to do something in this field. My MTech. Project is titled as “Estimation of Delay, Power
and Bandwidth for on-chip VLSI global interconnects” which gave me the indepth
knowledge about VLSI global interconnect. I also completed my PhD in the same research
area with thesis titled as “Performance Parameters’ Estimation of On-Chip VLSI
Interconnections “. In addition, I was in charge of mentoring a couple of master's students
during my PhD. I also gave tutorials on my research to an audience, unfamiliar with my area
of research. I have published 56 International Journals and 50 IEEE International Conference
papers mostly in the area of on-chip VLSI global interconnects.

Research Activity: Most of my research area is focused on VLSI global interconnects having
three sub-sections discussed as bellow:

• RC Tree Model: In this section the research work is focussed on the delay, slew and
crosstalk calculation based on moment matching technique using two and three
moments of the impulse response of the RC systems.
• RLC Tree Model: In this section the importance and extraction of on-chip
inductance is discussed. It also contains the delay calculation model, crosstalk
including inductive and capacitive coupling for both step as well as ramp inputs.
Instead of that the performance of the distributed RLC interconnect lines are studied
under skin-effects, fringing effect etc.
• RLCG Tree Model: This section contains the importance of the RLCG model, basic
theory about crosstalk, glitch and modes. This section describes the modelling of
crosstalk, coupling aware delay, bandwidth.

Presently supervising two PhD candidates in the research field of Microelectronics and
VLSI (ECE) as a co-supervisor. Details are as bellow:
• Mr Thakurendra Singh Solanki
University: GLA University Mathura, U.P. India
Registered Year: 2018
• Mr S. Somashekhar
University: Sri Satya Sai University of Technology & Medical Sciences Sehore, M.P.
Registered Year: 2017.

Patent Applied/Published: Somashekhar Malipatil, Vikas Maheshwari, Rajendra R Patil,

Sharangouda Nawaldagi, “System and Method for Identification of Futuristic faults in the Digital
Systems”, Application number 202021005603A filed and published. The patent office Journal
No.07/2020 dated 14.02.2020.
Future Research Plan: To enhance the knowledge and skill of the PG, UG students/
faculties in the field of Microelectronics and VLSI Design, I want to establish a Centre of
Excellence with the collaboration with industries having Integrated circuits simulation and
VLSI design laboratory with all the modern EDA tools e.g. CADENCE, SYNOPSYS,
Mentor Graphics, XILINX based gate array design & programming tools, etc. with adequate
hardware in the form of servers and good number of workstations for research and course
work. I am highly interested in carrying out a number of long-term research directions
regarding the issues of fault detection, execution reconfiguration and communication cost
reduction in nanoelectronics systems design. Under the banner of Centre of Excellence, I will
try to provide a platform for the UG, PG students and faculties to interact with other experts
in their area of specialization within India and abroad which provide an opportunity for others
to understand the research quality and also pave way for scientific collaboration.
I believe that I have the qualities to be a good researcher and teacher. I
am a creative person and often think in a contemplative way about various issues of practical
importance. Being able to identify patterns and relationships that are not obvious to others is
perhaps my greatest strength. This will prove very valuable because an integral part of being
a researcher and teacher is to perceive the balance between theory and practice, analytical
rigor and intuition. My communication skills are good and I like expressing ideas and
concepts both in oral and written form - an ideal platform for the dissemination of knowledge
in my chosen field of specialization. I hope you will take a favourable decision regarding my
candidature as a faculty in your esteemed organization.

Yours sincerely,
Dr. Vikas Maheshwari