qa Address

NA-109, ECE Dett,

Bharat Institute of Engineering and Technology
Mangalpally(V), Ibrahimpatnam(M), R.R. (Dist)
Telangana State, India-501510
Mob. 9818467308, 8982508376, 7017007350
E-mail: maheshwarivikas1982@gmail.com

DR. VIKAS MAHESHWARI MIEEE, MISTE,MIACSIT, MITCHEE....

To optimize the utilization of my technical and professional skills to nurture my career to the
Objective peak of responsibilities, and always be a learner to everything new.

Doctoral’s Degree (Ph.D.) in Microelectronics & VLSI Design from NATIONAL

Academics INSTITUTE OF TECHNOLOGY, Durgapur, West-Bengal.
Registration No: NITD/PhD/ECE/2011/00322.
Awarded in June, 2014.
Title of the Thesis: Performance Parameters’ Estimation of On-Chip VLSI Interconnections.

Master’s Degree in Technology (M.Tech.) in Microelectronics & VLSI Design from

NATIONAL INSTITUTE OF TECHNOLOGY, Durgapur, West Bengal.
Completed in May 2010 with aggregate 9.44 cgpa (at the scale of cgpa 10).

Advanced Post-Graduate Diploma (APGD) in VLSI Design from VEDANT Center,

Semi-Conductor Laboratory, Mohali, Punjab (Deptt. of Space, Govt. of India).
Completed in June 2007.
Modules: Verilog, ASIC, FPGA, CMOS, Electronic Design Technique, Static Timing Analysis.

Bachelor’s Degree in Technology (B.Tech.) in Electronics & Communication

Engineering from UP Technical University, Lucknow, Uttar-Pradesh.
Completed in June 2006 with aggregate 66.81%.

Intermediate from UP State Board

Completed in June 2000 with distinction (aggregate 79.20%).

H. S. C. from UP State Board

Completed in June 1998 with aggregate 72.16%.

• Working as an Associate Professor in Electronics and Communication Department in

Academic Exp. Bharat Institute of Engineering and Technology, Ibrahimpatnam, Hyderabad,
Telangana since 10th Feb, 2017.
Job Profile:
• Training In charge- Presently I am holding the position of Training In Charge of the
department since April 2018. My key role is to arrange pre-placement training and
GATE classes to the ECE department students from IInd year onwards by allocating the
subjects to be taught by individual faculty and monitoring their performance. I also
introduced the concept of free in-house summer training classes in the department and
successfully implemented and monitored the training for all the ECE students of IInd,
IIIrd and IVth year students for the consecutive two academic sessions for 2017-18 and
2018-19 in the month of June. I arranged guest lectures from the industry experts and
also arranged industrial tours to companies like Infosys, ACD Communication and other
Govt. organizations.
• Academic In charge-Worked as an Academic In charge of the ECE department for
almost one and half year. My key role was during academic in-charge position was to
 collaborate with fellow Prof./Associate, Professors/Assistant Professors on lesson plans,
time table, workload distribution and performed administrative tasks to enhance
classroom learning environment and acting as a facilitator to promote student leadership
in initiating and creating positive learning opportunities.

• Worked as an Assistant Professor-II in Electronics and Communication Department in

Amity School of Engineering and Technology, Amity University Madhya-Pradesh,
Gwalior, M.P. since 16TH Feb, 2015 to 9th December 2016.

• Worked as an Assistant Professor in Electronics and Communication Department in

School of Engineering and Technology, Apeejay Stya University, Sohna, Gurgaon,
Haryana since 9TH august, 2012 to 9th Feb 2015.

• Worked as an Assistant Professor for 2 Year in Electronics and Communication

Department in Sharda Group of Institutions Agra, U.P. since 7TH August, 2010 to
12TH July, 2012 as follows:
• Worked as an Assistant Professor in Electronics and Communication Department
in Anand Engineering College, Agra Affiliated to U.P. Technical University,
Lucknow, U.P. since 16TH January, 2012 to 12TH July, 2012.
• Worked as an Assistant Professor in Electronics and Communication Department
in Hindustan College of Science and Technology, Mathura affiliated to U.P.
Technical University, Lucknow, U.P. since 7TH Aug, 2010 to 15TH January, 2012.
Job Profile:
• M.Tech. Class Teacher- Worked as Class Teacher for the program of M. Tech (VLSI
DESIGN). My core responsibilities was to administrate the department by allocating the
subjects to be taught by individual faculty and monitoring their performance, managing
quality of the education for this program by conducting counseling sessions, seminars
etc. and guiding the students in all the ways to meet the high-end industrial
requirements.
• CAD/PG Lab In charge- Re-installed the ECE Cad lab with all the latest educational
software and tools. I usually interacted with Faculty and students regarding the
Laboratory problems/suggestions and based on that instructed lab staff to update
instruction manuals.

• Worked as Teaching Assistant for 1.5 year for senior faculty in ECE Deptt, National
Institute of Technology Durgapur West-Bengal from 27th Feb, 2009 to 25th June,
2010.
Subjects Taught: Basic Electronics, Analog Electronics. VLSI Lab for UG Students

• Worked as a lecturer for 1 Year in Electronics Department in Institute of Engineering

& Technology, Agra affiliated to Dr. B.R. Ambedkar University, Agra (formerly
Agra University, Agra) from 16th July,2007 to 19th July,2008.

Patent
Patent Applied/Published
Somashekhar Malipatil, Vikas Maheshwari, Rajendra R Patil, Sharangouda Nawaldagi,
“System and Method for Identification of Futuristic faults in the Digital Systems”, Application
number 202021005603A filed and published. The patent office Journal No.07/2020 dated
14.02.2020.
Abstract : The present invention relates to a system and method for fault diagnosis for fault
identification in industrial applications wherein proposed system is bifurcated in two parts; in
the first part industrial process control system is continuously observed for the performance,
which is compared with the default parameters and the data set to which the process control
system is calibrated and trained. The comparison output is considering as input to the system,
the FPGA-based system monitors the degree of variations with respect to the expected outcome
if there is any variations in the performance, it is noted in the list of the new data set and is used
 as input to the process control system for calibrations and in second part the newly created data
base is used for fault diagnosis, fault correction and estimating life span of the machine.
Following invention described in detail with the help of figure 1 of sheet 1 shows block
diagram of proposed invention.

Grant Received • Got the Grant and Sanction of Rs.500000 under AQIS Scheme from AICTE New Delhi
for organizing of two days National Conference in ECE Department, Bharat Institute
of Engineering And TECHNOLOGY Hyderabad, Telangana.

Achievements • Organized AICTE Sponsored Two Days National Conference on Recent Advances and
Challenges in Electronics and Hardware Design (RACE-2020) as a Convener in ECE
Department, Bharat Institute of Engineering And TECHNOLOGY Hyderabad,
Telangana on 28th-29th February, 2020.
• NAAC (BIET) and NBA(Department of ECE) committee member IN 2018-19 at
Bharat institute of Engineering and Technology.
• Mentor the Team of BIET and presented and Innovative solution/Prototype in the Final
of National Convention of 2nd AICTE-ECI-ISTE Chhatra Vishwakarma Awards
held on 20-21 January 2019 at AICTE New Delhi with the title ”Automatic Weed
Digger” i.e An Agriculture Assistant System(Robot).
• Mentor the Team for AICTE-ECI-ISTE Chhatra Vishwakarma Awards 2018 and
got Fourth Rank at Regional Level at Bhimavaram (SRKR Engineering College,
Bhimavaram, A.P) under the Theme of “Empowerment of Villages through
Technologies” with Subtheme Agriculture and Food.
• Qualified in GATE-2010 with score 467. (94.91 Percentile).
• Teaching Assistance for senior faculty in M.Tech. from January 2009 to May 2010.
• Got Scholarship of Rs 8000/- per month from MHRD, New Delhi.
• Qualified in GATE-2007 with score 286. (81.25 Percentile).
• School Topper in Intermediate and High School Exams.

Professional • Life Member of ISTE.

Membership • IEEE Member
• Editor of ICSES Transactions on Computer Hardware and Electrical Engineering, Iran.
• Committee, Scientific and Technical Committee and Editorial Review Board Member of
World Academy of Science, Engineering and Technology (WASET), USA.
• Member of International Computer Science and Engineering Society (ICSES), Iran.
• Reviewer of Alexandria Engineering Journal, Elsevier, Egypt.
• Reviewer of Microelectronics Journal, Elsevier, USA.
• Lifetime Member of IACSIT, Singapore (Member NO. : 80340954)
• Editorial Board Member of Blue Eyes Intelligence Engineering & Sciences
Publication Pvt. Ltd., India.
• International Journal of Soft Computing and Engineering (IJSCE).
• International Journal of Engineering and Advanced Technology (IJEAT).
• International Journal of Recent Technology and Engineering (IJRTE).
• International Journal of Innovative Technology and Exploring Engineering.
• International Journal of Innovative Science and Modern Engineering (IJISME).
• International Journal of Advanced Engineering and Nano Technology (IJAENT).
• International Journal of Inventive Engineering and Sciences (IJIES).
• International Journal of Emerging Science and Engineering (IJESE).
• Reviewer/ Member of IJEECSE, India (ISSN-2348-2273).
• Reviewer/ Member of IJICAR, INDIA (ISSN-2395-4310).
• Editorial Board Member of IJESE, India (ISSN: 2319–6378).

Ph.D Thesis supervision: Presently supervising two PhD candidates in the research field of
PhD Supervision Microelectronics and VLSI (ECE) as a co-supervisor. Details are as bellow:
Undergoing • Mr Thakurendra Singh Solanki
 University: GLA University Mathura, U.P. India
Registered Year: 2018
• Mr S. Somashekhar
University: Sri Satya Sai University of Technology & Medical Sciences Sehore, M.P.
Registered Year: 2017

M.Tech Thesis M.Tech Thesis supervised : Following thesises are successfully defended and awarded in
Supervised the field of Microelectronics and VLSI for the programme M.Tech.-VLSI affiliated by
• G.B.Technical University, Lucknow, U.P., INDIA.
• Efficient Synthesis Methodology for Heterogeneous Multiprocessor Chip.
Student: Anuj Sharma Enrollment No.: 030012100143
• Coupling Aware Explicit Delay Metric For On Chip RLCG Interconnect For Ramp
Input
Student: Hemlata Yadav Enrollment No.: 020643112993
• Modified Built In Self Test Algorithm (8n) For Memory Testing
Student: Supriya Agarwal Enrollment No.: 031393128288
• An Explicit Approach For Modelling Of On Chip VLSI Global Interconnects
Student: Sumita Gupta Enrollment No.: 020023100524
• Design of Analog Filters using Folded Cascode OTA in 180 nm CMOS Technology
Student: Rahul Katiyar Enrollment No.: 064MT/04/2006
• Design And Implementation Of Bist For Ram
Student: Deshraj Singh Enrollment No.: 064MT/07/2008
• Design and Implementation of JTAG TAP Controller using FPGA
Student: Sanjay Chahar Enrollment No: 064MT/11/2008
• An Explicit Approach for Digital Image Compression using Discrete Cosine Transform
Student: Shruti Mittal Enrollment No.: 040643113870
• Analysis and Design of Low Noise Amplifier
Student: Vimal Yadav Enrollment No.:
• Design of High Speed, Low Power BiCMOS Circuits and Comparision with CMOS
Technology
Student: Abhisheke Mittal Enrollment No.: 240013100509
• Modeling and Analysis of On-Chip High Speed VLSI RLC Interconnections with
Mutual Inductance
Student: Apoorva Gupta Enrollment No.: 050013100273

• J.N.T.U. Hyderabad, Hyderabad, Telangana State., INDIA.

• Low Power Carry Save Adder Multiplier using Domino Logic
Student: Banavath Rajendhar Enrollment No.: 15E11D5701

Other Academic • Appointment as examiner for Spot Valuation at University Examination Branch for
M.Tech answer scripts of subject “CMOS Mixed Signal Circuit Design” by JNTUH
Responsibilities
Hyderabad, Telangana.
• Organized a online hands on workshop on “VLSI Design using Verilog HDL” in
association with Maven Silicon, Bangalore on 19/06/2019 in Department of Electronics
and Communication Engineering at Bharat Institute OF Engineering And Technology,
Hyderabad.
• Acted Seminar Advisor for one day seminar on “Current and Future Radar
Technologies” organized by Department of Electronics and Communication
Engineering in collaboration with senior Scientists of DRDO Ministry of Defence on
16th February 2018 at Bharat Institute OF Engineering And Technology, Hyderabad.
• Served as one of the Technical Programme Committee Member in National Seminar
on “ Communication, Network and Cyber Security (CNCS-2016)” organized by Amity
School of Engineering & Technology, Amity University Madhya-Pradesh, Gwalior,
M.P. held on 13-14 April 2016.
 • Served as one of the Technical Programme Committee Member in National
Conference on “Emerging Trends in Engineering & Technology” organized by Apeejay
Stya University, Gurgaon, Haryana held on May 3, 2014.
• Appointed as Member of Flying Squade team by G.B. Technical University, Lucknow,
U.P. in the session year May-June Exam 2011-2012.
• Appointed as one of the Deputy Head Evaluator by G.B. Technical University,
Lucknow, U.P. in the session year May-June Exam 2011-2012.
• Served as a one of the Editorial Board Member in National Conference on Emerging
Trends in Electrical, Instrumentation & Communication Engineering (ETEIC-2012)
organized by Anand Engineering College, Keetham, Agra, U.P. held on April 6-7, 2012.
• Appointed as Member of Flying Squade team by G.B. Technical University, Lucknow,
U.P. in the session year May-June Exam 2012-2013.

Workshops/Semi • One Week short term training Programme (STTP-2K19) for “Integration and control
nar/FDPs of Embedded Electrical Systems” in collaboration with NI Systems organized by
Department of Electrical and Electronics Engineering, BIET from 11th – 16th March
2019.
• Two day National Workshop on “Preparing for NBA Accreditation & SAR filing” in
Mechanical Engineering Department, JNTUH College of Engineering, Hyderabad,
during 18th and 19th February 2019.
• One week AICTE Sponsored Short term Course on “Digital system Design” through
ICT conducted by Electronics and Communication Engineering Department, BIET from
28th Jan 2019 to 1st February 2019.
• Attended Two Day National Level Seminar on “Deep Learning for Cancer Diagnosis
Using Python” conducted during 29th and 30th June 2018 by the department of
Computer Science and Engineering, Bharat Institute of Engineering and Technology,
Hyderabad.
• One day Seminar attended on “ Current and Future Radar Technologies” organized
by Department of Electronics and Communication Engineering in collaboration with
senior Scientists of DRDO Ministry of Defence on 16th February 2018 at Bharat
Institute of Engineering and Technology, Hyderabad.
• Two weeks Faculty Development Program on RF and Microwave Antenna Design
Organized by Department of Electronics and Communication Engineering at Bharat
Institute of Engineering and Technology from 27TH November to 9th December 2017.
• Two days Workshop on MATLAB Programming for Advanced Learners Organized
by Department of Electronics and Communication Engineering at Bharat Institute of
Engineering and Technology from 22nd – 23rd March 2017.
• Participated in national seminar on “Emerging Trends in Manufacturing &
Automation Engineering (NSMAE-2015)” organized by Amity School of Engineering
& technology, Amity University Madhya-Pradesh, Gwalior, M.P. held on 9-10 October
2015.
• Participated in IEEE international conference on “Communication Systems and
Network Technologies (IEEE CSNT-2015)” held at Gwalior, M.P. on 4-6 April 2015.
• Participated in international conference on “Recent Trends and Innovation in Social
Sciences, Management & Technology (RTISSMT-2015)” held at Dr. K.N. Modi
University, Newai, Rajasthan on 21 March, 2015.
• One day National Seminar on “MATLAB and Simulink in Engineering Education”
organized by University School of Communication and Information Technology,
GGSIP University, Dwarka, New Delhi held on 16TH April, 2014.
• Two days workshop attended on “Open Education Resources (OER)” Organized by
School of Engineering and Technology, Apeejay Stya University, Gurgaon, Haryana
held on April 26-28, 2013.
• Five days workshop attended on “MATLAB” organized by School of Engineering and
Technology, Apeejay Stya University, Gurgaon, Haryana.
• One day workshop attended on “Low Power VLSI Design” Organized by IEEE
Computer Society, BITS Pilani, Hyderabad Campus, Hyderabad, Andhra Pradesh held
 on 5TH December, 2012.
• Twenty days Faculty Development Programme conducted at B.M.A.S. Engineering
College, Agra, U.P. from 17 July to 07 August 2010.
• One day national conference on “Advances in Information Technology”, organized by
Institute of Engineering and Technology, Khandari Campus, Agra U.P. held February16,
2008.

Skill Summary EDA TOOLS

• Simulation: NCsim (Cadence), Modelsim (Mentor Graphics), Quartus-II (Altera).
• Synthesis: ISE Web pack 14.7i (Xilinx) Quartus-II (Altera), RTL Compiler (Cadence).
• Physical Synthesis and Place & Route: SOC Encounter (Cadence).
• FPGA implementation tools: Quartus-II (Altera), ISE Web pack 14.7i (Xilinx).
• Schematic Editor: Virtuoso Schematic Composer (Cadence).
• Simulation: using Spectre in Analog design environment (Cadence).
• Layout: Virtuoso Layout Editor (Cadence).
• Physical Verifications (LVS, DRC, RCX): Assura (Cadence).
• Hardware description Languages: Verilog HDL,

Academic Project Ph.D Thesis : Performance Parameters’ Estimation of On-Chip VLSI Interconnections
Description : This thesis discusses among the modelling and the design methodology of on-chip
high-performance interconnection. Today’s high speed VLSI technologies integrate more than
several million transistors on a chip using deep submicron fabrication processes. Modern
technology has demonstrated a continuous trend toward faster circuits, larger die sizes, shorter
rise times, and smaller pulse width. With these technology trends, it is said that on-chip
interconnect inductance effects, such as delay increase, overshoot, and inductive crosstalk, can
no longer be ignored. This work proposes a difference model approach to derive the expression
for delay for RLC and RLCG transmission line interconnects. In this thesis some of the
problems like inductive effect, capacitive effect, skin effect, crosstalk including inductive and
capacitive coupling and the interconnect models used to represent these problems, will be
discussed. This thesis will also attempt to introduce some solutions and different performance
analysis techniques to alleviate these problems.

M.Tech Major Project : Estimation of Delay, Power and Bandwidth for On-Chip VLSI
Global Interconnects
Description :This work discusses about the different interconnect models as RC, RLC and
RLCG transmission line model and different techniques that are very much usefull for the
estimation of delay, power and bandwidth of global interconnects.For the calculation of delay
for RC interconnect we used moment matching technique. A brief analytical model is presented
for calculation of delay and power of RLC interconnects. The phase of work proposed a
distributed RLCG transmission model of interconnect using difference model approach.

M.Tech Mini Project :Design of Analog Amplifier in 0.18 µm CMOS Technology using
Gm/Id technique
Description: This project is aimed to design analog amplifiers and comperators in 180 nm
CMOS technology using Gm/Id technique. In this methodology, we consider the relationship
between the ratio of the transconductance gm over DC drain current ID and the normalized drain
current ID/(W/L) as a fundamental design relation to explore the design space. The main
advantage of the Gm/Id design technique is the simple sizing method based on the transistor
inversion coefficient, which is calculated by a single technology specific characteristic curve
Gm/Id versus ID/(W/L). The circuit is composed in Virtuoso Schematic Editor (Cadance) and its
results are simulated by using Spectre (Cadance).

APDG Project : D-Register using CMOS Technology.

Description : This project aimed to calculate the set-up time, hold time and the clock to Q time
(tcq) of D-Register which is implemented by using the mux based latches. The circuit is
composed in Virtuoso Schematic Editor (Cadance) and its results are simulated by using Spectre
 (Cadance), then its layout is composed by using Virtouso Layout Editor and it is verified by
Assura (Cadance).

APDG Project : Static Random Access Memory Cell.

Description:In this project we made a memory cell by using the CMOS inverters
connecting back to back. We use the sense amplifier for read operation. Word line and bit lines
are used for selecting the cell. Pre-charge circuit is used for increasing the speed of the memory
access time. This project is done on the Virtuoso Schematic Composer.

B.Tech Project : Text Data Transmission Through Optical Fibre using CDMA Technology.
Description : One way or Two way optical communication system using a short wavelength
visible laser diode as the light emitting element and optical fibre for long distance as the
transmission media and a photodiode as receiving element. In CDMA Technology data is
transmitted with code. Receiver circuit receives the data only when code is macthed.

Company : DOEACC Centre-Gorakhpur (formerly CEDTI, Gorakhpur,U.P.)

Summer Training Tranning : Embedded Systems
Duration : One Month

Seminar • Seminar presented on “Analysis and Design of Amplifiers and Comparators in

CMOS 0.18 µm Technology” at college level in M.Tech.
• Seminar presented on “Delay-Estimation for On-Chip VLSI Interconnect using
Gamma Distribution Function” at college level in M.Tech.
• Seminar presented on “Determination of discrete frequency components of
continous waves by using Lissajous pattern” at college level in B.Tech.

Research Papers
National Conference/Journal Publications
1. Vikas Maheshwari,” Modeling of VLSI ASIC for Automotive Applications with
Recurrent Networks”, National Seminar on Emerging Trends in manufacturing &
Automation Engineering (NSMAE-2016) organized by Amity School of Engineering
and Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held during 29-30
September 2016.

2. Vikas Maheshwari,” Modeling of Vending Machine Controller with Auto-Billing

Features based on Finite State Machine”, National Seminar on Emerging Trends in
manufacturing & Automation Engineering (NSMAE-2016) organized by Amity School
of Engineering and Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held
during 29-30 September 2016.

3. Vikas Maheshwari,” Development of a Custom Microprocessor for Automotive

Control”, National Seminar on Emerging Trends in manufacturing & Automation
Engineering (NSMAE-2016) organized by Amity School of Engineering and
Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held during 29-30
September 2016.

4. Vikas Maheshwari,” Design of Automatic Front Lighting System in Automobiles

based on FPGA”, National Seminar on Emerging Trends in manufacturing &
Automation Engineering (NSMAE-2016) organized by Amity School of Engineering
and Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held during 29-30
September 2016.

5. Amar Baboo, Vikas Maheshwari, “Analytical Delay and Threshold Voltage Models ”,
National Seminar on Advances in Computer Networks, Communication and Security
organized by Amity School of Engineering and Technology, Amity University Madhya-
Pradesh, Gwalior, M.P. held during 13-14 April 2016.
6. Vikas Maheshwari, “Peak Crosstalk Voltage Model”, National Seminar on Advances
in Computer Networks, Communication and Security organized by Amity School of
Engineering and Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held
during 13-14 April 2016.

7. Vikas Maheshwari, Apoorva Gupta, “Crosstalk Noise and Delay Analysis of High
Speed On-Chip Global RLC VLSI Interconnects”, National Seminar on Advances in
Computer Networks, Communication and Security organized by Amity School of
Engineering and Technology, Amity University Madhya-Pradesh, Gwalior, M.P. held
during 26-27 February 2015.

8. Vikas Maheshwari, Neha Gupta, “ Delay and Slew Modeling for On-Chip VLSI RC
Global Interconnect for Ramp Input using Three Circuit Moments”, National
Conference on Emerging Trends in Engineering & Technology organized by Apeejay
Stya University, Gurgaon, Haryana, May 3, 2014.

9. Vikas Maheshwari, Neha Gupta, “Stability Analysis for On-Chip High Speed
Interconnection Network”, National Conference on Emerging Trends in Engineering &
Technology organized by Apeejay Stya University, Gurgaon, Haryana, May 3, 2014.

10. Vishal Goel, Vikas Maheshwari, “Simulated Models for RLC Interconnect Crosstalk
Glitches and Delay Noise Effects”, National Conference on Emerging Trends in
Engineering & Technology organized by Apeejay Stya University, Gurgaon, Haryana,
May 3, 2014.

11. Vishal Goel, Vikas Maheshwari, “Analytical Crosstalk Noise Estimation for
Capacitively Coupled RLCG On-Chip Interconnects”, National Conference on
Emerging Trends in Engineering & Technology organized by Apeejay Stya University,
Gurgaon, Haryana, May 3, 2014.

12. Vikas Maheshwari, Alka Goyal, Prabhakar Sharma, Sampath Kumar, Vimal K. Yadav,
“Closed Form Expressions for Delay to Ramp Inputs for On-Chip VLSI RC
Interconnect”, National Conference on Emerging Trends in Electrical, Instrumentation
& Communication Engineering (ETEIC), Agra, U.P., India, pp.504-509, April 6-7,
2012.

13. Vikas Maheshwari, Alka Goyal, Prabhakar Sharma, Vimal K. Yadav, Sampath Kumar,
“Closed Form Expressions for Extending Step Slew Metrics to Ramp Inputs for On-
Chip VLSI RC Global Interconnect”, National Conference on Emerging Trends in
Electrical, Instrumentation & Communication Engineering (ETEIC-2012), Agra, U.P.,
India, pp. 510-515, April 6-7, 2012.

14. Prabhakar Sharma, Shilpa Sharma, Vikas Maheshwari, Ravi Singh, Sudhir Kumar,
“Explicit Approach for Voice Compression using Daubechies Wavelet Transform
Method”, National Conference on Emerging Trends in Electrical, Instrumentation &
Communication Engineering (ETEIC-2012), Agra, U.P., India, pp. 516-518, April 6-7,
2012.

15. Anuradha Kumari, Naveen Rathee, Vikas Maheshwari, “On FPGA Implementation of
Biometric EVM Using AADHAAR Authentication”, AICTE Sponsored Two Days
National Conference on Recent Advances and Challenges in Electronics and Hardware
Design (RACE-2020), 28th-29th February, 2020.

16. Amit Kumar Gupta, Sanjay Kumar Suman, Vikas Maheshwari, “ Vhdl Implementation
of QPSK Modulator & Demodulator”, AICTE Sponsored Two Days National
Conference on Recent Advances and Challenges in Electronics and Hardware Design
(RACE-2020), 28th-29th February, 2020.
17. Nimmagadda Sai Krishna, Vikas Maheshwari, “An Analysis on SMART
AGRICULTURE Using IOT”, AICTE Sponsored Two Days National Conference on
Recent Advances and Challenges in Electronics and Hardware Design (RACE-2020),
28th-29th February, 2020.

18. Pampee Das, Neeta Kadam, Vikas Maheshwari “An Augmented-Agent Framework For
Disaster Response (AADR) In Academic Community”, AICTE Sponsored Two Days
National Conference on Recent Advances and Challenges in Electronics and Hardware
Design (RACE-2020), 28th-29th February, 2020.

19. Neeta Kadam, Vikas Maheshwari, Pampee Das, “An Enhanced Credit Card Transaction
for Outlier Fraud Detection System Using Artificial Neural Network”, AICTE
Sponsored Two Days National Conference on Recent Advances and Challenges in
Electronics and Hardware Design (RACE-2020), 28th-29th February, 2020.

20. Anita Bai, Vikas Maheshwari, “Object Multi-Tracking with Identification Via Deep
Learning”, AICTE Sponsored Two Days National Conference on Recent Advances and
Challenges in Electronics and Hardware Design (RACE-2020), 28th-29th February,
2020.

21. L. Dharani, K. Leeladhar Rao, D. Anurudh Reddy, Vikas Maheshwari, “Design And
Implementation Of Near-End Communication System Using Verilog HDL”, AICTE
Sponsored Two Days National Conference on Recent Advances and Challenges in
Electronics and Hardware Design (RACE-2020), 28th-29th February, 2020.

22. K.Nikhil Goud, K. Alekhya, M.Lakshman., V. Ankitha, Vikas Maheshwari, “Smart

Speech Glove For Deaf And Dumb Using Hand Gesture Technique”, AICTE Sponsored
Two Days National Conference on Recent Advances and Challenges in Electronics and
Hardware Design (RACE-2020), 28th-29th February, 2020.

23. S. Santhoshi, Naveen Rathee, Vikas Maheshwari, “Internet Protocol Technology”,

AICTE Sponsored Two Days National Conference on Recent Advances and Challenges
in Electronics and Hardware Design (RACE-2020), 28th-29th February, 2020.

24. Amarender Reddy Muppidi, Ravi Teja kalluri, Nagapuri Sairam, Ramya Sree J, Vikas
Maheshwari, “Anti-Theft Protection Of Vehicle By Gsm And Gps With Fingerprint
Verification”, AICTE Sponsored Two Days National Conference on Recent Advances
and Challenges in Electronics and Hardware Design (RACE-2020), 28th-29th February,
2020.

25. Ravi Teja Kalluri, Muppidi Amarender Reddy, Nagapuri Sairam, Kaveti Sowmya,
Vikas Maheshwari, “Analysis Of Body Sensor Networks And Programming
Frameworks For wearable Computing”, AICTE Sponsored Two Days National
Conference on Recent Advances and Challenges in Electronics and Hardware Design
(RACE-2020), 28th-29th February, 2020.

26. Jvl.Ramyasree, Kaveti Sowmya, Gadasi Divya, Mupiidi Amarender, Vikas Maheshwari,
“Emlore Delay Estimation Of 2 Adjacent Coupling Interconnects”, AICTE Sponsored
Two Days National Conference on Recent Advances and Challenges in Electronics and
Hardware Design (RACE-2020), 28th-29th February, 2020.

27. Pola Naveen, Venu GM, Swetha, Vikas Maheshwari, “Performance Modeling and
Optimization Techniques in the presence of Random Process Variations to Improve
Parametric yield of VLSI Circuits”, AICTE Sponsored Two Days National Conference
on Recent Advances and Challenges in Electronics and Hardware Design (RACE-2020),
28th-29th February, 2020.
 28. Venu Gopal, Swetha, Pola Naveen, Vikas Maheshwari, “Expressions for Closed Form
On Delay to Ramp Inputs For On-Chip VLSI RC Interconnect”, AICTE Sponsored
Two Days National Conference on Recent Advances and Challenges in Electronics and
Hardware Design (RACE-2020), 28th-29th February, 2020.

International Journal Papers

1. Rajib Kar, Md. Maqbool, V. Maheshwari, A. K. Mal, A. K. Bhattacharjee, “Power-
Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order
Reduction Technique”, International Journal of Computer Application (Foundation
of Computer Science (FCA) Press, USA), vol. 1, no.14. pp. 92-97, 2010. (ISSN 0975 -
8887.)

2. Rajib Kar, V. Maheshwari, A.K. Mal, A.K. Bhattacharjee, “A Model for Slew
Evaluation for On-Chip RC Interconnects using Gamma Distribution Function”,
International Journal of Computer Application (Foundation of Computer Science
(FCA) Press, USA), vol. 1, no. 10, Article 13, pp. 68-73. 2010. (ISSN 0975 - 8887.)

3. Rajib Kar, V. Maheshwari, A. K. Mal, A. K. Bhattacharjee, “Delay Analysis for On-

Chip VLSI Interconnect using Gamma Distribution Function”, International Journal
of Computer Application (Foundation of Computer Science (FCA) Press, USA), vol.
1, no. 3, Article 11, pp. 65-68, 2010. (ISSN 0975 - 8887.)

4. Rajib Kar, V. Maheshwari, D. Sengupta, A. K. Mal, A. K. Bhattacharjee, “Analytical

Delay Model for Distributed On-Chip RLCG Interconnects”, International Journal of
Embedded systems and Computer Engineering (Serial Publications, India), vol. 2, no.
1, pp. 17-21 , 2010. (indexed in Scopus) (ISSN : 0975-4482).

5. Rajib Kar, V. Maheshwari, S. Pathak, M. Sunil K Reddy, A. K. Mal, A. K.

Bhattacharjee, “Closed Form Expressions for Delay and Slew Metrics of On-Chip VLSI
RC Interconnects for Ramp Inputs using Beta Distribution Function”, International
Journal of Micro and Nano Electronics, Circuits and Systems (Serial Publications,
India), vol. 2, no. 2, pp. 101-107, 2010. (Indexed in Scopus) (ISSN : 0975-4768).

6. Rajib Kar, V. Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “An Explicit

Coupling Aware Delay Model for Distributed On-Chip RLCG Interconnects Using
Difference Model Approach”, International Journal of Embedded Systems and
Computer Engineering (Serial Publications, India), vol. 2, no. 1, pp. 39-44, 2010.
(indexed in Scopus) (ISSN : 0975-4482)

7. Rajib Kar, V. Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “An Explicit

Model of Delay and Slew Metric for On-Chip VLSI RC Interconnects for Ramp Inputs
using Gamma Distribution Function”, International Journal of Recent Trends in
Engineering (Academy Publisher, Finland), vol. 3, no.3, pp. 111-115, 2010. (ISSN:
1797-9617)

8. Rajib Kar, V. Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “A Closed

Form Modelling of Cross-talk for Distributed RLCG On-Chip Interconnects using
Difference Model Approach”, International Journal on Communication Technology,
vol. 1, no. 1, pp. 17-22, India, 2010. (ISSN: 0976-0091)

9. Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, “Coupling Aware

Explicit Delay Metric for On-Chip RLC Interconnect for Ramp input”, International
Journal of Signal & Image Processing (IJSIP), Vol. 1, Issue 2, pp. 14-19, 2010,
ACEEE, USA. (ISSN 2152-5048)
10. Rajib Kar, Vikas Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “An
Accurate Modelling of Delay and Slew Metrics for On-Chip VLSI RC Interconnects for
Ramp Inputs using Burr’s Distribution Function,” International Journal on
Communication Technology (IJCT), Vol. 1 Issue. 3, pp 137-142, 2010, India. (ISSN:
0976-0091)

11. Rajib Kar, V. Maheshwari, Abirjyoti Mondal, Ashis K. Mal, A.K.Bhattacharjee,

“Closed Form Expressions for Slew Metrics for On-Chip VLSI RC Interconnect using F
Distribution”, Indian Journal of VLSI and Electronic System Design (IJVED),
Vol.1, Issue. 1, VSI press, 2011, India.

12. Rajib Kar, V. Maheshwari, M. Sunil K Reddy, V. Agarwal, Ashis K. Mal,

A.K.Bhattacharjee, “An accurate approach of delay estimation for global on-chip VLSI
RC interconnects using first three circuit moments”, Indian Journal of VLSI and
Electronic System Design (IJVED), Vol.1, Issue. 1, VSI press, 2011, India

13. Vikas Maheshwari, Shilpi Lavania, Rajib Kar, Durbadal Mandal & A. K.
Bhattacharjee,“Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect”,
Journal of VLSI Design Tools & Technology, STM Journal, Volume 1, Issue 1,
July, 2011, Pages 17-29. (ISSN: 2321–6492)

14. Vikas Maheshwari, Shilpi Lavania , D. Sengupta, Rajib Kar, D. Mandal, A.K.
Bhattacharjee, “An Explicit Crosstalk Aware Delay Modelling for On-Chip VLSI RLC
Interconnect with Skin Effect”, Journal of Electronic Devices, Vol. 10, 2011, pp. 499-
505, France. ( ISSN: 1682-3427)

15. Vikas Maheshwari, Abhishek Sharma, D. Mandal, R. Kar, A.K. Bhattacharjee,

“Transient and Delay Analysis for On-Chip high Speed VLSI RLCG Interconnection
Network in 0.18μm Technology” Journal of Electronic Devices vol. 11, 2011 pp.
554-559 ( ISSN: 1682-3427).

16. Vikas Maheshwari, Jogendra Singh, R. P. Sharma, S. Pathak, R. Kar,” An Explicit

Approach for Delay Evaluation for On-Chip RC Interconnects using Beta Distribution
Function using Three Moments” IUP Journal of Electrical and Electronics
Engineering, 2011. (ISBN: 9788131427958).

17. Shilpi Lavania, Vikas Maheshwari, “An Explicit Crosstalk Aware Delay Modelling
For On-Chip RLC Interconnect for Ramp Input With Skin Effect”, International
Journal of Engineering Research and Applications (IJERA), Vol.1, Issue 4, 2011,
pp. 1352-1359. (ISSN : 2248-9622).

18. Vikas Maheshwari, Anushree, Rajib Kar, Durbhadal Mandal, A.K. Bhattacharjee,
“Noise Modelling for RC Interconnects in Deep Submicron VLSI Circuit for Unit Step
Input”, Journal of Electron Devices, Vol. 11, 2011, pp. 632-636. ( ISSN: 1682-3427)

19. V. Maheshwari, Sumita Gupta, V. Satyanarayan, R. Kar, D. Mandal, and A. K.

Bhattacharjee, ” Delay Estimation for Global RC Interconnect Using Inverse Gamma
Distribution Function”, International Journal of Information and Electronics
Engineering, Vol. 2, No. 2, pp. 259-263, March 2012.( ISSN: 2010-3719)

20. Vikas Maheshwari, Sumita Gupta, V. Satyanarayana, R. Kar, D. Mandal, A. K.

Bhattacharjee, ” Estimation of RC Global Interconnect Slew in 0.18μm Technology
Using Inverse Gamma Distribution Function”, International Journal of Information
and Electronics Engineering, Vol. 2, No. 2, pp. 264-268, March 2012. .( ISSN: 2010-
3719)

21. V. Maheshwari, Hemlata Yadav, R. Kar, D. Mandal, A.K. Bhattacharjee, ” Delay

 Metric for On-Chip RLCG Coupled Interconnects for Ramp”, Journal of Electron
Devices, Vol.14, 2012, pp.1122-1127. ( ISSN: 1682-3427)

22. V. Maheshwari, S. Gupta, V. Satyanarayana, R. Kar, D. Mandal, A. K. Bhattacharjee,

“Inverse Gamma Distribution based Delay and Slew Modeling for On- Chip VLSI RC
Interconnect for Arbitrary Ramp Input”, ACEEE Int. J. on Control System and
Instrumentation, Vol. 03, No. 02, pp. 31-34, March 2012. (ISSN: 2158-0006)

23. V. Maheshwari, D. Sengupta, R. Kar, D. Mandal, A.K. Bhattacharjee, “Analytical

Delay Model for Distributed On-Chip RLCG Global Interconnects for Different Pole
Conditions”, ACEEE International Journal on Electrical and Power Engineering,
Vol. 02, No. 03, pp. 9-13, Nov 2011. (ISSN: 2158-7574)

24. V. Maheshwari, S. Gupta, R. Kar, D. Mandal, A. K. Bhattacharjee, “Modelling of

Crosstalk and Delay for Distributed RLCG On-Chip Interconnects For Ramp Input”,
ACEEE International Journal on Information Technology, Vol. 02, No. 02, pp. 1-5,
April 2012.( ISSN:2158-0138)

25. V.Maheshwari, Suvra Mukherjee, R. Kar, D. Mandal, A.K. Bhattacharjee, “Analytical

Crosstalk Modelling of On-Chip RLC Global Interconnects with Skin Effect for Ramp
Input”, Procedia Technology, vol. 6, pp. 814 – 821, 2012, Elsevier. (Indexed in Scopus)
(ISSN: 2212-0173)

26. V. Maheshwari, A. Bansal, S. K. Chhotray, R. Kar, D. Mandal, A. K. Bhattacharjee,

“Crosstalk aware Bandwidth Modelling for VLSI RC Global Interconnects using 2-π
Model”, Procedia Technology, vol. 6, pp. 832 – 839, 2012, Elsevier. (Indexed in
Scopus) (ISSN: 2212-0173)

27. Alka Goyal, Vikas Maheshwari, Sampath Kumar, ”Explicit Timing Analysis of
Discontinous RC Global VLSI Interconnect Lines under Ramp Input”, Journal of
Electron Devices, Vol.15, 2012, pp.1249-1253. ( ISSN: 1682-3427)

28. Priyanka Agarwal, Hemlata Yadav, V. Maheshwari, Suraj Sharma, R. Kar, "Analytical
Delay Metric For On-Chip RLCG Interconnect For Generalised Input", Journal of
Electron Devices, Vol. 16, pp. 1315-1320, 2012. ( ISSN: 1682-3427)

29. Amandeep kour, Vimal Yadav, Vikas Maheshwari, Deepak Prashar, “A Review on
Image Processing”, International Journal of Electronics Communication and
Computer Engineering, Volume 4, Issue 1, 2013, pp. 270–275. (ISSN:2249-071X)

30. Amandeep kour, Vimal Yadav, Vikas Maheshwari, Deepak Prashar, “Web Mining in
Soft Computing Relevance and Future Directions”, International Journal of
Electronics Communication and Computer Engineering, Volume 4, Issue 1, 2013,
pp. 276–282. (ISSN:2249-071X)

31. Brajesh Kumar, Vikas Maheshwari, D.C. Dhubkariya, R.Kar, “Analytical Modeling of
Crosstalk Noise and delay for high speed on-chip global RLC VLSI interconnects”,
Journal of Electronic Devices, France, Vol. 17, 2013, pp. 1452-1456. ( ISSN: 1682-
3427)

32. Rahul Singh Bhadauria, V. Maheshwari, R. Kar, D. Mandal, A.K.Bhattacharjee, “

Delay Modelling of On-Chip RC Global VLSI Interconnect for Step Input”,
International Journal of Computer Information Systems and Industrial
Management Applications, MIR Labs , Volume 6 (2014) pp. 355 – 363.(Indexed in
Scopus) (ISSN 2150-7988)

33. Vishal Goyal, Vikas Maheshwari, Rajib Kar, D. Mandal, A.K. Bhattacharjee, “Explicit
 Models for RLC Transient Decoupled Interconnect Crosstalk Glitches and Delay Noise
Effects using 90nm Process Technology”, Journal of Electronic Devices, France, Vol.
19, 2014, pp. 1620-1626. ( ISSN: 1682-3427).

34. Neha Gupta Maheshwari, Vikas Maheshwari, “Analytical Modelling of Delay and
Slew for On-Chip VLSI RC Global Interconnect using Three Circuit Moments”,
Journal of Electron Devices, France, Vol. 20, 2014, pp. 1761-1767. ( ISSN: 1682-
3427)

35. Anushree, Vikas Maheshwari, “Crosstalk Noise Reduction using Wire Spacing in VLSI
RC Global Interconnects”, Journal of Electron Devices, France, Vol. 20, 2014, pp.
1755-1760. ( ISSN: 1682-3427).

36. Vikas Maheshwari, Anushree, “Crosstalk Noise Reduction using Driver Sizing
Optimization in VLSI RC Global Interconnects using 90nm Process Technology”,
Journal of Electron Devices, France, Vol. 22, 2015, pp. 1874-1889, 2015. ( ISSN:
1682-3427)

37. Vashali Kirar, Ankita Gupta, Hemant Kumar Gupta, Vikas Maheshwari, “Design of
Very Low Losses and High Bandwidth Rectangular Microstrip Patch Antenna for
satellite Communication”, International Journal for Innovative Research in Science
& Technology, India, Vol.2, Issue 02, July 2015, pp. 51-56.( ISSN:2349-6010).

38. Vikas Maheshwari, Prabhakar Sharma, “Closed Form Expressions for Delay to Ramp
Inputs for On-Chip VLSI RC Interconnect”, International Journal of Innovative
Systems Design and Engineering, India, Vol.4, Issue 07, 2013, pp. 56-62.
(ISSN:2222-2871).

39. Nitin Bansal, Vikas Maheshwari, Pankaj Kumar Mishra, “Single Electron Transistors:
A Review”, International Journal of Innovative Research & Growth, Volume-I Issue-4 ,
pp. 34-38, february-2016.

40. Hemant Kumar Gupta, Vikas Maheshwari, Vandana Vikas Thakery, “Miniaturized
Ultra Wide band Microstrip Antenna with Defect Ground Structure for Brain Tumor
Detection”, International Journal of Hybrid Information Technology, Vol 9, No 11,
pp. 13 -24, 2016. (Indexed in Scopus) ( ISSN 1738-9968).

41. Hemant Kumar Gupta, Vikas Maheshwari, Vandana Vikas Thakery,”Brain Tumor
Detection by Microwave Imaging using Planner Antenna”, International Journal of
Bio-Science and Bio-Technology, Vol 8, No 5, pp. 201-210, 2016. (Indexed in Scopus)
(ISSN: 2233-7849)

42. Priyanka Jain, Vikas Maheshwari, Vandana Vikas Thakre, “Optimization of a Novel
Shape Micro-strip Patch Antenna using Genetic Algorithm”, International Journal of
Engineering Sciences & Research Technology, Vol 5, Issue 5, pp. 482-489, 2016.
(Indexed in Thomson Reuters ENDNOTE).

43. Shally Goyal, Vikas Maheshwari, Vandana Vikas Thakare, “ Comparative Study of
UWB BPF to Enhance Bandwidth using Defected Ground”, International Journal of
Engineering Research, Volume No.5, Issue No.2, pp : 83- 85, 2016.

44. Vikas Maheshwari, Ravindra Singh Rajawat, “Artificial Intelligence: Prosthetic

Quantum Brain”, ICSES Transactions on Computer Hardware and Electrical
Engineering (ITCHEE), pp. 1-2, Dec 2017. (Editorial)

45. B. Rajendhar, Vikas Maheshwari, Kalyan Kasturi, “Low Power Carry Save Adder
Multipliers using Domino Logic”, International Journal On Recent & Innovative
 Trend In Technology Volume: 4 Issue: 1 January 2018. (ISSN: 2454-1400)

46. Kalyan Kasturi, K. Sri Mourya, I. Mahendra, Vikas Maheshwari,” Gesture Recognition
Based Device Control Using MEMS Accelerometer”, International Journal of
Engineering Science, Advanced Computing and Bio-Technology Vol. 8, No. 4, pp. 256
– 264, October – December 2017,

47. Vikas Maheshwari, Govardhanam P. Ramacharyulu, “Dielectric Resonator based

Multifunctional Antennas for Next Generation Communication Devices”, ICSES
Transactions on Computer Hardware and Electrical Engineering (ITCHEE), Vol. 4, No.
3, September 2018. . (Editorial).

48. Vikas Maheshwari, Pankaj Kumar Mishra, Neha Gupta Maheshwari, ” Modified WKB
Approximation for Fowler-Nordheim Tunneling Phenomenon in Nano-Structure based
Semiconductors”, Materials Today: Proceedings, Elsevier , 2018. (Indexed in
Scopus)…..in Press.

49. Narendra K. Garg, Vikas Maheshwari, Manisha Patnaik,” Modelling and Analysis of
Crosstalk aware Voltage for Global On-Chip RLC VLSI Interconnect Tree Network
using 2-π Model”, Materials Today: Proceedings, Elsevier , 2018. (Indexed in
Scopus)…..in Press.

50. Narendra Kumar Garg, Vikas Maheshwari, Manisha Pattanaik, ” Energy Consumption
in VLSI RC Tree Interconnect for a Saturated Ramp Input”, Materials Today:
Proceedings, Elsevier , 2018. (Indexed in Scopus)…..in Press.

51. Ravindra Singh Rajawat, Vikas Maheshwari, “New Leap in Quantum: Prosthetic
Brain”, Journal of Artificial Intelligence Research & Advances, STM Journal, Volume
6, Issue 1, March 2019.

52. Somashekhar, Vikas Maheshwari, R.P.Singh, “Analysis of Micro Inversion to Improve

Fault Tolerance in High Speed VLSI Circuits”, International Research journal of
Enginerring and Technology, Volume 06, Issue 03, pp. 5041-5044, March 2019.

53. Somashekhar, Vikas Maheshwari, R.P.Singh, “A Study of Fault Tolerance in High

Speed VLSI Circuits” International Journal of Scientific & Technology Research,
Volume 8, Issue 08, August 2019. (ISSN 2277-8616)
(SCOPUS).

54. Somashekhar, Dr.Vikas Maheshwari, Dr.R. P. Singh, “FPGA Implementation

of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures”,
International Journal of Engineering and Advanced Technology (IJEAT),
Volume-9 Issue-6, April 2020. (ISSN:2249–89589)
(SCOPUS).

55. Narendra K. Garg, Somashekhar Malipatil, Vikas Maheshwari, Rajib Kar, “Two
Dimensional Analytical Expression of Threshold Voltage for Un-Doped Double Gate
MOSFET”, Communicated to journal IOP Semiconductor Science & Technology (SCI).
(Final Stage to publish).

56. Somashekhar, Dr.Vikas Maheshwari, Dr.R. P. Singh,“FPGA Implementation of High

Speed Systolic Multiplier Architecture for ML”, Accepted for International Journal of
Information Technology (IJIT) (Springer).
International Conference Papers

1. Rajib Kar, V. Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “A Closed

form Delay Evaluation Approach using Burr’s Distribution Function for High Speed
On-Chip RC Interconnects”, IEEE 2nd International Advance Computing Conference
(IACC 2010), Patiala, India, pp. 129-133, Feb. 19-20, 2010. (ISBN: 9781424447916)

2. Rajib Kar, V. Maheshwari, S. Pathak, M. Sunil K. Reddy, A. K. Mal, A. K.

Bhattacharjee, “Beta Distribution Based Slew Evaluation Approach for On-Chip RC
Interconnects by Using Moment Matching Technique”, IEEE International Conference
on Recent Trends in Information, Telecommunication and Computing (ITC 2010),
Kochi, Kerala, India, pp. 18-22, 12-13 March, 2010. (ISBN:9781424459568)

3. Rajib Kar, V. Maheshwari, S. Pathak, M. Sunil K Reddy, A.K. Mal, A.K.

Bhattacharjee, “An Explicit Approach for Delay Evaluation for On-Chip RC
Interconnects using Beta Distribution Function by Moment matching Technique”, IEEE
International Conference on Recent Trends in Information, Telecommunication and
Computing (ITC 2010), Kochi, Kerala, India, pp. 5-8, March 12-13, 2010.
(ISBN:9781424459568)

4. Rajib Kar, V. Maheshwari, Md. Maqbool, A. K. Mal, A. K. Bhattacharjee, “A Closed

form Slew Evaluation Approach using Burr’s Distribution Function for High Speed On-
Chip RC Interconnects”, International Conference on Recent Trends in Business
Administration and Information Processing (BAIP 2010), Springer-Verlag, LNCS-
CCIS, March 26-27, 2010, Kerala, India, vol. 70, pp.71-75, 2010.

5. Rajib Kar, V. Maheshwari, Md. Maqbool, S. Mandal, A. K. Mal, A. K. Bhattacharjee,

“An Novel Power Estimation Method for On-Chip VLSI Distributed RLCG Global
Interconnects using Model Order Reduction Technique”, IEEE International Conference
on Advances in Computer Engineering (ACE 2010), Bangalore, India, pp.105-109, June
20-21, 2010. (ISBN:9781424471546)

6. Rajib Kar, V. Maheshwari, Md. Maqbool, S. Mandal, A. K. Mal, A. K. Bhattacharjee,

“Closed Form Bandwidth Expression for Distributed On-Chip RLCG Interconnects”,
IEEE International Conference on Advances in Computer Engineering (ACE 2010), pp.
144-147, June 20-21, 2010 , Bangalore, India. (ISBN:9781424471546)

7. Rajib Kar, V. Maheshwari, A. Mondal, A. K. Mal, A. K. Bhattacharjee, “A Closed

Form Expression for Slew Metric for On-Chip VLSI RC Interconnects using F-
Distribution Function”, 14th IEEE VLSI Design And Test Symposium (VDAT), July 7-
9, India, 2010.

8. Rajib Kar, V. Maheshwari, M. Sunil K Reddy, V. Agarwal, A. K. Mal, A. K.

Bhattacharjee, “An Accurate Delay Metric for Global On-Chip VLSI RC Interconnects
using First Three Circuit Moments”, 14th IEEE VLSI Design And Test Symposium
(VDAT 2010), July 7-9, 2010, India.

9. Rajib Kar, V. Maheshwari, S. Mandal , A. K. Mal, A. K. Bhattacharjee, “A Novel and

Acurate Delay and Slew Metrics for Ramp Inputs for On-Chip VLSI RC Interconnect
using Weibull Distribution Function”, 2nd IEEE International Conference on
Computing, Communication and Networking Technologies (ICCCNT 2010), 29-31
July, pp. 1-5, Karur, India, 2010.(ISBN: 9781424465910)

10. Rajib Kar, V. Maheshwari, Md. Maqbool, S. Mandal, A. K. Mal, A. K. Bhattacharjee,

“Crosstalk Aware Bandwidth Modelling for Distributed On-Chip RLCG Interconnects
Using Difference Model Approach”, 2nd IEEE International Conference on Computing,
Communication and Networking Technologies (ICCCNT 2010), 29-31 July, pp. 1-5,
 Karur, India, 2010. .(ISBN: 9781424465910)

11. Rajib Kar, V. Maheshwari, A. Choudhary, A. Singh, A. K. Mal, A. K. Bhattacharjee,

“Inductive Coupling Aware Explicit Cross-Talk and Delay Formula for On-Chip VLSI
RLCG Interconnects using Difference Model Approach,” 2nd IEEE International
Conference on Computing, Communication and Networking Technologies (ICCCNT
2010), 29-31 July, pp. 1-6, Karur, India, 2010. .(ISBN: 9781424465910)

12. Rajib Kar, V. Maheshwari, A. Choudhary, A. Singh, A. K. Mal, A. K. Bhattacharjee,

“Coupling Aware Power Estimation for On-Chip VLSI Distributed RLCG Global
Interconnects Using Model Order Reduction Technique”, 2nd IEEE International
Conference on Computing, Communication and Networking Technologies (ICCCNT
2010), 29-31 July, pp. 1-7, Karur, India, 2010.(ISBN: 9781424465910)

13. Rajib Kar, V. Maheshwari, A. Choudhary, A. Singh, V. Agarwal, A. K. Mal, A. K.

Bhattacharjee, “Accurate Estimation of On-Chip Global RLC Interconnect Delay for
Step Input”, IEEE International Conference on Computer and Communications
(ICCCT-2010), Sept 17-19, Allahabad, pp. 673-677, 2010.. (ISBN:9781424490332)

14. Rajib Kar, V. Maheshwari A. Mondal, A. K. Mal, A. K. Bhattacharjee, “Closed Form

Modelling for Delay and Slew Metrics for On-Chip VLSI RC Interconnect for Ramp
Inputs Using F-Distribution,” 2010 IEEE Symposium on Industrial Electronics and
Applications (ISIEA 2010), 3-6 October 2010, pp. 526-531, Penang, Malaysia, 2010.
(ISBN: 9781424476459)

15. Rajib Kar, V. Maheshwari, V. Agarwal, A. K. Mal, A. K. Bhattacharjee, “Modelling of

RLC Interconnect Delay for Ramp Input Using Diffusion Model Approach,” 2010 IEEE
Symposium on Industrial Electronics and Applications (ISIEA 2010), 3-5 October 2010,
pp. 436-440, Penang, Malaysia, 2010. (ISBN: 9781424476459)

16. Rajib Kar, V. Maheshwari, S. Pathak, M. Sunil K Reddy, A.K.Mal,

A.K.Bhattacharjee, “Closed Form Expressions for Delay and Slew Metrics of On-Chip
VLSI RC Interconnects for Ramp Inputs using Beta Distribution Function”, First
International Conference on VLSI, Communication, Computation and Security
(ICVCCS’10), pp. 64-69, 9-10th April 2010, Coimbatore.

17. Rajib Kar, V. Maheshwari, Dyuti Sengupta, A.K.Mal, A.K.Bhattacharjee, “Analytical

Delay Model for Distributed On-Chip RLCG Interconnects”, First International
Conference on VLSI, Communication, Computation and Security (ICVCCS’10) , pp.
54-58, 9-10th April 2010, Coimbatore.

18. Rajib Kar, V. Maheshwari, Md. Maqbool, A.K.Mal, A.K.Bhattacharjee, “An Explicit
Coupling Aware Delay Model for Distributed On-Chip RLCG Interconnects Using
Difference Model Approach”, First International Conference on VLSI, Communication,
Computation and Security (ICVCCS’10), pp. 59-63, 9-10th April 2010, Coimbatore.

19. Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, “Wave Propagation
based Analytical Delay and Crosstalk Noise Model for Distributed On-Chip RLCG
Interconnects,” 2010 IEEE International Conference on Semiconductor Electronics
(ICSE2010), Malacca , Malaysia, June 28th -30th , 2010, pp.153-157. (ISBN:
:9781424466085)

20. Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, “Modeling of On-Chip
Global RLCG Interconnect Delay for Step Input”, IEEE International Conference on
Computer and Communications Technology (ICCCT-2010). Allahabad, Sept 17-19, pp.
318-323, 2010. (ISBN:9781424490332)
21. R. Kar, V. Maheshwari, A. Choudhary, A. Singh, M. Datta, S. Sahoo,“ Delay Analysis
for Resistive Interconnect Based on Three Moments Approach,” International
Conference on Computational Vision and Robotics (ICCVR), 21st-22nd August, 2010.

22. Dyuti Sengupta, Vikas Maheshwari, Rajib Kar, “Unified Delay Analysis for On-Chip
RLCG Interconnects for Ramp Input using Fourth Order Transfer Function,” IEEE
International Conference on Signal and Image Processing(ICSIP), pp. 357-361,
Dec.15th -17th , 2010, Chennai. (ISBN: 9781424485956)

23. Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, Ashis K. Mal,
A.K.Bhattacharjee, “An Accurate Crosstalk Noise Estimation Method for Two
Simultaneously Switched On-Chip VLSI Distributed RLCG Global Interconnects,”
IEEE International Conference on Signal and Image Processing(ICSIP), pp. 362-367,
Dec.15th -17th , 2010, Chennai. (ISBN: 9781424485956)

24. Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, Ashis K. Mal,
A.K.Bhattacharjee, “A Novel Bandwidth Estimation Method for Distributed On-Chip
RLCG Interconnects,” IEEE International Conference on Signal and Image
Processing(ICSIP), pp. 372-376, Dec.15th -17th , 2010, Chennai. (ISBN:
9781424485956).

25. Vikas Maheshwari, Sumita Gupta, Venugopal Satyanarayans, Rajib Kar, A.K.
Bhattacharjee, “Estimation of RC Global Interconnect Slew in 0.18μm Technology
using Inverse Gamma Distribution Function”, IEEE International Conference on
Network Communication and Computer – ICNCC 2011, pp. 224-228, March 19-20,
2011, New Delhi, India. .(ISBN:9781424487110)

26. Vikas Maheshwari, Sumita Gupta, Venugopal Satyanarayans, Rajib Kar, A.K.
Bhattacharjee, “Delay-Estimation for Global RC Interconnects using Inverse Gamma
Distribution Function” IEEE International Conference on Network Communication and
Computer – ICNCC 2011, , pp. 220-223, March 19-20, 2011, New Delhi,
India.(ISBN:9781424487110)

27. V. Maheshwari, S. Gupta, V. Satyanarayana, R. Kar, Durbadal Mandal, A. K.

Bhattacharjee, “Inverse Gamma Distribution based Delay and Slew Modelling for On-
Chip VLSI RC Interconnect for Arbitrary Ramp Input,” Second International
Conference on Advances in Electrical & Electronics (AEE 2011), pp.110-113,
December 20-21, 2011 in Noida, India (ISBN:9781634391092)

28. V. Maheshwari, S. Gupta, Gaurav Khetan, R. Kar, D. Mandal, A. K. Bhattacharjee

“Modelling of Crosstalk and Delay for Distributed RLCG On-Chip Interconnects For
Ramp Input”, Second International Conference on Advances in Electrical & Electronics
(AEE 2011), pp.10-14, December 20-21, 2011 in Noida, India. (ISBN:9781634391092)

29. Vikas Maheshwari, Dyuti Sengupta, Durbadal Mandal, Rajib Kar, A.K. Bhattacharjee,
“Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for
Different Pole Conditions” Second International Conference on Advances in Electrical
& Electronics (AEE 2011), , pp. 6-10, December 20-21, 2011 in Noida, India.
(ISBN:9781634391092)

30. Vikas Maheshwari, Abhishek Sharma, Randheer Kumar, Rajib Kar, Durbadal Mandal,
A.K. Bhattacharjee “Transient Analysis for On-Chip High Speed VLSI RLCG Global
Interconnect for Unit Impulse Input”, Proc. 9TH IEEE SCOReD 2011, Cyberjaya /
Putrajaya, Malaysia, 19th – 20th December 2011.( ISBN:9781467300995)

31. Vikas Maheshwari, Shruti Gupta, Kapil Khare, Vimal Yadav, Rajib Kar, Durbadal
Mandal, Anup Kr. Bhattacharjee, “Efficient Coupled Noise Estimation for RLC On-
 Chip Interconnect”, IEEE Symposium on Humanities, Science and Engineering
Research (SHUSER-2012), Kuala Lumpur, Malaysia, pp.1125-1129,June 24-27, 2012.
( ISBN:9781467313117)

32. Vikas Maheshwari, Portia Banerjee, Madhumanti Datta, Susmita Sahoo, Rajib Kar,
Durbadal Mandal, Anup Kr. Bhattacharjee, “Delay and Transient Response Modelling
of On-Chip RLCG Interconnect Using Two-port Network Functions” IEEE Symposium
on Humanities, Science and Engineering Research (SHUSER-2012), Kuala Lumpur,
Malaysia, pp. 153-157,June 24-27, 2012. ( ISBN:9781467313117)

33. Vikas Maheshwari, Naomi Joshi, Er Anushree, Rajib Kar, Durbadal Mandal, Anup Kr.
Bhattacharjee, “4-π Crosstalk Noise Model for Deep Submicron VLSI Global RC
Interconnects”, IEEE Symposium on Humanities, Science and Engineering Research
(SHUSER-2012), Kuala Lumpur, Malaysia, pp. 355-360, June 24-27, 2012.
34. ( ISBN:9781467313117)

35. Vikas Maheshwari, Sristi Agarwal, Alka Goyal, Jitesh Jain, Sampath Kumar, Anup Kr.
Bhattacharjee, Rajib Kar, Durbadal Mandal, “Elmore's approximations based Explicit
Delay and Rise Time Model for Distributed RLC On-Chip VLSI Global Interconnect”,
IEEE Symposium on Humanities, Science and Engineering Research (SHUSER-2012),
Kuala Lumpur, Malaysia, pp. 1135-1139,June 24-27, 2012.( ISBN:9781467313117)

36. Vikas Maheshwari, Arka Halder, Alka Goyal, Rajib Kar, Durbadal Mandal,
A.K.Bhattacharjee, “Moment based Delay Modelling for On-Chip RC Global VLSI
Interconnect for Unit Ramp Input”, IEEE 9th International Joint Conference on
Computer Science and Software Engineering (JCSSE-2012), Bangkok, Thailand, pp.
164-167, May 30- 01June 2012. (ISBN:9781467319201)

37. V. Maheshwari, R.S. Bhadauria, D. Mandal, R. Kar, A.K. Bhattacharjee, “Delay

Modelling of On-Chip RC Global VLSI Interconnect for Step Input”, Proc. IEEE WICT,
Mumbai, October 30-November 02, pp. 458-463, 2012.( ISBN:9781467348065)

38. V. Maheshwari, S. Majumdar, R. Kar, D. Mandal, A. K. Bhattacharjee, “A Novel

Method for Delay Analysis of CMOS Inverter with RLC Interconnect Load”, Proc.
IEEE CODEC 2012, Kolkata, December 17-19, 2012.( ISBN:9781467326193)

39. V. Maheshwari, S. Mazumdar, Anushree, R. Kar, D. Mandal, “2-π Crosstalk Noise

Model for Deep Submicron VLSI Global RC Interconnects”, Proc. IEEE ICEDSA 2012,
Kuala Lumpur, Malaysia, 5 - 6 November, pp. 225-229, 2012.( ISBN:9781467321624)

40. V. Maheshwari, K. Khare, S. K. Jha, R. Kar, D. MandaI,” An Analytical Crosstalk and

Delay Model for VLSI RLC Coupled Interconnects”, IEEE International Advanced
Computing Conference, pp.1568-1572, 2013 (ISBN: 97814673 45293).

41. V. Maheshwari, A. Baboo, R. Kar, D. Mandal, A. K. Bhattacharjee, "Delay Model for

VLSI RLCG Global Interconnects Line", Proc. IEEE PrimeAsia 2012, December 5-7,
2012, Hyderabad, India. ( ISBN:9781467350655)

42. V. Maheshwari, K. Khare, R. Kar, D. Mandal, A. K. Bhattacharjee, "Crosstalk Noise

Estimation for Generic RLC Trees with Capacitive Coupling", Proc. IEEE PrimeAsia
2012, December 5-7, 2012, Hyderabad, India.( ISBN:9781467350655)

43. V. Maheshwari, J. Rakshit, S. Mazumdar, H. Jadav, R. Kar, D. Mandal, “Delay Metric

for On-Chip RLCG Interconnect for Arbitrary input", Proc. IEEE CODIS 2012,
Kolkata, Dec. 28-29, 2012.( ISBN:9781467346993 .)
 44. Amandeep Kour, Vimal kishore Yadav, Vikas Maheshwari, Deepak Prashar, “Face
Recognition Using Template Matching”, “ IEEE International Conference on Signal and
Image Processing (ICCSP), Melmaruvathur, Tamilnadu, April. 3rd-5th, 2013.
(ISBN:9781467348645)

45. Vikas Maheshwari, Samir K. Jha, K. Khare, R. Kar, D.Mandal,”Accurate Crosstalk

Analysis for RLCG On-Chip VLSI Global Interconnect”, IEEE Conference on
Information and Communication Technologies (ICT 2013), Thuckalay, Tamil Nadu,
India, pp. 281-286, 11-12 Aprill, 2013. (ISBN: 9781467357593)

46. V. Maheshwari, Kapil Khare, Suvra Mukherjee, R. Kar, D. Mandal, “Peak Noise and
Noise Width Modelling for RLC Global Interconnects in Deep Submicron VLSI
Circuits”, IEEE Conference on Information and Communication Technologies (ICT
2013), Thuckalay, Tamil Nadu, India, pp. 321-326, 11-12 Aprill, 2013. (ISBN:
9781467357593)

47. Apoorva Gupta, Vikas Maheshwari, Shalini Sharma, Rajib kar, “Crosstalk Noise and
Delay Analysis for High Speed On-Chip Global RLC VLSI Interconnects with Mutual
Inductance using 90nm Process Technology,” IEEE International Conference on
Computing, Communication and Automation (ICCCA-2015), Greater Noida, India, pp.
1215-1219, 15-16 May, 2015. (ISBN:978-1-4799-8891-4).

48. Somashekhar, Vikas Maheshwari, R.P.Singh, “FPGA Implementation of Fault Tolerant

Full Adder Design for High Speed VLSI Architecture”, Spinger International Cnference
on Intelligent Computing and Smart Communication Technologies, Hyderabad
Telangana, India,26-27th July, 2019.

49. Somashekhar Malipatil, Vikas Maheshwari, Marepally Bhanu Chandra, “Area

Optimization of CMOS Full Adder Design Using 3T XOR”, publishes in IEEE Xplore
978-1-7281-5284-4/20/$31.00 ©2020 IEEE.
(SCOPUS).

50. Vikas Maheshwari, Somashekhar Malipatil, Neha Gupta, Rajib Kar “Modified WKB
Approximation for Fowler-Nordheim Tunneling Phenomenon in Nano-Structure based
Semiconductors”, IEEE International Conference on Emerging Trends in
Information Technology and Engineering (ic-ETITE), pp. 1-5, 2020.
(SCOPUS).

Personal Details • Date of Birth : Day 15th, August 1983

• Nationality : Indian
• Permanent Address : 32, Pushpanjali Bagh Phase-I, DayalBagh, Agra, U.P.
• Current Package : 15 L.P.A.

Dr Rajib Kar Dr A.K. Bhattacharjee

References Assistant Professor, ECE Deptt Professor, ECE Deptt
National Institute of Technology Durgapur National Institute of Technology Durgapur
West-Bengal, INDIA West-Bengal, INDIA
Email:rajibkarece@gmail.com Email:akbece12@yahoo.com
Mob:09434788056 Mob:09434788021
Dr A.K. Mal Dr Durbadal Mandal
Associate Professor, ECE Deptt Assistant Professor, ECE Deptt
National Institute of Technology Durgapur National Institute of Technology Durgapur
West-Bengal, INDIA West-Bengal, INDIA
 Email:toakmal@gmail.com Email: durbadal.bittu@gmail.com
Mob:09434788055 Mob: 09434788059
Dr Aniruddha Chandra Dr Deepak Garg
Assistant Professor, ECE Deptt Professor & HOD, Deptt of CSE
National Institute of Technology Durgapur School of Engineering & Applied Sciences
West-Bengal, INDIA Bennet University, Greater Noida, U.P.
Mob: 0 9231346620 Email: deepak.garg@bennett.edu.in
Email: aniruddha.chandra@ece.nitdgp.ac.in Mob:+919815599654
Dr Rajeev Upadhyay Dr Sukumar Ray Chodhury
Director, Hindustan College of Science & Director, Techno India Group of Institutions,
Technology Farah, Mathura, U.P., India Kolkata, West-Bengal, India
Mob:+91917064447 Email:rcsukumar@yahoo.com
Mob:+91927010773

Date: (VIKAS MAHESHWARI)