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CHAPTER 1 INTRODUCTION In the province of Forward Error Correction (FEC) TURBO

CODES charter utmost evolution. Turbo codes are a class of high performance error
correction codes in electrical engineering and digital communications, and it is
developed in 1993 which are using in deep satellite communication and other claims
where the designers entreat to attain maximal data convey atop a restricted bandwidth
conveyance association in the spectre of dossier corrupting noise.

Exhibiting concert converging the Shannon limit, Turbo Codes (TC)have the turbo code
block set attributes methodical encoder and decoder sketches glimpsed swift
endorsement in the design of digital communication systems. Desirable and Designable
instigates the essences of turbo codes in their different flavours (more concretely,
collateral progressed convolutional turbo codes and block turbo codes).

Through the application of systemic design methodology that considers data transfer
and storage a cessation priority candidate for optimization, the author’s show how turbo
codes can be contrivance and in throughput, latency alluring performance results can be
achieved .The last ten years have visually perceived the appearance of an incipient type
of rectification.

This represents a consequential development in the field of error-rectifying codes. In an

iterative reciprocity of information between elementary decoders, called extrinsic
information the proposition of decoding is to be found, and it is this principle from
which the phrase turbo originates.

To block codes as well as other parts of a digital transmission system, the turbo
hypothesis is now pertained, such as diagnosis, demodulation. Mobile communications,
wireless networks and local radio loops are the applications that amalgamate turbo
codes into their grades. Cable transference, short-distance communication could
incorporate in future requisitions or scalable transmission includes in data storage. 1.1.

TURBO CODE In information theory, turbo codes (pristinely in French Turbocodes) are a
class of high-performance forward error rectification (FEC) codes developed in 1993, to
proximately approach the channel extent, a conjectural vertex for the code rate at which
reliable communication is still possible given a categorical noise level. Turbocodes are
finding use in 3Gmobile communications and (profound space) satellite
communications as well as other applications.

Turbo codes are rivalling with LDPC codes, which furnish homogeneous performance.
With rapid magnification of multimedia accommodations, the convolutional turbo code
(CTC) has been widely adopted as one of forward error redressing (FEC) schemes of
wireless standards to have a reliable transmission over strepitous channels.

Single-binary (SB) CTC, proposed in 1993[1], has been the well-kenned FEC code that
can achieve high data rates and coding gains proximate to the Shannon limit. In the FEC
schemes of wideband code division multiple access (WCDMA) [2], high speed downlink
packet access (HSDPA), and long term evolution (LTE) [2], the SB CTC code has been
embraced. To accomplish loftier conduction than the SB CTC in 1999, non-binary CTC
[3] was launched.

In recent years, double-binary (DB) CTC has been adopted inadvanced wireless
communication standards, such as ecumenical interoperability for microwave access
(WiMAX). Some CTC decoders have been implemented as application-concrete
integrated circuits (ASICs), such as the HSDPA CTC decoder and WiMAX CTC decoder.
Contemporarily, high-end portable/mobile contrivances become ubiquitous in wireless
markets.

There are immensely colossal growing emergences and injuctively authorizes for an
inexpensive solution to access the ubiquitous wireless accommodations. Wireless
standards adopted CTC schemes with different coding parameters and throughput
rates, such as 3GPP and WiMAX standards. To deal with the expedited evolution of
these standards, across the multiple standards propounded in, the multi standard
platforms works lodely.

Desired to achieve the sleek departure for the multiple wireless applications, a CTC
decoding expeditor works in the multi standard platforms. For multi standard CTC
schemes, area-efficient scalable processor designs of the maximum a posteriori
algorithm (MAP) were proposed. The suggested MAP processor can be the intent or
reconfigurable FEC components.

For system-on-chip (MPSoC) technology for a multi standard platform, several proposed
MAP processors can be employed in multiple processors. For high-throughput multi
standard CTC schemes, the proposed scalable MAP processor design has two features
verbalized as follows. Sophisticated channel coding schemes and corresponding
high-throughput, low area, and energy-efficient decoder implementations are required
for genuine data transmission in wireless communication systems.

Convolutional codes (CCs), utilized in stand-alone form [5] or as a component of turbo

codes[6], are among the most popular codes utilized in current and next-generation
wireless communication standards, such as HSDPA[7], 3GPP-LTE[8], LTE-Advanced[9], or
IEEE 802.11n [10]. CCs and turbo codes are of consequential practical interest due to the
fact that they offer excellent error-rectification performance and can be implemented to
achieve high throughput, while being efficient in terms of silicon area and power
consumption [11]-[18].

A key enabler for wireless communication systems operating proximate to the Shannon
limit is iterative decoding algorithms reckoning on CCs, since the emergence of turbo
codes. CCs have withal been considered for wireless communication systems hiring
iterative identification and decoding, i.e., between a detector and the channel decoder
where reliability information is exchanged iteratively.

Iterative detection and decoding in multiple-input multiple-output (MIMO) wireless

systems[19] or systems exhibiting inter-symbol interference[20] is becoming an integral
part of future transceiver designs because it is an efficient designates to substantially
ameliorate the throughput and quality-of accommodation (i.e., link reliability, coverage,
and range) compared to non-iterative decoding schemes. 1.1.1.

PRINCIPLES OF TURBO CODES: By utilizing the block code with convolutional code and
additionally with the longer constraint length and immensely colossal block length it is
theoretically possible to approach the Shannon limit. It became absurd due to the
processing power entailed to decode. The turbo codes vanquish this snag by utilizing
recursive coders and iterative soft decoders.

The main aim of the recursive coder is to make the convolutional codes with shorter
constraint lengths which appear as a sizably voluminous curtailment length of a block
codes and iterative soft decoder coherently amends the appraisal of the procured
message. The below shown figure generally gives the encoder for implementation which
describes a classical encoder which spares the general design of the turbo codes.

The 3bits of the sub block can be sended by utilizing this encoder implementation. The
m-bit block of payload data is in the first sub block. The n/2 parity bits for a well-kenned
permutation incorporate in the 3rd sub block which is once again computed with the
RSC code. Interleaver is a contrivance which generally carries out the permutation of the
payload data.

This turbo code encoder includes two RSC codes (identical), as shown in the figure. By
utilizing the concatenation scheme these are coupled to each other which are referred
as parallel concatenation. 1.1.2. TURBO CODES V/S CONVOLUTIONAL CODES: There are
some differences between the comportment of turbo codes and the convolutional
codes.

As we ken that the performance of the convolutional codes increases with the
incrementing constraint length (code involution). This is not for the turbo codes where
the best codes of the turbo codes have the minuscule constraint lengths. With
decrementing code rate the performance of the convolutional codes does not
ameliorate significantly.

Whereas for the turbo codes even for the lower coding rates it achieves a very
consequential coding gain. While visually perceiving from the implementation
perspective, soft output encoders and recursive decoders are essential in turbo code
schemes, in convolutional codes they are not vital and omitting the successive
configuration. 1.1.3.

TURBO V/S LINEAR BLOCK CODES: The Hybrid model of the both the linear block codes
and the convolutional codes respectively are the turbo codes. To compose a turbo
product code (TPC), the linear block codes are utilized in the turbo codes in lieu of the
convolutional codes. With the truancy of an interleaver in between them, two hamming
codes are concatenated serially.

They can perform well in low SNR and can be composed by any block code. The
convolutional codes utilized in the turbo codes conventionally form a parallel
progressed convolutional code (PCCC) which has the minuscule constraint length. They
are systematic. 1.2. PERFORMANCE OF TURBO CODES: Berrou’s impressive BER of 10-5
at Eb/No of 0.7 dB does not tell the whole story.

To achieve this required 18 iterations and a block length of 65532 data bits. If this
channel fortified a verbalization coder at 4.8 Kbit/s it would take 15 seconds to receive a
block. This latency would be impractical for telephony, but would be more than ample
for getting images from a intense space scrutiny.

Most of the judgements of turbo code performance have resulted from simulation. In
the ideal environment of a simulation, free of the constraints of authentic systems, it is
possible to engender highly impressive results. To apply turbo codes to authentic
systems requires acceptance of authentic world constraints such as latency and
computing puissance.

Wang6 has reconnoitred the performance of codes with parameters set to values that
are more practical. The four main factors supremacies the performance of turbo codes:
the number of iterations, constraint length, interleaver design and transfixing. His
simulations were predicated on utilization of the MAP decoder and constraint lengths of
3-5. He concluded that: • Decoding iterations of ten decoders are adequate.

• A constraint length of greater than 3 adds little coding gain for short block sizes
(around 100) • The best all round performance provided by Random interleavers. • The
use of 1/2 rate punctured codes degrades the BER performance by only 0.5 to 0.7 dB
relative to 1/3 rate unpunctured codes. There is a performance floor around Eb/No of
3dB spotted additionally by Wang. The reasons for this floor are the subject of current
inspection.

While there is illustrious material heralding on the ideal performance of turbo codes,
astonishingly little material subsists announcing on the performance of turbo codes in
practical scenarios. Limpidly, exploring the lower limits of turbo code performance can
provide an intuition into their practical inhibitions. In the less time authentic decoders
need to provide the best BER from the worst channel. 1.3.

REED SOLOMON CODES: In digital communications and storage Reed-Solomon codes

are block-predicated error rectifying codes with a vast assortment of applications. To
redress errors in many systems including: Storage devices (including tape, Compact
Disk, DVD, barcodes, etc), they are acclimated Wireless or mobile communications
(including cellular telephones, microwave links, etc) Satellite communications Digital
television / DVB High-speed modems such as ADSL, XDSL, etc.

The Reed-Solomon encoder takes a block of digital data and integrates extra
"redundant" bits. During transference or hoarding errors occur for a number of
rationales (for example noise or interference, scratches on a CD, etc). The Reed-Solomon
decoder processes each block and endeavours to rectify errors and recuperate the
pristine data.
The number and type of errors that can be redressed depends on the characteristics of
the Reed-Solomon code. These are subset of BCH codes and are linear block codes. The
following diagram shows a typical Reed-Solomon codeword (this is known as a
Systematic code because the data is left unchanged and the parity symbols are affixed):
__ Fig 1: TYPICAL REED –SOLOMON CODEWORD CHAPTER 2 TURBO ENCODER
Cooperative and relay communication has accrued much heed recently [4]-[7] due to
the potential performance amelioration. At the network level, relays can elongate
wireless network coverage direct source-to destination link does not subsist .At the
physical level, the utilization of relays can achieve the diversity gains offered by multiple
antenna space time systems through utilizing several relay nodes, possibly with only one
antenna per physical node .The latter is the primary focus of this paper.

This paper considers a three node (source (S), relay (R) and destination (D)) wireless
cooperative communication system, which can be considered as a building block for
more sizably voluminous wireless networks. The rudimentary cooperative schemes that
have been anteriorly considered include Amplify-and-Forward (AF) and
Decode-and-Forward (DF) [2].

Here we consider a form of DF. It has been shown in that DF schemes, in which the relay
nodes always forward the decoded results without betokening their reliability, incline to
not achieve the desired miscellany gain due to fallacious decoding at the relay.

Simple selective DF was proposed in to decipher this quandary, where the relay keeps
silent when errors are detected in its decoded data. Note this conventionally requires
the utilization of acyclic redundancy check (CRC) code embedded in the source-to-relay
(S-R) link. Among the coded DF schemes, those utilizing distributed Turbo codes (DTCs)
have been shown to afford good performance.

In a DTC was proposed utilizing DF, where the two component codes are discretely
engendered at the source and relay. It, however, surmises an ideal S-R link. The DTC
schemes proposed showed that end to- end performance can be ameliorated
significantly without utilizing a CRC, by congruously weighting the relayed information
which may contain errors.

A simple non-selective DF scheme was proposed for DTCs [21], to address this
quandary, without performing a CRC check the relay decodes the received signals. Here
are many different instances of turbo codes, utilizing different component encoders,
input/output ratios, interleavers, and transfixing patterns. This example encoder
implementation describes a classic turbo encoder, and manifests the general design of
parallel turbo codes.

This encoder implementation sends three sub-blocks of bits. m-bit block of payload
data is the first sub-block. For the payload data, enumerated utilizing a recursive
systematic convolutional code (RSC code) the second sub-block is n/2 parity bits. For a
kenned permutation of the payload data, again computed utilizing an RSC convolutional
code, the third sub-block is n/2 parity bits.

Thus, two redundant but different sub-blocks of parity bits are sent with the payload.
The consummate block has m + n bits of data with a code rate of m/(m + n). The
permutation of the payload data is carried out by a contrivance called an interleaver.
Hardware-sapient, this turbo-code encoder consists of two identical RSC coders, ?1 and
C2, as depicted in the figure, which are connected to each other utilizing a
concatenation scheme, called parallel concatenation.

Turbo-codes can be coded in different ways, but can be summarized by Here the
scheme commences with the Convolutional encoder, Interleaver and modulator
accordingly some encoders puncture the result and the result or codeword can then be
sent over a channel. As mentioned earlier, turbo-codes can be coded in different ways.
One of the methods is called convolutional coding and this method was described in
the early days of turbo-codes.

The encoders are arranged in soi-disant parallel concatenation to compose different

structures. The code symbol c?? enters the digital modulator, performing a one-to-one
mapping with its signals, or channel input symbols x?????= {??1, ??2...???}. Then the
channel symbolhttps://www.facebook.com/ x?? are transmitted over a stationary
discrete recollection less channel with output symbols y??.

An additive white Gaussian noise (AWGN) model with zero mean and variance 0/2 is
considered. The encoder designed utilizing astute and flexible compare and redress
algorithm is built utilizing the same agenda as mentioned above. At the source node
this PCCC circuit is utilized for encoding data packets, while the PCCC circuits present on
the routing nodes to the base station work as Detect-Correct circuits [22].

This function at the forwarding nodes is consequential, not only it can redress some
error bits in the forwarded packets but it withal monitors the error pattern occurring in
the packets. Detect-Compare circuit finds it and invocate the anterior routing node or
source node to reimpart only the damaged part of the packet, if bursts of error occurred
in the packet. At the forwarding nodes, the pristine data is extricated from the packet
and re-encoded utilizing the PCCC circuit.
The outputs of the RSC encoders are compared with the parity bits in the received
packet. This operation obviates highly corrupted packet from propagating through the
network to the base station, where it could be undecodable and lost. Withal it reduces
the size of the retransmitted packets to be only size of the strike part of the packet
when a near node transmits on the same packet transmission duration. The interleaver
here is modeled as a block of variable size N.

The first Recursive Systematic Convolutional encoder (RSC) reads serially data bits from
the recollection row-by-row, while the second RSC encoder reads the data symbol from
the recollection in arbitrary sequence through the interleaver block. The outputs of the
RSC encoders are cumulated with the data sequence to compose the output coded
packet.

Interleaver size which accounts for the amended performance of the turbo codes is the
most influential parameter in the design of turbo codes. To scramble bits in a
pseudo-arbitrary, predetermined fashion is the assignment of interleaver. / Fig 2: TURBO
ENCODER CHAPTER 3 TURBO DECODER Decoding a binary turbo code is based on loop
allows each decoder to take advantage of all the information available.

The values considered at each node of the layout are LLRs, the decoding operations
being performed in the logarithmic domain. The LLR at the output of a decoder of
systematic codes can be seen as the sum of two terms: the intrinsic information, coming
from the transmission channel, and the extrinsic information, which this decoder adds to
the former to perform its correction operation.

As the intrinsic information is used by the two decoders (at different instants), it is the
extrinsic information fabricated by each of the decoders that must be transmitted to the
other as new information, to ensure joint convergence. The MAP algorithm or its
simplified Max-Log-MAP version. Because of latency effects, the exchange of extrinsic
information, in a digital circuit, must be implemented via an iterative process: first
decoding.

If we wanted to decode the turbo code using a single decoder, which would take into
account all the possible states of the encoder, for each element of the message
decoded, we would obtain one and only one probability of having a binary value equal
to 0 or to 1. As for the composite structure, it uses two decoders working jointly. By
analogy with the result that the single decoder would provide, they therefore need to
converge towards the same decisions, with the same probabilities, for each of the data
considered. That is the fundamental principle of "turbo" processing, which justifies the
structure of the decoder, as the following reasoning shows.

/ Fig 3: Turbo Decoder Iterative decoding of turbo codes that can be utilized for very
high-speed decoders. This method was first introduced by Abbasfar and Yao. Albeit this
method is applicable for every turbo code, we will explicate it in the case of a block
PCCC code. The algorithm is as follows. First of all, the received data for each constituent
codes are divided into several contiguous non-overlapping sub-blocks, called windows.

Then, each window is decoded discretely in parallel utilizing the BCJR algorithm. In other
words, each window processor is a vector decoder. However, the initial values for alpha
and beta variables emanate from anterior iteration of adjacent windows. Since all the
windows are being processed concurrently, in the next iteration the initial values for all
of them are yare to load.

Moreover, there is no extra processing needed for the initialization of state probabilities
at each iteration. The size of windows is a very paramount parameter that will be
discussed later. The variables that computed at the same time are simply superseded
with a vector. Each vector has M elements, which belong to different window processors
(SISOs).

For example, we have a0 = [a0 aN a2N • • • aMN-N ]T and b0 = [b0 bN b2N • • •

bMN-N ]T. This notation is the generalization of the serial decoder. It will withal avail to
appreciate the incipient interleaver structure for the parallel decoder discussed later. The
proposed structure stems from the message-passing algorithm itself.

We have only partitioned the graph into some sub graphs and used parallel scheduling,
to diminish the puissance exhaustion of the SMC the trace forward turbo decoding is
proposed. It has five major stages/phases. The branch metrics are computed with the
received code words and the a priori LLR in the natural order. With the help of NRP with
the branch metrics in the natural order, the forward state metrics are recursively
computed and the difference metrics are stored into the SMC. Note that the difference
metric is the distinguishment between two state metrics and has the same bit-length of
the state metric.

TRP recursively traces the forward state metrics with the stored difference metrics in the
inversion order. Concurrently, the forward state metrics are recursively computed with
the branch metrics. The a posteriori LLR is computed with regenerated forward state
metrics, the forward state metrics, and branch metrics by the LAPO in the forward order.

The extrinsic values and hard bits are computed in the inversion order with the a
posterioriLLR. In contrast to the conventional MAP decoding, the trace forward MAP
decoding reduces the number of stored metrics by accessing the difference metrics.
Hence, the SMC power consumption is reduced.

In integration, the computational power overhead of tracing the state metrics back is
much more diminutive than the SMC power consumption. Thus, the overall power
consumption of the MAP decoding is reduced. The work in has introduced that not
absolute value but differences between the state metrics are consequential for the a
posteriori LLR.

The differences between state metrics are kept by storing the difference metrics in the
proposed trace forward computation. Hence, the trace forward MAP decoding performs
without losing rectification ability. In additament, the proposed trace forward
computation works in the L-MAP and (E) ML-MAP. The size of the interleaver defines the
length n of the codeword.

As said in the prelude of this chapter, when n goes to illimitability the probability of
error in the decoding can be kept as minute as desired. This efficaciously holds in a
turbo manner we can have performance very proximate to the channel capacity with n
relatively diminutive. To the above encoder the decoder is built in a kindred way. In
serial way, two elementary decoders are interconnected to each other.

On lower speed the decoder is operated (i.e.,), thus, it is intended for the encoder, and is
for correspondingly. Delay is caused by yielding a soft decision. The delay line in the
encoder causes same delay. The operation causes delay. CHAPTER 4 INTERLEAVER
Interleaving is a process of rearranging the authoritatively mandating of a data
sequence in a one-to-one deterministic format.

The inverse of this process is deinterleaving which recuperates the received sequence to
its pristine order. We consider an interleaver of size N. For simplicity, we postulate that
the data sequence at the input of the interleaver is binary, given by ??=( ?? 1 , ?? 2 , ?? 3
,…, ?? ?? ) Where ci, e {0, 1}, the interleaver permutes the sequence c to a binary
sequence. ??=( ?? 1 , ?? 2 , ?? 3 ,…, ?? ?? ) Where tje {0, 1}, 1 j N.The t bas all the elements
of c but in a different order.

If we consider the input sequence c and the output sequence t as a dyad of sets with N
elements, there is one-to-one correspondence ci—>tj- between each element of c and
each element of C. Let us define a set A as A = { 1, 2, ... N}. The interleaver can then be
defined by a one-to-one index mapping function ?? ????? :??= ?? ?? , ??,?? ?? ?? Where i
and j are the index of an element in the original sequence c and the interleaved
sequence C, respectively.

The mapping function can be represented by an interleaving vector ?? ?? =(?? 1 , ?? 2 ,

?? 3 ,…, ?? ?? ) 4.1. INTERLEAVING IN TURBO DECODER: In turbo coding, an interleaver is
employed afore the information data is encoded by the second component encoder. In
general, the interleaver size N is significantly more immensely colossal than the code
recollection v and the interleaver vector elements are culled desultorily.

The rudimental role of an arbitrary interleaver with immensely colossal size is to

construct a long block code from diminutive recollection convolutional codes, as long
codes can approach the Shannon capacity limit. Secondly, it spreads out burst errors.
second component encoder is provided "scrambled" information data and decorrelates
the inputs to the two component decoders so that an iterative suboptimum decoding
algorithm predicated on "uncorrelated" information exchange between the two
component decoders can be applied.

For example, after rectification of some of the errors in the first component decoder,
some of the remaining errors can be spread by the interleaver such that they become
correctable in the other decoder. By incrementing the number of iterations in the
decoding process the bit error probability approaches the channel capacity. To break
low weight input sequences, and hence increase the code free Hamming distance or
reduce the number of codewords with minuscule distances in the code distance
spectrum is the final role of the interleaver. In turbo coding, the interleaving size and
structure affect the turbo code error performance considerably.

At low SNR'S, the interleaver size is the only paramount n factor, as the code BER
performance is dominated by the interleaver gain. The effects induced by transmuting
the interleaver structure at low SNR region are not paramount. Turbo code minimum
free distance and first several distance spectral lines are affected by interleaver size and
structure.

They play a paramount role in determining the code performance at high SNR'S, and
consequently, the asymptotic performance of the turbo code. It is possible to design
particular interleavers which can result in good code performance at high SNR'S. This is
achieved by breaking several low weight input patterns that engender low weight
codewords in the overall turbo code.

INTERLEAVER DESIGN : From the precedent code performance analysis, the design
criteria of an interleaver for turbo codes can be formulated as follows: 1. Keep the
interleaver desultory. Note that in iterative soft output decoding algorithms, the
information exchange between the two component decoders is possible because of the
interleaving/deinterleaving operations. The input and output sequences of the
interleaver should be uncorrelated.

The more "scrambled" the interleaver, the more "uncorrelated" the information
exchange. 2. Eliminate low-weight codewords with consequential contributions to the
error performance. The most consequential input patterns are those giving immensely
colossal contributions to the code error probability at high SNR'S.

These input patterns engender low weight codewords corresponding to the first several
distance spectral lines in turbo code distance spectrum. The most consequential input
patterns are tenacious on the substratum of the performance analysis. The interleaver
design ascertains that these input patterns are broken such, that the first several
distance spectral lines of the pristine distance spectrum are eliminated. 3. Reduce the
number of other low-weight codewords which could not be eliminated.

Conspicuously, there are quite a sizably voluminous number of low-weight codewords.

In practice, it is not possible to eliminate all the low-weight codewords. Thus, one
should eliminate as many as possible the consequential codewords in the interleaver
design and reduce the number of the code words which could not be eliminated.
CHAPTER 5 PROPOSED SYSTEM ARCHITECTURE __ Fig 4: Turbo ENCODER Schematic
using SB/DB Mode As shown in Fig.

The Turbo encoding scheme in the LTE standard is a parallel concatenated convolutional
code with two 8-state constituent encoders and one convolutional interleaver [23]-[24].
To take a block of N-bit data and produce a permutation of the input data block is the
function of the convolutional interleaver. The performance of a Turbo code depends
critically on the interleaver structure from the coding theory perspective. The basic LTE
Turbo coding rate is 1/3.

It encodes an N-bit information data block in to a code word with 3N+12 data bits,
where 12 tail bits are used for trellis termination. When starting to encode the input
information bits the initial value of the shift registers of the 8-state constituent encoders
shall be all zeros. LTE has defined 188 different block sizes.

The convolutional encoder can be represented as follows: • g0 = 1 + D + D2 + D3 + D6

• g1 = 1 + D2 + D3 + D5 + D6 The convolutional encoder basically multiplies the
generator Polynomials by the input bit string, as follows: • A(x) = g0(x) * I(x) = a b c … g
• B(x) = g1(x) * I(x) = P Q R … V Interleaving the two outputs from the convolutional
encoder yields E(x) = aPbQcR… gV, which can also be written as: E(x) = (a0 b0 c0 … g0) +
(0P0Q0R … 0V) = A(x2)+x*B(x2) Therefore, E(x) = A(x2) +x*B(x2) and A(x2)=g0 (x2)
+I(x2)and B(x2) = g1(x2) * I(x2), with the following: E(x) = g0(x2) * I(x2) + x * g1(x2) * I(x2)
= I(x2) * (g0(x2) + x * g1(x2)) = I(x2) * G(x) Where G(x) = g0(x2) + x * g1(x2) i.e. G(x) =1 +
x + x2 + x4 + x5 + x6 + x7 + x11 + x12 +x13.

__ Fig 5: Generation of SB/DB Modes by Turbo Decoder The general scheme of a basic
decoder is shown in Fig. two interleavers and de-interleavers links the two component
decoders. Each component decoder has three inputs: the systematic information, the
parity information, and the information from the other component decoder.

This information from the other decoder is referred to as a priori information. Both
component decoders have to process both the inputs from the channel as well as a
priori information from each other. Normally used component decoders are having
more complexity and architecture for the purpose of reduced architecture the
component decoders are implemented with the normal decoding architecture. CHAPTER
6 BASIC COMPONENTS Gateway Design Automation Inc started Verilog as an ownership
tackle modeling language in 1984.

It is alleged that the veritable language was designed by taking features from HDL
language of the time, named HiLo, as well as from traditional computer languages such
as C. At that time, it was not standardized and the language reoriented itself in almost
all the emendations that came out within 1984 to 1990. In 1985 Verilog simulator was
first used and broadened greatly through 1987. Gateway sold the implementation of
Verilog simulator.

The first utmost augmentation of Verilog is Verilog-XL adds few features and
implements the infamous "XL algorithm", a very coherent method for doing gate-level
simulation. Later 1990, Cadence Design System, whose primary product at that time
included thin film process simulator, opted to grab Gateway Automation System, along
with other Gateway products. Verilog language is owned by cadence, and pursued to
market Verilog as both a language and a simulator.

Using Verilog, synopsys was marketing the top-down design methodology. This was a
sturdy combination. In 1990, Cadence systematized the Open Verilog International
(OVI), and in 1991 gave it the documentation for the Verilog Hardware Description
Language. This was the event which "opened" the language. 6.1.

HARDWARE DESCRIPTION LANGUAGE: Two things distinguish an HDL from a linear

language like “C”: Concurrency: • The ability to do several things in concert i.e. different
code-blocks can run coincidently. Timing: • Calibre to represent the progressing of time
and sequence events accordingly. 6.2. VERILOG INTRODUCTION: • Verilog HDL is a
Hardware Description Language (HDL).

• A Hardware Description Language is a language to evoke a digital system; one may

describe a digital system at several levels. • It elucidates the layout of the wires, resistors
and transistors on an Integrated Circuit (IC) chip, i.e., the switch level. • The logical gates
and flip flops in a digital system are described, i.e., the gate level.

• The registers and the transfers of vectors of information between registers are narrated
by an even higher level. This is called the Register Transfer Level (RTL). • Verilog
supports all of these stratums. • Verilog HDL can use the same language for expressing,
testing and detecting your system. 6.3. VERILOG FEATURES: • Strong Background:
Supported by OVI, and standardized in 1995 as IEEE std 1364 • Industrial support: Fast
pretention and potential synthesis (85% were used in ASIC foundries by EE TIMES) •
Universal: Allows complete process in one design abode (including analysis and
verification) • Extensibility: Verilog PLI that allows for elongation of Verilog capabilities
VLSI DESIGN FLOW : The typical design flow is shown in figure Fabrication & testing Fig
6: VLSI Design Flow 6.4.1

DESIGN SPECIFICATIONS: • Prescriptions are inscribed first-Requirement/needs about

the project • Describe the functionality inclusive architecture of the digital circuit to be
designed. • Specification: Word processor like Word, Kwriter, AbiWord and for drawing
waveform use tools like wave former or test bencher or Word. 6.4.2. RTL DESCRIPTION: •
Conversation of Specification in coding format using CAD Tools. 6.4.3.

CODING STYLES: • Gate Level Modeling • Data Flow Modeling • Behavioral Modeling •
RTL Coding Editor: Vim, Emacs, context, HDL TurboWriter Functional Verification
&Testing: • Comparing the coding with the specifications. • Testing the Process of
coding with corresponding inputs and outputs. • If testing fails – once again check the
RTL Description.

• Simulation: Modelsim, VCS, Verilog-XL, Xilinx Fig 7: Simulation Output View of 4:1 MUX
Using Modelsim Wave form Viewer Logic Synthesis: • Parley of RTL description into Gate
level -Net list form. • Delineation of the circuit in terms of gates and connections. •
Synthesis: Design Compiler, FPGA Compiler, Simplify Pro, Leonardo Spectrum, Altera
and Xilinx.

/ Fig 8: Synthesis of 4:1 MUX Using Leonardo Spectrum Logical Verification and Testing:
• Functional Checking of HDL coding by simulation and synthesis. If fails – check the RTL
description. Floor Planning Automatic Place and Route • Creation of Layout with the
corresponding gate level Net list. • Arrange the blocks of the net list on the chip • Place
& Route: For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools
like Apollo.

Students can use LASI, Magic Physical Layout: • Overhauling a circuit description into
the physical layout is processed by physical design. The position of cells and routes for
the interconnections between them are described. Layout Verification: • The physical
layout structure is ratified. • Once again check Floor Planning Automatic Place and
Route and RTL Description if any modification. Implementation: • Final stage in the
design process.

• Implementation of coding and RTL in the form of IC.

Fig 9: Layout view of a system 6.5. DESIGN HIERARCHIES: 6.5.1. BOTTOM UP DESIGN
The traditional method of electronic design is bottom up. At the gate level using the
standard gates each design is performed. It is impossible to maintain with increasing
complexity of new designs. A way is given to new structural, hierarchical design
methods.

It would be impossible to handle the new complexity without these design practices.
Fig 10: Bottom up Design 6.5.2. TOP-DOWN DESIGN: Real top design allows early
testing, easy change of different technologies, and a structured system design and offer
many other advantages. It is hard to follow a pure top-down design. Both the methods
are mixed of most designs, implementing both design styles key elements.

/ Fig 11: Top-Down Design 6.5.3. LEXICAL CONVENTIONS: C programming language has
similar basic lexical conventions in Verilog HDL Verilog contains a stream of tokens.
They are comments, delimiters, numbers, strings, identifiers, and keywords. It is a
case-sensitive language. All keywords are in lower case. Whitespace: It contains the
characters for blanks, tabs, newlines, and form feeds. When they serve to separate other
tokens these are ignored.

However, blanks and tabs are significant in strings. White space characters are: • Blank
spaces (\b) • Tabs(\t) • Carriage returns(\r) • New-line (\n) • Form-feeds (\a) Example
modulepound_one; reg[7:0] a,a$b,b,c; //registerdeclarations regcl; initial begin clk=0;
//initialize the clock c = 1; forever #25 clk = !clk; end /* This section of code implements
a pipeline */ Always @ {posedgeclk} begin a = b; b = c; end end module Comments:
Comments can be inserted in the code for readability and documentation.

There are two forms to introduce comments. • Single line comments begin with the
token // and end with a carriage return • Multi line comments begin with the token /*
and end with the token */ Example modulepound_one; reg[7:0] a,a$b,b,c;
//registerdeclarations regclk; initial begin clk=0; //initialize the clock c = 1; forever
#25clk = !clk; end /* This section of code implements a pipeline */ always @
{posedgeclk} begin a = b; b = c; end end module 6.6.

IDENTIFIERS AND KEYWORDS: Identifiers are names used to give an object, such as a
register or a function or a module, a name in a description can be referenced from other
places. To define the language constructs keywords are reserved. • It must begin with an
alphabetic character or the underscore character (a-z A-Z _) • It may contain alphabetic
characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $) •
They can be up to 1024 characters long. • Keywords are in lowercase.

Examples of legal identifiers: • data_input mu • clk_inputmy$clk • i386 Examples of

keywords: • always • begin • end 6.6.1. ESCAPED IDENTIFIERS: Allows any character by
Verilog HDL to be used in an identifier by escaping the identifier. It supplies a means of
including any of the printable. ASCII characters in an identifier (the decimal values 33
through 126, or 21 through 7E in hexadecimal).

• Escaped identifiers begin with the back slash ( \ ) • Back slash escapes entire identifier.
• White space terminates it (Characters such as commas, parentheses, and semicolons
become part of the escaped identifier unless preceded by a white space) • Cease it with
white space, otherwise the identifier followed by characters are considered as part of it.
6.6.2.

NUMBERS IN VERILOG: Numbers in Verilog can be specified constant numbers in

decimal, hexadecimal, octal, or binary format. In 2's complement form negative numbers
are represented. The question mark (?) character is the Verilog alternative for the z
character, when used in a number. Except as the first character the underscore character
(_) is legal anywhere in a number, where it is ignored. 6.6.2.1.

INTEGER NUMBERS: Integer numbers can be specified as • Sized or unsized numbers

(Unsized size is 32 bits) • In a radix of binary, octal, decimal, or hexadecimal • Radix and
hex digits (a, b, c, d, e, and f) are case insensitive • Spaces are allowed between the size,
radix and value Integer numbers are represented as <size>’<base
format><number><size>is written only in decimal and specifies the number of bits in
the number.

Legal base formats are decimal (‘d or ‘D), hexadecimal (‘h or ‘H), binary (‘b or ‘B) and
octal (‘o or ‘O). the number is specified as consecutive digits from
0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular base.
Uppercase letters are legal for number specification. 4’b1111 –this is a 4-bit binary
number 12’habc – this is a 12-bit hexadecimal number 16’d255 – this is a 16-bit decimal
number 8’o44-this is 8 bit octal number 6.6.2.2.

REAL NUMBERS: • Verilog supports real constants and variables • Verilog converts real
numbers to integers by rounding • Real Numbers can not contain 'Z' and 'X' • Real
numbers may be specified in either decimal or scientific notation • < value >.< value > •
< mantissa >E< exponent > • Real numbers are rounded off to the nearest integer when
assigning to an integer. Example Real Number _Decimal notation _ _1.2

_1.2 _ _0.6 _0.6 _ _3.5E6 _3,500000.0 _ _ 6.6.2.3. SIGNED AND UNSIGNED NUMBERS:
Verilog supports both types of numbers, but with certain restrictions. Like in C language
it doesn’t have int and unint types to say if a number is signed integer or unsigned
integer. Any number that does not have negative sign prefix is a positive number. Or
indirect way would be "Unsigned".

By putting a minus sign before the size for a constant number negative numbers can be
specified, thus they become signed numbers. Verilog internally represents negative
numbers in 2's complement format. Signed arithmetic is added by an optional signed
specifier. Example Number _Description _ _32’hDEAD_BEEF _Unsigned or signed positive
number _ _-14’h1234 _Signed negative number _ _ Example modulesigned_number; reg
[31:0] a; initial begin a = 14'h1234; $display ("Current Value of a = ‰h", a); a =
-14'h1234; $display ("Current Value of a = ‰h", a); a = 32'hDEAD_BEEF; $display
("Current Value of a = ‰h", a); a = -32'hDEAD_BEEF; $display ("Current Value of a =
‰h", a); #10 $finish; end endmodule 6.6.3.

STRINGS: Double quotes are enclosed in a string, a sequence of character. It must be

contained on a single line, that is, without a carriage return. It cannot be on multiple
lines. They are treated as a sequence of one-byte ASCII values. Examples “hello Verilog
world” “a/b” “aa+a” 6.6.4. DATA TYPES: A data type associated with every signal: •
Explicitly declared with a declaration in your Verilog code.

• Implicitly declared with no declaration when used to connect structural building blocks
in your code. Implicit declaration is always a net type "wire" and is one bit wide. 6.6.4.1.
DATA TYPES VALUE SET: To model the functionality of real hardware Verilog supports
four values and eight strengths.

The four levels are listed in table Value level Condition in hardware circuits: 0 logic zero,
false condition 1 logic one, true condition x unknown value z High impedance, floating
state 6.6.4.2. REGISTER DATA TYPES: • The last value assigned to them stored by register
until another assignment statement changes their value. • It represents data storage
constructs. • Regs arrays called memories can be formed. • Variables are used as register
data types in procedural blocks.

• It is required if a signal is assigned a value within a procedural block • Procedural

blocks begin with keyword initial and always. Example Data Types _Functionality _ _reg
_Unsigned variable _ _integer _Signed variable – 32 bits _ _time _Unsigned integer – 64
bits _ _real _Double precision floating point variable _ _ 6.6.4.3. VECTORS: Vectors are
declared as net or reg data types. Scalar is default, if bit width is not mentioned
(1-bit).Vectors can be declared at [high#: low#] or [low#: high#], but the left number in
the squared brackets is always the most significant bit of the vector.

Examples wire a // scalar net variable default wire [7:0]bus; // 8-bit bus wire [31:0] busA,
busB, busC; // 3 buses of 32-bit width reg clock // scalar register busA[7]; // bit #7 of
vector busA bus [2:0] // three least significant bits of vector bus 6.6.4.4. INTEGER, REAL
AND TIME REGISTER DATA TYPES INTEGER: For manipulating quantities an integer is a
general purpose register data type used.

Integers are declared by the keyword integer. Reg is used as a general-purpose variable
and to declare an integer variable for purposes such as counting it is more convenient.
For an integer the default width is the host-machine word size, but is at least 32 bits and
implementation specific.

Registers store values as unsigned quantities and integers store as signed quantities.
Example integer counter; // general purpose variable used as a counter initial
counter=-1; // A negative one is stored in the counter Real: Keyword real declares real
number constants and real register data types. They can be specified in decimal notation
or in scientific notation.

Real numbers cannot have a range declaration, and their default value is 0. When a real
value is assigned to an integer, the real number is rounded off to the nearest integer.
Example real delta; // define a real variable called delta initial begin delta=4e10; // delta
is assigned in scientific notation delta=2.13 ; // delta is assigned a value 2.13 end integer
i; // define an integer i Time: Verilog simulation is done with respect to simulation time.

To store simulation time, a special time register data type is used in Verilog. Keyword
time is declared with a time variable. The width for time register data types is
implementation specific but is at least 64 bits. To get the current simulation time, the
system function $time is invoked. Example timesave_sim_time; // define a time variable
save_sim_time initial save_sim_time=$time; // save the current simulation time Arrays:
Arrays are allowed in Verilog for reg, integer, time and vector register data types. Arrays
are not allowed for real variables. Arrays are accessed by <array_name>[<subscript>].

Multidimensional arrays not permitted in Verilog. Example integer count[7:0]; // an array

of 8 count variables reg bool[31:0]; // array of 32 one-bit Boolean register variables
integer matrix[4:0][4:0]; // illegal declaration Multidimensional array Memories: One
often needs to model register files, RAMs and ROMs in digital simulation.

In Verilog, they are modeled as an array of registers. Word is defined as each element of
the array. One or more bits are in each word. Differentiation of n 1-bit registers and one
n-bit register is crucial. A particular word in memory is obtained by using the address as
a memory array subscript. Example reg mem1bit[0:1023]; // memory mem1bit with 1K
1-bit words reg [7:0]membyte[0:1023]; // memory membyte with 1K 8-bit words
Parameters: In a module constants are allowed by Verilog are define with the keyword
parameter. Parameters cannot be used as variables.

At compile time parameter values for each module instance can be overridden
individually. The module instances are customized. Example parameterport_id = 5;
//Defines a constant port_id parametercache_line_width= 256; // Constant defines width
of cache line Strings: In reg strings are stored. To hold it the width of the register
variables must be large enough. In it each character takes up 8 bits (1 byte).

Verilog fills bits to left of the string with zeros, if the width of the register is greater than
the size of the string. Verilog truncates the leftmost bits of the string, if the register
width is smaller than the string width. It is always safe to declare that is slightly wider
than necessary.

Example reg [8*81:1] string_value; // declare a variable that is 18 bytes wide initial
string_value=”hello Verilog course team”; // string can be stored in variable 6.7.
MODULE STRUCTURE: As shown in figure a module in Verilog consists of distinct parts.
A module definition always begins with the keyword module. In a module definition the
module name, port list, port declarations, and optional parameters must come first.

If the module has any ports to interact with the external environment, only port list and
port declarations are presented. The five components within a module are; • variable
declarations, • dataflow statements • instantiation of lower modules • behavioral blocks
• tasks or functions. These components can be in any order and at any place in the
module definition. The end module statement must always come last in a module
definition.

Except module, module name, and end module, all components are optional and can be
mixed and matched as per design needs. Multiple modules defined in a single file are
allowed by Verilog. They can be defined in any order in the file. Fig 12: Module Structure
Example Module Structure: module<module name>(<module_terminals_list>); …..
<module internals> ….

Endmodule Instances: A template is provided by module from which you can create
actual objects. Verilog creates a unique object from the template, when it is invoked.
Each object has its own name, variables, parameters and I/O interface. Instantiation is
explained as the process of creating objects from a module template, and the objects
are called instances.

In Example below, the top-level block creates four instances from the T flip- flop (T_FF)
template. Each T_FF instantiates a D_FF and an inverter gate. Each Instance must be
given a unique name. Example // Define the top-level module called ripple carry //
counter. It instants 4 T-filpflops. // four instances of the module T_FF are created. Each
has a unique name.

// each instance is passed a set of signals moduleripple_carry_counter(q,clk,reset);

output [3:0]q; inputclk,reset; T_FF tff0(q[0],clk,reset); T_FF tff1(q[1],q[0],reset); T_FF
tff2(q[2],q[1],reset); T_FF tff3(q[3],q[2],reset); endmodule // define the module T_FF. it
instantiates a D-filpflop. module T_FF(q,clk,reset); output q; inputclk,reset; wire d; D_FF
dff0(q,d,clk,reset); not n1(d,q); endmodule 6.8.

PORTS: It provides the interface by which a module communicates with its environment.
For example, the input/output pins of an IC chip are its ports. The module only through
its ports can be interacted by environment. The internals of the module are not visible to
the environment. This provides a very powerful flexibility to the designer.

The module internals can be changed without affecting the environment as long as the
interface is not modified. Ports are also referred to as terminals. 6.8.1. PORT
DECLARATION: All ports in the list of ports must be declared in the module. Ports can be
declared as follows 6.8.1.1. VERILOG KEYWORD TYPE OF PORT: inputInput port
outputOutput port inout Bidirectional port Each port in the port list is defined as input,
output, or inout, based on the direction of the port signal. 6.8.2.

PORT CONNECTION RULES: One can visualize a port as consisting of two units, one unit
that is internal to the module another that is external to the module. The internal and
external units are connected. When modules are instantiated within other modules,
there are rules governing port connections. The Verilog simulator complains if any port
connection rules are violated. They are summarized in figure. / Fig 13: Port connection
Rules 6.8.2.1

INPUTS: • Internally must be of net data type (e.g. wire) • Externally the inputs may be
connected to a reg or net data type 6.8.2.2. OUTPUTS: • Internally may be of net or reg
data type • Externally must be connected to a net data type 6.8.2.3 INOUTS: • Internally
must be of net data type (tri recommended) • Externally must be connected to a net
data type (tri recommended) 6.8.3.

PORTS CONNECTION TO EXTERNAL SIGNALS: Making connections between signals

specified in the module instantiation and ports in a module definition, there are two
methods. The two methods cannot be mixed. • Port by order list • Port by name 6.8.3.1
PORT BY ORDER LIST Connecting port by order list is the most intuitive method for
most beginners.

The signals to be connected must appear in the module instantiation in the same order
as the ports in the ports list in the module definition. Syntax for instantiation with port
order list: module_name instance_name (signal, signal...); From the below example,
notice that the external signals a, b, out appear in exactly the same order as the ports a,
b, out in the module defined in adder below.
Example module adder(a,b,out); module top_example; input[1:0]a; reg [1:0]a; input[1:0]b;
reg [1:0]b; output[1:0]out; wire[1:0]out; wire[1:0]out; assign out = a+b; adder
ex1(a,b,out); endmodule; endmodule; 6.8.3.2 PORT BY NAME For larger designs where
the module have ,say 5o ports , remembering the order of the ports in the module
definition is impractical and error prone.

Verilog provided the capability to connect external signals to ports by the port names,
rather than by position. Syntax for instantiation with port name: module_name
instance_name (.port_name(signal), .port_name (signal)… ); From the below example,
note that the port connections in any order as long as the port name in the module
definition correctly matches the external signal. 6.8.4. MODELING CONCEPTS Verilog is
both a behavioral and a structural language.

At four levels of abstraction internals of each module to be defined, depending on the

needs of the design. With the external environment the module behaves identically
irrespective of the level of abstraction at which it is described. The internals of the
module are hidden from the environment. A module can be changed without any
change in the environment described by the level of abstraction.

The levels are defined below 6.8.4.1. BEHAVIORAL OR ALGORITHMIC LEVEL Verilog HDL
provided this highest level of abstraction. Without concern for the hardware
implementation details a module can be implemented in terms of the desired design
algorithm. At this level designing is similar to C programming 6.8.4.2. DATAFLOW LEVEL
By specifying the data flow module is designed.

How data flows between hardware registers and the data processed in the design is
known by designer. 6.8.4.3. GATE LEVEL The module is implemented in terms of logic
gates and interconnections between these gates. Design at this level is similar to
describing a design in terms of a gate-level logic diagram. 6.8.4.4. SWITCH LEVEL This is
the last level of abstraction in Verilog.

A module can be implemented in terms of switches, storage nodes, and the

interconnections between them. Design requires knowledge of switch-level
implementation details. The designer mix and match all four levels of abstractions in a
design by Verilog. Register Transfer Level (RTL) is frequently used for a Verilog
description that uses a combination of behavioral and dataflow constructs and is
acceptable to logic synthesis tools. Verilog allows four modules to be written at a
different level of abstraction.
Gate-level implementations are replaced in the place of modules, as the design matures.
The more flexible and technology Independent of the design is the higher level of
abstraction. As one goes lower toward switch-level design, the design becomes
technology dependent and inflexible.

A significant number of changes in the design causes by small modification. Compare

the analogy with C programming and assembly language programming. It is easier to
program in higher level language such as C. The program can be easily ported to any
machine. However, if the design at the assembly level, the program is specific for that
machine and cannot be easily ported to another machine.

This attack[2] basically exploits the fact that to the round function of AES two particular
inputs transform into output vectors with a unique Hamming distance in between after
one round of encryption. For instance, the Hamming distance between the one round
output vectors can only have a handful of values, if two plaintexts with an XOR
difference of 0x01 in their least significant byte (LSB), are encrypted using only one
round of AES.

Due to the structure of the Mix Column operation, a one byte difference in the plaintext
will transform into a four byte difference. One can easily verify that there are four
Hamming distance values (9, 12, 23 and 24) which can only be generated by a unique
pair of inputs, by analyzing the distribution of the Hamming distances for all 27 pairs
generated with the byte difference 0x01 in their LSB.

Therefore, whenever such a Hamming distance is observed between the output vectors,
one can XOR the corresponding plaintext byte with the pre-computed value to recover a
byte of the encryption key. CHAPTER 7 GATE LEVEL MODELING Gates, transmission
gates, and switches are Verilog built in primitives. For modeling the ASIC/FPGA cells
these are rarely used in design (RTL Coding), and used in post synthesis world; these
cells are then used for gate level simulation.

The output netlist format from the synthesis tool is also in Verilog gate level primitives
which are imported into the place and route tool. GATE TYPES : Logic gates are helped
to design the logic circuit. They are predefined primitives. Which are instantiated as
modules except the predefined in Verilog and a module definition is not necessary.
Basic gates are helpful in circuit design.

There are two classes of basic gates: and/or gates and buf/not gates. And/or gates
And/or gates has multiple scalar inputs and one scalar output. In list of gate terminals
the first terminal is an output and remaining are inputs. As soon as one of the inputs
changes the output of a gate is evaluated. These gates available in Verilog are shown
below. And or xornand nor xnor The corresponding logic symbols for these gates are
shown in figure.

We consider gates with two inputs and are instantiated to build logic circuits in Verilog.
Examples of gate Instantiations are shown below. In the below example, for all instances,
OUT is connected to the output out, and IN1 and IN2 are connected to the two inputs i1
and i2 of the gate primitives. / Fig 14: Gates symbol The instance name does not need
to be specified for primitives.

More than two inputs can be specified in gate instantiation, by simply adding more
ports. The appropriate gate is instantiated by Verilog automatically. Example Gate
Instantiation of And/Or gates / The truth tables for these gates are given below,
assuming two inputs. Outputs of gates with more than two inputs are computed by
applying the truth table iteratively.

Buf/Bufif1/Bufif0/Not/Notfif1/Notfif0 Gates Buf/not gates have one or more scalar

output and one scalar input. Input is connected to the lasts terminal in the port list.
Other terminals are connected the outputs. Bufif1, Bufif0, Notif1, Notifo gates propagate
only if their control signal is asserted. Such a situation is applicable when multiple
drivers drive the signal.

To drive the signal on mutually exclusive control these drivers are designed. If their
control signal is deasserted they propagate z. They propagate z if their control signal is
deasserted. buf not bufif1 notfif1 bufif1 bufif0 / Fig 15: Gates Buf, Not, Bufif1, Bufif0,
Notif1, Notif0 / Fig 16: Truth Table Example Gate Instantiation of Buf/Not gates Example
/ From the above example, these gates can have multiple outputs but exactly one input,
which is the last terminal in the port list.

The truth tables for these gates are shown below. / Examples AND Gate from NAND
Gate / Fig 17: Structural model of AND gate from two NANDS moduleand_from_nand();
reg X, Y; wire F, W; // Two instantiations of the module NAND nand U1(W,X, Y); nand
U2(F, W, W); // Testbench Code initial begin $monitor ("X = %b Y = %b F = %b", X, Y, F);
X = 0; Y = 0; #1 X = 1; #1 Y = 1; #1 X = 0; #1 $finish; end endmodule Simulation Output
X = 0 Y = 0 F = 0 X = 1 Y = 0 F = 0 X = 1 Y = 1 F = 1 X = 0 Y = 1 F = 0 D-Flip flop from
NAND Gate / Fig 18: Structural model of D Flip-flop from NAND Gate
moduledff_from_nand(); wire Q,Q_BAR; reg D,CLK; nand U1 (X,D,CLK) ; nand U2 (Y,X,CLK)
; nand U3 (Q,Q_BAR,X); nand U4 (Q_BAR,Q,Y); // Test bench initial begin $monitor("CLK
= %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR); CLK = 0; D = 0; #3 D = 1; #3 D =
0; #3 $finish; end always #2 CLK = ~CLK; endmodule Simulation Output CLK = 0 D = 0
Q = x Q_BAR = x CLK = 1 D = 0 Q = 0 Q_BAR = 1 CLK = 1 D = 1 Q = 1 Q_BAR = 0 CLK =
0 D = 1 Q = 1 Q_BAR = 0 CLK = 1 D = 0 Q = 0 Q_BAR = 1 CLK = 0 D = 0 Q = 0 Q_BAR =
1 7.2.

BEHAVIORAL AND RTL MODELING Designers were provided the ability by Verilog to
describe design functionality in an algorithmic manner. The designer describes the
behavior of the circuit. The circuit at a very high level of abstraction is represented by
behavioral modeling. Design resembles C programming more than it resembles digital
circuit design. In many ways behavioral Verilog constructs are similar to C language
constructs.

Verilog provides the designer with a great amount of flexibility due to rich in behavioral
constructs. 7.3. OPERATORS Verilog provided many different operators types. Operators
can be, • Arithmetic Operators • Relational Operators • Bit-wise Operators • Logical
Operators • Reduction Operators • Shift Operators • Concatenation Operator •
Replication Operator • Conditional Operator • Equality Operator Arithmetic Operators •
These perform arithmetic operations.

The + and - can be used as either unary (-z) or binary (x-y) operators. • Binary: +, -, *, /,
% (the modulus operator) • Unary: +, - (This is used to specify the sign) • Integer division
truncates any fractional part • The result of a modulus operation takes the sign of the
first operand • If any operand bit value is the unknown value x, then the entire result
value is x • Register data types are used as unsigned values (Negative numbers are
stored in two's complement form) Example module arithmetic_operators(); initial begin
$display (" 5 + 10 = %d", 5 + 10); $display (" 5 - 10 = %d", 5 - 10); $display (" 10 - 5 =
%d", 10 - 5); $display (" 10 * 5 = %d", 10 * 5); $display (" 10 / 5 = %d", 10 / 5); $display ("
10 / -5 = %d", 10 / -5); $display (" 10 %s 3 = %d","%", 10 % 3); $display (" +5 = %d", +5);
$display (" -5 = %d", -5); #10 $finish; end endmodule Simulation Output 5 + 10 = 15 5 -
10 = -5 10 - 5 = 5 10 * 5 = 50 10 / 5 = 2 10 / -5 = -2 10 % 3 = 1 +5 = 5 -5 = -5
Relational Operators Two operands are compared and return a single bit 1or 0. These
operators synthesize into comparators.

Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d1 10,
however for integers -1< 6 Operator _Description _ _a < b _a less than b _ _a > b _a
greater than b _ _a <= b _a less than or equal to b _ _a >= b _a greater than or equal to
b _ _ • The result is a scalar value (example a < b) • 0 if the relation is false (a is bigger
than b) • 1 if the relation is true ( a is smaller than b) • x if any of the operands has
unknown x bits (if a or b contains X) Note: If any operand is x or z, then the result of that
test is treated as false (0) Example modulerelational_operators(); initial begin $display ("
5 <= 10 = %b", (5 <= 10)); $display (" 5 >= 10 = %b", (5 >= 10)); $display (" 1'bx <= 10
= %b", (1'bx <= 10)); $display (" 1'bz<= 10 = %b", (1'bz <= 10)); #10 $finish; end
endmodule Simulation Output 5 <= 10 = 1 5 >= 10 = 0 1'bx <= 10 = x 1'bz<= 10 = x
Bit-wise Operators A bit wise operation is performed on two operands.

The operation is performed by taking each bit in one operand with the corresponding
bit in the other operand. It will be extended on the left side with zeroes to match the
length of the longer operand, if one operand is shorter than the other. Operator
_Description _ _~ _negation _ _& _and _ _| _inclusive or _ _^ _exclusive or _ _^~ or ~^
_exclusive nor (equivalence) _ _ • Computations include unknown bits, in the following
way: • -> ~x = x • -> 0&x = 0 • -> 1&x = x&x = x • -> 1|x = 1 • -> 0|x = x|x = x • -> 0^x
= 1^x = x^x = x • -> 0^~x = 1^~x = x^~x = x • When operands are of unequal bit
length, the shorter operand is zero-filled in the most significant bit positions. Logical
Operators It returns a single bit 1 or 0.

They are the same as bit-wise operators only for single bit operands. Treat all values that
are nonzero as “1” and they can work on expressions, integers or groups of bits. Logical
operators are typically used in conditional (if ... else) statements since they work with
expressions.

Operator _Description _ _! _logical negation _ _&& _logical and _ _|| _logical or _ _ •

Expressions connected by && and || are evaluated from left to right • Evaluation stops
as soon as the result is known • The result is a scalar value: • -> 0 if the relation is false •
-> 1 if the relation is true • -> x if any of the operands has x (unknown) bits Reduction
Operators On all the bits of an operand vector and return a single bit value are
operated.

These are the unary (one argument) form of the bit-wise operators. Operator
_Description _ _& _and _ _~& _nand _ _| _or _ _~| _nor _ _^ _xor _ _^~ or ~^ _xnor _ _•
Reduction operators are unary. • They perform a bit-wise operation on a single operand
to produce a single bit result.

• Reduction unary NAND and NOR operators operate as AND and OR respectively, but
with their outputs negated. • -> Unknown bits are treated as described before Shift
Operators Shift operators shift the first operand by the number of bits specified by the
second operand. For both left and right shifts, vacated positions are filled with zeros
(There is no sign extension).

Operator _Description _ _<< _Left shift _ _>> _Right shift _ _ • The number of bit
positions shifts the left operand given by the right operand. • The vacated bit positions
are filled with zeroes Concatenation Operator To form a larger vector the concatenation
operator combines two or more operands. • They are expressed using the brace
characters {and}, with commas separating the expressions within.

• ->Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24
bits • Unsized constant numbers are not allowed in concatenations. Example module
concatenation_operator(); initial begin // concatenation $display (" {4'b1001,4'b10x1} =
%b", {4'b1001,4'b10x1}); #10 $finish; End 7.4. OPERATOR PRECEDENCE Operator
_Symbols _ _Unary, Multiply, Divide, Modulus _!, ~, *, /, % _ _Add, Subtract,Shift _+, -, <<,
>> _ _Relation, Equality _<, >, <=, >=, ==, !=, ===, !== _ _Reduction _&, !&, ^, ^~, |, ~|
_ _Logic _&&, || _ _Conditional _? : _ _ 7.5.

PROCEDURAL BLOCKS Procedure blocks contain Verilog behavioral code, but there is an
exception: some behavioral code also exist outside procedure blocks. We can see this in
detail as we make progress. There are two types of procedural blocks in Verilog: • initial:
initial blocks execute only once at time zero (start execution at time zero).

• always: always blocks loop to execute over and over again; in other words, as the name
suggests, it executes always. Example – initial moduleinitial_example();
regclk,reset,enable,data; initial begin clk = 0; reset = 0; enable = 0; data = 0; end
endmodule In the above example, the initial block execution and always block execution
starts at time 0.

Always block waits for the event, here positive edge of clock, whereas initial block just
executed all the statements within begin and end statement, without waiting. Example –
always modulealways_example(); regclk,reset,enable,q_in,data; always @ (posedgeclk) if
(reset) begin data<= 0; end else if (enable) begin data<= q_in; end endmodule In an
always block, the code inside begin and end is executed, when the trigger event occurs;
the always block waits for next event triggering once again. Till simulation stops this
process of waiting and executing on event is repeated.

CHAPTER 8 SIMULATION RESULTS / Fig 19: RTL Schematic of Turbo Encoder / Fig 20:
Technology Schematic of Turbo Encoder
Fig 21: Output wave forms of Turbo Encoder
Fig 22: Technology Schematic of Turbo Decoder
Fig 23: RTL schematic of Turbo Decoder / Fig 24: Simulation Results of Turbo Decoder
Fig 25: RTL Schematic of SB/DB Modes of Turbo Decoder
Fig 26: Simulation Results of SB/DB Modes CHAPTER 9 APPLICATIONS With the
excellent performance compared to that of other existing codes, turbo codes and its
successors have been adopted into many communication systems and incorporated
with various industrial standards.
TURBO CODE APPLICATIONS provide vast coverage of those applications starting from
data storage systems through wire-line wireless communication. That includes the
utilization in digital video broadcasting, satellite communications, space exploring
systems, and the implementation technologies. It is a rich source for scientists,
engineers, and students who are searching for numerous aspects of turbo code
applications which revolutionized the digital communications.

CHAPTER 10 CONCLUSION In this paper, we demonstrated that upon aiming for a high
throughput, conventional LUT-Log-BCJR architectures may have wasteful designs
requiring high chip areas and hence high energy consumptions. However, in
energy-constrained applications, achieving a low energy consumption has a higher
priority than having a high throughput.

This motivated our low-complexity energy-efficient architecture, which achieves a low

area and hence a low energy consumption by decomposing the LUT-Log-BCJR
algorithm into its most fundamental ACS operations. In this paper, the high-throughput
dual-mode (SB/DB) EML-MAP processor for wireless WAN has been presented and
implemented. CHAPTER 11 REFERENCES [1] R. Lin, P. A. Martin, and D. P. Taylor,
“Cooperative signalling with soft information combining,” J. Electr. Comput. Eng.,
Hindawi, vol.

2010, Article ID 530190, 2010. [2] J. N. Laneman, D. N. C. Tse, and G. W. Wornell,

“Cooperative diversity in wireless networks: efficient protocols and outage behavior,”
IEEE Trans. Inf. Theory, vol. 50, pp. 3062–3080, Dec. 2004. [3] M. Janani, A. Hedayat, T. E.
Hunter, and A. Nosatinia, “Coded cooperation in wireless communications: space- time
transmission and iterative decoding,” IEEE Trans.

Signal Process., vol. 52, pp. 362–370, Feb. 2004. [4] “3rd generation partnership project
(3GPP),”[Online]. Available: http://www.3gpp.org/ [5] C. Berrou and M. Jezequel,
“Non-binaryconvolutional codes for turbo coding,” Electron.Lett., vol. 35, no. 1, pp.
39–40, Jan. 1999. [6] “Worldwide interoperability for microwaveaccess (WiMAX),”
[Online]. Available:http://www.wimaxforum.org/home/ [7] M. Bickerstaff, L. Davis, C.
Thomas, D.

Garrett,and C. Nicol, “A 24Mb/s radix-4 LogMAPturbodecoder for 3GPP-HSDPA mobile

wireless,” in Proc.IEEE Int. Solid-State Circuits Conf. (ISSCC), 2003,pp. 1–10. [8] C.-H. Lin,
C.-Y.Chen, and A.-Y.Wu, “Highthroughput12-Mode CTC decoder for WiMAXstandard,” in
Proc. IEEE Int. Symp. VLSI Des.,Autom., Test (VLSI-DAT), 2008, pp. 216–219. [9] U.
Ramacher, “Software-defined radio prospectsformultistandard mobile phones,” IEEE
Comput.,vol. 40, no. 10, pp. 62–69, Oct. 2007. [10] T.

Vogt and N. Wehn, “A reconfigurable ASIPfor convolutional and turbo decoding in an

SDRenvironment,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 16, no. 10, pp.
1309–1320, Oct.2008. [11] O. Muller, A. Baghadadi, and M. Jezequel, “Fromparallelism
levels to a multi-ASIP architecture forturbo decoding,” IEEE Trans. Very Large
ScaleIntegr. (VLSI) Syst., vol. 17, no. 1, pp. 92–102, Jan.2009. [12] L. R. Bahl, J. Cocke, F.
Jelinek, and J.

Raviv,“Optimal decoding of linear codes for minimizingsymbol error rate,” IEEE Trans.
Inf. Theory, vol. 20,no. 2, pp. 284–287, Mar. 1974. [13] J.-M. Hsu and C.-L.Wang, “A
parallel decodingscheme for turbo decoders,” in Proc. IEEE Int. Symp.Circuits Syst.
(ISCAS), 1998, vol. 4, pp. 445–448. [14] A. Worm, H. Lamm, and N. Wehn, “A
highspeedMAP architecture with optimized memory sizeand power consumption,” in
Proc. IEEE WorkshopSignal Processing Syst. (SiPS), 2000, pp. 265–274.

[15] C. Schurgers, F. Catthoor, and M. Engels,“Memory optimization of MAP turbo

decoder algorithms,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 9, no. 2, pp.
305–312, Apr. 2001. [16] M. M. Mansour and N. R. Shanbhag, “VLSIarchitectures for
SISO-APP decoders,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4,pp.
627–650, Aug. 2003. [17] S.-J. Lee, N. R. Shanbhag, and A. C. Singer,“Area-efficient
highthroughput MAP decoderarchitectures,” IEEE Trans.

Very Large Scale Integr.(VLSI) Syst., vol. 13, no. 8, pp. 921–933, Aug. 2005. [18] S.-J. Lee,
N. R. Shanbhag, and A. C. Singer, “A285-MHz pipelined MAP decoder in 0.18.umCMOS,”
IEEE J. Solid-State Circuits, vol. 40, no. 8,pp. 1718–1725, Aug. 2005. [19] Z.Wang, Z. Chi,
and K. K. Parhi, “Area-efficient high-speed decoding schemes for turbo decoders,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp. 902–912, Aug. 2002.

[20] Y. Sun, Y. Zhu, M. Goel, and J. R. Cavallaro, “Configurable and scalable high
throughput turbo decoder architecture for multiple 4G wireless standards,” in Proc. IEEE
Int. Conf. Appl.-Specific Syst., Arch. Processors (ASAP), 2008, pp. 209–214. [21] C. Berrou,
A. Glavieux, and P.

Thitimajshima,“Near Shannon limit error-correcting coding anddecoding: Turbo codes,”

in Proc. Int. Conf.Commun., 1993, pp. 1064–1070. [22] N. Abughalieh, Kris Steenhaut,
Ann Nowe •\Adaptive Parallel Concatenation Turbo Codes for Wireless Sensor
Networks•h 2011 International Conference on Communications and Information
Technology (ICCIT), Aqaba [23] C.-Y. Chen, C.-H.Lin, and A.-Y.Wu, “Highthroughput
dual-mode single/double binary MAP processor design for wireless WAN,” in Proc. IEEE
Workshop Signal Process. Syst. (SiPS), 2008, pp. 83–87.

[24] P. Robertson, E. Villebrun, and P. Hoeher, “A comparison of optimal and

sub-optimal MAP decoding algorithms operating in the log domain,” in IEEE Int. Conf.
Commun. (ICC), 1995, pp. 1009–1013.

INTERNET SOURCES:
-------------------------------------------------------------------------------------------
<1% - http://dias.library.tuc.gr/view/manf/81082
<1% -
http://assets.cambridge.org/97805217/61741/frontmatter/9780521761741_frontmatter.
pdf
1% - https://en.wikipedia.org/wiki/Turbo_code
<1% - http://ijiset.com/vol2/v2s11/IJISET_V2_I11_15.pdf
<1% - http://www.ijesrt.com/issues%20pdf%20file/Archives-2014/January-2014/1.pdf
<1% -
https://www.researchgate.net/publication/3877166_A_high-speed_MAP_architecture_wit
h_optimized_memory_size_and_power_consumption
<1% -
https://www.researchgate.net/publication/3337319_Area-efficient_high-speed_decoding
_schemes_for_turbo_decoders
<1% - http://www.csl.cornell.edu/~studer/papers/12TCASI-bcjr.pdf
<1% - http://vip.ece.cornell.edu/papers/19SSCL_LAMA.pdf
<1% - http://www.philsrockets.org.uk/turbocodes.pdf
<1% -
https://www.ukessays.com/essays/computer-science/differences-between-linear-block-a
nd-convolutional-codes-computer-science-essay.php
<1% - https://math.nd.edu/assets/209991/05695133.pdf
<1% - http://www.ijaerd.co.in/papers/finished_papers/ijaerd%2014-0274.pdf
<1% - https://www.google.com/chrome/
<1% - http://ripublication.com/irph/ijece/ijecev4n3__2.pdf
<1% -
https://www.academia.edu/852580/Reusable_IP_Core_for_Forward_Error_Correcting_Cod
es
<1% -
https://www.cs.cmu.edu/~guyb/realworld/reedsolomon/reed_solomon_codes.html
<1% - http://www.ijptonline.com/wp-content/uploads/2016/10/18498-18504.pdf
<1% - https://core.ac.uk/display/24010420
<1% -
https://www.academia.edu/6097971/Design_and_Implementation_of_Map_Decoding_for
_DB_Convolutional_Turbo_Decoder
<1% -
https://ipfs.io/ipfs/QmXoypizjW3WknFiJnKLwHCnL72vedxjQkDDP1mXWo6uco/wiki/Tur
bo_codes.html
<1% -
http://www.iosrjournals.org/iosr-jece/papers/Vol.%2013%20Issue%203/Version-3/E1303
032228.pdf
<1% - https://patents.google.com/patent/US20100268918A1/en
<1% - https://tmo.jpl.nasa.gov/progress_report/42-124/124G.pdf
<1% - https://en.wikipedia.org/wiki/Additive_white_Gaussian_noise
<1% - https://www.slideshare.net/ijerd_editor/i0145363
<1% -
https://www.researchgate.net/publication/35699005_Turbo_decoding_for_transmit_diver
sity_communication_systems
<1% -
https://perso-etis.ensea.fr/declercq/Elsevier/Chapter1_TurboCodesPrinciples_Douillard/C
hapter1_DouillardJezequel.docx
<1% -
https://www.academia.edu/338643/Concatenated_Convolutional_Codes_With_Interleave
rs
<1% - https://quizlet.com/44612323/politics-222-flash-cards/
<1% - https://epdf.pub/turbo-like-codes.html
1% -
https://www.academia.edu/6151347/Memory_Optmization_In_Map_Decoding_Algorith
m_Using_Trace_Forward_Technique_In_Turbo_Decoder_By_Using_Of_VLSI_Implementati
on
<1% -
https://www.researchgate.net/publication/228091046_Performance_Analysis_of_Optimu
m_Interleaver_based_on_Prime_Numbers_for_Multiuser_Iterative_IDMA_Systems
<1% -
http://www.iosrjournals.org/iosr-jece/papers/Vol9-Issue2/Version-4/B09240813.pdf
<1% - https://www.ijesird.com/july/paper%206.pdf
<1% -
https://www.academia.edu/1292117/Performance_Evaluation_of_Maximal_Ratio_Receive
r_Combining_Diversity_with_Prime_Interleaver_for_Iterative_IDMA_Receiver
<1% - https://ijsr.net/archive/v3i12/U1VCMTQ3ODM=.pdf
<1% - http://acadjournal.com/2005/v15/part6/p7/
<1% -
https://www.academia.edu/5413406/Analysis_of_the_Asymptotic_Performance_of_Turbo
_Codes
<1% -
http://users.ece.utexas.edu/~bevans/papers/2002/turboCodec/turboCodecAsil2002pape
r.pdf
<1% -
https://www.coursehero.com/file/p32vgl0/The-CBC-detection-algorithm-are-briefly-liste
d-which-is-used-in-receiver/
<1% -
https://www.researchgate.net/publication/4080910_Serialparallel_SP_turbo_codes_for_lo
w_error_rates
<1% - https://patents.google.com/patent/US6023783A/en
<1% - http://icact.org/upload/2013/0012/20130012_finalpaper.pdf
<1% -
https://www.researchgate.net/publication/49707793_Intelligent_Postoperative_Morbidit
y_Prediction_of_Heart_Disease_Using_Artificial_Intelligence_Techniques
1% -
https://www.ijser.org/paper/Design_and_Performance_analysis_of_a_3GPP_LTE_LTE-Adva
nce_turbo_decoder_using_software_reference_models.html
<1% -
https://www.ijser.org/researchpaper/Design_and_Performance_analysis_of_a_3GPP_LTE_L
TE-Advance_turbo_decoder_using_software_reference_models.pdf
<1% -
https://www.academia.edu/16490941/Design_and_Performance_analysis_of_a_3GPP_LTE
_LTE-Advance_turbo_decoder_using_software_reference_models
<1% - https://www.ijeat.org/wp-content/uploads/papers/v4i6/F4211084615.pdf
<1% - https://www.scribd.com/presentation/41648413/KARTHIK
1% - https://hdlprogramming.blogspot.com/2010/01/history-of-verilog.html
<1% - https://www.scribd.com/doc/74241477/VLSI-DESIGN
1% - https://hdlprogramming.blogspot.com/
<1% -
https://www.slideshare.net/EceRljit/fpga-implementation-of-multilayer-feed-forward-ne
ural-network-architecture-using-vhdl
<1% - https://hdlprogramming.blogspot.com/2010/01/design-hierarchies.html
<1% - http://classweb.ece.umd.edu/enee359a/verilog_tutorial.pdf
<1% -
https://www.scribd.com/presentation/80886244/Digital-System-Design-by-Using-VERIL
OG
1% -
https://www.slideshare.net/Riteshraushanrockstar/verilog-hdl-2ndeditionsamirpalnitkar
3% - https://hdlprogramming.blogspot.com/2010/01/language-elements.html
<1% - https://wiki.eecs.yorku.ca/course_archive/2013-14/S/2021/_media/app_b_1.pdf
<1% -
http://ssrout.weebly.com/uploads/1/8/4/0/1840236/fpga_programming_using_verilog_h
dl_language_summer_training.pdf
<1% -
http://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/
docs/verilog/VerilogLangRef.pdf
<1% -
https://www.coursehero.com/file/p5msuo5/Escaped-identifiers-begin-with-the-back-sla
sh-Entire-identifier-is-escaped-by/
<1% - http://www.asic-world.com/verilog/syntax1.html
<1% -
https://profs.basu.ac.ir/abbasi/upload_file/unit3%20-%20introduction%20to%20logic%2
0design%20with%20verilog(932.3636.file_ref.3740.4053).pdf
<1% -
https://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Desig
n/2013x/Nexys4/Verilog/docs-pdf/lab2.pdf
<1% - https://www.scribd.com/document/36464932/Verilog-Tutorial
<1% -
https://www.coursehero.com/file/p1ra4e0/Verilog-internally-represents-negative-numb
ers-in-2s-complement-format-An/
2% - https://hdlprogramming.blogspot.com/2010/01/data-typesvaluse-sets.html
<1% - https://www.slideshare.net/itembedded/verilog-14596615
<1% - https://www.slideshare.net/maliktauqir/fpga-05verilogprogramming
<1% - https://www.slideshare.net/mohamedrayan89/verilog-31510176
1% - https://www.academia.edu/27411266/INTRODUCTION_TO_VLSI_DESIGN
<1% -
https://www.caclubindia.com/experts/can-interim-dividend-be-declared-after-financial-
year-711160.asp
<1% -
https://www.coursehero.com/file/p74o6bf/Example2-for-j0-j31-jj1-byte-data1j88-Seque
nce-is-70-158-255248-Can-initialize/
<1% - http://verilog.renerta.com/source/vrg00040.htm
<1% -
http://www.dailyfreecode.com/code/read-numbers-round-them-nearest-2243.aspx
<1% - http://feeds.feedburner.com/Vlsi-Automation
<1% -
http://eacharya.inflibnet.ac.in/data-server/eacharya-documents/53e0c6cbe413016f2344
3704_INFIEP_33/11/LM/33-11-LM-V1-S1__dsd_mod11_model_verilog.pdf
<1% -
https://www.slideshare.net/maliktauqir/fpga-06datatypessystemtaskscompilerdirectives
3% - https://hdlprogramming.blogspot.com/2010/01/modules-and-ports.html
<1% -
https://www.cerc.utexas.edu/~deronliu/vlsi1/lab3/2014_fall_VLSI_I/LAB3_Website/lab3a/
example/Verilog_Example.html
<1% - https://quizlet.com/273965628/java-classes-flash-cards/
<1% -
https://www.researchgate.net/profile/Michael_Hitchens2/publication/2678728_Linguistic
_Support_for_Persistent_Modules_and_Capabilities/links/02bfe513ff70e1c84b000000.pdf
<1% - https://www.hdlworks.com/hdl_corner/verilog_ref/items/PortDeclaration.htm
<1% - https://www.coursehero.com/file/13049052/chapter2-1/
<1% - https://www.coursehero.com/file/13633980/Chapter-4/
<1% - https://arslanhelpyoucom.files.wordpress.com/2016/05/dld_11.pdf
<1% - https://www.scribd.com/presentation/182550476/Verilog-HDL-ppt
<1% - http://www.vlsifacts.com/different-coding-styles-verilog-language/
<1% -
https://www.academia.edu/15382548/Conversion_of_Number_Systems_using_Xilinx
<1% - http://scale.engin.brown.edu/classes/EN2911XF14/topic02.pdf
<1% - https://alex9ufoexploer.blogspot.com/2012/10/gate-level-modeling.html
<1% - https://www.slideshare.net/VikasTiwari20/report-star-topology-using-noc-router
<1% -
https://www.academia.edu/25678128/Topic_2_Chapter_2_Hierarchical_Modeling_Conce
pts
<1% -
https://www.tutorialspoint.com/assembly_programming/assembly_quick_guide.htm
<1% - https://stackoverflow.com/a/2684384
1% - https://www.esat.kuleuven.be/cosic/publications/article-2343.pdf
<1% - http://www.cosic.esat.kuleuven.be/publications/article-2343.pdf
2% - https://hdlprogramming.blogspot.com/2010/01/gate-level-modeling.html
<1% -
http://www.rgcetpdy.ac.in/Notes/CSE/II%20YEAR/DIGITAL%20SYSTEM%20DESIGN/Unit
%205.pdf
<1% - https://www.scribd.com/presentation/338680598/Verilog-Mano
<1% -
https://mafiadoc.com/verilog-hdl-a-guide-to-digital-design-and-synthesis-second-_59f
34cc91723dd8fe02cf9ed.html
2% - https://hdlprogramming.blogspot.com/2010/01/operators-and-operands.html
<1% - https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05.pdf
1% - http://www-scf.usc.edu/~ee577/tutorial/verilog/verilog_lec.pdf
<1% - https://www.mathworks.com/help/matlab/ref/ge.html
<1% - https://en.m.wikipedia.org/wiki/Arithmetic_shift
<1% - http://ee.ump.edu.my/hazlina/teaching_ESD/teaching_ESD_chap6_HDL_b.pdf
<1% - https://www.academia.edu/4722994/Verilog_HDL_Abstraction_Levels
1% - https://hdlprogramming.blogspot.com/2010/01/behavioral-modeling_13.html
<1% -
https://www.researchgate.net/publication/269326686_Using_gudermannian_to_improve
_the_turbo-code_mathematical_principles_in_3g_communication_systems
<1% -
https://www.worldcat.org/title/turbo-code-applications-a-journey-from-a-paper-to-reali
zation/oclc/209848364
<1% - https://dl.acm.org/citation.cfm?id=2485028
<1% - http://charm.cs.illinois.edu/newPapers/15-01/paper.pdf
<1% -
https://www.researchgate.net/profile/OK_Tonguz/publication/271327094_On_the_Poten
tial_of_Bluetooth_Low_Energy_Technology_in_Vehicular_Applications/links/54c54a970cf2
19bbe4f4751b.pdf
<1% - http://www.rroij.com/open-access/pdfdownload.php?aid=42828
<1% - https://www.scirp.org/reference/ReferencesPapers.aspx?ReferenceID=328
<1% - https://www.ijitee.org/download/volume-8-issue-4/
<1% - https://link.springer.com/article/10.1134/S1064226914120201
<1% -
https://www.researchgate.net/publication/4337604_High-throughput_12-mode_CTC_de
coder_for_WiMAX_standard
<1% -
https://www.academia.edu/38390532/A_Flexible_LDPC_Turbo_Decoder_Architecture
<1% - https://link.springer.com/chapter/10.1007/978-3-319-10569-7_2
<1% - http://ijiset.com/vol2/v2s8/IJISET_V2_I8_133.pdf
<1% -
https://www.academia.edu/7754909/Memory_sub-banking_scheme_for_high_throughpu
t_MAP-based_SISO_decoders
<1% -
https://mafiadoc.com/a-survey-of-neuromorphic-computing-and-neural-networks-in-ar
xiv_5afefb6b8ead0eae868b4567.html
<1% - http://www.ece.rice.edu/~ys4937/
<1% -
https://www.academia.edu/17868432/ASIC_implementation_comparison_of_SIC_and_LS
D_receivers_for_MIMO-OFDM
<1% - https://ieeexplore.ieee.org/xpl/dwnldReferences?arnumber=4608972
<1% - https://www.hindawi.com/journals/aai/2009/421425/ref/
<1% - http://access.ee.ntu.edu.tw/prof_4_old.htm
<1% - https://www.hindawi.com/journals/jece/2018/5763461/ref/