Layout tutorial

Only begin the layout after you achieve all the specs for design 3 to prevent having to start over.
1. After you meet or exceed the specs for design 3, copy your design in the Cadence Library
Manager.
Your design 3 should look like the following:

Remove the beta multiplier and the capacitor and resistor within the OTA. The new
schematic should look like the following:
2. In order to use a multiplier you will have to manipulate your transistors slightly by doing
the following:

After Before

In order to make this change you will have to set your multiplier to 1 and change the instance
name as follows:

This will allow you to auto generate two separate transistors with the same dimensions.
Usually you can do m = 2 to achieve this but when you auto generate in this process
technology it gives you one component with two transistors in it as if you set the fingers to 2.
In order to avoid LVS issues, you will have to name all your nets in your schematic with an
arbitrary name. (i.e. f, k, j). It will look like the following.
NOTE: In the picture I used a different multiplier for my input pair (m=4 for better
matching), in order to achieve this to autogenerate the transistors, you will have to make your
schematic look as follows (Outlined in yellow *only shows right branch*):
Once you have adjusted your schematic and labeled all the nets and change all your
transistors go to Launch> Layout GXL
After you click on Layout GXL the following window will appear, press create new for both
Layout and Configuration as shown below:

After you press OK, this window will appear, just press OK again:
The ‘Create Physical Configuration View’ window will appear and press OK again:

The following window will pop up, click on Cells as highlighted below:
After you select on cells, change the ‘Physical Library’ from NCSU_Analog_Parts to
NCSU_TechLib_tsmc03 as shown below. Under ‘Physical Library’ change nmos4 to nmos.
Repeat this same step for pmos as well. (*Not shown in picture*):
If you setup the configuration properly it will look like the following:

Click Save in the top left of the window, highlighted above.

After you saved your configuration, go back to your layout window then click on
Connectivity> Generate> All From Source… The following window will appear:

Deselect the PR Boundary which should look like the following:

Then press OK.

If done correctly your transistors should autogenerate and look like the following:
All the transistors will be in outline view, in order to see the actual transistor layout press
‘Shift+f’ and to go back to outline view if needed press ‘Ctrl+f’, if done correctly the
transistors will look like the following:

Now that all the transistors are autogenerated you will have to do all the placing and routing
yourself.
To run DRC, while in your layout window go to Verify>DRC… and the following window
will appear:

Press OK and DRC will run. To check your DRC errors open up the virtuoso window and the
DRC report will look like the following:
Before you run LVS, (instructions to run LVS are below this) make sure the label you added to
your nets on the schematic matches the label you add to the metal that is making the connection
for this net. It will look like the following:
To run LVS, while in your layout window go to Verify>Extract… and the following window
will appear:

Press OK.
After extracted properly, go to Verify>LVS… and this window will pop up:
Make sure that the schematic in your LVS window matches the schematic you used to auto
generate your layout. Then under the extracted side, click Browse then find the extracted file
that you created from your layout above. Once it is setup properly it will look like the
following:

After setup properly, click Run. Make sure your layout and schematics are checked and
saved.
The following window will appear if your schematic does not match your layout:
To check your LVS report, click on Output in the LVS window right next to Run. Your LVS
report will appear and look like the following:

When your layout matches your schematic, the window above that said your net-list do not
match will say that the net-list match.
Please see a lab TA if you have any other layout related questions.