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PCB 8L STACK UP QLC 14" (Huron River) BLOCK DIAGRAM 01


LAYER 1 : TOP
VRAM DDR3*4
LAYER 2 : SGND DDR3 800,1066,1333 MT/s (512MB) (1GB)
A LAYER 3 : IN1(High)
DDR3-SODIMM1 A
PAGE 18
LAYER 4 : IN2(Low) PAGE 12 Intel Sandy
LAYER 5 : SVCC
LAYER 6 : IN3(High) DDR3 800,1066,1333 MT/s
DDR3-SODIMM2 CPU 35Watt
LAYER 7 : SGND PCI-Express
PAGE 13 Gen2 X 16 nVidia
LAYER 8 : BOT
Dual Core N12P-GV
( rPGA 989 )
PAGE 2-5 PAGE 14-17

FDI*8 BCLK133M 32.768KHz


DMI*4 DMI100M 27MHz
DP120M LCD CONN for
SATA0 300MB/s 100M PCIE dual channel
SATA - 1st HDD
CRT (14")
PAGE 25 PCH 3.5Watt PAGE 20
B
Dual Channel LVDS B

SATA0 300MB/s Platform iGPU HDMI


SATA - CD-ROM CRT PAGE 19
PAGE 25 Controller
Hub HDMI CON
LVDS (1920*1200)
PAGE 6-11
PAGE 19
USB2.0 48M
8,9 4 1 3 11
USB2.0 Port Webcam w/ Mic
PAGE 26 PAGE 20 Card Reader USB2.0 Port
PCI-E 100M PAGE 26
Realtek
DDR III SMDDR_VTERM and RTS5138
GPU+1.5V/+1.0V(RT8207G) Azalia
X1 X1
PAGE 36 SPI ROM PAGE 21
System BIOS half size
PAGE 7 LAN
BATTERY SELECTOR Athous PCIE-LAN mini-card
C LPC 5-in-1 C

PAGE 38 Audio Wireless LAN flash media


Realtek AR8151
GigaLAN slot(SD/MS/MMC/
ALC269Q-VB5-GR PAGE 25 XD/MSP)
SYSTEM CHARGER(P2806) PAGE 24 PAGE 21
PAGE 22
PAGE 37
25MHz
SYSTEM POWER RT8206B
PAGE 31 Keyboard
Touch Pad
PAGE 26 ITE RJ45
PAGE 24
+1.05V_VTT and GPU
+1.8V/+3V(VT358) GMT G9931P1U IT8518/BX
SYSTEM FAN
PAGE 34
PAGE 26 PAGE 27
VCCP +1.05V/+1.8V(RT8204)

PAGE 32
D D

VGACORE/VDDCI(RT8208/RT9018A) Audio Jack Jack to


PAGE 35 (Headphone/MIC) Speaker
PAGE 23 PAGE 22 PROJECT : QLC
Quanta Computer Inc.
CPU CORE (ADP3212)
PAGE 33 Size Document Number Rev
Custom BLOCK DIAGRAM ?
NB5
Date: Friday, November 26, 2010 Sheet 1 of 36
1 2 3 4 5 6 7 8

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Sandy Bridge Processor (DMI,PEG,FDI)


U17A
PEG_ICOMPI J22
J21
PEG_COMP PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
02
PEG_ICOMPO PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
[6] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[6] DMI_TXN1 B25 DMI_RX#[1] PEG_RX#[0..15] [14] BCLK A28 CLK_CPU_BCLKP [8]
A25 C26 A27

MISC

CLOCKS
[6] DMI_TXN2 DMI_RX#[2] [7] H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_BCLKN [8]
B24 K33 PEG_RX#0
[6] DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1
PEG_RX#[1] PEG_RX#2 SKTOCC#
[6] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34 SNB_IVB# N.A at SNB EDS #27637 0.7v1 TP3 AN34 SKTOCC#
D B26 J35 PEG_RX#3 A16 CLK_DPLL_SSCLKP_R D
[6] DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_SSCLK
A24 J32 PEG_RX#4 A15 CLK_DPLL_SSCLKN_R
[6] DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RX#5 DPLL_REF_SSCLK#

DMI
[6] DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_RX#6
PEG_RX#[6] PEG_RX#7 TP_CATERR#
[6] DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33 TP5 AL33 CATERR#
E22 G30 PEG_RX#8
[6] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RX#9 Placement close to EC.
[6] DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_RX#10

THERMAL
[6] DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_RX#11 [27] EC_PECI R465 43_4 H_PECI AN33 R8 CPU_DRAMRST#
PEG_RX#[11] PEG_RX#12 PECI SM_DRAMRST#
[6] DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_RX#13

DDR3
MISC
[6] DMI_RXP1 DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_RX#14
[6] DMI_RXP2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_RX#15 PEG_RX[0..15] [14] [27,35] H_PROCHOT# R108 56.2/F_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R94 140/F_4
[6] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0]

PCI EXPRESS* - GRAPHICS


A5 SM_RCOMP_1 R371 26.1/F_4
PEG_RX0 C543 *0.1U/10V_4 SM_RCOMP[1] SM_RCOMP_2 R369 200/F_4
PEG_RX[0] J33 SM_RCOMP[2] A4
L35 PEG_RX1 PV: Reserve for future
PEG_RX[1] PEG_RX2 R110 *0_4/S PM_THRMTRIP#_R AN32
PEG_RX[2] K34 [9,27] PM_THRMTRIP# THERMTRIP# SM_RCOMP[0] W:20mils/S:20mils/L: 500mils,
A21 H35 PEG_RX3
[6] FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RX4
SM_RCOMP[1] W:20mils/S:20mils/L: 500mils,
[6] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PEG_RX5 PV: Change to short pad SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,
[6] FDI_TXN2 FDI0_TX#[2] PEG_RX[5] PEG_RX6
[6] FDI_TXN3 F18 FDI0_TX#[3] PEG_RX[6] G31
B21 F33 PEG_RX7 AP29 XDP_PRDY#
[6] FDI_TXN4 TP40
Intel(R) FDI

FDI1_TX#[0] PEG_RX[7] PEG_RX8 PRDY# XDP_PREQ#


[6] FDI_TXN5 C20 FDI1_TX#[1] PEG_RX[8] F30 PREQ# AP27 TP49 CPU XDP
D18 E35 PEG_RX9 PV: Change to short pad
[6] FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_RX10 AR26 XDP_TCLK
[6] FDI_TXN7 FDI1_TX#[3] PEG_RX[10] TCK TP45
F32 PEG_RX11 AR27 XDP_TMS TP38

PWR MANAGEMENT
PEG_RX[11] TMS

JTAG & BPM


D34 PEG_RX12 R107 *0_4/S PM_SYNC_R AM34 AP30 XDP_TRST#
PEG_RX[12] [6] PM_SYNC PM_SYNC TRST# TP48
A22 E31 PEG_RX13
[6] FDI_TXP0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_RX14 AR28 XDP_TDI_R TP46
[6] FDI_TXP1 FDI0_TX[1] PEG_RX[14] TDI
E20 B32 PEG_RX15 AP26 XDP_TDO
C [6] FDI_TXP2 FDI0_TX[2] PEG_RX[15] TDO TP50 C
G18 [9] H_PWRGOOD R128 *0_4/S H_PWRGOOD_R AP33
[6] FDI_TXP3 FDI0_TX[3] UNCOREPW RGOOD
B20 M29 C_PEG_TX#0 R137 *1K_4
[6] FDI_TXP4 FDI1_TX[0] PEG_TX#[0] +3V
C19 M32 C_PEG_TX#1 R467 10K_4
[6] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 C_PEG_TX#2 AL35
[6] FDI_TXP6 FDI1_TX[2] PEG_TX#[2] DBR# XDP_DBRST# [6]
F17 L32 C_PEG_TX#3 PM_DRAM_PWRGD_R V8
[6] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] SM_DRAMPW ROK
L29 C_PEG_TX#4 +1.05V_VTT R136 *75_4
PEG_TX#[4] C_PEG_TX#5 XDP_BPM0
[6] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 BPM#[0] AT28 TP37
J17 K28 C_PEG_TX#6 AR29 XDP_BPM1
[6] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] BPM#[1] TP47
J30 C_PEG_TX#7 U3 AR30 XDP_BPM2
H20
PEG_TX#[7]
J28 C_PEG_TX#8 CPU RESET# 3 4 CPU_PLTRST# R468 *43_4 CPU_PLTRST#_R AR33
BPM#[2]
AT30 XDP_BPM3
TP39
TP43
[6] FDI_INT FDI_INT PEG_TX#[8] GND OUT RESET# BPM#[3]
H29 C_PEG_TX#9 AP32 XDP_BPM4
PEG_TX#[9] +3VS5 BPM#[4] TP36
J19 G27 C_PEG_TX#10 2 AR31 XDP_BPM5
[6] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] [8,14,24,25,27] PLTRST# IN C232 PV: Unstuff BPM#[5] TP42
H17 E29 C_PEG_TX#11 AT31 XDP_BPM6 TP44
[6] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6]
F27 C_PEG_TX#12 1 5 R466 AR32 XDP_BPM7
PEG_TX#[12] NC VCC BPM#[7] TP41
D28 C_PEG_TX#13
PEG_TX#[13] C_PEG_TX#14 *74LVC1G07GW 750/F_4
PEG_TX#[14] F26
C_PEG_TX#15 *0.1U/10V_4 Sandy Bridge_rPGA_Rev0p61
PEG_TX#[15] E25
eDP_COMP A18 rpga989-47989-socket
eDP_COMPIO C_PEG_TX0 R469 1.5K/F_4 DGG^9000014
A17 eDP_ICOMPO PEG_TX[0] M28
INT_eDP_HPD_Q B16 M33 C_PEG_TX1 IC SOCKET RPGA 989P(P1.0,M/H3.0)
eDP_HPD PEG_TX[1]
PEG_TX[2] M30
L31
C_PEG_TX2
C_PEG_TX3
SM_DRAMPWROK Processor Input. DDR3 DRAM RESET
PEG_TX[3] C_PEG_TX4 +3VS5 +3VS5
C15 eDP_AUX PEG_TX[4] L28
D15 K30 C_PEG_TX5 PV: Unstuff R25 1K_4 R24 *0_4
eDP_AUX# PEG_TX[5] +1.5V_CPU +1.5VSUS
K27 C_PEG_TX6 DV2: un-stuff
PEG_TX[6] C_PEG_TX7
eDP

PEG_TX[7] J29
C17 J27 C_PEG_TX8 PV: Unstuff R23 1K_4 3 1 CPU_DRAMRST#
eDP_TX[0] PEG_TX[8] [12,13] DDR3_DRAMRST#
F16 H28 C_PEG_TX9 R142 U5 C254
eDP_TX[1] PEG_TX[9] C_PEG_TX10 *10K_4 *0.1U/10V_4
C16 eDP_TX[2] PEG_TX[10] G28 1 NC VCC 5
G15 E28 C_PEG_TX11 R141 CPU_DRAMRST#_R Q6

2
B eDP_TX[3] PEG_TX[11] C_PEG_TX12 PM_DRAM_PWRGD_PU 200/F_4 2N7002 B
PEG_TX[12] F28 2 IN
C18 D27 C_PEG_TX13 *0_4/S R21
eDP_TX#[0] PEG_TX[13] [8] DRAMRST_CNTRL_PCH
E16 E26 C_PEG_TX14 3 4 PM_DRAM_PWRGD_C R104 130/F_4 PM_DRAM_PWRGD_R R27
eDP_TX#[1] PEG_TX[14] C_PEG_TX15 GND OUT R139 C23 4.99K/F_4
D16 eDP_TX#[2] PEG_TX[15] D25
F15 eDP_TX#[3]
R145 *74LVC1G07GW PV: Change to short pad .047U/25V_4
*0_4

3
39_4
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
DV2: Change net name PM_DRAM_PWRGD_C PM_DRAM_PWRGD [6]
DGG^9000014 2 MAIN_ONG [4,36]
IC SOCKET RPGA 989P(P1.0,M/H3.0) R101 0_4 PM_DRAM_PWRGD_C
[6,7,8,9,10,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. R96 Q18 [6,7,8,9,10,14,24,27,29,31,33,34,35,36] +3VS5
*3K/F_4 2N7002
eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. [4,10,25] +1.5V_CPU

1
DV2: Change to 0 ohm [4,10,27,32,34,35] +1.05V_VTT
[4,10,12,13,30,31] +1.5VSUS

FDI disable PEG x16 disable (UMA only remove) Embedded Display PLL Clock DP & PEG Compensation Processor pull-up (CPU)
(DIS only stuff) [14] PEG_TX[0..15] [14] PEG_TX#[0..15]
Ra +1.05V_VTT R374 10K_4 INT_eDP_HPD_Q +1.05V_VTT
RP6
C_PEG_TX0 C578 0.1U/10V_4 PEG_TX0 C_PEG_TX#0 C582 0.1U/10V_4 PEG_TX#0 CLK_DPLL_SSCLKP_R 3 4 H_PROCHOT# R111 62_4
CLK_DPLL_SSCLKP [8]
FDI_INT C_PEG_TX1 C571 0.1U/10V_4 PEG_TX1 C_PEG_TX#1 C575 0.1U/10V_4 PEG_TX#1 CLK_DPLL_SSCLKN_R 1 2 CLK_DPLL_SSCLKN [8] +1.05V_VTT R375 24.9/F_4 eDP_COMP XDP_TDO R479 51_4
C_PEG_TX2 C569 0.1U/10V_4 PEG_TX2 C_PEG_TX#2 C573 0.1U/10V_4 PEG_TX#2 XDP_TMS R477 51_4
R475 *0_4 FDI_FSYNC0 C_PEG_TX3 C566 0.1U/10V_4 PEG_TX3 C_PEG_TX#3 C568 0.1U/10V_4 PEG_TX#3 0_4P2R_4 XDP_TDI_R R472 51_4
R480 *0_4 FDI_FSYNC1 C_PEG_TX4 C565 0.1U/10V_4 PEG_TX4 C_PEG_TX#4 C567 0.1U/10V_4 PEG_TX#4 eDP_COMPIO and ICOMPO signals should be shorted XDP_PREQ# R471 *51_4
A R478 *0_4 FDI_LSYNC0 C_PEG_TX5 C562 0.1U/10V_4 PEG_TX5 C_PEG_TX#5 C564 0.1U/10V_4 PEG_TX#5 XDP_TCLK R476 51_4 A
Rb near balls and routed with typical impedance <25 mohms
FDI_LSYNC1 C_PEG_TX6 C561 0.1U/10V_4 PEG_TX6 C_PEG_TX#6 C563 0.1U/10V_4 PEG_TX#6 CLK_DPLL_SSCLKP_R R373 *0_4 XDP_TRST# R473 51_4
C_PEG_TX7 C558 0.1U/10V_4 PEG_TX7 C_PEG_TX#7 C560 0.1U/10V_4 PEG_TX#7 Rc
R483 *1K_4 C_PEG_TX8 C556 0.1U/10V_4 PEG_TX8 C_PEG_TX#8 C559 0.1U/10V_4 PEG_TX#8 CLK_DPLL_SSCLKN_R R372 *0_4 R43 24.9/F_4 PEG_COMP
+1.05V_VTT
R474 *1K_4 C_PEG_TX9 C551 0.1U/10V_4 PEG_TX9 C_PEG_TX#9 C555 0.1U/10V_4 PEG_TX#9
C_PEG_TX10 C548 0.1U/10V_4 PEG_TX10 C_PEG_TX#10 C552 0.1U/10V_4 PEG_TX#10

FDI_FSYNC can gang all these 4


C_PEG_TX11
C_PEG_TX12
C545
C546
0.1U/10V_4
0.1U/10V_4
PEG_TX11
PEG_TX12
C_PEG_TX#11
C_PEG_TX#12
C547
C542
0.1U/10V_4
0.1U/10V_4
PEG_TX#11
PEG_TX#12
Ra Rb Rc PEG_ICOMPI and RCOMPO signals PROJECT : QLC
should be routed within 500 mils typical
signals together and tie them C_PEG_TX13
C_PEG_TX14
C538
C536
0.1U/10V_4
0.1U/10V_4
PEG_TX13
PEG_TX14
C_PEG_TX#13
C_PEG_TX#14
C540
C539
0.1U/10V_4
0.1U/10V_4
PEG_TX#13
PEG_TX#14
DIS NC Stuff Stuff
impedance = 43 mohms PEG_ICOMPO
Quanta Computer Inc.
with only one 1K resistor to GND C_PEG_TX15 C532 0.1U/10V_4 PEG_TX15 C_PEG_TX#15 C535 0.1U/10V_4 PEG_TX#15 SG/UMA Stuff NC NC signals should be routed within 500 mils
(DG V0.5 Ch2.2.9). Size Document Number Rev
0.22uF AC coupling Caps for PCIE GEN1/2/3 0.22uF AC coupling Caps for PCIE GEN1/2/3 typical impedance = 14.5 mohms 1A
NB5 SNB 1/4 (PCIE&DMI&FDI)
Date: Friday, November 26, 2010 Sheet 2 of 36
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Sandy Bridge Processor (DDR3) 03


U17C U17D

D D

SA_CLK[0] AB6 M_A_CLKP0 [12] [13] M_B_DQ[63:0] SB_CLK[0] AE2 M_B_CLKP0 [13]
[12] M_A_DQ[63:0] SA_CLK#[0] AA6 M_A_CLKN0 [12] SB_CLK#[0] AD2 M_B_CLKN0 [13]
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
SA_DQ[0] SA_CKE[0] M_A_CKE0 [12] SB_DQ[0] SB_CKE[0] M_B_CKE0 [13]
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
M_A_DQ3 D2 M_B_DQ3 C8
M_A_DQ4 SA_DQ[3] M_B_DQ4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_A_CLKP1 [12] A9 SB_DQ[4] SB_CLK[1] AE1 M_B_CLKP1 [13]
M_A_DQ5 C6 AB5 M_A_CLKN1 [12] M_B_DQ5 A8 AD1 M_B_CLKN1 [13]
M_A_DQ6 SA_DQ[5] SA_CLK#[1] M_B_DQ6 SB_DQ[5] SB_CLK#[1]
C2 SA_DQ[6] SA_CKE[1] V10 M_A_CKE1 [12] D9 SB_DQ[6] SB_CKE[1] R10 M_B_CKE1 [13]
M_A_DQ7 C3 M_B_DQ7 D8
M_A_DQ8 SA_DQ[7] M_B_DQ8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
M_A_DQ9 F8 M_B_DQ9 F4
M_A_DQ10 SA_DQ[9] M_B_DQ10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
M_A_DQ11 G9 AA4 M_B_DQ11 G1 AA2
M_A_DQ12 SA_DQ[11] SA_CLK#[2] M_B_DQ12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
M_A_DQ13 F7 M_B_DQ13 F5
M_A_DQ14 SA_DQ[13] M_B_DQ14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
M_A_DQ15 G7 M_B_DQ15 G2
M_A_DQ16 SA_DQ[15] M_B_DQ16 SB_DQ[15]
K4 SA_DQ[16] SA_CLK[3] AB3 J7 SB_DQ[16] SB_CLK[3] AA1
M_A_DQ17 K5 AA3 M_B_DQ17 J8 AB1
M_A_DQ18 SA_DQ[17] SA_CLK#[3] M_B_DQ18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W 10 K10 SB_DQ[18] SB_CKE[3] T10
M_A_DQ19 J1 M_B_DQ19 K9
M_A_DQ20 SA_DQ[19] M_B_DQ20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
M_A_DQ21 J4 M_B_DQ21 J10
M_A_DQ22 SA_DQ[21] M_B_DQ22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 M_A_CS#0 [12] K8 SB_DQ[22] SB_CS#[0] AD3 M_B_CS#0 [13]
M_A_DQ23 K2 AL3 M_B_DQ23 K7 AE3
SA_DQ[23] SA_CS#[1] M_A_CS#1 [12] SB_DQ[23] SB_CS#[1] M_B_CS#1 [13]
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ[24] SA_CS#[2] M_B_DQ25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
M_A_DQ26 N8 M_B_DQ26 N2
C M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26] C
N7 SA_DQ[27] N1 SB_DQ[27]
M_A_DQ28 M10 M_B_DQ28 M4
M_A_DQ29 SA_DQ[28] M_B_DQ29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_A_ODT0 [12] N5 SB_DQ[29] SB_ODT[0] AE4 M_B_ODT0 [13]

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A
SA_DQ[30] SA_ODT[1] M_A_ODT1 [12] SB_DQ[30] SB_ODT[1] M_B_ODT1 [13]
M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
M_A_DQ32 SA_DQ[31] SA_ODT[2] M_B_DQ32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
M_A_DQ34 SA_DQ[33] M_B_DQ34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
M_A_DQ35 AK5 M_B_DQ35 AP3
M_A_DQ36 SA_DQ[35] M_B_DQ36 SB_DQ[35]
AH5 SA_DQ[36] M_A_DQSN[7:0] [12] AN3 SB_DQ[36] M_B_DQSN[7:0] [13]
M_A_DQ37 AH6 C4 M_A_DQSN0 M_B_DQ37 AN2 D7 M_B_DQSN0
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQSN1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQSN1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQSN2 M_B_DQ39 AP2 K6 M_B_DQSN2
M_A_DQ40 SA_DQ[39] SA_DQS#[2] M_A_DQSN3 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQSN3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ41 AK8 AL6 M_A_DQSN4 M_B_DQ41 AN9 AN5 M_B_DQSN4
M_A_DQ42 SA_DQ[41] SA_DQS#[4] M_A_DQSN5 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQSN5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
M_A_DQ43 AK9 AR12 M_A_DQSN6 M_B_DQ43 AT6 AK12 M_B_DQSN6
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQSN7 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQSN7
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ[45] M_B_DQ46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
M_A_DQ47 AL8 M_B_DQ47 AR5
M_A_DQ48 SA_DQ[47] M_B_DQ48 SB_DQ[47]
AP11 SA_DQ[48] M_A_DQSP[7:0] [12] AR9 SB_DQ[48] M_B_DQSP[7:0] [13]
M_A_DQ49 AN11 D4 M_A_DQSP0 M_B_DQ49 AJ11 C7 M_B_DQSP0
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQSP1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQSP1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
M_A_DQ51 AM12 K3 M_A_DQSP2 M_B_DQ51 AT9 J6 M_B_DQSP2
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQSP3 M_B_DQ52 SB_DQ[51] SB_DQS[2] M_B_DQSP3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
M_A_DQ53 AL11 AL5 M_A_DQSP4 M_B_DQ53 AR8 AN6 M_B_DQSP4
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQSP5 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQSP5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ55 AN12 AR11 M_A_DQSP6 M_B_DQ55 AH12 AK11 M_B_DQSP6
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQSP7 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQSP7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
B M_A_DQ57 AH14 M_B_DQ57 AN14 B
M_A_DQ58 SA_DQ[57] M_B_DQ58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ[59] M_B_DQ60 SB_DQ[59]
AL14 SA_DQ[60] M_A_A[15:0] [12] AT12 SB_DQ[60] M_B_A[15:0] [13]
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ[63] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[2] M_B_A3
SA_MA[3] W7 SB_MA[3] T6
V3 M_A_A4 T2 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
SA_MA[5] V2 SB_MA[5] T4
W3 M_A_A6 T3 M_B_A6
SA_MA[6] M_A_A7 SB_MA[6] M_B_A7
[12] M_A_BS#0 AE10 SA_BS[0] SA_MA[7] W6 [13] M_B_BS#0 AA9 SB_BS[0] SB_MA[7] R2
AF10 V1 M_A_A8 AA7 T5 M_B_A8
[12] M_A_BS#1 SA_BS[1] SA_MA[8] [13] M_B_BS#1 SB_BS[1] SB_MA[8]
V6 W5 M_A_A9 R6 R3 M_B_A9
[12] M_A_BS#2 SA_BS[2] SA_MA[9] [13] M_B_BS#2 SB_BS[2] SB_MA[9]
AD8 M_A_A10 AB7 M_B_A10
SA_MA[10] M_A_A11 SB_MA[10] M_B_A11
SA_MA[11] V4 SB_MA[11] R1
W4 M_A_A12 T1 M_B_A12
SA_MA[12] M_A_A13 SB_MA[12] M_B_A13
[12] M_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 [13] M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 M_A_A14 AB8 R5 M_B_A14
[12] M_A_RAS# SA_RAS# SA_MA[14] [13] M_B_RAS# SB_RAS# SB_MA[14]
[12] M_A_WE# AF9 V7 M_A_A15 [13] M_B_WE# AB9 R4 M_B_A15
SA_W E# SA_MA[15] SB_W E# SB_MA[15]

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61


rpga989-47989-socket rpga989-47989-socket
DGG^9000014 DGG^9000014
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)

A A

PROJECT : QLC
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 SNB 2/4 (DDR3 I/F)
Date: Friday, November 26, 2010 Sheet 3 of 36
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SNB: 55A
Sandy Bridge Processor (POWER)
+VCC_CORE
U17F
Sandy Bridge Processor (GRAPHIC POWER)
22uF_8 x2 Socket TOP cavity U17G
R100 100_4
04
+1.05V_VTT 22uF_8 x2 Socket BOT cavity +VCC_GFX
SNB: 8.5A 22uF_8 x4 Socket TOP edge
AG35 AT24 AK35

SENSE
LINES
VCC1 VAXG1 VAXG_SENSE VCC_AXG_SENSE [35]
AG34 VCC2 VCCIO1 AH13 22uF_8 x4 Socket BOT edge AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE [35]
AG33 VCC3 VCCIO2 AH10 470uF_7343 x2 AT21 VAXG3
AG32 AG10 AT20 R103 100_4
C156 C28 C517 VCC4 VCCIO3 C41 C38 C487 VAXG4
AG31 VCC5 VCCIO4 AC10 AT18 VAXG5
D 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AG30 Y10 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AT17 D
VCC6 VCCIO5 +VCC_GFX VAXG6
AG29 VCC7 VCCIO6 U10 SNB: 21.5A AR24 VAXG7
AG28 VCC8 VCCIO7 P10 AR23 VAXG8
AG27 VCC9 VCCIO8 L10 AR21 VAXG9
AG26 VCC10 VCCIO9 J14 AR20 VAXG10 CAD Note: +VDDR_REF_CPU should
AF35 J13 AR18 +VDDR_REF_CPU

VREF
VCC11 VCCIO10 C139 C89 C30 C523 C138 VAXG11 have 10 mil trace width
AF34 VCC12 VCCIO11 J12 AR17 VAXG12
C512 C504 C500 AF33 J11 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AP24 AL1 R119 *0_8 DDR_VTTREF [12,13,30]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC13 VCCIO12 VAXG13 SM_VREF
AF32 VCC14 VCCIO13 H14 AP23 VAXG14
AF31 VCC15 VCCIO14 H12 AP21 VAXG15
AF30 VCC16 VCCIO15 H11 AP20 VAXG16 1 3
AF29 VCC17 VCCIO16 G14 AP18 VAXG17
AF28 G13 AP17 R114 Q17
VCC18 VCCIO17 C45 C117 C518 C152 C127 VAXG18 100K_4 2N7002
AF27 G12 AN24

2
VCC19 VCCIO18 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG19
AF26 VCC20 VCCIO19 F14 AN23 VAXG20

PEG AND DDR


C161 C528 C136 AD35 F13 AN21 MAIND MAIND [36]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC21 VCCIO20 VAXG21
AD34 VCC22 VCCIO21 F12 AN20 VAXG22
AD33 F11 AN18

DDR3 -1.5V RAILS


VCC23 VCCIO22 VAXG23
AD32 VCC24 VCCIO23 E14 AN17 VAXG24
AD31 E12 AM24 AF7

GRAPHICS
VCC25 VCCIO24 C527 C98 C50 C149 C522 VAXG25 VDDQ1 +1.5V_CPU
AD30 VCC26 AM23 VAXG26 VDDQ2 AF4 SNB: 5A
AD29 E11 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AM21 AF1
VCC27 VCCIO25 VAXG27 VDDQ3
AD28 VCC28 VCCIO26 D14 AM20 VAXG28 VDDQ4 AC7
C155 C96 C33 AD27 D13 AM18 AC4
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC29 VCCIO27 VAXG29 VDDQ5
AD26 VCC30 VCCIO28 D12 AM17 VAXG30 VDDQ6 AC1
AC35 D11 AL24 Y7 C88 C121 C150 C123
VCC31 VCCIO29 VAXG31 VDDQ7 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
AC34 VCC32 VCCIO30 C14 AL23 VAXG32 VDDQ8 Y4
AC33 C13 C491 C51 C151 C157 C570 AL21 Y1
VCC33 VCCIO31 VAXG33 VDDQ9
AC32 VCC34 VCCIO32 C12 22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AL20 VAXG34 VDDQ10 U7 4/27: layout modify
AC31 VCC35 VCCIO33 C11 AL18 VAXG35 VDDQ11 U4
C AC30 B14 AL17 U1 C
VCC36 VCCIO34 VAXG36 VDDQ12

1
C93 C39 C92 AC29 B12 AK24 P7
22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 VCC37 VCCIO35 VAXG37 VDDQ13 + C574
AC28 VCC38 VCCIO36 A14 AK23 VAXG38 VDDQ14 P4
AC27 A13 AK21 P1 C137 C158
VCC39 VCCIO37 C80 C505 C131 C509 C226 VAXG39 VDDQ15 10U/6.3V_8 10U/6.3V_8 *390U/2.5V_6X5.8ESR10
AC26 A12 AK20

2
VCC40 VCCIO38 *22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG40
AA35 VCC41 VCCIO39 A11 AK18 VAXG41
AA34 VCC42 AK17 VAXG42
AA33 VCC43 VCCIO40 J23 AJ24 VAXG43 330uF x1, 10uF_8 x6 Socket BOT edge.
AA32 VCC44 AJ23 VAXG44
C488 C115 C147 AA31 AJ21 3/26 DB change 10U FP to 0805.
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC45 VAXG45
AA30 VCC46 AJ20 VAXG46
AA29 C513 C499 C64 C142 C508 AJ18
VCC47 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG47
AA28 VCC48 AJ17 VAXG48 +VCCSA
AA27 VCC49 AH24 VAXG49 SNB: 6A

SA RAIL
AA26 VCC50 AH23 VAXG50
Y35 VCC51 AH21 VAXG51 VCCSA1 M27
Y34 VCC52 22uF_8 x7 Socket TOP cavity AH20 VAXG52 VCCSA2 M26
CORE SUPPLY

C125 C124 C495 Y33 5/4: add C8260/ C8322 AH18 L26
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC53 22uF_8 x5 Socket BOT cavity VAXG53 VCCSA3
Y32 VCC54 Ra R127 *0_4 AH17 VAXG54 VCCSA4 J26 C78 C483 C40 C489
Y31 22uF_8 x2 Socket TOP cavity (no stuff) J25 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8
VCC55 VCCSA5
Y30 VCC56
22uF_8 x5 Socket BOT cavity (no stuff) VCCSA6 J24
Y29 VCC57 330uF_7343 x2 DIS SG/UMA VCCSA7 H26
Y28 VCC58 VCCSA8 H25 330uF x1, 10uF_8 x1 Socket BOT edge,
Y27 VCC59 Ra Stuff NC 10uF_8 x2 Socket BOT cavity.
Y26

1.8V RAIL
C42 C35 C79 VCC60 +1.05V_VTT
V35 VCC61 3/26 DB change 10U FP to 0805.
*22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 +1.8V
V34 VCC62 +1.05V_VTT_40
SNB: 1.5A
V33 R42 *0_4/S
VCC63
V32 VCC64 B6 VCCPLL1 VCCSA_SENSE H23 VCCUSA_SENSE_R R370 *0_4/S VCCUSA_SENSE [34]
V31 A6

MISC
B VCC65 VCCPLL2 B
V30 VCC66 A2 VCCPLL3 PV: Change to short pad
V29 AJ29 H_CPU_SVIDALRT# C52 C53 C54 + C59
SVID

VCC67 VIDALERT# H_CPU_SVIDCLK


V28 VCC68 VIDSCLK AJ30 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4
FC_C22 C22 H_FC_C22 R377 10K_4
C61 C496 C135 V27 AJ28 H_CPU_SVIDDAT 330U/2V_7343 C24 VCCSA_SEL [34]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC69 VIDSOUT VCCSA_VID1
V26 VCC70
U35 330uF x1, 10uF_8 x1, 1uF_4 x2 R378 *10K_4
VCC71
U34 VCC72 Socket BOT edge.
U33 VCC73
Sandy Bridge_rPGA_Rev0p61 5/11: Add for intel CRB
U32 3/26 DB change 10U FP to 0805. rpga989-47989-socket
VCC74
U31 VCC75
DGG^9000014 DV2: Unstuff
U30 IC SOCKET RPGA 989P(P1.0,M/H3.0)
C492 C87 C148 VCC76
U29 VCC77
22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 U28 VCC78
U27 VCC79
U26 VCC80 Layout note: need routing Place PU resistor SVID CLK
R35 +1.5VSUS JP1 +1.5V_CPU +1.5VSUS
VCC81 together and ALERT need close to VR *SOLDERJUMPER-2
R34 VCC82
22uF_8 x8 Socket TOP cavity R33 between CLK and DATA. R124 *54.9/F_4 +1.05V_VTT 2 1 C572 0.1U/10V_4
VCC83 R93 100_4
22uF_8 x10 Socket BOT cavity R32 VCC84 +VCC_CORE Q43
SENSE LINES

R31 C577 0.1U/10V_4


22uF_8 x8 Socket TOP edge VCC85 H_CPU_SVIDCLK AON7410
R30 VCC86 VCC_SENSE AJ35 VCC_SENSE [35] VR_SVID_CLK [35]
470uF_7343 x4 R29 VCC87 VSS_SENSE AJ34 VSS_SENSE [35] 1 R129 C581 0.1U/10V_4
R28 5 2 220_8
VCC88 R95 100_4 C584 0.1U/10V_4
3/26 DB change 10U FP to 0805. R27 VCC89 3
R26 +1.05V_VTT +1.05V_VTT
VCC90 SVID DATA

3
P35 VCC91 3/26 DB add for Intel.
P34 Placement close to CPU.

4
VCC92 MAIND
P33 VCC93
P32 VCC94 VCCIO_SENSE B10 VCCP_SENSE [32] Place PU resistor Place PU resistor 2 MAIN_ONG [2,36]
P31 A10 VSSP_SENSE R125 R126
A VCC95 VSSIO_SENSE TP33 close to CPU 130/F_4 *130/F_4
close to VR C235 Q19 A
P30 VCC96
P29 Trace Route to Power IC area. *470P/50V_4 2N7002
VCC97 H_CPU_SVIDDAT
P28 VR_SVID_DATA [35]
CPU VDDQ

1
VCC98 R632
P27 VCC99
P26 VCC100 10_4
DV2: Add PD 10 ohm
[7,10,33,36] +1.8V
Place PU resistor close to CPU SVID ALERT PROJECT : QLC
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
[2,10,12,13,30,31] +1.5VSUS +1.05V_VTT R115 75_4 Quanta Computer Inc.
[2,10,25] +1.5V_CPU
DGG^9000014 [2,10,27,32,34,35] +1.05V_VTT
IC SOCKET RPGA 989P(P1.0,M/H3.0) [34,36] +VCCSA H_CPU_SVIDALRT# R112 43_4 VR_SVID_ALERT# [35] Size Document Number Rev
1A
[35] +VCC_GFX NB5 SNB 3/4 (POWER)
[35] +VCC_CORE
Date: Friday, November 26, 2010 Sheet 4 of 36
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AT35
U17H
Sandy Bridge Processor (GND)

AJ22
U17I
Sandy Bridge Processor (RESERVED, CFG)
U17E
05
VSS1 VSS81
AT32 VSS2 VSS82 AJ19 For CPU debug. RSVD28 L7
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22 RSVD29 AG7
AT27 AJ13 T34 F19 CFG0 AK28 AE7
VSS4 VSS84 VSS162 VSS235 TP8 CFG[0] RSVD30
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 TP9 AK29 CFG[1] RSVD31 AK2
AT22 AJ7 T32 E27 CFG2 AL26 W8
VSS6 VSS86 VSS164 VSS237 CFG[2] RSVD32
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24 TP6 AL27 CFG[3]
D AT16 AJ3 T30 E21 CFG4 AK26 D
VSS8 VSS88 VSS166 VSS239 CFG5 CFG[4]
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 AL29 CFG[5] RSVD33 AT26
AT10 AJ1 T28 E15 CFG6 AL30 AM33
VSS10 VSS90 VSS168 VSS241 CFG7 CFG[6] RSVD34
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AM31 CFG[7] RSVD35 AJ27
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10 AM32 CFG[8]
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM30 CFG[9]
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8 AM28 CFG[10]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM26 CFG[11]
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AN28 CFG[12]
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5 AN31 CFG[13] RSVD37 T8
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4 AN26 CFG[14] RSVD38 J16
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 AM27 CFG[15] RSVD39 H16
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2 AK31 CFG[16] RSVD40 G16
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1 AN29 CFG[17]
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26 RSVD41 AR35
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20 AJ31 RSVD1 RSVD42 AT34
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17 AH31 RSVD2 RSVD43 AT33
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34 AJ33 RSVD3 RSVD44 AP35
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31 AH33 RSVD4 RSVD45 AR34
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25 AJ26 RSVD5

RESERVED
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1 RSVD46 B34
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22 [12] SMDDR_VREF_DQ0_M3 B4 RSVD6 RSVD47 A33
AN25 AE29 L4 B19 D1 A34
C AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
[13] SMDDR_VREF_DQ1_M3 RSVD7 RSVD48
RSVD49
RSVD50
B35
C35
C

AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13


AN13 AE9 K35 B11 R368 R36 F25
VSS41 VSS121 VSS199 VSS272 *1K_4 *1K_4 RSVD8
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9 F24 RSVD9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8 F23 RSVD10
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 G24 RSVD13
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2 E23 RSVD14
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35 D23 RSVD15
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32 C30 RSVD16 RSVD53 AH27
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29 A31 RSVD17
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26 B30 RSVD18
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23 B29 RSVD19
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 TP35
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD55 AM35 TP34
AM2 VSS55 VSS135 AB29 H10 VSS213 A30 RSVD22
AM1 VSS56 VSS136 AB28 H9 VSS214 C29 RSVD23 #27636 SNB EDS0.7v1 no function.
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216 PV: Change to short pad
AL28 VSS59 VSS139 Y9 H6 VSS217 J20 RSVD24
AL25 VSS60 VSS140 Y8 H5 VSS218 B18 RSVD25 RSVD56 AT2
AL22 Y6 H4 R376 *0_4/S A19 AT1
VSS61 VSS141 VSS219 [32] H_VTTVID1 RSVD26 RSVD57
AL19 VSS62 VSS142 Y5 H3 VSS220 RSVD58 AR1
AL16 VSS63 VSS143 Y3 H2 VSS221
AL13 VSS64 VSS144 Y2 H1 VSS222 J15 RSVD27 For rPGA socket, RSVD59 pin should be left NC.
AL10 VSS65 VSS145 W 35 G35 VSS223
AL7 VSS66 VSS146 W 34 G32 VSS224
AL4 VSS67 VSS147 W 33 G29 VSS225 KEY B1
B AL2 W 32 G26 B
VSS68 VSS148 VSS226
AK33 VSS69 VSS149 W 31 G23 VSS227
AK30 VSS70 VSS150 W 30 G20 VSS228
AK27 VSS71 VSS151 W 29 G17 VSS229
AK25 VSS72 VSS152 W 28 G11 VSS230
AK22 VSS73 VSS153 W 27 F34 VSS231
AK19 W 26 F31 Sandy Bridge_rPGA_Rev0p61
VSS74 VSS154 VSS232 rpga989-47989-socket
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 U8 DGG^9000014
VSS76 VSS156 IC SOCKET RPGA 989P(P1.0,M/H3.0)
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61


rpga989-47989-socket rpga989-47989-socket
DGG^9000014 DGG^9000014
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)

CFG[6:5] (PCIE Port Bifurcation Straps)


The CFG signals have a default value of '1' if not terminated on the board.
Processor Strapping 11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
1 0 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
CFG2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
A A
(PEG Static Lane Reversal) Normal Operation Lane Reversed CFG2 R132 1K_4

CFG4 CFG4 R134 *1K_4

(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG7 R120 *1K_4
PROJECT : QLC
CFG7 PEG train immediately following PEG wait for BIOS training CFG5 R121 *1K_4 Quanta Computer Inc.
(PEG Defer Training) xxRESETB de assertion CFG6 R116 *1K_4
Size Document Number Rev
1A
NB5 SNB 4/4 (GND)
Date: Friday, November 26, 2010 Sheet 5 of 36
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Cougar Point (DMI,FDI,PM)

BC24
U28C

BJ14
[20] PCH_LVDS_BLON
Cougar Point (LVDS,DDI)
J47
M45
U28D
L_BKLTEN SDVO_TVCLKINN AP43
AP45
06
[2] DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0 [2] [20] PCH_DISP_ON L_VDD_EN SDVO_TVCLKINP
[2] DMI_RXN1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_TXN1 [2]
[2] DMI_RXN2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_TXN2 [2] [20] PCH_DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42
[2] DMI_RXN3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_TXN3 [2] SDVO_STALLP AM40
BC12 [20] PCH_EDIDCLK PCH_EDIDCLK T40
FDI_RXN4 FDI_TXN4 [2] L_DDC_CLK
BE24 BJ12 PCH_EDIDDATA K47 AP39
[2] DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 [2] [20] PCH_EDIDDATA L_DDC_DATA SDVO_INTN
[2] DMI_RXP1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_TXN6 [2] SDVO_INTP AP40
D BJ18 BG9 CTRL_CLK T45 D
[2] DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 [2] L_CTRL_CLK
[2] DMI_RXP3 BJ20 CTRL_DATA P39
DMI3RXP L_CTRL_DATA
FDI_RXP0 BG14 FDI_TXP0 [2]
AW 24 BB14 LVD_IBG AF37 P38
[2] DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 [2] LVD_IBG SDVO_CTRLCLK SDVO_CLK [19]
[2] DMI_TXN1 AW 20 DMI1TXN FDI_RXP2 BF14 FDI_TXP2 [2] T25 AF36 LVD_VBG SDVO_CTRLDATA M39 SDVO_DATA [19]
[2] DMI_TXN2 BB18 DMI2TXN FDI_RXP3 BG13 FDI_TXP3 [2]
[2] DMI_TXN3 AV18 DMI3TXN FDI_RXP4 BE12 FDI_TXP4 [2] AE48 LVD_VREFH

INT. HDMI
FDI_RXP5 BG12 FDI_TXP5 [2] AE47 LVD_VREFL DDPB_AUXN AT49

DMI
FDI
[2] DMI_TXP0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TXP6 [2] DDPB_AUXP AT47
[2] DMI_TXP1 AY20 BH9 AT40 DPB_HPD_Q
DMI1TXP FDI_RXP7 FDI_TXP7 [2] DDPB_HPD
AY18 PCH_LA_CLK# AK39
[2] DMI_TXP2 DMI2TXP [20] PCH_LA_CLK# LVDSA_CLK#
AU18 PCH_LA_CLK AK40 AV42 DPB_LANE0_N

LVDS
[2] DMI_TXP3 DMI3TXP [20] PCH_LA_CLK LVDSA_CLK DDPB_0N
AW 16 AV40 DPB_LANE0_P
FDI_INT FDI_INT [2] DDPB_0P
PCH_LA_DATAN0 AN48 AV45 DPB_LANE1_N
[20] PCH_LA_DATAN0 LVDSA_DATA#0 DDPB_1N
BJ24 AV12 PCH_LA_DATAN1 AM47 AV46 DPB_LANE1_P
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [2] [20] PCH_LA_DATAN1 LVDSA_DATA#1 DDPB_1P
PCH_LA_DATAN2 DPB_LANE2_N

Digital Display Interface


[20] PCH_LA_DATAN2 AK47 LVDSA_DATA#2 DDPB_2N AU48
+1.05V R589 49.9/F_4 DMI_COMP BG25 BC10 AJ48 AU47 DPB_LANE2_P
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [2] LVDSA_DATA#3 DDPB_2P
AV47 DPB_LANE3_N
R578 750/F_4 DMI_RBIAS PCH_LA_DATAP0 DDPB_3N DPB_LANE3_P
BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 [2] [20] PCH_LA_DATAP0 AN47 LVDSA_DATA0 DDPB_3P AV49
[20] PCH_LA_DATAP1 PCH_LA_DATAP1 AM49
PCH_LA_DATAP2 LVDSA_DATA1
FDI_LSYNC1 BB10 FDI_LSYNC1 [2] [20] PCH_LA_DATAP2 AK49 LVDSA_DATA2
PV: Change to short pad AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
SUS_PWR_ACK_R *0_4/S R570 A18 DSWVREN DV2: Change to RSMRST# PCH_LB_CLK# AF40
DSW VRMEN [20] PCH_LB_CLK# LVDSB_CLK#
[20] PCH_LB_CLK PCH_LB_CLK AF39 AP47

System Power Management


*0_4/S R585 RSMRST# PV: Change to short pad LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
[27] SUSACK# R565 *0_4 SUSACK#_R C12 E22 R586 *0_4 DPWROK [20] PCH_LB_DATAN0 PCH_LB_DATAN0 AH45 AT38
SUSACK# DPW ROK PCH_LB_DATAN1 LVDSB_DATA#0 DDPC_HPD
[20] PCH_LB_DATAN1 AH47 LVDSB_DATA#1
5/7: DEL R8293 for SUSACK# From EC PCH_LB_DATAN2 AF49 AY47
C
[20] PCH_LB_DATAN2 LVDSB_DATA#2 DDPC_0N C
XDP_DBRST# K3 B9 PCIE_WAKE# PCIE_WAKE# [24] AF45 AY49
[2] XDP_DBRST# SYS_RESET# W AKE# LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
PV: Change to short pad (+3V) PCH_LB_DATAP0 AH43 AY45
[20] PCH_LB_DATAP0 LVDSB_DATA0 DDPC_1P
SYS_PWROK *0_4/S R568 SYS_PWROK_R P12 N3 CLKRUN# PCH_LB_DATAP1 AH49 BA47
SYS_PW ROK CLKRUN# / GPIO32 CLKRUN# [27] [20] PCH_LB_DATAP1 LVDSB_DATA1 DDPC_2N
R573 *0_4 PCH_LB_DATAP2 AF47 BA48
[20] PCH_LB_DATAP2 LVDSB_DATA2 DDPC_2P
(+3VS5) AF43 LVDSB_DATA3 DDPC_3N BB47
R576 0_4 EC_PWROK_R L22 G8 BB49
[27] EC_PWROK PW ROK SUS_STAT# / GPIO61 TP17 DDPC_3P
(+3VS5)
EC_PWROK_R *0_4/S R151 APWROK_R L10 N14 PCH_SUSCLK_L R166 0_4 PCH_CRT_B N48 M43
APW ROK SUSCLK / GPIO62 PCH_SUSCLK [27] [19] PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
PCH_CRT_G P49 M36
TP14 [19] PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
PV: Change to short pad (+3VS5) PCH_CRT_R T49
[19] PCH_CRT_R CRT_RED
[2] PM_DRAM_PWRGD PM_DRAM_PWRGD B13 D10 SLP_S5 [27]
DRAMPW ROK SLP_S5# / GPIO63
DDPD_AUXN AT45
T39 AT43

CRT
[19] PCH_DDCCLK CRT_DDC_CLK DDPD_AUXP
[27] RSMRST# RSMRST# C21 H4 *0_4/S R165 SUSC# [27] [19] PCH_DDCDATA M40 BH41
RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
PV: Change to short pad (+3VS5) PV: Change to short pad BB43
*0_4/S R571 SUS_PWR_ACK_R *0_4/S R547 PCH_HSYNC_R DDPD_0N
[27] SUS_PWR_ACK K16 SUSW ARN#/SUSPW RDNACK/GPIO30 SLP_S3# F4 SUSB# [27] M47 CRT_HSYNC DDPD_0P BB45
PCH_VSYNC_R M49 BF44
PV: Unstuff CRT_VSYNC DDPD_1N
DDPD_1P BE44
*0_4/S R582 DNBSWON#_R E20 G10 R160 *0_4 BF42
[27] DNBSWON# PW RBTN# SLP_A# SLP_A# [27] DDPD_2N
DAC_IREF T43 BE42
DAC_IREF DDPD_2P
(DSW) T42 CRT_IRTN DDPD_3N BJ42
R596 *0_4 AC_PRESENT_R H20 G16 R583 *0_4 BG42
[27] AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# [27] DDPD_3P
R274
(+3VS5) 1K/F_4 CougarPoint_Rev_0p7
DV2: Unstuff PM_BATLOW# E10 AP14 fcbga989-intel-cougarpoint
BATLOW # / GPIO72 PMSYNCH PM_SYNC [2]
AJ0QNJH0T08
(+3VS5) IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B PM_RI# A10 K14 SLP_LAN# B
RI# SLP_LAN# / GPIO29
[7,20,26,27,28,29] +3VPCU
CougarPoint_Rev_0p7 [7,10,19,20,22,25,26,36] +5V
fcbga989-intel-cougarpoint [2,7,8,9,10,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
AJ0QNJH0T08 [2,7,8,9,10,14,24,27,29,31,33,34,35,36] +3VS5
IC CTRL(989P)COUGARPOINT QMVY TOP B/S [7,10] +3V_DSW
[7,10,27] +3V_RTC
[7,8,10,31,33] +1.05V

PCH Pull-high/low(CLG) INT LVDS & CRT disable INT HDMI disable (DIS only remove) System PWR_OK(CLG) DPWROK FOR DSW
+3VS5 (DIS only remove) +3VS5 DV2: unstuff +3VPCU
+3VPCU

DPB_LANE0_N
IN_D2# [19]
PM_RI# R562 10K_4 DPB_LANE0_P C647 *0.1U/10V_4
IN_D2 [19]
R285 2.2K_4 CTRL_CLK DPB_LANE1_N
+3V IN_D1# [19] +3V_DSW
PM_BATLOW# R561 *8.2K_4 R273 2.2K_4 CTRL_DATA DPB_LANE1_P R206 R199
IN_D1 [19]

5
DPB_LANE2_N *10K_4 *10K_4
IN_D0# [19]
PCIE_WAKE# R559 10K_4 R267 2.37K/F_4 LVD_IBG DPB_LANE2_P 2 D9
IN_D0 [19] IMVP_PWRGD [35]
DPB_LANE3_N SYS_PWROK 4 +3VPCU DPWROK
IN_CLK# [19]
SLP_LAN# R231 *10K_4 DPB_LANE3_P 1 EC_PWROK
IN_CLK [19]

3
R295 33_4 PCH_HSYNC_R *RB500V-40
[19] PCH_HSYNC

3
SUS_PWR_ACK R572 10K_4 R296 33_4 PCH_VSYNC_R U29 C316
[19] PCH_VSYNC

3
*TC7SH08FU R614 D10 *0.1U/10V_4
AC_PRESENT_R R595 10K_4 100K_4 2 2 add cap to
INT HDMI Detect Function +3VS5
R615 0_4 *RB500V-40
timing tune
A +3V R603 0_4 Q21 Q20 A
PD Res place close to PCH

1
*PDTC144EU *2N7002

1
CLKRUN# R519 8.2K_4 PCH to Res routeing 50 ohm Impedance.
XDP_DBRST# R523 10K_4
Res to connector filter routeing 37.5ohm Impedance. DPB_HPD_Q 1 3 HDMI_HPD_CON [19]
R542 *1K_4 R298 150/F_4 PCH_CRT_B
Q52
+3V_RTC R579 330K_4 DSWVREN R580 *330K_4
PROJECT : QLC
2

RSMRST# R251 10K_4 R297 150/F_4 PCH_CRT_G R608


*100K_4
*2N7002K R607
*100K_4 On Die DSW VR Enable
Quanta Computer Inc.
SYS_PWROK R567 *10K_4 R299 150/F_4 PCH_CRT_R +5V
High = Enable (Default) Size Document Number Rev
DV2: Unstuff Low = Disable NB5 PCH 1/6 (DMI/FDI/VIDEO) 1A

Date: Friday, November 26, 2010 Sheet 6 of 36


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RTC_X1
Cougar Point (HDA,JTAG,SATA)
A20
U28A

RTCX1 FW H0 / LAD0 C38


A38
LAD0 [25,27]
RTC Clock 32.768KHz 07

LPC
FW H1 / LAD1 LAD1 [25,27]
RTC_X2 C20 B37 LAD2 [25,27]
RTCX2 FW H2 / LAD2 C638 18P/50V_4 RTC_X1
FW H3 / LAD3 C37 LAD3 [25,27]
RTC_RST# D20 RTCRST#

2
1
FW H4 / LFRAME# D36 LFRAME# [25,27]

RTC
SRTC_RST# G22 SRTCRST# PCH_DRQ#0 Y3 R591
LDRQ0# E36 TP24
R240 1M_4 SM_INTRUDER# K22 K36 PCH_DRQ#1 32.768KHZ 10M_4
D
+3V_RTC INTRUDER# LDRQ1# / GPIO23 TP25 D
(+3V)

3
4
PCH_INVRMEN C17 V5 SERIRQ R188 8.2K_4 +3V C641 18P/50V_4 RTC_X2
INTVRMEN SERIRQ
SERIRQ [27]
AM3 SATA_RXN0_C C397 0.01U/25V_4
ACZ_BCLK SATA0RXN SATA_RXP0_C SATA_RXN0 [25]
N34 AM1 C394 0.01U/25V_4
HDA_BCLK SATA0RXP SATA_RXP0 [25]
AP7 SATA_TXN0_C C405 0.01U/25V_4
SATA0TXN SATA_TXN0 [25] HDD0 (SATA3 6.0Gb/s)

SATA 6G
ACZ_SYNC_R L34 AP5 SATA_TXP0_C C413 0.01U/25V_4
HDA_SYNC SATA0TXP SATA_TXP0 [25]
SPKR SATA_RXN1_C
30mils
T10 AM10 C388 0.01U/25V_4
[22] SPKR SPKR SATA1RXN SATA_RXN1 [25] +3V_RTC
AM8 SATA_RXP1_C C389 0.01U/25V_4
SATA1RXP SATA_RXP1 [25]
ACZ_RST# K34 AP11 SATA_TXN1_C C383 0.01U/25V_4 R590
HDA_RST# SATA1TXN
AP10 SATA_TXP1_C C382 0.01U/25V_4
SATA_TXN1 [25] ODD (SATA1 1.5Gb/s) RTC Circuitry(RTC) RTC_RST#
SATA1TXP SATA_TXP1 [25]

1
IHDA
[22] ACZ_SDIN0 E34 AD7 20K/F_4
HDA_SDIN0 SATA2RXN R574 *0_6 C639
SATA2RXP AD5 +3V_DSW FOR DSW
TP23 G34 AH5 RTC Power trace width 20mils. J2
HDA_SDIN1 SATA2TXN 1U/6.3V_4 *SOLDERJUMPER-2
AH4

2
SATA2TXP +5VPCU PV: Change to short pad
C34 HDA_SDIN2
PV: Change to TP3050 AB8 +3VPCU R575 *0_6/S +3V_RTC_2 R584
SATA3RXN SRTC_RST#
A34 HDA_SDIN3 SATA3RXP AB10

SATA
SATA3TXN AF3 +VCCRTC_13 1 +3V_RTC_0 R577 1K_4 +3V_RTC_1 20K/F_4

1
AF1 R339 4.7K_4
ACZ_SDOUT SATA3TXP Q32 C630
A36 HDA_SDO

1
PV: reserver Y7 MMBT3904 D28 C635 J1

2
SATA4RXN R340 4.7K_4 +VCCRTC_2 BT2 BAT54C 1U/6.3V_4 1U/6.3V_4 *SOLDERJUMPER-2
(+3V) Y5

2
GPIO33 SATA4RXP
C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3 RTC_CONN
+3VS5 R644 *10K_4 AD1
(+3VS5) SATA4TXP R341
TP22 N32 HDA_DOCK_RST# / GPIO13
Y3 12K/F_4
C SATA5RXN PV: Remove BT1 C
Y1 4/20 DB add.

2
SATA5RXP
SATA5TXN AB3
TP13 PCH_JTAG_TCK_R J3 AB1 RTC_RST# R239 *0_6 SRTC_RST#
JTAG_TCK SATA5TXP
TP10 PCH_JTAG_TMS H7 Y11 2nd source DFHS02FS043
JTAG_TMS SATAICOMPO
Coil:AHL03017100/AHL03001424
JTAG

TP12 PCH_JTAG_TDI_R K5 Y10 SATA_COMP R209 37.4/F_4


JTAG_TDI SATAICOMPI +1.05V

TP52 PCH_JTAG_TDO_R H1 JTAG_TDO


SATA3RCOMPO AB12
HDA Bus(CLG) +3VS5 DV2: Unstuff
AB13 SATA3_COMP R222 49.9/F_4
SATA3COMPI +1.05V
[22] BIT_CLK_AUDIO R275 33_4 ACZ_BCLK PCH JTAG Debug(CLG)
PCH_SPI_CLK T3 AH1 SATA3_RBIAS R516 750/F_4 R278 33_4 ACZ_RST#
[27] PCH_SPI_CLK SPI_CLK SATA3RBIAS [22] ACZ_RST#_AUDIO
PCH_SPI_CS0# Y14 R261 33_4 ACZ_SDOUT
[27] PCH_SPI_CS0# SPI_CS0# [22] ACZ_SDOUT_AUDIO
SATA_LED# [26] R180 R169 R528
R537 *10K_4 PCH_SPI_CS1# T1 R301 33_4 ACZ_SYNC *210/F_4 *210/F_4 *210/F_4
+3VS5 SPI_CS1# [22] ACZ_SYNC_AUDIO
SPI

P3 R518 10K_4 +3V


SATALED# PCH_JTAG_TMS
PCH_SPI_SI (+3V) SATA0GP R190 10K_4 R294 1M_4 PCH_JTAG_TDI_R
[27] PCH_SPI_SI V4 SPI_MOSI SATA0GP / GPIO21 V14 +3V
C657 220P/50V_4 PCH_JTAG_TDO_R
PCH_SPI_SO (+3V) BBS_BIT0 DV2: DG PCH_JTAG_TCK_R
[27] PCH_SPI_SO U3 SPI_MISO SATA1GP / GPIO19 P1

+5V R300 10K_4 DV2: EMI suggest


CougarPoint_Rev_0p7 R175 R184 R527 R152

2
fcbga989-intel-cougarpoint *100/F_4 *100/F_4 *100/F_4 *51_4
AJ0QNJH0T08

B
PCH Strap Table IC CTRL(989P)COUGARPOINT QMVY TOP B/S ACZ_SYNC 1
Q27
3 ACZ_SYNC_R
B

Pin Name Strap description Sampled Configuration Circuit 2N7002

Different from 0 = Default (weak pull-down 20K) SPKR


SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode R185 *1K_4 Vender Size P/N
Calpella +3V
PCH SPI ROM(CLG)
0 = "top-block swap" mode R292 *1K_4 EON 4MB AKE39FN0Q00 (EN25F32-100HIP)
PCI_GNT3# [8]
GNT3# / GPIO55 Top-Block Swap Override PWROK 1 = Default (weak pull-up 20K) +3V R290 10K_4 Bios request, for can't boot Capella 4/23.
Winbond 4MB AKE391P0N00 (W25Q32BVSSIG)
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up PCH_INVRMEN R581 330K_4 +3V_RTC Socket DG008000031 +3V
Flash Descriptor Security 0 = Override U10
HDA_DOCK_EN#/GPIO33 Only for Interposer PWROK 1 = Default (weak pull-up 20K) GPIO33 R600 *1K_4 PCH_SPI_CS0# 1 8
GPIO33_E [27] CE# VDD
PCH_SPI_CLK R303 *0_4 PCH_SPI1_CLK_R 6
PCH_SPI_SI R308 *0_4 PCH_SPI1_SI_R SCK
[Need external pull-down for LPC BIOS] 5 SI
GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1# PCH_SPI_SO R307 *0_4 PCH_SPI1_SO_R 2 7 R315 *3.3K_4
SO HOLD#
1 1 SPI
Different from 0 0 LPC R538 *1K_4 BBS_BIT0 3 4
R288 *1K_4 C401 W P# VSS C420
GPIO19 Calpella Boot BIOS Selection 0 [bit-0] PWROK BBS_BIT1 [8]
*22P/50V_4 *SPI Flash Socket *0.1U/10V_4
Should not be pull-down
GNT2# / GPIO53 ESI strap (Server only) PWROK (weak pull-up 20K) USE GPIO PIN
Intel Anti-Theft HDD protection +3V R321 *3.3K_4
NV_ALE Only for Interposer PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V R212 *1K_4 [2,6,8,9,10,14,24,27,29,31,33,34,35,36] +3VS5
NV_ALE [8]
[6,10,19,20,22,25,26,36] +5V
4/29 modify R548 2.2K_4 R549 4.7K_4
NV_CLE DMI Termination voltage PWROK weak pull-down 20kohm +1.8V NV_CLE [8]N.A at CPT EDS 0.7 [6,20,26,27,28,29] +3VPCU
H_SNB_IVB# [2] [10] +V3.3A_1.5A_HDA_IO
DV2:unstuff [2,6,8,9,10,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
A 0 = Support by 1.8V (weak pull-down) R283 1K_4 ACZ_SYNC_R A
HDA_SYNC On-Die PLL VR Voltage Select RSMRST 1 = Support by 1.5V
+3VS5 [6,10] +3V_DSW
[6,10,27] +3V_RTC
0 = Override ACZ_SDOUT R259
[4,10,33,36] +1.8V
HDA_SDO Flash Descriptor Security PWROK 1 = Default (weak pull-up 20K) [27] GPIO33_E *1K_4 +V3.3A_1.5A_HDA_IO [6,8,10,31,33] +1.05V
4/29 reserve.
GPIO8 Integrated Clock Chip Enable RSMRST# Should be pull-down (weak pull-up 20K) R566 *1K_4
ICC_EN# [9] PROJECT : QLC
Different from 0 = Disable
R550 *1K_4
Quanta Computer Inc.
GPIO28 Calpella On-die PLL Voltage Regulator RSMRST# 1 = Enable (Default) PLL_ODVR_EN [9] Arrandale+VGA
0 = Default (weak pull-down 20K) Size Document Number Rev
SPI_MOSI iTPM function Disable APWROK 1 = Enable PCH_SPI_SI R173 1K_4 1A
+3V NB5 PCH 2/6 (SATA/HDA/SPI)
Date: Friday, November 26, 2010 Sheet 7 of 36
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PCI/USBOC# Pull-up(CLG)
Cougar Point-M (PCI,USB,NVRAM)

BG26
U28E
NV_CE#0
NV_CE#1
AY7
AV7
AU3
[25]
[25]
PCIE_RXN1
PCIE_RXP1
Cougar Point-M (PCI-E,SMBUS,CLK)
BG34
BJ34
U28B

PERN1
(+3VS5)
E12 SMBALERT#
08
TP1 NV_CE#2 C373 0.1U/10V_4 PCIE_TXN1_C PERP1 SMBALERT# / GPIO11
+3V
BJ26
TP2 NV_CE#3
BG4 WLAN [25] PCIE_TXN1
C372 0.1U/10V_4 PCIE_TXP1_C
AV32
PETN1 SMB_PCH_CLK
BH25 [25] PCIE_TXP1 AU32 H14
TP3 PETP1 SMBCLK
BJ16 AT10
PCI_PIRQA# R265 8.2K_4 TP4 NV_DQS0 SMB_PCH_DAT
BG16 BC8 [24] PCIE_RXN2_LAN BE34 C9
PCI_PIRQB# R601 8.2K_4 TP5 NV_DQS1 PERN2 SMBDATA
AH38 [24] PCIE_RXP2_LAN BF34
PCI_PIRQC# R264 8.2K_4 TP6 C375 0.1U/10V_4 PCIE_TXN2_LAN_C PERP2
AH37 AU2 LAN BB32

SMBUS
TP7 NV_DQ0 / NV_IO0 [24] PCIE_TXN2_LAN PETN2
PCI_PIRQD# R266 8.2K_4 AK43 AT4 [24] PCIE_TXP2_LAN C374 0.1U/10V_4 PCIE_TXP2_LAN_C AY32 (+3VS5)
TP8 NV_DQ1 / NV_IO1 PETP2 DRAMRST_CNTRL_PCH
D AK45 AT3 A12 DRAMRST_CNTRL_PCH [2] D
TP9 NV_DQ2 / NV_IO2 SML0ALERT# / GPIO60
3/26 DB change C18
TP10 NV_DQ3 / NV_IO3
AT1 BG36
PERN3
+3V N30 AY3 BJ36 C8 SMB_ME0_CLK
Part reference. TP11 NV_DQ4 / NV_IO4 PERP3 SML0CLK
RP8 H3 AT5 AV34
TP12 NV_DQ5 / NV_IO5 PETN3 SMB_ME0_DAT
10 1 AH12 AV3 AU34 G12
MPC_PWR_CTRL# TP13 NV_DQ6 / NV_IO6 PETP3 SML0DATA
9 2 AM4 AV1
TP14 NV_DQ7 / NV_IO7

NVRAM
8 3 BT_COMBO_EN# AM5 BB1 BF36
TP15 NV_DQ8 / NV_IO8 PERN4
7 4 Y13
TP16 NV_DQ9 / NV_IO9
BA3 BE36
PERP4 (+3VS5)
LCD_BK 6 5 K24 BB5 AY34 C13 SML1ALERT#_R TP18
TP17 NV_DQ10 / NV_IO10 PETN4 SML1ALERT# / PCHHOT# / GPIO74
L24 BB3 BB34 (+3VS5)
10K_10P8R_6 TP18 NV_DQ11 / NV_IO11 PETP4 SMB_ME1_CLK
AB46 BB7 E14
TP19 NV_DQ12 / NV_IO12 SML1CLK / GPIO58
AB45 BE8 BG37 (+3VS5)
TP20 NV_DQ13 / NV_IO13 PERN5 SMB_ME1_DAT
3/26 DB change BD4 BH37 M16

RSVD

PCI-E*
+3VS5 NV_DQ14 / NV_IO14 PERP5 SML1DATA / GPIO75
Part reference. BF6 AY36
RP7 NV_DQ15 / NV_IO15 PETN5
BB36
USB_OC6# NV_ALE PETP5
10 1 B21 AV5 NV_ALE [7]
USB_OC4# USB_OC0# TP21 NV_ALE NV_CLE PV: Change to TP3050
9 2 M20 AY1 NV_CLE [7] BJ38
USB_OC1# USB_OC7# TP22 NV_CLE PERN6
8 3 AY16 BG38
TP23 PERP6

Controller
USB_OC2# 7 4 USB_OC5# BG46 AV10 AU36 M7 CL_CLK_R TP15
USB_OC3# TP24 NV_RCOMP PETN6 CL_CLK1
6 5 AV36
PETP6
AT8
NV_RB#

Link
10K_10P8R_6 BG40 T11 CL_DAT_R TP16
PERN7 CL_DATA1
BE28 AY5 BJ40
TP25 NV_RE#_WRB0 PERP7
BC30 BA2 AY40
TP26 NV_RE#_WRB1 PETN7 CL_RST#_R
BE32 BB40 P10 TP20
TP27 PETP7 CL_RST1#
MPC Switch Control BJ32
TP28 NV_WE#_CK0
AT12
BC28 BF3 BE38
TP29 NV_WE#_CK1 PERN8
Low = MPC ON BE30
TP30
BC38
PERP8
MPC_PWR_CTRL# High = MPC OFF (Default) BF32
TP31
AW38
PETN8
BG32
TP32 USBP0N
C24 AY38
PETP8 (+3VS5)
AV26 A24 M10 CLK_PEGA_REQ#
MPC_PWR_CTRL# R606 *1K_4 TP33 USBP0P PEG_A_CLKRQ# / GPIO47
BB26
TP34 USBP1N
C25 USBP1- [26] Left_USB CLK_PCH_SRC0N
C +3V
AU28
TP35 USBP1P
B25 USBP1+ [26]
CLK_PCH_SRC0P
Y40
CLKOUT_PCIE0N CLK_PCH_PEGAN
GPU C
AY30 C26 USBP2- [26] Y39 AB37
TP36 USBP2N CLKOUT_PCIE0P CLKOUT_PEG_A_N CLK_PCH_PEGAP
R631 10K_4 DGPU_HOLD_RST_N
AU26
TP37 USBP2P
A26 USBP2+ [26] Right side WLAN CLK_PCIE_REQ0# CLKOUT_PEG_A_P
AB38
AY26 K28 J2
TP38 USBP3N PCIECLKRQ0# / GPIO73
AV28 H28
TP39 USBP3P
DV2: Add pull high AW30
TP40 USBP4N
E28 USBP4- [26] (+3VS5) CLKOUT_DMI_N
AV22 CLK_CPU_BCLKN [2]
D28 USBP4+ [26] Right side CLK_PCH_SRC2N AB49 AU22 CLK_CPU_BCLKP [2]
USBP4P CLK_PCH_SRC2P CLKOUT_PCIE1N CLKOUT_DMI_P
USBP5N
C28 LAN AB47
CLKOUT_PCIE1P
USBP5P
A28
C29 CLK_PCIE_REQ1# M1
CLOCKS AM12
USBP6N PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLK_DPLL_SSCLKN [2]
PCI_PIRQA# USBP6P
B29 HM65 Port6 & Port7 CLKOUT_DP_P
AM13 CLK_DPLL_SSCLKP [2]
K40
PIRQA# USBP7N
N28 (+3V)
PCI_PIRQB# K38 M28 are disable AA48
PCI_PIRQC# PIRQB# USBP7P CLKOUT_PCIE2N CLK_BUF_PCIE_3GPLL#
H38 L30 AA47 BF18
PCI

PCI_PIRQD# PIRQC# USBP8N CLKOUT_PCIE2P CLKIN_DMI_N CLK_BUF_PCIE_3GPLL


G38 K30 BE18
PIRQD# USBP8P CLK_PCIE_REQ2# CLKIN_DMI_P
G30 USBP9- [20] V10
BT_COMBO_EN# USBP9N PCIECLKRQ2# / GPIO20
[25] BT_COMBO_EN# C46
REQ1# / GPIO50 (+3V) USBP9P
E30 USBP9+ [20] Webcam CLK_BUF_BCLK_N
C44 C30 (+3V) BJ30
USB

REQ2# / GPIO52 (+3V) USBP10N USBP10- [25] CLKIN_GND1_N CLK_BUF_BCLK_P


E40
REQ3# / GPIO54 (+3V) USBP10P
A30 USBP10+ [25] Mini PCI-E Card - WLAN Y37
CLKOUT_PCIE3N CLKIN_GND1_P
BG30
USBP11N
L32 Y36
CLKOUT_PCIE3P
3/26 DB del external
BBS_BIT1 D47 K32 clock generator.
[7] BBS_BIT1 GNT1# / GPIO51 (+3V) USBP11P CLK_PCIE_REQ3# CLK_BUF_DREFCLK#
E42 (+3V) G32 USBP12- [21] A8 G24
PCI_GNT3# GNT2# / GPIO53 USBP12N PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLK_BUF_DREFCLK
[7] PCI_GNT3# F46
GNT3# / GPIO55 (+3V) USBP12P
E32 USBP12+ [21] Card Reaer CLKIN_DOT_96P
E24
USBP13N
C32 (+3VS5)
7/27:BIOS swap GPIO USBP13P
A32 Y43
CLKOUT_PCIE4N
MPC_PWR_CTRL# G42 Y45 AK7 CLK_BUF_DREFSSCLK#
LCD_BK PIRQE# / GPIO2 (+3V) CLKOUT_PCIE4P CLKIN_SATA_N CLK_BUF_DREFSSCLK
[20] LCD_BK G40 (+3V) AK5
DGPU_HOLD_RST_N PIRQF# / GPIO3 USB_BIAS CLK_PCIE_REQ4# CLKIN_SATA_P
TP30 C42 (+3V) C33 L12
PIRQG# / GPIO4 USBRBIAS# PCIECLKRQ4# / GPIO26
[17] DGPU_IDLE_INT# D44 (+3V)
PIRQH# / GPIO5 R598 CLK_PCH_14M
(+3VS5) REFCLK14IN
K45
B33 22.6/F_4 V45 DV2: Change to 27pF
PCI_PME# USBRBIAS CLKOUT_PCIE5N
Bios swap GPIO 4/23. TP11 K10
PME#
V46
CLKOUT_PCIE5P
H45 CLK_PCI_FB
PCI_PLTRST# USB_OC0# CLKIN_PCILOOPBACK C648
B C6 A14 [9] BOARD_ID0 L14 B
PLTRST# (+3VS5) OC0# / GPIO59
K20 USB_OC1# PCIECLKRQ5# / GPIO44 27P/50V_4
(+3VS5)

2
OC1# / GPIO40 USB_OC2#
(+3VS5) OC2# / GPIO41
B17 (+3VS5)
TP31 CLK_PCI_TPM_R H49 C16 USB_OC3# CLK_PCIEF#_R AB42 R616 Y5
CLKOUT_PCI0 (+3VS5) OC3# / GPIO42 TP29 CLKOUT_PEG_B_N
TP28 CLK_PCI_CARD_R H43 L16 USB_OC4# CLK_PCIEF_R AB40 V47 XTAL25_IN 1M_4 25MHZ
CLKOUT_PCI1 (+3VS5) OC4# / GPIO43 TP27 CLKOUT_PEG_B_P XTAL25_IN
J48 A16 USB_OC5# V49 XTAL25_OUT

1
R280 22_4 K42
CLKOUT_PCI2 (+3VS5) OC5# / GPIO9
D14 USB_OC6# CLK_PEGB_REQ# E6
XTAL25_OUT
[25] CLK_33M_DEBUG CLKOUT_PCI3 (+3VS5) OC6# / GPIO10 PEG_B_CLKRQ# / GPIO56
[27] CLK_33M_KBC R277 22_4 H40 C14 USB_OC7# C649
CLKOUT_PCI4 (+3VS5) OC7# / GPIO14
(+3VS5) 27P/50V_4
CLK_PCI_FB R284 22_4 V40
CougarPoint_Rev_0p7 CLKOUT_PCIE6N XCLK_RCOMP R286 90.9/F_4
V42 Y47 +1.05V
CLK_PCI_FB_R fcbga989-intel-cougarpoint CLKOUT_PCIE6P XCLK_RCOMP
CLK_PCI_LPC_R AJ0QNJH0T08 [25] INT_BT_COMBO_EN# T13
CLK_PCI_EC_R IC CTRL(989P)COUGARPOINT QMVY TOP B/S PCIECLKRQ6# / GPIO45
(+3VS5) (+3V)
V38 K43 CLK_FLEX0 R281 22_4
PV: Change to TP3050 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_48M_CR [21]
Ra

FLEX CLOCKS
V37 (+3V)
CLKOUT_PCIE7P CLK_FLEX1
F47
CLKOUTFLEX1 / GPIO65 TP57
K12
PLTRST#(CLG) +3VS5 SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG) +3V [9] BOARD_ID2 PCIECLKRQ7# / GPIO46 (+3V)
H47 CLK_FLEX2
(+3VS5) CLKOUTFLEX2 / GPIO66 TP32 DV2: Removed 27MHz
TP21 AK14
CLKOUT_ITPXDP_N (+3V) Rb
C607 *0.1U/10V_4 CLK_PCIE_REQ1# R521 10K_4 AK13 K49 CLK_FLEX3
TP19 CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
2N7002K CLK_PCIE_REQ2# R189 10K_4 TP58
5

[13,17,27] MBCLK2 1 3 SMB_ME1_CLK CLK_PCH_ITPN Remove Ra, Rb for UMA & SG.
2 +3VS5 CLK_PCH_ITPP CougarPoint_Rev_0p7 AJ0QNJH0T08 27MHz support DIS only.
4 PLTRST# Q24 R219 2.2K_4 fcbga989-intel-cougarpoint IC CTRL(989P)COUGARPOINT QMVY TOP B/S
PCI_PLTRST# 1 CLK_PCIE_REQ0# R545 10K_4
2

CLK_PCIE_REQ3# R555 10K_4 3/26 DB change Part reference.


U26
+3V +3VS5
CLK_PCIE_REQ4# R214 10K_4 PCIE Clock[25] RP5 1 2 CLK_PCH_SRC0N
CLK_PCIE_WLANN SMBus/Pull-up(CLG)
3

*TC7SH08FU R533 R233 2.2K_4 0_4P2R_4 3 CLK_PCH_SRC0P +3VS5


100K_4 CLK_PEGB_REQ# R200 10K_4
WLAN [25] CLK_PCIE_WLANP 4

[13,17,27] MBDATA2 1 3 SMB_ME1_DAT CLK_PEGA_REQ# Ra R182 *10K_4 [25] PCIE_CLKREQ_WLAN# *0_4/S R526 CLK_PCIE_REQ0# R208 1K_4 DRAMRST_CNTRL_PCH
CLK_PEGA_REQ# Rb R183 *10K_4
Q26 PV: Change to short pad 3/26 DB change Part reference. R217 10K_4 SMBALERT#
A
*0_4/S R532 PLTRST# 2N7002K SG : Rb ; UMA : Ra RP4 3 4 CLK_PCH_SRC2N R227 2.2K_4 SMB_PCH_CLK
A
PLTRST# [2,14,24,25,27] [24] CLK_PCIE_LANN
CLK_BUF_BCLK_N R592 10K_4 LAN [24] CLK_PCIE_LANP 0_4P2R_4 1 2 CLK_PCH_SRC2P R203 2.2K_4 SMB_PCH_DAT
CLK_BUF_BCLK_P R593 10K_4 R552 2.2K_4 SMB_ME0_CLK
SMB_PCH_DAT 3 1 SMB_RUN_DAT [12,13] [24] PCIE_CLKREQ_LAN# *0_4/S R540 CLK_PCIE_REQ1# R220 2.2K_4 SMB_ME0_DAT
R224 10K_4 SML1ALERT#_R
PV: Change to short pad Q49 CLK_BUF_PCIE_3GPLL# R236 10K_4 PV: Change to short pad 3/26 DB change Part reference.
2N7002K R498 4.7K_4 CLK_BUF_PCIE_3GPLL R230 10K_4 [14] CLK_PCIE_VGA# RP3 2 1 CLK_PCH_PEGAN
2

+3V
R499 4.7K_4
CLK_BUF_DREFCLK#
CLK_BUF_DREFCLK
R247
R252
10K_4
10K_4
GPU [14] CLK_PCIE_VGA 0_4P2R_4 4 3 CLK_PCH_PEGAP
Remove for UMA only.
PROJECT : QLC
2

CLK_BUF_DREFSSCLK#
CLK_BUF_DREFSSCLK
R205
R204
10K_4
10K_4
[14] PCIE_CLKREQ_VGA# *0_4/S R167 CLK_PEGA_REQ# Quanta Computer Inc.
SMB_PCH_CLK 3 1 SMB_RUN_CLK [12,13] CLK_PCH_14M R279 10K_4 PV: Change to short pad Arrandale+VGA

http://www.vinafix.vn
[2,6,7,9,10,14,24,27,29,31,33,34,35,36] +3VS5 Size Document Number Rev
Q50 CLOCK TERMINATION for FCIM 1A
NB5 PCH 3/6 (PCIE/USB/CLK)
http://www.vinafix.vn
[6,7,10,31,33] +1.05V
2N7002K [2,6,7,9,10,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
Date: Friday, November 26, 2010 Sheet 8 of 36
5 4 3 2 1
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Vin
5 4 3 2 1

Cougar Point (GPIO,VSS_NCTF,RSVD)


09
DV2: Add RF power on/off control

5/11 stuff R9144


Bios swap GPIO 4/23. U28F RF_POWER_OFF [25]
S_GPIO R187 0_4 T7 C40 GPIO68 R271 *10K_4 +3V
BMBUSY# / GPIO0 TACH4 / GPIO68
SIO_EXT_SMI# (+3V) (+3V) GPIO69 R610 1.5K/F_4
[27] SIO_EXT_SMI# A42 TACH1 / GPIO1 TACH5 / GPIO69 B41
4/29 modify (+3V) (+3V)
R611 *1.5K/F_4 +3V
SIO_EXT_SCI# H36 C41 TACH0
[27] SIO_EXT_SCI# TACH2 / GPIO6 TACH6 / GPIO70 TP55
BT_OFF# (+3V) (+3V) GPIO71
TP26 E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 TP56
D ICC_EN# (+3V) D
[7] ICC_EN# C10 GPIO8 (+3V)
LAN_DISABLE#_R C4
(+3VS5)
LAN_PHY_PW R_CTRL / GPIO12
RF_OFF# G2
(+3VS5) P4
[25] RF_OFF# GPIO15 A20GATE EC_A20GATE [27]

(+3VS5) PECI AU16


Reserve R536 *0_4 ODD_PRSNT#_R U2

CPU/MISC
[25] ODD_PRSNT# SATA4GP / GPIO16
P5 EC_RCIN# EC_RCIN# [27]
RCIN#
(+3V)
R272 0_4 D40 AY11

GPIO
[14,16,27] DGPU_PWROK TACH0 / GPIO17 PROCPW RGD H_PWRGOOD [2]
BIOS_REC T5
(+3V) AY10 PCH_THRMTRIP# R226 390_4
Bios swap GPIO 4/23. SCLOCK / GPIO22 THRMTRIP# PM_THRMTRIP# [2,27] MFG-TEST GPIO Pull-up/Pull-down(CLG)
R163 0_4 BOARD_ID5 (+3V)
[14,27] DGPU_HOLD_RST# E8 GPIO24 / MEM_LED INIT3_3V# T14
+3V
GPIO27 (+3VS5) +3VS5
E16 GPIO27 MFG_MODE R520 10K_4
R553 0_4 PLL_ODVR_EN_R (DSW) LAN_DISABLE#_R R546 10K_4
[7] PLL_ODVR_EN P8 GPIO28
AH8 R539 *0_4
BOARD_ID3 (+3VS5) NC_1
K1 STP_PCI# / GPIO34
AK11 +3V
BOARD_ID4 (+3V) NC_2
K4 GPIO35
AH10 SIO_EXT_SCI# R262 10K_4
R558 0_4 DGPU_PWR_EN_R V8
(+3V) NC_3 SIO_EXT_SMI# R612 10K_4
[27,31] DGPU_PWR_EN SATA2GP / GPIO36
AK10 R221 0_4 BT_OFF# R270 10K_4
FDI_OVRVLTG (+3V) NC_4 EC_A20GATE R155 10K_4
M5 SATA3GP / GPIO37
P37 Bios swap GPIO 4/23. EC_RCIN# R154 10K_4
MFG_MODE (+3V) NC_5 SATA5GP R502 10K_4
N2 SLOAD / GPIO38 TACH0 R609 1.5K/F_4
C DGPU_PRSNT# (+3V) DG rev0.9 suggest to TS_VSS connect to GND 4/23. +3V GPIO71 R605 1.5K/F_4 C
M3 SDATAOUT0 / GPIO39 ODD_PRSNT#_R R517 10K_4
TEST_SET_UP V13
(+3V) BG2 S_GPIO R157 10K_4 DGPU_PWROK R269 *10K_4
SDATAOUT1 / GPIO48 VSS_NCTF_15 R172 *0_4
SATA5GP (+3V)
V3 SATA5GP / GPIO49 VSS_NCTF_16 BG48
DGPU_PWROK R276 *10K_4
DV2: Unstuff
SV_DET (+3V) GPIO27 R232 10K_4
D6 GPIO57 VSS_NCTF_17 BH3
R535
(+3VS5)
*10K_4 VSS_NCTF_18 BH47
4/29 modify
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44


+3VS5
7/21:Remove ESATA A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
+3V
A46
NCTF BJ46 RF_OFF# R529 1K_4
VSS_NCTF_4 VSS_NCTF_22 R170 *0_4 BIOS_REC R156 10K_4
OPTIMUS POWER control pin A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
Intel ME Crypto Transport Layer
DGPU_PWROK GPIO17 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 Security (TLS) cipher suite
BIOS RECOVERY High = Disable (Default)
DGPU_HOLD_RST# GPIO24 B3 C2 Low = Disable (Default) Low = Enable
VSS_NCTF_7 VSS_NCTF_25 High = Enable
DGPU_PWR_EN GPIO36 B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49


B BE1 E1 +3V +3V B
VSS_NCTF_11 VSS_NCTF_29
BE49 E49 R171 *0_4 TEST_SET_UP R186 10K_4 R162 100K_4 SV_DET R179 *10K_4
VSS_NCTF_12 VSS_NCTF_30
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
SV_SET_UP TEST DETECT
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
High = Strong (Default) Low = Default
CougarPoint_Rev_0p7 IC CTRL(989P)COUGARPOINT QMVY TOP B/S
fcbga989-intel-cougarpoint
AJ0QNJH0T08

7/27: BIOS swap GPIO


DV2: Unstuff
BOARD ID SETTING +3V +3V

DV2: Removed board ID1 DGPU_PWR_EN_R R158 *200K/F_4 R168 100K_4 FDI_OVRVLTG R153 *1K_4
BOARD_ID0
Board ID ID0 ID1 ID2 ID3 ID4 ID5 ID6 [8] BOARD_ID0
BOARD_ID2 Low = Tx, Rx terminated to
LG 0=LG [8] BOARD_ID2
DMI TERMINATION FDI TERMINATION LOW - Tx, Rx terminated
same voltage (DC Coupling Mode)
1-CB VOLTAGE OVERRIDE (DEFAULT) VOLTAGE OVERRIDE to same voltage
RD0 RU0
UMA/Dis. R563 10K_4 BOARD_ID0 R560 *10K_4 +3VS5

RD1 RU1
15.6"/ 14" 0=QLH/TWH R164 10K_4 BOARD_ID1 R181 *10K_4
1=QLC/SWH
A
RD2 BOARD_ID2
RU2 A
R210 *10K_4 R216 10K_4
GFX Present +3V [2,6,7,8,10,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
MDC RD3 BOARD_ID3
RU3 [2,6,7,8,10,14,24,27,29,31,33,34,35,36] +3VS5
R543 *10K_4 R524 10K_4 +3V Rb Ra
R541 *100K_4 DGPU_PRSNT# R522 10K_4
0=NO RD4 RU4
Dobly 1=YES R544 10K_4 BOARD_ID4 R525 *10K_4
OPT UMA
PROJECT : QLC
R551
RD5
*10K_4 BOARD_ID5 R554
RU5
10K_4 Stuff Ra Rb
Quanta Computer Inc.
Optiums +3VS5 Arrandale+VGA
DV2: Change ID2 setting NC Rb Ra Size Document Number Rev
1A
NB5 PCH 4/6 (GPIO/MISC)
Date: Friday, November 26, 2010 Sheet 9 of 36
5 4 3 2 1

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http://www.vinafix.vn
a f i x
Vin
5 4 3 2 1

R618 *0_8 +VCCACLK


Cougar Point-M (POWER)

AD49
U28J

N26
+1.05V_VCCUSBCORE

R291
+1.05V

*0_8/S +1.05V
1.3 A (60mils)
+1.05V_PCH_VCC
COUGAR POINT (POWER)
U28G
1mA (10mils) PV: Change to 1.5uH
10
+1.05V VCCACLK VCCIO[29] +VCCA_DAC_1_2 +3V
+3V_DSW R229 *0_4 R223
P26 L21
*0_4/S R235 +VCCPDSW VCCIO[30] C370
+3VS5 T16 VCCDSW 3_3 AA23 VCCCORE[1] VCCADAC U48
3mA (10mils) P28 1U/6.3V_4 119mA (20mils) 0.002/F_1206 AC23 1.5uH
C329 VCCIO[31] C365 C357 VCCCORE[2]
AD21

CRT
C343 PCH_VCCDSW +3VS5 1U/6.3V_4 1U/6.3V_4 VCCCORE[3] C417 10U/6.3VS_6
V12 DCPSUSBYP VCCIO[32] T27 AD23 VCCCORE[4] VSSADAC U47
D 0.1U/10V_4 AF21 D
*0.1U/10V_4 R243 *0_6/S VCCCORE[5] C402 0.1U/10V_4
T29 AF23

VCC CORE
+3V_SUS_CLKF33 T38 VCCIO[33] VCCCORE[6]
VCC3_3[5] AG21 VCCCORE[7]
AG23 C406 0.01U/25V_4
+3V_VCCPUSB VCCCORE[8]
DV2: un-stuff VCCSUS3_3[7] T23 C356 AG24 VCCCORE[9]
BH23 0.1U/10V_4 AG26 R312 *0_6
+1.05V +VCCAPLL_CPY_PCH VCCAPLLDMI2 C345 C362 VCCCORE[10]
VCCSUS3_3[8] T24 AG27 VCCCORE[11]
L42 +VCCDPLL_CPY AL29 10U/6.3VS_6 1U/6.3V_4 AG29 1mA (10mils)
VCCIO[14] VCCCORE[12]

USB
V23 R245 *0_6/S AJ23
VCCSUS3_3[9] VCCCORE[13] +VCCALVDS +3V
AJ26 VCCCORE[14]
*10uH/100mA_8 +VCCSUS1 AL24 V24 AJ27 Ra
C634 DCPSUS[3] VCCSUS3_3[10] C359 VCCCORE[15] R599 0_4
AJ29 VCCCORE[16] VCCALVDS AK36
*10U/6.3V_6 P24 +3V_VCCAUBG 0.1U/10V_4 +1.05V +1.05V_PCH_VCCDPLL_EXP AJ31 Rb
C353 VCCSUS3_3[6] VCCCORE[17] R597 *0_4
VSSALVDS AK37
+1.05V *1U/6.3V_4 AA19 R244 *0_6/S
VCCASW [1] +VCCAUPLL R253 *0_6/S
VCCIO[34] T26 +1.05V 60mA (10mils)
R250 *0_6/S AA21 Ra
VCCASW [2] +VCC_TX_LVDS L22 +1.8V
VCCTX_LVDS[1] AM37
AA24 M26 +5V_PCH_VCC5REFSUS +1.05V +1.05V_VCCAPLL_EXP AN19 0.1uH/250mA_8
VCCASW [3] V5REF_SUS L40 VCCIO[28]
AM38

LVDS
+1.05V +1.05V_VCCEPW VCCTX_LVDS[2]
1.01A (60mils) AA26 VCCASW [4] Rb
R619 AN23 +VCCA_USBSUS C352 *1U/6.3V_4 AP36 R319 *0_4
DCPSUS[4] *1uH/25mA_6 VCCTX_LVDS[3]
AA27 VCCASW [5]
AN24 +3V_VCCPSUS C628 AP37 C432 22U/6.3VS_8

Clock and Miscellaneous


0.002/F_1206 VCCSUS3_3[1] *10U/6.3V_6 VCCTX_LVDS[4]
AA29 VCCASW [6] BJ22 VCCAPLLEXP
C364 C358 C363 SG & UMA : Ra C422 0.01U/25V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 AA31 VCCASW [7] DIS : Rb C416 0.01U/25V_4
AC26 P34 +5V_PCH_VCC5REF
VCCASW [8] V5REF +1.05V +1.05V_VCCIO AN16 VCCIO[15]
C AC27 R257 2.925 A (140mils) +3V_VCC_GIO +3V C
VCCASW [9]
VCCSUS3_3[2] N20 AN17 VCCIO[16]

PCI/GPIO/LPC
AC29 V33 R602 *0_6/S

HVCMOS
C377 C376 VCCASW [10] 0.002/F_1206 VCC3_3[6]
VCCSUS3_3[3] N22 119mA (15mils)
22U/6.3VS_8 22U/6.3VS_8 AC31 C380 C379 AN21 V34
VCCASW [11] +3V_VCCPSUS R237 *0_6/S 1U/6.3V_4 1U/6.3V_4 VCCIO[17] VCC3_3[7] C643
VCCSUS3_3[4] P20 +3VS5
AD29 AN26 0.1U/10V_4
VCCASW [12] VCCIO[18]
VCCSUS3_3[5] P22
AD31 C341 AN27 42mA (10mils)
VCCASW [13] 1U/6.3V_4 VCCIO[19]

VCCIO
W 21 AA16 266mA (20mils) AP21 AT16 +VCCAFDI_VRM +1.1V_VCC_DMI +1.05V_VTT
VCCASW [14] VCC3_3[1] C384 C361 C366 VCCIO[20] VCCVRM[3]
W 23 W 16 +3V_VCCPCORE R178 *0_6/S 10U/6.3VS_6 1U/6.3V_4 1U/6.3V_4 AP23 AT20 *0_4/S R238

DMI
VCCASW [15] VCC3_3[8] +3V VCCIO[21] VCCDMI[1]
W 24 T34 AP24 +1.1V_VCC_DMI_CCI
VCCASW [16] VCC3_3[4] +3V VCCIO[22]
C315 C342
W 26 0.1U/10V_4 AP26 AB36 1U/6.3V_4
VCCASW [17] C317 +3V +3V_VCC_EXP VCCIO[23] VCCCLKDMI
W 29 0.1U/10V_4 AT24
VCCASW [18] R594 0_8 VCCIO[24] C408 C414
W 31 AJ2 +3V 1U/6.3V_4 *10U/6.3V_6
R534 *0_6/S VCCASW [19] VCC3_3[2]
+1.05V AN33 VCCIO[25]
W 33 C637
VCCASW [20] C371 0.1U/10V_4 AN34 VCCIO[26]
C613 0.1U/10V_4 190 mA (15mils)
1U/6.3V_4 C331 +VCCRTCEXT N16 AF13 160mA (15mils) AG16
0.1U/10V_4 DCPRTC VCCIO[5] VCCPNAND[1] +VCCP_NAND +1.8V
BH29

NAND / SPI
+V1.05S_SATA3 R176 *0_8/S +VCCAFDI_VRM VCC3_3[3]
VCCIO[12] AH13 +1.05V (Mobile 1.5V)
+1.05V R621 *0_6/S +VCCAFDI_VRM Y49 AG17 R218 *0_8/S
VCCVRM[4] R263 0_6 VCCPNAND[2]
160mA (20mils) VCCIO[13] AH14 +1.5V_CPU
B C318 B
C650 +1.05V_VCCA_A_DPL BD47 AF14 1U/6.3V_4 R260 *0_6 +VCCAFDI_VRM AP16 AJ16 C338
VCCADPLLA VCCIO[6] +1.05V VCCVRM[2] VCCPNAND[3]
SATA

1U/6.3V_4 65mA (10mils) 0.1U/10V_4


+1.05V_VCCAPLL_FDI
+1.05V_VCCA_B_DPL BF47 AK1 +V1.1LAN_VCCAPLL L38 AJ17
VCCADPLLB VCCAPLLSATA +1.05V VCCPNAND[4]
+1.05V R323 *0_6/S 8mA (10mils) *10uH/100mA_8 +1.05V R202 *0_8 BG6
+VCCAFDI_VRM VccAFDIPLL
AF11 20mA (10mils)

FDI
+VCCDIFFCLK VCCVRM[1] C614 R248 *0_8/S
AF17 VCCIO[7] AP17 VCCIO[27]
C421 +VCCDIFFCLKN AF33 *10U/6.3V_6 +3V_VCCME_SPI +3V
1U/6.3V_4 VCCDIFFCLKN[1] +1.05V_VCCDPLL_FDI
55mA (10mils) AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 V1 R515 *0_6/S
VCCDIFFCLKN[3] +1.05V_VCCIO1 R198 *0_6/S VCCSPI
VCCIO[3] AC17 +1.05V +1.05V_VTT AU20 VCCDMI[2]
+V1.05V_SSCVCC AG33 AD17 C610
R241 *0_6 VCCSSC VCCIO[4] C319 CougarPoint_Rev_0p7 1U/6.3V_4
+1.05V 95mA (10mils)
1.01A (60mils) 1U/6.3V_4 fcbga989-intel-cougarpoint
C333 +VCCSST V16 AJ0QNJH0T08
C339 0.1U/10V_4 DCPSST +1.05V_VCCEPW +1.05V IC CTRL(989P)COUGARPOINT QMVY TOP B/S
65mA (10mils)
*1U/6.3V_4 +5V_PCH_VCC5REF R258 10_4 +5V
T17 T21 L45 +1.05V_VCCA_A_DPL C410 1U/6.3V_4
+V1.05M_VCCSUS DCPSUS[1] VCCASW [22] 10uH/100MA_8 D12 RB500V-40
V19 DCPSUS[2] V5REF= 1mA +3V
C419 *220U/2.5V_3528 C381

+
MISC

+1.05V_VTT *0_4/S R564 +VTT_VCCPCPU V21 8mA (10mils) 1U/6.3V_4


VCCASW [23]
10mA (10mils) DV2: Unstuff
CPU

V_PROC_IO=1mA BJ8 L44 +1.05V_VCCA_B_DPL C409 1U/6.3V_4


C622 C624 C620 V_PROC_IO +V3.3A_1.5A_HDA_IO 10uH/100MA_8
(10mils) VCCASW [21] T19
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 C418 *220U/2.5V_3528 +5V_PCH_VCC5REFSUS R282 10_4

+
+5VS5
R256 *0_4 +1.5VSUS
DV2: Unstuff VCC5REFSUS=1mA D13 RB500V-40
RTC

+3V +3VS5
A22 P32 R249 0_4 20mA (10mils) C386
HDA

A
+3V_RTC VCCRTC VCCSUSHDA +3VS5 A
0.1U/10V_4
VCCRTC<1mA R316 *0_6 +3V_SUS_CLKF33 C404 1U/6.3V_4
C348 C347 C346 CougarPoint_Rev_0p7 C369 C368
(10mils) 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 fcbga989-intel-cougarpoint 0.1U/10V_4 *1U/6.3V_4 R318 1/F_4 +3V_SUS_CLKF33_R C411 10U/6.3VS_6
AJ0QNJH0T08 L20
IC CTRL(989P)COUGARPOINT QMVY TOP B/S 10uH/100mA_8

[6,7,19,20,22,25,26,36] +5V
20mA (10mils) PROJECT : QLC
[4,7,33,36] +1.8V [20,26,29,30,31,32,33,34,35,36] +5VS5
+1.05V +VCC_DMI_CCI +1.1V_VCC_DMI_CCI
Quanta Computer Inc.
[2,4,12,13,30,31] +1.5VSUS [2,6,7,8,9,12,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
[2,4,27,32,34,35] +1.05V_VTT [2,6,7,8,9,14,24,27,29,31,33,34,35,36] +3VS5 R622 *1/F_4
[6,7,8,31,33] +1.05V [6,7] +3V_DSW L23 Size Document Number Rev
R317 *0_4/S *10uH/100mA_8 1A
[2,4,25] +1.5V_CPU [6,7,27] +3V_RTC NB5 PCH 5/6 (POWER)
Date: Friday, November 26, 2010 Sheet 10 of 36
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IBEX PEAK-M (GND)


U28I
IBEX PEAK-M (GND)
U28H
11
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26 H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46 AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7 AA2 VSS[2] VSS[81] AK4
D B19 L18 AA3 AK42 D
VSS[165] VSS[265] VSS[3] VSS[82]
B23 VSS[166] VSS[266] L2 AA33 VSS[4] VSS[83] AK46
B27 VSS[167] VSS[267] L20 AA34 VSS[5] VSS[84] AK8
B31 VSS[168] VSS[268] L26 AB11 VSS[6] VSS[85] AL16
B35 VSS[169] VSS[269] L28 AB14 VSS[7] VSS[86] AL17
B39 VSS[170] VSS[270] L36 AB39 VSS[8] VSS[87] AL19
B7 VSS[171] VSS[271] L48 AB4 VSS[9] VSS[88] AL2
F45 VSS[172] VSS[272] M12 AB43 VSS[10] VSS[89] AL21
BB12 VSS[173] VSS[273] P16 AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18 AB7 VSS[12] VSS[91] AL26
BB20 VSS[175] VSS[275] M22 AC19 VSS[13] VSS[92] AL27
BB22 VSS[176] VSS[276] M24 AC2 VSS[14] VSS[93] AL31
BB24 VSS[177] VSS[277] M30 AC21 VSS[15] VSS[94] AL33
BB28 VSS[178] VSS[278] M32 AC24 VSS[16] VSS[95] AL34
BB30 VSS[179] VSS[279] M34 AC33 VSS[17] VSS[96] AL48
BB38 VSS[180] VSS[280] M38 AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4 AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42 AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46 AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8 AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18 AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30 AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47 AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11 AD26 VSS[26] VSS[105] AN2
BC34 VSS[189] VSS[289] P18 AD27 VSS[27] VSS[106] AN29
BC36 VSS[190] VSS[290] T33 AD33 VSS[28] VSS[107] AN3
BC40 VSS[191] VSS[291] P40 AD34 VSS[29] VSS[108] AN31
BC42 VSS[192] VSS[292] P43 AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47 AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7 AD38 VSS[32] VSS[111] AP28
C BD5 R2 AD39 AP30 C
VSS[195] VSS[295] VSS[33] VSS[112]
BE22 VSS[196] VSS[296] R48 AD4 VSS[34] VSS[113] AP32
BE26 VSS[197] VSS[297] T12 AD40 VSS[35] VSS[114] AP38
BE40 VSS[198] VSS[298] T31 AD42 VSS[36] VSS[115] AP4
BF10 VSS[199] VSS[299] T37 AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4 AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W 34 AD46 VSS[39] VSS[118] AP8
BF20 VSS[202] VSS[302] T46 AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47 AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8 AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11 AF10 VSS[43] VSS[122] AT13
BF28 VSS[206] VSS[306] V17 AF12 VSS[44] VSS[123] AT18
BD3 VSS[207] VSS[307] V26 AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27 AD16 VSS[46] VSS[125] AT26
BF38 VSS[209] VSS[309] V29 AF16 VSS[47] VSS[126] AT28
BF40 VSS[210] VSS[310] V31 AF19 VSS[48] VSS[127] AT30
BF8 VSS[211] VSS[311] V36 AF24 VSS[49] VSS[128] AT32
BG17 VSS[212] VSS[312] V39 AF26 VSS[50] VSS[129] AT34
BG21 VSS[213] VSS[313] V43 AF27 VSS[51] VSS[130] AT39
BG33 VSS[214] VSS[314] V7 AF29 VSS[52] VSS[131] AT42
BG44 VSS[215] VSS[315] W 17 AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W 19 AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2 AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W 27 AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W 48 AF46 VSS[57] VSS[136] AV16
BH19 VSS[220] VSS[320] Y12 AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38 AF7 VSS[59] VSS[138] AV24
BH27 VSS[222] VSS[322] Y4 AF8 VSS[60] VSS[139] AV30
BH31 VSS[223] VSS[323] Y42 AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46 AG2 VSS[62] VSS[141] AV4
B BH35 Y8 AG31 AV43 B
VSS[225] VSS[325] VSS[63] VSS[142]
BH39 VSS[226] VSS[328] BG29 AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24 AH11 VSS[65] VSS[144] AW 14
BH7 VSS[228] VSS[330] AJ3 AH3 VSS[66] VSS[145] AW 18
D3 VSS[229] VSS[331] AD47 AH36 VSS[67] VSS[146] AW 2
D12 VSS[230] VSS[333] B43 AH39 VSS[68] VSS[147] AW 22
D16 VSS[231] VSS[334] BE10 AH40 VSS[69] VSS[148] AW 26
D18 VSS[232] VSS[335] BG41 AH42 VSS[70] VSS[149] AW 28
D22 VSS[233] VSS[337] G14 AH46 VSS[71] VSS[150] AW 32
D24 VSS[234] VSS[338] H16 AH7 VSS[72] VSS[151] AW 34
D26 VSS[235] VSS[340] T36 AJ19 VSS[73] VSS[152] AW 36
D30 VSS[236] VSS[342] BG22 AJ21 VSS[74] VSS[153] AW 40
D32 VSS[237] VSS[343] BG24 AJ24 VSS[75] VSS[154] AW 48
D34 VSS[238] VSS[344] C22 AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13 AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14 AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3 AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
G20 BG28 CougarPoint_Rev_0p7
VSS[245] VSS[351]
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
A H30 A
VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]

CougarPoint_Rev_0p7
PROJECT : QLC
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 PCH 6/6 (GND)
Date: Friday, November 26, 2010 Sheet 11 of 36
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[3] M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
95
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ[63:0] [3]
2.48A +1.5VSUS

75
76
81
JDIM1B
VDD1
VDD2
VSS16
VSS17
44
48
49
12
M_A_A4 A3 DQ3 M_A_DQ1 VDD3 VSS18
92 A4 DQ4 4 82 VDD4 VSS19 54
M_A_A5 91 6 M_A_DQ0 87 55
M_A_A6 A5 DQ5 M_A_DQ3 VDD5 VSS20
90 A6 DQ6 16 88 VDD6 VSS21 60
M_A_A7 86 18 M_A_DQ2 93 61
M_A_A8 A7 DQ7 M_A_DQ9 VDD7 VSS22
89 A8 DQ8 21 94 VDD8 VSS23 65
M_A_A9 85 23 M_A_DQ8 99 66
D M_A_A10 A9 DQ9 M_A_DQ15 VDD9 VSS24 D
107 A10/AP DQ10 33 100 VDD10 VSS25 71
M_A_A11 84 35 M_A_DQ10 105 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


83 A12/BC# DQ12 22 106 VDD12 VSS27 127
M_A_A13 119 24 M_A_DQ13 111 128
M_A_A14 A13 DQ13 M_A_DQ14 VDD13 VSS28
80 A14 DQ14 34 112 VDD14 VSS29 133
M_A_A15 78 36 M_A_DQ11 117 134
A15 DQ15 M_A_DQ21 VDD15 VSS30

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 118 VDD16 VSS31 138
109 41 M_A_DQ16 123 139
[3] M_A_BS#0 BA0 DQ17 VDD17 VSS32
108 51 M_A_DQ19 124 144
[3] M_A_BS#1 BA1 DQ18 VDD18 VSS33
79 53 M_A_DQ18 145
[3] M_A_BS#2 BA2 DQ19 VSS34
114 40 M_A_DQ20 199 150
[3] M_A_CS#0 S0# DQ20 +3V VDDSPD VSS35
121 42 M_A_DQ17 151
[3] M_A_CS#1 S1# DQ21 VSS36
101 50 M_A_DQ23 77 155
[3] M_A_CLKP0 CK0 DQ22 NC1 VSS37
103 52 M_A_DQ22 122 156
[3] M_A_CLKN0 CK0# DQ23 NC2 VSS38
102 57 M_A_DQ25 R431 *10K_4 125 161
[3] M_A_CLKP1 CK1 DQ24 M_A_DQ24 +3V NCTEST VSS39
[3] M_A_CLKN1 104 CK1# DQ25 59 VSS40 162
73 67 M_A_DQ30 PM_EXTTS#0 198 167
[3] M_A_CKE0 CKE0 DQ26 [13] PM_EXTTS#0 EVENT# VSS41
74 69 M_A_DQ26 30 168
[3] M_A_CKE1 CKE1 DQ27 [2,13] DDR3_DRAMRST# RESET# VSS42
115 56 M_A_DQ28 172
[3] M_A_CAS# CAS# DQ28 VSS43
110 58 M_A_DQ29 PV: Change to short pad 173
[3] M_A_RAS# RAS# DQ29 M_A_DQ31 SMDDR_VREF_DQ0_M1*0_6/S +SMDDR_VREF_DQ0 VSS44
113 68 R32 1 178
[3] M_A_WE# W E# DQ30 VREF_DQ VSS45
R117 10K_4 DIMM0_SA0 197 70 M_A_DQ27 +SMDDR_VREF_DIMM 126 179
R118 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 SMDDR_VREF_DQ0_M3 R30 *0_6 VREF_CA VSS46
201 SA1 DQ32 129 [5] SMDDR_VREF_DQ0_M3 VSS47 184
SMB_RUN_CLK 202 131 M_A_DQ37 185
[8,13] SMB_RUN_CLK SCL DQ33 VSS48
SMB_RUN_DAT 200 141 M_A_DQ34 2 189
[8,13] SMB_RUN_DAT SDA DQ34 VSS1 VSS49
143 M_A_DQ38 3 190
DQ35 M_A_DQ32 VSS2 VSS50
116 130 7/21: Remove M2 solution 8 195

(204P)
[3] M_A_ODT0 ODT0 DQ36 VSS3 VSS51
120 132 M_A_DQ33 9 196
[3] M_A_ODT1 ODT1 DQ37 VSS4 VSS52
140 M_A_DQ35 13
M_A_DM1 DQ38 M_A_DQ39 VSS5
11 DM0 DQ39 142 14 VSS6
C 28 147 M_A_DQ41 19 C
DM1 DQ40 M_A_DQ45 VSS7
46 149 20

(204P)
DM2 DQ41 M_A_DQ47 VSS8
63 DM3 DQ42 157 25 VSS9
M_A_DM2 136 159 M_A_DQ46 26 203
DM4 DQ43 VSS10 VTT1 +0.75V_DDR_VTT
153 146 M_A_DQ40 31 204
DM5 DQ44 M_A_DQ44 VSS11 VTT2
170 DM6 DQ45 148 32 VSS12
187 158 M_A_DQ42 37 205
DM7 DQ46 M_A_DQ43 VSS13 GND
[3] M_A_DQSP[7:0] DQ47 160 38 VSS14 GND 206
M_A_DQSP0 12 163 M_A_DQ49 43
M_A_DQSP1 DQS0 DQ48 M_A_DQ48 VSS15
29 DQS1 DQ49 165
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ55 DDR3-DIMM0_H=5.2_RVS
64 DQS3 DQ51 177
M_A_DQSP4 137 164 M_A_DQ53 DDR-78279-001-RVS-204P
M_A_DQSP5 DQS4 DQ52 M_A_DQ52 DGMK4000206
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ50 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
M_A_DQSP7 DQS6 DQ54 M_A_DQ51
[3] M_A_DQSN[7:0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ61
M_A_DQSN1 DQS#0 DQ56 M_A_DQ60
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ62
M_A_DQSN3 DQS#2 DQ58 M_A_DQ63
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ56
M_A_DQSN5 DQS#4 DQ60 M_A_DQ57
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ59
M_A_DQSN7 DQS#6 DQ62 M_A_DQ58
186 DQS#7 DQ63 194

DDR3-DIMM0_H=5.2_RVS
DDR-78279-001-RVS-204P
DGMK4000206
IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
B B

VREF DQ0 M2 Solution Place these Caps near So-Dimm0. VREF DQ0 M1 Solution
+1.5VSUS +0.75V_DDR_VTT +1.5VSUS

C99 1U/6.3V_4 C248 1U/6.3V_4 +1.5VSUS

C104 1U/6.3V_4 C251 1U/6.3V_4


R89 R79
C94 1U/6.3V_4 C250 1U/6.3V_4 1K/F_4 10K_4

C71 1U/6.3V_4 C249 1U/6.3V_4 DDR_VTTREF R85 *0_6 SMDDR_VREF_DQ0_M1

C60 10U/6.3VS_6 C247 10U/6.3V_6 R84 *0_6 +SMDDR_VREF_DIMM


[4,13,30] DDR_VTTREF
C69 10U/6.3VS_6 C253 *10U/6.3V_6 R90
1K/F_4
C95 10U/6.3VS_6 R76 C143
+SMDDR_VREF_DIMM 10K_4 470P/50V_4
C67 10U/6.3VS_6
C153 0.1U/10V_4
C116 10U/6.3VS_6
C154 2.2U/10V_6
C101 10U/6.3VS_6

A C65 *10U/6.3V_6 +SMDDR_VREF_DQ0 A


[2,6,7,8,9,10,13,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
[2,6,7,8,9,10,14,24,27,29,31,33,34,35,36] +3VS5
C86 10U/6.3V_8 C34 0.1U/10V_4 [2,4,10,13,30,31] +1.5VSUS
[13,30,36] +0.75V_DDR_VTT
C85 10U/6.3V_8 C36 2.2U/10V_6

1 2 +3V PROJECT : QLC


C586 Quanta Computer Inc.
+

*390U/2.5V_6X5.8ESR10 C243 0.1U/10V_4


4/29: reserve M2 solution Arrandale+VGA
4/27: layout modify C242 2.2U/10V_6 Size Document Number Rev
1A
7/21: Remove M2 solution NB5 DDR3 DIMM0-RVS (5.2H)
Date: Friday, November 26, 2010 Sheet 12 of 36
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[3] M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
98
97
96
JDIM2A
A0
A1
DQ0
DQ1
5
7
15
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ[63:0] [3]
+1.5VSUS

75
76
81
JDIM2B
VDD1
VDD2
VSS16
VSS17
44
48
49
13
M_B_A3 A2 DQ2 M_B_DQ2 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
M_B_A5 A4 DQ4 M_B_DQ1 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 M_B_DQ12
D M_B_A9
89
85
A8 DQ8 21
23 M_B_DQ13
2.48A 99
100
VDD9 VSS24 66
71 D
M_B_A10 A9 DQ9 M_B_DQ14 VDD10 VSS25
107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ10

PC2100 DDR3 SDRAM SO-DIMM


84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ8 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ9 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ11 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ20

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ21 124 144
[3] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
[3] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ22 199 150
[3] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ17 151
[3] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ16 77 155
[3] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ19 122 156
[3] M_B_CLKP0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 R436 10K_4 125 161
[3] M_B_CLKN0 CK0# DQ23 M_B_DQ25 +3V NCTEST VSS39
[3] M_B_CLKP1 102 CK1 DQ24 57 VSS40 162
104 59 M_B_DQ29 PM_EXTTS#0 198 167
[3] M_B_CLKN1 CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ27 30 168
[3] M_B_CKE0 CKE0 DQ26 [2,12] DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ26 PV: Change to short pad 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
[3] M_B_CAS# CAS# DQ28 M_B_DQ24 SMDDR_VREF_DQ1_M1*0_6/S +SMDDR_VREF_DQ1 VSS44
110 58 R50 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ31 126 179
[3] M_B_WE# W E# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R130 10K_4 DIMM1_SA0 197 70 M_B_DQ30 [5] SMDDR_VREF_DQ1_M3 SMDDR_VREF_DQ1_M3 R44 *0_6 184
R131 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ36 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ37 2 189
[8,12] SMB_RUN_CLK SCL DQ33 VSS1 VSS49
M_B_DQ35
[8,12] SMB_RUN_DAT 200 SDA DQ34 141
143 M_B_DQ34
7/21: Remove M2 solution 3
8
VSS2 VSS50 190
195

(204P)
DQ35 M_B_DQ33 VSS3 VSS51
[3] M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
[3] M_B_ODT1 120 132 M_B_DQ32 13
ODT1 DQ37 M_B_DQ39 VSS5
DQ38 140 14 VSS6
C M_B_DM1 11 142 M_B_DQ38 19 C
DM0 DQ39 M_B_DQ44 VSS7
28 DM1 DQ40 147 20 VSS8
46 149 M_B_DQ40 25

(204P)
DM2 DQ41 M_B_DQ42 VSS9
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM2 136 159 M_B_DQ43 31 204
DM4 DQ43 M_B_DQ45 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
170 148 M_B_DQ41 37 205
DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43
[3] M_B_DQSP[7:0] DQ47 VSS15
M_B_DQSP0 12 163 M_B_DQ49
M_B_DQSP1 DQS0 DQ48 M_B_DQ48
29 DQS1 DQ49 165
M_B_DQSP2 47 175 M_B_DQ54 DDR3-DIMM1_H=9.2_RVS
M_B_DQSP3 DQS2 DQ50 M_B_DQ55 DDR-AS0A626-UARN-7F-204P
64 DQS3 DQ51 177
M_B_DQSP4 137 164 M_B_DQ52 DGMK4000207
M_B_DQSP5 DQS4 DQ52 M_B_DQ53 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS)
154 DQS5 DQ53 166
M_B_DQSP6 171 174 M_B_DQ50
M_B_DQSP7 DQS6 DQ54 M_B_DQ51
[3] M_B_DQSN[7:0] 188 DQS7 DQ55 176
M_B_DQSN0 10 181 M_B_DQ61
M_B_DQSN1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQSN2 45 191 M_B_DQ62
M_B_DQSN3 DQS#2 DQ58 M_B_DQ63
62 193
M_B_DQSN4 135
DQS#3 DQ59
180 M_B_DQ57 PV: Unstuff DDR3 Thermal Sensor
M_B_DQSN5 DQS#4 DQ60 M_B_DQ60
152 DQS#5 DQ61 182
M_B_DQSN6 169 192 M_B_DQ59 U19 C503 *0.01U/25V_4
M_B_DQSN7 DQS#6 DQ62 M_B_DQ58
186 DQS#7 DQ63 194
MBCLK2 8 1
[8,17,27] MBCLK2 SCLK VCC +3V
DDR3-DIMM1_H=9.2_RVS MBDATA2 7 2 DDR_THERMDA
[8,17,27] MBDATA2 SDA DXP
DDR-AS0A626-UARN-7F-204P

3
DGMK4000207 PM_EXTTS#0 6 3
B
[12] PM_EXTTS#0 ALERT# DXN B
IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) C510 2 Q38
+3V R430 *10K_4 4 5 *2200P/50V_4 *MMBT3904-7-F
OVERT# GND

1
DDR_THERMDC
*G780P81U

VREF DQ1 M1 Solution


VREF DQ1 M2 Solution Place these Caps near So-Dimm1. +1.5VSUS

+1.5VSUS +0.75V_DDR_VTT +SMDDR_VREF_DIMM


R63
C70 1U/6.3V_4 C223 1U/6.3V_4 C144 0.1U/10V_4 1K/F_4

C72 1U/6.3V_4 C217 1U/6.3V_4 C140 2.2U/10V_6


[4,12,30] DDR_VTTREF R75 *0_6 SMDDR_VREF_DQ1_M1
C100 1U/6.3V_4 C210 1U/6.3V_4

C120 1U/6.3V_4 C231 1U/6.3V_4 +SMDDR_VREF_DQ1 R73


1K/F_4
C97 10U/6.3VS_6 C227 10U/6.3V_6 C27 0.1U/10V_4

C66 10U/6.3VS_6 C204 *10U/6.3V_6 C26 2.2U/10V_6

C68 10U/6.3VS_6

A C83 10U/6.3VS_6 +3V A


[2,6,7,8,9,10,12,14,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
[2,6,7,8,9,10,14,24,27,29,31,33,34,35,36] +3VS5
C82 10U/6.3VS_6 C238 0.1U/10V_4 [2,4,10,12,30,31] +1.5VSUS
[12,30,36] +0.75V_DDR_VTT
C90 10U/6.3VS_6 C241 2.2U/10V_6

C114 *10U/6.3V_6
PROJECT : QLC
4/29 reserve M2 solution C113 10U/6.3V_8 Quanta Computer Inc.
C91 10U/6.3V_8
7/21: Remove M2 solution Size Document Number Rev
1A
NB5 DDR3 DIMM1-RVS (9.2H)
Date: Friday, November 26, 2010 Sheet 13 of 36
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1 2 3 4 5 6 7 8

~C180
500mA AC9
U21A

PBGA533-NVIDIA-GEFORCE6250
N10M

1/13 PCI_EXPRESS
AE9 PEX_CLKREQ# R391 10K/F_4
DV2: Change graphic to N12P-GV-S (AJ0N12P0T11)
14
+1.05V_GFX PEX_IOVDD_01 PEX_CLKREQ +3V_GFX
0.1U/10V_4 AD7 PEX_IOVDD_02 PEX_RST* AD9 VGA_RST# R427 100/F_4 PEGX_RST#
C185 0.1U/10V_4 AD8
C108
C214
1U/6.3V_4
1U/6.3V_4
AE7
AF7
PEX_IOVDD_03
PEX_IOVDD_04
PEX_IOVDD_05 PEX_REFCLK AB10
C515 *0.1U/10V_4
CLK_PCIE_VGA [8]
power up sequence
C103 4.7U/6.3V_6 AG7 AC10
PEX_IOVDD_06 PEX_REFCLK* CLK_PCIE_VGA# [8]
C160 22U/6.3V_8
A A
C206 10U/6.3V_8
PEX_TX0 AD10 C_PEG_RX15 C168 0.1U/10V_4
PEG_RX15 [2]
AB13 PEX_IOVDDQ_01 PEX_TX0* AD11 C_PEG_RX#15 C177 0.1U/10V_4
PEG_RX#15 [2]
AB16 AD12 C_PEG_RX14 C183 0.1U/10V_4
+1.05V_GFX 1600mA
C109 0.1U/10V_4
AB17
AB7
PEX_IOVDDQ_02
PEX_IOVDDQ_03
PEX_TX1
PEX_TX1* AC12 C_PEG_RX#14
AB11 C_PEG_RX13
C189
C159
0.1U/10V_4
0.1U/10V_4
PEG_RX14 [2]
PEG_RX#14 [2]
PEX_IOVDDQ_04 PEX_TX2 PEG_RX13 [2]
C110 0.1U/10V_4 AB8 PEX_IOVDDQ_05 PEX_TX2* AB12 C_PEG_RX#13 C166 0.1U/10V_4
PEG_RX#13 [2]
C111 1U/6.3V_4 AB9 PEX_IOVDDQ_06 PEX_TX3 AD13 C_PEG_RX12 C184 0.1U/10V_4
PEG_RX12 [2]
C112 1U/6.3V_4 AC13 PEX_IOVDDQ_07 PEX_TX3* AD14 C_PEG_RX#12 C193 0.1U/10V_4
PEG_RX#12 [2]
C194 22U/6.3V_8 AC7 PEX_IOVDDQ_08 PEX_TX4 AD15 C_PEG_RX11 C197 0.1U/10V_4
PEG_RX11 [2]
C169 4.7U/6.3V_6 AD6 PEX_IOVDDQ_09 PEX_TX4* AC15 C_PEG_RX#11 C202 0.1U/10V_4
PEG_RX#11 [2]
C102 10U/6.3V_8 AE6 PEX_IOVDDQ_10 PEX_TX5 AB14 C_PEG_RX10 C198 0.1U/10V_4
PEG_RX10 [2]
AF6 PEX_IOVDDQ_11 PEX_TX5* AB15 C_PEG_RX#10 C203 0.1U/10V_4
PEG_RX#10 [2]
AG6 PEX_IOVDDQ_12 PEX_TX6 AC16 C_PEG_RX9 C208 0.1U/10V_4
PEG_RX9 [2]
PEX_TX6* AD16 C_PEG_RX#9 C213 0.1U/10V_4
PEG_RX#9 [2]
PEX_TX7 AD17 C_PEG_RX8 C209 0.1U/10V_4
PEG_RX8 [2]
+VGACORE AD18 C_PEG_RX#8 C215 0.1U/10V_4
PEX_TX7* PEG_RX#8 [2]
AC18 C_PEG_RX7 C220 0.1U/10V_4
PLACE UNDER BALLS
C164 0.01U/25V_4
18.19A J10 PEX_TX8
PEX_TX8* AB18 C_PEG_RX#7
AB19 C_PEG_RX6
C224
C222
0.1U/10V_4
0.1U/10V_4
PEG_RX7 [2]
PEG_RX#7 [2]
VDD_01 PEX_TX9 PEG_RX6 [2]
C163 0.01U/25V_4 J12 VDD_02 PEX_TX9* AB20 C_PEG_RX#6 C225 0.1U/10V_4
PEG_RX#6 [2]
C165 0.01U/25V_4 J13 VDD_03 PEX_TX10 AD19 C_PEG_RX5 C228 0.1U/10V_4
PEG_RX5 [2]
C178 0.01U/25V_4 J9 VDD_04 PEX_TX10* AD20 C_PEG_RX#5 C233 0.1U/10V_4
PEG_RX#5 [2]
C212 0.01U/25V_4 L9 VDD_05 PEX_TX11 AD21 C_PEG_RX4 C230 0.1U/10V_4
PEG_RX4 [2]
C179 0.01U/25V_4 M11 VDD_06 PEX_TX11* AC21 C_PEG_RX#4 C234 0.1U/10V_4
PEG_RX#4 [2]
C186 .047U/25V_4 M17 VDD_07 PEX_TX12 AB21 C_PEG_RX3 C236 0.1U/10V_4
PEG_RX3 [2]
C191 .047U/25V_4 M9 VDD_08 PEX_TX12* AB22 C_PEG_RX#3 C239 0.1U/10V_4
PEG_RX#3 [2]
C162 .047U/25V_4 N11 VDD_09 PEX_TX13 AC22 C_PEG_RX2 C237 0.1U/10V_4
PEG_RX2 [2]
C205 0.1U/10V_4 N12 VDD_10 PEX_TX13* AD22 C_PEG_RX#2 C240 0.1U/10V_4
PEG_RX#2 [2]
C181 4.7U/6.3V_6 N13 VDD_11 PEX_TX14 AD23 C_PEG_RX1 C244 0.1U/10V_4
PEG_RX1 [2]
B C200 4.7U/6.3V_6 N14 VDD_12 PEX_TX14* AD24 C_PEG_RX#1 C246 0.1U/10V_4
PEG_RX#1 [2]
B
C192 4.7U/6.3V_6 N15 VDD_13 PEX_TX15 AE25 C_PEG_RX0 C245 0.1U/10V_4
PEG_RX0 [2]
C199 4.7U/6.3V_6 N16 VDD_14 PEX_TX15* AE26 C_PEG_RX#0 C252 0.1U/10V_4
PEG_RX#0 [2]
C167 4.7U/6.3V_6 N17
C126 10U/6.3V_8 VDD_15
N19 VDD_16
C84 10U/6.3V_8 N9 VDD_17
P11 VDD_18
2 1 P12 VDD_19
+

P13 VDD_20
C81 P14
*330u_2.5V_3528 VDD_21
P15 VDD_22
PLACE NEAR BALLS P16 AE12 PEG_TX15
VDD_23 PEX_RX0 PEG_TX15 [2]
P17 AF12 PEG_TX#15
VDD_24 PEX_RX0* PEG_TX#15 [2]
R11 AG12 PEG_TX14
VDD_25 PEX_RX1 PEG_TX14 [2]
R12 AG13 PEG_TX#14
R13
VDD_26 PEX_RX1*
AF13 PEG_TX13
PEG_TX#14 [2]
PEG_TX13 [2]
PEX_RST timing
VDD_27 PEX_RX2 PEG_TX#13
R14 VDD_28 PEX_RX2* AE13 PEG_TX#13 [2]
R15 AE15 PEG_TX12
VDD_29 PEX_RX3 PEG_TX12 [2]
R16 AF15 PEG_TX#12
VDD_30 PEX_RX3* PEG_TX#12 [2]
R17 AG15 PEG_TX11
VDD_31 PEX_RX4 PEG_TX11 [2]
R9 AG16 PEG_TX#11 I/O 3.3V
VDD_32 PEX_RX4* PEG_TX#11 [2]
T11 AF16 PEG_TX10
VDD_33 PEX_RX5 PEG_TX10 [2]
T17 AE16 PEG_TX#10
VDD_34 PEX_RX5* PEG_TX9 PEG_TX#10 [2] +3V
T9 VDD_35 PEX_RX6 AE18 PEG_TX9 [2] PEX_RST
U19 AF18 PEG_TX#9
VDD_36 PEX_RX6* PEG_TX#9 [2]
U9 AG18 PEG_TX8 C279 0.1U/10V_4
W 10
W 12
VDD_37
VDD_38
VDD_39
PEX_RX7
PEX_RX7*
PEX_RX8
AG19
AF19
PEG_TX#8
PEG_TX7
PEG_TX8 [2]
PEG_TX#8 [2]
PEG_TX7 [2]
For DIS

5
W 13 AE19 PEG_TX#7 Trise >= 1uS Tfail <=500nS
VDD_40 PEX_RX8* PEG_TX#7 [2]
W 18 AE21 PEG_TX6 [2,8,24,25,27] PLTRST# 2
C VDD_41 PEX_RX9 PEG_TX6 [2] C
W 19 AF21 PEG_TX#6 4 PEGX_RST#
VDD_42 PEX_RX9* PEG_TX#6 [2]
W9 AG21 PEG_TX5 1
VDD_43 PEX_RX10 PEG_TX5 [2] [9,27] DGPU_HOLD_RST#
AG22 PEG_TX#5
PEX_RX10* PEG_TX#5 [2]
GPU_VDD_SENSE W 15 AF22 PEG_TX4 U4 R133
PEG_TX4 [2]

3
[31] GPU_VDD_SENSE VDD_SENSE PEX_RX11 PEG_TX#4 MC74VHC1G08DFT2G
W 16 GND_SENSE PEX_RX11* AE22 PEG_TX#4 [2]
E15 AE24 PEG_TX3 100K/F_4
VDD_SENSE PEX_RX12 PEG_TX3 [2]
E14 AF24 PEG_TX#3
GND_SENSE PEX_RX12* PEG_TX#3 [2]
AG24 PEG_TX2
+3V_GFX 120mA
C174 4.7U/6.3V_6
A12 VDD33_01
PEX_RX13
PEX_RX13* AF25 PEG_TX#2
PEG_TX1
PEG_TX2 [2]
PEG_TX#2 [2]
B12 VDD33_02 PEX_RX14 AG25 PEG_TX1 [2]
+1.05V_GFX C170 1U/6.3V_4 C12 AG26 PEG_TX#1
VDD33_03 PEX_RX14* PEG_TX#1 [2]
C171 0.1U/10V_4 D12 AF27 PEG_TX0
VDD33_04 PEX_RX15 PEG_TX0 [2]
C172 0.1U/10V_4 E12 AE27 PEG_TX#0
VDD33_05 PEX_RX15* PEG_TX#0 [2]
C521 0.1U/10V_4 F12
L10 VDD33_06
BLM18PG181SN1 180/1500mA
C525 0.1U/10V_4
C524 1U/6.3V_4
+PEX_PLLVDD 120mA AF9 PEX_PLLVDD
C130 4.7U/6.3V_6 12~16
R452
mils
*200_4 AE10 PEX_TSTCLK_OUT*
+3V_GFX L34 AF10
*BLM18PG181SN1 180/1500mA PEX_TSTCLK_OUT +3VS5
C529 0.01U/25V_4 +PEX_SVDD_3V3 AG9
C520 0.1U/10V_4
AG10
PEG_SVDD

PEX_TERMP
For DIS R470
+1.05V_GFX 10K/F_4
L35 R451 +3V_GFX
BLM18PG181SN1 180/1500mA +3V_GFX
[2,6,7,8,9,10,24,27,29,31,33,34,35,36] +3VS5
D +1.05V for N12M-GE/NS GPU R484 [16,17,19,31] +3V_GFX D
PCIE_CLKREQ_VGA# [8]
2.49K/F_4 10K/F_4 R482 [15,16,31] +1.05V_GFX

3
*10K/F_4 [31] +VGACORE
[2,6,7,8,9,10,12,13,16,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
[9,16,27] DGPU_PWROK R485 CLKREQ_C1 2 Q44
0_4 3 DTC144EUA
PROJECT : QLC

1
PEX_CLKREQ# 2 Q45
*DTC144EUA
Quanta Computer Inc.
Size Document Number Rev
1

Custom ?
NB5 N11M-GE2(PCIEI/F)
Date: Friday, November 26, 2010 Sheet 14 of 36
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C196
2.16A
.047U/25V_4
+1.5V_GFX

A13
U21B

PBGA533-NVIDIA-GEFORCE6250
N10M

2/13 FRAME_BUFFER
[18] VMA_DQ[63..0]
[18] VMA_DM[7..0]
[18] VMA_WDQS[7..0]
[18] VMA_RDQS[7..0]

U21I
15
C201 .047U/25V_4 FBVDDQ_01 VMA_DQ0
B13 FBVDDQ_02 FBA_D0 D22
N10M
C207 .047U/25V_4 C13 E24 VMA_DQ1 PBGA533-NVIDIA-GEFORCE6250
C211 0.01U/25V_4 FBVDDQ_03 FBA_D1 VMA_DQ2
D13 FBVDDQ_04 FBA_D2 E22 13/13 GND_NC
C187 0.01U/25V_4 D14 D24 VMA_DQ3 C15
C188 0.01U/25V_4 FBVDDQ_05 FBA_D3 VMA_DQ4 NC_01
E13 FBVDDQ_06 FBA_D4 D26 AC11 GND_01 NC_02 D15
C190 4.7U/6.3V_6 F13 D27 VMA_DQ5 AC14 J5 R408 10K/F_4
A
C221 4.7U/6.3V_6 FBVDDQ_07 FBA_D5 VMA_DQ6 GND_02 (NC_03)PGOOD A
F14 FBVDDQ_08 FBA_D6 C27 AC17 GND_03
F15 B27 VMA_DQ7 AC2 nVIDIA comment 8/18
FBVDDQ_09 FBA_D7 VMA_DQ8 GND_04
F16 FBVDDQ_10 FBA_D8 A21 AC20 GND_05
F17 B21 VMA_DQ9 AC23
FBVDDQ_11 FBA_D9 VMA_DQ10 GND_06
F19 FBVDDQ_12 FBA_D10 C21 AC26 GND_07
F22 C19 VMA_DQ11 AC5
FBVDDQ_13 FBA_D11 VMA_DQ12 GND_08
H23 FBVDDQ_14 FBA_D14 C18 AC8 GND_09
H26 D18 VMA_DQ13 AF11
FBVDDQ_15 FBA_D14 VMA_DQ14 GND_10
J15 FBVDDQ_16 FBA_D14 B18 AF14 GND_11
J16 C16 VMA_DQ15 AF17
FBVDDQ_17 FBA_D15 VMA_DQ16 GND_12
J18 FBVDDQ_18 FBA_D16 E21 AF2 GND_13
J19 F21 VMA_DQ17 AF20
FBVDDQ_19 FBA_D17 VMA_DQ18 GND_14
L19 FBVDDQ_20 FBA_D18 D20 AF23 GND_15
L23 F20 VMA_DQ19 AF26
FBVDDQ_21 FBA_D19 VMA_DQ20 GND_16
L26 FBVDDQ_22 FBA_D20 D17 AF5 GND_17
M19 F18 VMA_DQ21 AF8
FBVDDQ_23 FBA_D21 VMA_DQ22 GND_18
N22 FBVDDQ_24 FBA_D22 D16 B11 GND_19
U22 E16 VMA_DQ23 FBA_CMD0 R505 10K/F_4 B14
FBVDDQ_25 FBA_D23 VMA_DQ24 GND_20
Y22 FBVDDQ_26 FBA_D24 A22
C24 VMA_DQ25 FBA_CMD3 R506 10K/F_4 B17
FBA_D25 VMA_DQ26 GND_21
FBA_D26 D21 B2 GND_22
B22 VMA_DQ27 FBA_CMD16 R503 10K/F_4 B20
FBA_D27 VMA_DQ28 GND_23
[18] FBA_CMD0 G24 (FBA_CMD25)FBA_CMD0 FBA_D28 C22 B23 GND_24
TP51 FBA_CMD1 F27 A25 VMA_DQ29 FBA_CMD19 R504 10K/F_4 B26
(FBA_CMD23)FBA_CMD1 FBA_D29 VMA_DQ30 GND_25
[18] FBA_CMD2 F25 FBA_CMD2 FBA_D30 B25 B5 GND_26
[18] FBA_CMD3 F26 A26 VMA_DQ31 FBA_CMD20 R507 10K/F_4 B8
(FBA_CMD0)FBA_CMD3 FBA_D31 VMA_DQ32 GND_27
[18] FBA_CMD4 G26 (FBA_CMD10)FBA_CMD4 FBA_D32 U24 E11 GND_28
[18] FBA_CMD5 G27 V24 VMA_DQ33
(FBA_CMD26)FBA_CMD5 FBA_D33 VMA_DQ34
[18] FBA_CMD6 G25 (FBA_CMD14)FBA_CMD6 FBA_D35 V23 E17 GND_30
B J25 R24 VMA_DQ35 E2 B
[18] FBA_CMD7 FBA_CMD7 FBA_D35 GND_31
[18] FBA_CMD8 J24 T23 VMA_DQ36 E20
(FBA_CMD1)FBA_CMD8 FBA_D36 VMA_DQ37 GND_32
[18] FBA_CMD9 H24 (FBA_CMD22)FBA_CMD9 FBA_D37 R23 E23 GND_33
H22 P24 VMA_DQ38 E26
[18] FBA_CMD10 (FBA_CMD20)FBA_CMD10 FBA_D38 GND_34
J26 P22 VMA_DQ39 E5
[18] FBA_CMD11 (FBA_CMD24)FBA_CMD11 FBA_D39 GND_35
G22 AC24 VMA_DQ40 E8
[18] FBA_CMD12 (FBA_CMD18)FBA_CMD12 FBA_D40 GND_36
[18] FBA_CMD13 G23 AB23 VMA_DQ41 H2
(FBA_CMD9)FBA_CMD13 FBA_D41 VMA_DQ42 GND_37
[18] FBA_CMD14 J22 (FBA_CMD29)FBA_CMD14 FBA_D42 AB24 H5 GND_38
J27 W 24 VMA_DQ43 J11
[18] FBA_CMD15 (FBA_CMD8)FBA_CMD15 FBA_D43 GND_39
[18] FBA_CMD16 M24 AA22 VMA_DQ44 J14
TP7 FBA_CMD17 (FBA_CMD27)FBA_CMD16 FBA_D44 VMA_DQ45 GND_40
L24 (FBA_CMD15)FBA_CMD17 FBA_D45 W 23
J23 W 22 VMA_DQ46 J17
[18] FBA_CMD18 (FBA_CMD11)FBA_CMD18 FBA_D46 GND_41
K23 V22 VMA_DQ47 K19
[18] FBA_CMD19 (FBA_CMD16)FBA_CMD19 FBA_D47 GND_42
[18] FBA_CMD20 K22 AA25 VMA_DQ48 K9
(FBA_CMD28)FBA_CMD20 FBA_D48 VMA_DQ49 GND_43
[18] FBA_CMD21 M23 (FBA_CMD3)FBA_CMD21 FBA_D49 W 27 L11 GND_44
K24 W 26 VMA_DQ50 L12
[18] FBA_CMD22 (FBA_CMD17)FBA_CMD22 FBA_D50 GND_45
[18] FBA_CMD23 M27 W 25 VMA_DQ51 L13
(FBA_CMD5)FBA_CMD23 FBA_D51 VMA_DQ52 GND_46
[18] FBA_CMD24 N27 (FBA_CMD4)FBA_CMD24 FBA_D52 AB25 L14 GND_47
[18] FBA_CMD25 M26 AB26 VMA_DQ53 L15
(FBA_CMD21)FBA_CMD25 FBA_D53 VMA_DQ54 GND_48
[18] FBA_CMD26 K26 (FBA_CMD6)FBA_CMD26 FBA_D54 AD26 L16 GND_49
K27 AD27 VMA_DQ55 L17
[18] FBA_CMD27 (FBA_CMD13)FBA_CMD27 FBA_D55 GND_50
[18] FBA_CMD28 K25 V25 VMA_DQ56 L2
(FBA_CMD19)FBA_CMD28 FBA_D56 VMA_DQ57 GND_51
[18] FBA_CMD29 M25 (FBA_CMD12)FBA_CMD29 FBA_D57 R25 L5 GND_52
L22 V26 VMA_DQ58 M12
[18] FBA_CMD30 FBA_CMD30 FBA_D58 GND_53
V27 VMA_DQ59 M13
FBA_D59 VMA_DQ60 GND_54
FBA_D60 R26 M14 GND_55
T25 VMA_DQ61 M15
FBA_D61 VMA_DQ62 GND_56
FBA_D62 N25 M16 GND_57
VMA_CLK0 F24 N26 VMA_DQ63 P19
[18] VMA_CLK0 FBA_CLK0 FBA_D63 GND_58
VMA_CLK0# F23 P2
C [18] VMA_CLK0# FBA_CLK0* GND_59 C
VMA_CLK1 N24 P23
[18] VMA_CLK1 FBA_CLK1 GND_60
VMA_CLK1# N23 C26 VMA_DM0
[18] VMA_CLK1# FBA_CLK1* FBA_DQM0
B19 VMA_DM1 P26
FBA_DQM1 VMA_DM2 GND_61
FBA_DQM2 D19 P5 GND_62
D23 VMA_DM3 P9
FBA_DQM3 VMA_DM4 GND_63
FBA_DQM4 T24 T12 GND_64
R461 40.2/F_4 FB_CAL_PD_VDDQ B15 AA23 VMA_DM5 T13
+1.5V_GFX FB_CAL_PD_VDDQ FBA_DQM5 GND_65
AB27 VMA_DM6 T14
R463 40.2/F_4 FB_CAL_PU_GND FBA_DQM6 VMA_DM7 GND_66
A15 FB_CAL_PU_GND FBA_DQM7 T26 T15 GND_67
T16 GND_68
R105 60.4/F_4 FB_CAL_TERM_GND B16 U11
FB_CAL_TERM_GND VMA_WDQS0 GND_69
FBA_DQS_W P0 C25 U12 GND_70
A19 VMA_WDQS1 U13
R113 10K/F_4 FBA_DEBUG FBA_DQS_W P1 VMA_WDQS2 GND_71
+1.5V_GFX M22 (FBA_DEBUG)FBA_DEBUG0 FBA_DQS_W P2 E19 U14 GND_72
VMA_WDQS3
10mA FBA_DQS_W P3 A24
VMA_WDQS4
U15 GND_73
For debug only FBA_DQS_W P4 T22
VMA_WDQS5
U16 GND_74
FBA_DQS_W P5 AA24 U17 GND_75
AA26 VMA_WDQS6 U2
+1.05V_GFX FBA_DQS_W P5 VMA_WDQS7 GND_76
15mils width 200mA FBA_DQS_W P7 T27 U23 GND_77
U26 GND_78
L15 PBY160808T-301Y-N_6 +FB_PLLAVDD R19 U5
FB_PLLAVDD VMA_RDQS0 GND_79
FBA_DQS_RN0 D25 V19 GND_80
300 ohm/100MHz C216 4.7U/6.3V_6 T19 A18 VMA_RDQS1
C219 1U/6.3V_4 FB_DLLAVDD FBA_DQS_RN1 VMA_RDQS2
ESR=0.25ohm FBA_DQS_RN2 E18 V9 GND_81
C218 0.1U/10V_4 AC19 B24 VMA_RDQS3 W 11
C195 10U/6.3V_8 FB_PLLAVDD FBA_DQS_RN3 VMA_RDQS4 GND_82
FBA_DQS_RN4 R22 W 14 GND_83
Y24 VMA_RDQS5 W 17
FBA_DQS_RN5 VMA_RDQS6 GND_84
FBA_DQS_RN6 AA27 Y2 GND_85
R27 VMA_RDQS7 Y23
FBA_DQS_RN7 GND_86
D Y26 GND_87
D
Y5 GND_88
A16 +FB_VREF1
FB_VREF TP4

PROJECT : QLC
Quanta Computer Inc.
[14,16,31] +1.05V_GFX Size Document Number Rev
Custom ?
[16,18,31] +1.5V_GFX NB5 N11M-GE2(MEMORY/GND)
Date: Friday, November 26, 2010 Sheet 15 of 36
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16
U21F

PBGA533-NVIDIA-GEFORCE6250
N10M
U21D
Optimus:
6/13 IFPAB V4 PBGA533-NVIDIA-GEFORCE6250
All unstuff , one Cap stuff 10K ohm IFPA_TXD0*
V5
N10M
IFPA_TXD0
5/13 DACC
+DACB_VDD W 5 U6
DACB_VDD DACB_HSYNC
R61 IFPA_TXD1* AA4 DACB_VSYNC U4
IFPA_TXD1 AA5 T16 R6 DACB_VREF
+IFPAB_PLLVDD
AD5 IFPAB_PLLVDD R59
AB6 IFPAB_RSET A T15 V6 DACB_RSET
10K/F_4 IFPA_TXD2* Y4 DACB_RED T5
W4 10K/F_4 T4
A IFPA_TXD2 DACB_GREEN A
DACB_BLUE R4

R60 *1K/F_4 AB5


IFPA_TXD3*
IFPA_TXD3 AB4
U21G U21E
N10M N10M
DATA PBGA533-NVIDIA-GEFORCE6250

Optimus: V1 PBGA533-NVIDIA-GEFORCE6250
IFPB_TXD4* 8/13 IFPE 8/13 IFPE
W1
All unstuff , one Cap stuff 10K ohm IFPB_TXD4 DVI DP DVI DP
+IFPD_PLLVDD N6 IFPE_PLLVDD D7
IFPD_PLLVDD IFPE_PLLVDD(DACB_VDD)
IFPB_TXD5* W2 T5 M6 IFPD_RSET T14 F8 IFPD_RSET(DACB_RSET) IFPE_AUX* G6 T17
W3 R432 F7
IFPB_TXD5 R56 IFPE_AUX
R58
B D4 10K/F_4
+IFPAB_IOVDD 10K/F_4 IFPD_AUX*
V3 IFPA_IOVDD IFPB_TXD6* AA3 IFPD_AUX D3
IFPB_TXD6 AA2
10K/F_4
V2 IFPB_IOVDD
IFPD_L3* B4 IFPE_L3* E7
TXC TXC
IFPB_TXD7* AA1 D TXC IFPD_L3 B3 E IFPE_L3 E6
AB1 TXC
IFPB_TXD7
IFPD_L2* C4 IFPE_L2* B7
TXD0 TXD0
TXD0 IFPD_L2 C3 IFPE_L2 B6
AD4 TXD0
IFPA_TXC*
A IFPA_TXC AC4 TXD1 IFPD_L1* D5 IFPE_L1* A7
CLOCK +IFPDE_IOVDD H6 E4 TXD1 A6
IFPDE_IOVDD TXD1 IFPD_L1 IFPE_L1
TXD1

IFPB_TXC* AB2 TXD2 IFPD_L0* F4 IFPE_L0* C6


B AB3 R54 F5 TXD2 D6
IFPB_TXC TXD2 IFPD_L0 TXD2 IFPE_L0
B 10K/F_4 B
U21H
N10M
PBGA533-NVIDIA-GEFORCE6250
7/13 IFPC
R57 DVI DP
+IFPC_PLLVDD P6 IFPC_PLLVDD
R5 IFPC_RSET
10K/F_4
Optimus: U21C
G5
IFPC_AUX*
G4
All unstuff , one Cap stuff 10K ohm
IFPC_AUX N10M
PBGA533-NVIDIA-GEFORCE6250

IFPC_L3* J4 3/13 DACA


R397 *1K/F_4 TXC H4 R395 10K/F_4 +DACA_VDD AG2 AD2
TXC IFPC_L3 DACA_VDD DACA_HSYNC
C DACA_VSYNC AD1
K4 C502 *0.1U/10V_4 DACA_VREF AF1
TXD0 IFPC_L2* DACA_VREF
nVIDIA comment 8/18 TXD0 IFPC_L2 L4
R396 *124/F_4 DACA_RSET AE1 DACA_RSET
+IFPC_IOVDD
TXD1 IFPC_L1* M4 nVIDIA comment 8/18 DACA_RED AE2
J6 IFPC_IOVDD TXD1 IFPC_L1 M5 DACA_GREEN AE3
R55 10K/F_4 AD3
DACA_BLUE
IFPC_L0* N4
TXD2
TXD2 IFPC_L0 P4
+3V_GFX
DV2:unstuff
BLM18PG181SN1 180/1500mA65mA
+1.05V_GFX +NV_PLLVDD
C +3V C
L7 R37
50mA C62 10U/6.3V_8 U21J
N10M
C63 0.1U/10V_4 PBGA533-NVIDIA-GEFORCE6250
C58 0.1U/10V_4 12/13 XTAL_PLL *4.7K_4
C106 0.1U/10V_4 4.7K_4 R39
DGPU_PWROK [9,14,27]
C107 0.1U/10V_4 K5 PLLVDD

3
K6 Q10 R38
BLM18PG181SN1 180/1500mA VID_PLLVDD
+1.05V_GFX
45mA+SP_PLLVDD L6 DGPU_PGOK-1 2
100K/F_4

L8 SP_PLLVDD

3
PV: nVidia suggest R40 DTC144EUA

1
4.7K_4 DGPU_POK4 2 Q11 C55
+1.05V_GFX
R458 10K/F_4 XTAL_SSIN D11
XTAL_SSIN
E9 BXTALOUT MMBT3904-7-F 1000P/50V_4

1
XTAL_OUTBUFF
DV2: Removed 27MHz C56
C73 22U/6.3VS_8 XTALIN D10 E10XTALOUT *1000P/50V_4
C75 0.1U/10V_4 XTAL_IN XTAL_OUT
C74 0.1U/10V_4 R82

3
C77 0.1U/10V_4 Y2 27MHZ 10K/F_4 R41
C76 0.1U/10V_4 2 1 4.7K_4 DGPU_POK2 2
+1.5V_GFX
C141 27P/50V_4 C132 27P/50V_4
Q12

1
C57 MMBT3904-7-F
*1000P/50V_4

D
DV2: Change to 27pF D

PROJECT : QLC
Quanta Computer Inc.
[2,6,7,8,9,10,12,13,14,19,20,21,22,23,24,25,26,27,31,32,35,36] +3V
[14,17,19,31] +3V_GFX Size Document Number Rev
Custom ?
[14,15,31] +1.05V_GFX NB5 N11M-GE2(DISPLAY)
Date: Friday, November 26, 2010 Sheet 16 of 36
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4.99K/F_4: CS24992FB26 [RES CHIP 4.99K 1/16W +1%(0402)]

STRAP0 C7
STRAP1 B9
U21K
N10M
PBGA533-NVIDIA-GEFORCE6250
11/13 MISC

STRAP0
ROM_CS* B10

A10 ROM_SI
N12P-GV -> 0x17F
N12M-GE -> 0xA7A 1010 ->PU15K
10K/F_4: CS31002FB26 [RES CHIP 10K 1/16W +1% (0402)]
15K/F_4: CS31502FB24 [RES CHIP 15K 1/16W +1% (0402)]
30.1K/F_4: CS33012FB18 [RES CHIP 30.1K 1/16W +-1%(0402)]
35.7K/F_4: CS33572FB13 [RES CHIP 35.7K 1/16W +-1%(0402)]
45.3K/F_4: CS34532FB18 [RES CHIP 45.3K 1/16W +-1% (0402)]
PCI_DEVID[4]/SUBVENDOR
17
STRAP2 A9 STRAP1 ROM_SI
C10 ROM_SO Logical Strap Bit Mapping
STRAP2 ROM_SO ROM_SCLK +3V_GFX +3V_GFX
ROM_SCLK C9 ROM_SI -> based on VRAM. PU-VDD PD PV: Change as nVidia setting

A3 HDCP_SCL R418 2.2K_4 ROM_SO -> PU 10K


R91 40.2K/F_4 STRAP_REF_3V3 F11 (I2CH_SCL)GPIO20
A4 HDCP_SDA R421 2.2K_4
+3V_GFX 5K 1000 0000 R450 R456 R447 R435 R441 R444
A STRAP_REF_3V3
(I2CH_SDA)GPIO21 A
R86 40.2K/F_4 STRAP_REF_MIOBF10 ROM_SCLK -> PU 10K 10K 1001 0001 *5.7K/F_4
STRAP_REF_MIOB
15K 1010 0010 *4.99K/F_4 10K/F_4 10K/F_4 45.3K/F_4 *45.3K/F_4
N5 STRAP0 -> PU 45K ROM_SI STRAP0
BUFRST* T13 20K 1011 0011 ROM_SO STRAP1
R635 *10K/F_4 F9 ROM_SCLK STRAP2
+3V_GFX
4.99K/F_4 R464 STRAP3(SPDIF) STRAP1 -> PD 35K 25K 1100 0100
PV: nVidia suggest F6 R449 R455 R446 R434 R440 R443
nVIDIA comment 10/15
GND0
STRAP2 -> PD 5K
30K 1101 0101
TESTMODE AD25 TESTMODE 35K 1110 0110 (Ra) 15K/F_4 *10K/F_4 *10K/F_4
*10K/F_4

35.7K_4
4.99K/F_4

STRAP3 -> PD 15K 45K 1111 0111 PV: Change as nVidia setting
+3V_GFX R403 *10K/F_4 N2
R402 10K/F_4 STRAP4(CEC) R140
GND1 AC6 Default: Hynix VRAM
10K/F_4 STRAP 4 -> PD 10K.
nVIDIA comment 8/18
Logical Logical Logical Logical
PV: Change as nVidia setting Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
DV2: Reserve as vendor comment XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SO
ROM_SCLK PCI_DEVIDE[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
PBGA533-NVIDIA-GEFORCE6250
U21L
N10M +3V_GFX PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP2
9/13 I2C_GPIO_THERM_JTAG
R1 R399 33_4 GPU_DDCCLK 4.7K/F_4 R388 STRAP1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
I2CA_SCL R398 33_4GPU_DDCDATA 4.7K/F_4 R387
B
I2CA_SDA T3 B
STRAP0 USER[3] USER[2] USER[1] USER[0]
I2CB_SCL R2 I2CB_SCL_G R400 2.2K_4 +3V_GFX
T18 D8 THERMDN I2CB_SDA R3 I2CB_SDA_G STRAP3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
R401 2.2K_4
T19 D9 A2 I2CC_SCL_G R419 33_4 R420 2.2K_4 +3V_GFX STRAP4 RESERVED RESERVED PCIE_MAX_SPEED DP_PLL_VDD33V
THERMDP I2CC_SCL I2CC_SDA_G R414 33_4 R415 2.2K_4
I2CC_SDA B1
JTAG_TCK AF3 VRAM Configuration Table
JTAG_TMS JTAG_TCK
AF4 JTAG_TMS
JTAG_TDI AG4 RAMCFG
T11 JTAG_TDO
JTAG_TRST#
AE4
AG3
JTAG_TDI
JTAG_TDO
JTAG_TRST*
[3:0]
0000
DESCRIPTION Vendor
Reserved
Vendor P/N ROM_SI
(Ra)
N1 DGPU_PIN_N1 T8 0010 DDR3 64Mx16x8, 128bit, 1GB,800MHz Hynix PD 15K
GPIO0 TMDS_HPD
GPIO1 G1 T3 0011 DDR3 64Mx16x8, 128bit, 1GB,800MHz Samsung PD 20K
C1 DPST_PWM_DGPU R53 0_4 GPU_DPST_PWM T1 0110 DDR3 128Mx16x4, 128bit, 1GB,800MHz Hynix PD 35K
GPIO2 DISP_ON_DGPU R406 0_4 GPU_DISP_ON
GPIO3 M2 T27 0111 DDR3 128Mx16x4, 128bit, 1GB,800MHz Samsung PD 45K
DGPU_I2CS_SCL T1 M3 LVDS_BLON_DGPU R404 0_4 GPU_LVDS_BLON T26 XXXX
DGPU_I2CS_SDA I2CS_SCL GPIO4
T2 I2CS_SDA GPIO5 K3 GFX_CORE_CNTRL0 [31] XXXX
GPIO6 K2 GFX_CORE_CNTRL1 [31]
J2 DGPU_PIN_J2
GPIO7 T4
R47 40.2K/F_4 T6 C2 VGA_OVT#

nVIDIA comment 8/18


W6
Y6
AA6
MULTI_STRAP_REF2_GND
DBG_DATA1
DDBG_DATA2
GPIO8
GPIO9
GPIO10
M1
D2
D1
ALERT

GFX_GPIO11
T6
VGA_OVT# [27] +3V_GFX
GPIO ASSIGNMENTS
DBG_DATA3 GPIO11 R45 10K/F_4 JTAG_TMS R392 *10K/F_4
N3 DBG_DATA4 GPIO12 J3 +3V_GFX
GPIO13 J1
K1 GFX_GPIO14
T9
JTAG_TDI R393 *10K/F_4
GPIO I/O ACTIVE USAGE
C GPIO14 DVI_DET C
GPIO15 F3
VGA_OVT# R413 10K/F_4
GPIO16 G3
G2
T10 0 N/A N/A
GPIO17 T12
DGPU_IDLE# ALERT R405 10K/F_4
GPIO18 F1
F2 R52 10K/F_4
+3V_GFX 1 IN N/A Hot plug detect for IFP link C
GPIO19 T7
JTAG_TRST# R394 1K/F_4
2 OUT HIGH PANEL BACKLIGHT PWM
GFX_GPIO11 R411 *10K/F_4
GFX_GPIO14 R407 *10K/F_4
3 OUT HIGH PANEL POWER ENABLE
DVI_DET R410 *10K/F_4
JTAG_TCK R48 10K/F_4
4 OUT HIGH PANEL BACKLIGHT ENABLE
R429 *0_4 DPST_PWM_DGPU R412 *10K/F_4
GPU_DISP_ON R389 *10K/F_4
5 OUT N/A NVVDD VID0
GPU_LVDS_BLON R385 *10K/F_4
DGPU_I2CS_SCL 1 3
6 OUT N/A NVVDD VID1
MBCLK2 [8,13,27]
2N7002E
7 OUT N/A NVVDD VID2
R425 Q39 DGPU_IDLE# 1 3 DGPU_IDLE_INT# [8] 8 I/O LOW OVERT
2

2.2K_4
Q14
*2N7002E
9 I/O LOW ALERT
2

+3V_GFX 10 OUT N/A Memory VREF SELECT