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Abstract—This paper presents a single-phase transformerless international regulations pose strict limits to its magnitude. This
grid-connected photovoltaic converter based on two cascaded full issue must be confronted in all transformerless PV converters,
bridges with different dc-link voltages. The converter can syn- regardless of architecture. In particular, in full-bridge-based
thesize up to nine voltage levels with a single dc bus, since one
of the full bridges is supplied by a flying capacitor. The mul- topologies, the ground leakage current is mainly due to high-
tilevel output reduces harmonic distortion and electromagnetic frequency variations of the common-mode voltage at the output
interference. A suitable switching strategy is employed to regulate of the power converter [4]. Several solutions can be found in
the flying-capacitor voltage, improve the efficiency (most devices literature aiming at the reduction of the common-mode voltage
switch at the grid frequency), and minimize the common-mode harmonic content [5]–[7]. Once the grid frequency transformer
leakage current with the help of a novel dedicated circuit (tran-
sient circuit). Simulations and experiments confirm the feasibility is removed from a PV converter, the bulkiest wound and re-
and good performance of the proposed converter. active components that remain are those that form the output
filter used to clean the output voltage and current from high-
Index Terms—Leakage current, multilevel systems, photo-
voltaic (PV) systems, pulsewidth modulation (PWM) inverters. frequency switching components. Further reduction in cost
and weight and improvement in efficiency can be achieved
by reducing the filter size, and this is the goal of multilevel
I. I NTRODUCTION converters.
Multilevel converters have been investigated for years [8],
G RID-CONNECTED photovoltaic (PV) converters repre-
sent the most widespread solution for residential renew-
able energy generation. While classical designs of PV converters
but only recently have the results of such researches found their
way to commercial PV converters. Since they can synthesize
feature a grid frequency transformer, which is a typically heavy the output voltages using more levels, multilevel converters out-
and costly component, at the interface between the converter perform conventional two- and three-level converters in terms
and the electrical grid, researchers are now considering trans- of harmonic distortion. Moreover, multilevel converters subdi-
formerless architectures in order to reduce costs and weight and vide the input voltage among several power devices, allowing
improve efficiency. Removing the grid frequency transformer for the use of more efficient devices. Multilevel converters were
entails all the benefits above but worsens the output power qual- initially employed in high-voltage industrial and powertrain
ity, allowing the injection of dc current into the grid [1], [2] and applications. They were first introduced in renewable energy
giving rise to the problem of ground leakage current [3], [4]. converters inside utility-scale plants, in which they are still
Although the active parts of PV modules might be electri- largely employed [9]–[13]. Recently, they have found their
cally insulated from the ground-connected mounting frame, a way to residential-scale single-phase PV converters, where they
path for ac ground leakage currents generally exists due to a currently represent a hot research topic [14]–[29]. Single-phase
parasitic capacitance between the modules and the frame and multilevel converters can be roughly divided into three cate-
to the connection between the neutral wire and the ground, gories based on design: neutral point clamped (NPC), cascaded
usually realized at the low-voltage/medium-voltage (LV/MV) full bridge (CFB), and custom.
transformer [3]. In addition to deteriorating power quality, the In NPC topologies, the electrical potential between the PV
ground leakage current increases the generation of electromag- cells and the ground is fixed by connecting the neutral wire of
netic interference and can represent a safety hazard, so that the grid to a constant potential, resulting from a dc-link capac-
itive divider [15]. A huge advantage is that single-phase NPC
converters are virtually immune from ground leakage currents,
Manuscript received March 4, 2013; revised June 13, 2013 and August 1, although the same is not true for three-phase NPC converters
2013; accepted September 16, 2013. Date of publication October 21, 2013; [12], [30]. A recent paper has proposed an interesting NPC
date of current version February 7, 2014.
G. Buticchi, D. Barater, C. Concari, and G. Franceschini are with the De- design for exploiting next-generation devices such as super
partment of Information Engineering, University of Parma, 43124 Parma, Italy junction or SiC MOSFETs [16]. The main drawback of NPC
(e-mail: giampaolo.buticchi@unipr.it; davide.barater@nemo.unipr.it; carlo. designs, with respect to full bridge, is that they need twice the
concari@unipr.it; giovanni.franceschini@unipr.it).
E. Lorenzani is with the Department of Science and Methods for Engineer- dc-link voltage.
ing, University of Modena and Reggio Emilia, Modena, Italy (e-mail: emilio. CFBs make for highly modular designs. Usually, each full
lorenzani@unimore.it). bridge inside a CFB converter needs an insulated power supply,
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. matching well with multistring PV fields [17]. In this case,
Digital Object Identifier 10.1109/TIE.2013.2286562 sequential permutation of the full bridges can be used to evenly
0278-0046 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
3952 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014
TABLE I
D ESCRIPTION OF THE C ONVERTER O PERATING Z ONES
V. S IMULATION R ESULTS
The proposed converter and PWM were extensively sim-
ulated under MATLAB/Simulink, using the PLECS toolbox.
The simulations cover a large range of active and reactive
power injected into the grid, dc-link voltage, and equivalent PV
parasitic capacitance.
A dc-link voltage VDC = 300 V was used in the simulations,
unless otherwise specified. The grid was represented by a sinu-
soidal voltage source at 50 Hz of amplitude vgrid = 230 V. The
output filter was composed of a capacitor Cf = 1 μF and an
inductor Lf = 1.5 mH. An additional inductor Lgrid = 40 μH
represented the total distributed grid inductance. The PWM
frequency was fs = 20 kHz, and the flying capacitor had a
capacitance of Cfc = 500 μF. The surge limiting resistance
RT was selected as 1.5 kΩ. The current injected into the grid Fig. 8. TC behavior with a 200 nF parasitic capacitor.
was regulated through a proportional-integral regulator plus
only a common-mode inductor of 1 mH was employed in this
feedforward at igrid = 8.5 A rms.
setup. The ground leakage current could be further reduced by
As stated above, the injection of both active and reactive
a more accurate design of the common-mode filter.
power was simulated; however, the switches being ideal and
In order to obtain further indications about the regulation of
the commutations instantaneous, performance did not depend
the flying-capacitor voltage, Fig. 9 reports the result of a step
on the power factor. For this reason, only the unity power factor
variation of Vfc from 150 to 190 V (inside the controllable
simulation results are reported. In the simulations, the grid
region in Fig. 5) occurring at time 0.1 s. As it can be seen,
voltage angle information is available; hence, a PLL was not
the average value of Vfc rapidly (in about 25 ms) rises to the
employed.
reference value without any overshoot.
Fig. 7 shows the output voltage and current under different
conditions of the dc voltage ratio. As expected, the THD of the
VI. E XPERIMENTAL R ESULTS
grid current increases with the dc voltage ratio, being 2.7%, 3%,
and 3.3%, respectively, for Vfc /VDC = 0.33, Vfc /VDC = 0.5, A prototype nine-level converter was designed and built in
and Vfc /VDC = 0.66. order to test the performance of the proposed solution. The
Fig. 8 shows the performance of the TC with a parasitic prototype is based on the Texas Instruments TMS320F28335
capacitance of the PV field of Cp = 200 nF. The ground microcontroller and features the two full bridges, the TC, the
leakage current results iground = 30 mA rms. Please note that sensors, and the output filter. Infineon IKW30N60H3 IGBTs
BUTICCHI et al.: GRID-CONNECTED CONVERTER TOPOLOGY FOR TRANSFORMERLESS PV SYSTEMS 3957
Fig. 12. Experimental results with unity power factor and Vfc = 0.33VDC .
Vout (300 V/div), igrid (10 A/div), and vgrid (200 V/div). Time base 5 ms/div.
Fig. 13. Experimental results with unity power factor and Vfc = 0.5VDC .
Vout (300 V/div), igrid (10 A/div), and vgrid (200 V/div). Time base 5 ms/div.
Fig. 10. Block scheme of the delay-based PLL.
Fig. 11. Schematic of the test bed employed for the experiments.
Fig. 14. Experimental results with unity power factor and Vfc = 0.66VDC .
Vout (300 V/div), igrid (10 A/div), and vgrid (200 V/div). Time base 5 ms/div.
and ST Microelectronics STW55NM60ND MOSFETs were
employed as active devices. The microcontroller implements tance is distributed between both the positive and negative sides
the PWM signal generation, the current controller, and the of the dc link, for analysis purposes, it can be considered as
proposed modulation. Synchronization with the grid is realized concentrated only on the negative side.
with a transport delay-based PLL structure (see Fig. 10). The For consistency, the same circuit parameters were chosen
schematic is the same as that of the d–q PLL in a synchronous as in the simulations, and the output current and voltage are
reference frame, except that the quadrature input signal and reported for different dc voltage ratios. Figs. 12–14 refer to Vfc /
the cosine of the estimated angle are realized with a constant VDC = 0.33, Vfc /VDC = 0.5, and Vfc /VDC = 0.66, respectively.
HV
delay equal to 1/4 of the nominal grid voltage period T . As For completeness, the output voltage of the HVFB, i.e., Vout ,
LV
demonstrated in [41], this modification allows to obtain a zero and of the LVFB, i.e., Vout is presented in Fig. 15. It can be
steady-state error for small-frequency variations of the input noted that the high-frequency voltage switching of the HVFB
signal with respect to the nominal grid voltage one. happens only in a limited time interval during a period of the
Fig. 11 shows a schematic of the test bed. The converter grid voltage.
was powered by an Agilent Technologies dc power supply, The experimental results show a low-frequency crossover
and its output was directly connected to the grid. In order to distortion, absent in the simulations, that is more evident for
simulate the parasitic capacitance of the PV field, a capacitor Vfc /VDC = 0.33. This behavior can be explained with the pres-
was connected between the negative dc-link terminal and the ence of dead times between the commutations of the devices.
neutral wire. Although in actual PV fields the parasitic capaci- As was shown in [32], extreme values of duty cycles lead to
3958 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014
Fig. 17. TC behavior. vground (200 V/div) and iground (500 mA/div). Time
Fig. 15. Experimental results with unity power factor and Vfc = 0.5VDC . base 5 ms/div.
HV (300 V/div), and V LV (200 V/div). Time base 5 ms/div.
Vout (300 V/div), Vout out
Fig. 18. Experimental results with step variation of the injected grid current
Fig. 16. Experimental results with power factor 0.85 and Vfc = 0.5VDC . from 1.2Arms to 7.4Arms . igrid (10 A/div) and vgrid (100 V/div). Time base
Vout (300 V/div), igrid (10 A/div), and vgrid (200 V/div). Time base 5 ms/div. 50 ms/div.
TABLE II R EFERENCES
E XPERIMENTAL M EASUREMENTS OF E FFICIENCY η AND THD
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3960 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014
using artificial neural network angle generation,” IEEE Trans. Ind. Appl., Giampaolo Buticchi (S’10–M’13) was born in
vol. 47, no. 5, pp. 2117–2124, Sep./Oct. 2011. Parma, Italy, in 1985. He received the Master’s de-
[24] P. Cortes, S. Kouro, F. Barrios, and J. Rodriguez, “Predictive control of a gree in electronics engineering and the Ph.D. degree
single-phase cascaded H-bridge photovoltaic energy conversion system,” in information technology from the University of
in Proc. IPEMC, Harbin, China, Jun. 2012, vol. 2, pp. 1423–1428. Parma, Parma, Italy, in 2009 and 2013, respectively.
[25] N. Rahim, K. Chaniago, and J. Selvaraj, “Single-phase seven-level grid- He is currently a Postdoctoral Research Associate
connected inverter for photovoltaic system,” IEEE Trans. Ind. Electron., with the University of Parma. His research area is
vol. 58, no. 6, pp. 2435–2443, Jun. 2011. focused on power electronics for renewable energy
[26] N. Rahim and J. Selvaraj, “Multistring five-level inverter with novel PWM systems, static energy conversion, and motor drives.
control scheme for PV application,” IEEE Trans. Ind. Electron., vol. 57,
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[27] J. Selvaraj and N. Rahim, “Multilevel inverter for grid-connected PV sys-
tem employing digital PI controller,” IEEE Trans. Ind. Electron., vol. 56,
no. 1, pp. 149–158, Jan. 2009. Davide Barater (S’11) was born in Pontremoli,
[28] J. Leon, R. Portillo, S. Vazquez, J. Padilla, L. Franquelo, and J. Carrasco, Italy, in 1983. He received the M.S. degree in elec-
“Simple unified approach to develop a time-domain modulation strat- tronics engineering from the University of Parma,
egy for single-phase multilevel converters,” IEEE Trans. Ind. Electron., Parma, Italy, in 2009, where he is currently working
vol. 55, no. 9, pp. 3239–3248, Sep. 2008. toward the Ph.D. degree in information technology.
[29] Y.-H. Liao and C.-M. Lai, “Newly-constructed simplified single-phase His research area is focused on power electronics
multistring multilevel inverter topology for distributed energy resources,” and static energy conversion.
IEEE Trans. Power Electron., vol. 26, no. 9, pp. 2386–2392, Sep. 2011.
[30] M. Cavalcanti, A. Farias, K. Oliveira, F. Neves, and J. Afonso, “Eliminating
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IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2761–2767, Aug. 2010. Emilio Lorenzani (S’03–M’07) was born in Parma,
[32] V. Antunes, V. Pires, and J. Silva, “Narrow pulse elimination PWM for Italy, in 1976. He received the Master’s degree in
multilevel digital audio power amplifiers using two cascaded H-bridges electronics engineering and the Ph.D. degree in in-
as a nine-level converter,” IEEE Trans. Power Electron., vol. 22, no. 2, formation technology from the University of Parma,
pp. 425–434, Mar. 2007. Parma, in 2002 and 2006, respectively.
[33] D. Zambra, C. Rech, and J. Pinheiro, “Comparison of neutral-point- Since 2011, he has been with the Department
clamped, symmetrical, and hybrid asymmetrical multilevel inverters,” of Science and Engineering Methods, University of
IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2297–2306, Jul. 2010. Modena and Reggio Emilia, Modena, Italy. He is
[34] S. Vazquez, J. Leon, L. Franquelo, J. Padilla, and J. Carrasco, “DC- the author or coauthor of more than 50 technical
voltage-ratio control strategy for multilevel cascaded converters fed with papers and holds four industrial patents. His research
a single DC source,” IEEE Trans. Ind. Electron., vol. 56, no. 7, pp. 2513– activity is mainly focused on power electronics for
2521, Jul. 2009. renewable energy resources, electric drives, and electric motor diagnostics.
[35] S. Vazquez, J. Leon, J. Carrasco, L. Franquelo, E. Galvan, M. Reyes,
J. Sanchez, and E. Dominguez, “Analysis of the power balance in the cells
of a multilevel cascaded H-bridge converter,” IEEE Trans. Ind. Electron., Carlo Concari (S’98–M’06) was born in San
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[36] S. Lu, S. Mariethoz, and K. Corzine, “Asymmetrical cascade multilevel M.S. degree in electronics engineering and the Ph.D.
converters with noninteger or dynamically changing dc voltage ratios: degree in information technology from the Uni-
Concepts and modulation techniques,” IEEE Trans. Ind. Electron., vol. 57, versity of Parma, Parma, Italy, in 2002 and 2006,
no. 7, pp. 2411–2418, Jul. 2010. respectively.
[37] B. Gu, J. Dominic, J.-S. Lai, C.-L. Chen, T. LaBella, and B. Chen, “High Since 2006, he has been an Assistant Professor
reliability and efficiency single-phase transformerless inverter for grid- with the Department of Information Engineering,
connected photovoltaic systems,” IEEE Trans. Power Electron., vol. 28, University of Parma. He is the author or coauthor of
no. 5, pp. 2235–2245, May 2013. more than 40 technical papers. His research activity
[38] W. Yu, J.-S. Lai, H. Qian, and C. Hutchens, “High-efficiency MOSFET in- is mainly focused on power electronics, digital drive
verter with h6-type configuration for photovoltaic nonisolated ac-module control, static power converters, and electric machine diagnostics.
applications,” IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1253–1260,
Apr. 2011.
[39] G. Buticchi, C. Concari, G. Franceschini, E. Lorenzani, and P. Zanchetta, Giovanni Franceschini was born in Reggio Emilia,
“A nine-level grid-connected photovoltaic inverter based on cascaded Italy, in 1960. He received the Master’s degree
full-bridge with flying capacitor,” in Proc. IEEE ECCE, Sep. 2012, in electronics engineering from the University of
pp. 1149–1156. Bologna, Bologna, Italy.
[40] S. Golestan, M. Monfared, F. Freijedo, and J. Guerrero, “Dynamics as- Since 1990, he has been with the Department
sessment of advanced single-phase PLL structures,” IEEE Trans. Ind. of Information Engineering, University of Parma,
Electron., vol. 60, no. 6, pp. 2167–2177, Jun. 2013. Parma, Italy, where he was first an Assistant Pro-
[41] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “Improved PLL structures fessor and is currently a Full Professor of electric
for single-phase grid inverters,” presented at the Int. Conf. Power Elec- machines and drives. His research interests in-
tronics Intelligent Control Energy Conversation (PELINCEC), Warsaw, clude high-performance electric drives and diagnos-
Poland, Oct. 2005. tic techniques for industrial electric systems.