AMSC Analog and Mixed Signal Center

Department of Electrical & Computer Engineering

Highly Linear Low Noise Amplifier

Sivakumar Ganesan
Texas A&M University
sivakumar@tamu.edu

Advisors: Dr. Edgar Sánchez-Sinencio

Dr. Jose Silva-Martinez

1
AMSC Outline

• Motivation
• Background
• Proposed Solution
• Testing Strategy
• Experimental Results
• Conclusion

2
AMSC Motivation

• Numerous co-existing wireless standards

and wireless equipment

3
AMSC Frequency Spectrum

• Limited spectrum allotted to each user

• Possible large interferers from other
channels in-band and out of band

4
AMSC Receiver Architecture

• Antenna receives the entire band of signals

• Stringent requirements on the receiver front-end
• BPF filters the out of band channels
• LNA receives the entire in-band signals
• In-band channel interference problems in LNA
– Blocking
– Intermodulation
5
AMSC Blocking

y (t ) = α 1 x (t ) + α 2 x 2 (t ) + α 3 x 3 (t )

x(t ) = A1 cos ω1t + A2 cos ω2t

⎛ 3 ⎞
y (t ) ≅ ⎜ α 1 + α 3 A22 ⎟ A1 cos ω1t + ......
⎝ 2 ⎠

– If α 3 < 0 , a large interferer results in signal

being “blocked”

6
AMSC Intermodulation
Interferers

Desired Desired
Interferers
Channel Channel

LNA

IM3

x(t ) = A1 cos ω1t + A2 cos ω2t

3 3
yIM 3 (t ) = α3 A1 A2 cos(2ω1 − ω2 ) + α3 A22 A1 cos(2ω2 − ω1 )
2

4 4

• Third order intermodulation (IM3) components

corrupt the signal resulting in distortion
7
AMSC Linearity Measurement

• Third order Input Intercept Point (IIP3) is a

measure of circuit non-linearity
3
α
• Fundamental = 1 ,IM3 = 4 3
A α A 3

8
AMSC Low Noise Amplifier

• Low Noise Amplifier

– First amplifying block in a receiver
– High gain, Low Noise Figure
– Presents amplified signals (desired + IM3) to
mixer
• Highly linear LNA with high gain and low
NF required

9
AMSC Background

• Existing Linearization Techniques

– Optimum Biasing
– Negative Feedback
– Input Impedance Frequency Termination
– Feedforward Cancellation

10
AMSC Optimum Biasing
• Current = id = g m1vgs + g m 2vgs2 + g m3vgs
3
+ ......

• IIP3= 43 gg
m1

m3

• gm3=0 results in very high IIP3

11
AMSC Optimum Biasing

• Drawbacks
– High IIP3 obtained over a narrow region
– Process variations degrade IIP3
– Limited voltage gain due to restricted input
transconductance (gm1)
– Poor NF

12
AMSC Negative Feedback

• Popular in baseband circuits to improve

linearity

4 g m1 (1 + To )3
, To = g m1β
• IIP3= 3 g m3 ⎛ 2 g m 2 To ⎞
2
⎜⎜1 − ⎟⎟
⎝ g m1 g m 3 1 + To ⎠

13
AMSC Negative Feedback

• Linearity improvement at the expense of

circuit gain
• Second order non-linearity effect on IIP3
• gm3<0, leads to further deterioration
• Feedback techniques not suitable at RF
frequencies

14
AMSC Negative Feedback

• Inductor LS acts as a feedback Cascode LNA

network
• Provides best gain and noise
performance
• Poor linearity performance due
to second order non-linearity
feedback

15
AMSC
Input Impedance Termination
• Feedback network is frequency dependent
• Different effect on different harmonics

3
⎧ ⎫
A ( s) VT
IIP3 ≈ 1 [
1 + sC je Z ( s) ⎨− 1 + 1 ]
A (∆s)
[ A (2s)
1 + ∆sC je Z (∆s) + 1 ]
1 + 2sC je Z (2 s) ⎬ Vs [ ] 2

IQ 4 ⎩ gm 2gm ⎭
where
∆s = ( sa − sb ) << s, sa = j 2πf a , sb = j 2πf b
gm
A1 ( s ) = , Z ( s) = Z b ( s) + Z e ( s)
sC je Z ( s) + sτ F g m Z ( s) + g m Z ( s)
β o + 1 + g m Z e ( s)
16
AMSC
Input Impedance Termination
• The input and output impedances selectively
tuned for second harmonic frequencies
• Requires huge passive elements

17
AMSC Feedforward

• Scaled versions of the input signal are fed

to two different amplifiers
Amplifier
(A)
Ymain(t)

X(t) Y(t)

Yaux(t)
Pre-scalar Amplifier
(β) (A) β

1
ymain (t ) = A.x.(1 + α 2 x 2 ), yaux (t ) = A.β .x.(1 + α 2 β 2 x 2 ) *
β3
y (t ) = ymain (t ) − yaux (t )
⎛ 1 ⎞
= A⎜⎜1 − 2 ⎟⎟.x
⎝ β ⎠
18
AMSC Feedforward-1

• Drawbacks
– Linearity improvement at the expense of gain
– Reduced NF due to additional active
components
– Mismatch and errors in signal scaling leads to
reduced improvement
• Derivative Superposition (DS) method
addresses the above problems

19
AMSC
Derivative Superposition (DS) Method

• DS method also addresses the problem of

narrow range with optimum biasing technique.
• gm3 negative in strong inversion and positive in
weak inversion
ZS
IN

OUT

Weak MA MB Strong
Inversion WA WB Inversion

L
VGS VOFF

20
AMSC DS-Method

• Wide range of bias values with very small gm3

and hence IIP3 improvement obtained
• Drawbacks
– Second order harmonics ( 2ωa ,2ωb ,±ωb ± ωa ) converted to
voltage at the source
– Control parameter Vgs has both fundamental and
second harmonics
4 g m2 1ω 2 LC gs
IIP3 = , Where
3ε
2 g m2 2 3
ε = g m3 −
1 C
g m1 + + 2 jωC gs + Z s (2ω ) gs
2 jω L L

21
AMSC Modified DS-Method
• Addresses the effect of second order non-
linearity feedback
• Magnitude and phase of second order non-
linearity contribution to IM3 is tuned to cancel
the third order non-linearity contribution to IM3
IN

OUT

Auxiliary Main
Transistor MB MA
Transistor

L2

L1
VGS VOFF

22
AMSC Modified DS-Method

4 g12Aω 2 [L1 (C A + C B ) + L2C A ]

IIP3 = , Where
3ε
⎡ L2C A ⎤ 2 g 22A 1
ε = g 3 B n( s ) n( s ) ⎢1 + ⎥ + g3 A −
2

⎣ L1 (C A + C B ) + L2 A⎦
C 3 g1 A 1 + 1
j 2ω ( L1 + L2 ) g1 A
n( s ) = 1 + jωL2 g1 A
23
AMSC Drawbacks

• Weak inversion transistor connected in

parallel degrades NF
2
ind = 4kT∆fγg d 0
ω 2 C gs2 g d 0 = I Dsat φt
i 2
ng = 4kT∆fδ
5g d 0

• Auxiliary transistor loads the input

affecting the frequency of operation
• Auxiliary transistor affects both linearity
and input match leading to increased
design steps

24
AMSC

Proposed Solution

25
AMSC Basic Idea

• An auxiliary circuit is unavoidable to achieve high

linearity
• IM3 components in the drain current of the main
transistor has the required information of its non-
linearity
• Auxiliary circuit is used to tune the magnitude
and phase of IM3 components
• Addition of main and auxiliary transistor currents
results in negligible IM3 components at output

26
AMSC Basic Idea

Im
g3B
(Magnitude and
angle tuned)

Re
g3A g2A

27
AMSC Proposed LNA

28
AMSC Theoretical Analysis
• IIP3 derived using the harmonic input method of
Volterra series analysis
ix iout
ZS vout

CA va ia

vx
vb CB ib
LA

LB

ia = g1a va + g 2 a va2 + g 3a va3

ib = g 3b vb3
iout = ia + ib = C1 ( s1 ) * v x + C2 ( s1 , s2 ) * v x2 + C3 ( s1 , s2 , s3 ) * v x3
29
AMSC Theoretical Analysis
1 ⎧ g1a ⎫
IIP3 = 2 ⎨ ⎬
6 Re(Z s ( s ) ) A1 ( s ) ⎩ ε ⎭
g 22a 2 2 + s LB C B
2
where, ε = g 3a − + g 3b n ( s ) n ( s )
3 g1a 2(1 + s 2 LB C B )
sLA ( g1a + sC A )
n( s ) =
1 + sC B ( sLA + sLB )

• The effect of second order non-linearity can be

seen in the above equation
• The value of g3bcan be tuned to obtain high IIP3 by
choosing appropriate values for the inductors LA and
LB and the aspect ratios of the transistors.

30
AMSC Theoretical Analysis
• MATLAB plots for different values of LA and LB is
plotted
• The result corroborates the idea of IIP3 improvement
by cancellation of IM3 components

Designed
Point

31
 AMSC IIP3 Sensitivity

Variation with La Variation with Lb

25 25

20 20

15 15

IIP3 (dBm)
IIP3 (dBm)

10 10

5 5

0 0
4 4.2 4.4 4.6 4.7 4.8 5 5.2 5.4 0.5 0.75 0.9 1 1.05 1.1 1.25 1.5

Main Transistor Inductor (nH) Aux Transistor Inductor (nH)

32
AMSC Effect on Input Match

• Ifs 2 L A C B << 1 ,
the input impedance can be
simplified to that of a cascode LNA
1 g1a L A
Z in = sLG + + sL A +
sC A CA

• The input matching is unaffected by the

auxiliary transistor

33
AMSC Effect on Input Match

• Effect on input match (S11) with and

without auxiliary transistor

202 MHz
188 MHz

Without Auxiliary

With Auxiliary

34
AMSC Effect on NF

• The gate noise current of the auxiliary transistor

gets added with the drain noise current of main
transistor and is attenuated by the gain of LNA

35
AMSC Effect on NF

NF without auxiliary transistor

NF with auxiliary transistor

• 0.3dB degradation in NF observed

• Lossy inductor in the auxiliary branch
contributes to increased NF

36
AMSC LNA Design

• Linear LNA was designed and fabricated in

TSMC 0.35µm CMOS technology
• The inductors were designed using ASITIC and
a Q of 2.5 was obtained
• The LNA was designed to have maximum gain
at 900MHz
• The LNA fabricated was a stand alone LNA
terminated by the 50Ω port impedance

37
AMSC Component Values

Component Value
MA 24 µm/0.4 µm, m=16
MC 24 µm/0.4 µm, m=16
MB 24 µm/0.4 µm, m=36
LG 30 nH
LA 5 nH
LB 1.05 nH
LD 10 nH

38
AMSC Chip Photograph

39
AMSC Testing Strategy
• The gain obtained in LNA is less as it sees a
50Ω load impedance
• Gain can be improved by connecting a
resistor in series with the port

Vx Vout R + 50
•LNA Gain= =
Vin Vin
*
50
40
AMSC Advantages

• Increased gain results in larger signal

swings
• LNA subject to large signal swings is an
ideal test for linearity
• Linearity of LNA unaffected due to linear
resistive element

41
AMSC Experimental Results

• R=0Ω, S11=-15.85 dB, S21=4.4 dB, Gain= 4.4 dB

S11 (Input Match) S21 (Power Gain)

42
AMSC Experimental Results
• R=75 Ω, S11=-11.7 dB, S21=1.5 dB, Gain= 9.5 dB

S11 (Input Match) S21 (Power Gain)

43
AMSC IIP3 Test Setup

44
AMSC IIP3 Measurement

• R=75 Ω
Pf − PIM 3
IIP3 (dBm) = Pin +
2
where Pin = Total Signal Input Power
Pf = Total Signal Output Power
PIM 3 = Total IM 3 tone Output Power

• Pin=-10dBm, Pf= -13.2dBm

PIM3= -75.07dBm
• IIP3 = +20.93 dBm

45
 Output Power per tone (dBm)
AMSC

46
IIP3 Measurement
AMSC Experimental Results

• R=100 Ω, S11=-10.7 dB, S21=1.1 dB, Gain= 10.6 dB

S11 (Input Match) S21 (Power Gain)

47
 Output Power per tone (dBm)
AMSC

48
IIP3 Measurement
AMSC Summary of Results

LNA Gain
R (Ω) S11 (dB) S21 (dB) IIP3 (dBm)
(dB)
0 -15.85 4.4 4.4 20

75 -11.7 1.5 9.5 20.9

100 -10.7 1.1 10.6 21

150 -9.5 -0.5 11.5 20.5

49
AMSC De-embedding Results

• 6dB increment in gain when ‘R’ is changed from 0Ω to 100Ω and

hence on-chip load resistance can be computed to be 150Ω
• Gain of LNA with Zext=∞ is 6dB more than gain with R=100Ω
• Gain of LNA adding other losses is estimated to be 18.5dB
• The NF of the LNA after de-embedding the noise contribution of
termination resistors (R=100Ω and 50Ω port) is calculated to be
1.76dB

50
AMSC Comparison of Results
Freq Gain NF IIP3 Pdc
Work Technology FOM
(GHz) (dB) (dB) (dBm) (mW)
This Work 0.35µm CMOS 0.95 18.5 1.76 21 22.5 793

JSSC ‘04 0.35µm CMOS 0.9 10 2.8 15.6 21.1 19

ISSCC ‘01 0.35µm CMOS 0.9 2.5 2.8 18 45 3

MTT ‘05 0.25µm CMOS 0.9 15.5 1.65 22 24.2 503

ISCAS ‘04 0.25µm CMOS 0.9 14.6 1.8 10.5 5.4 117
0.5µm SiGe
ESSCC ‘05 0.88 15.7 1.4 11.7 11.7 124
BiCMOS
ISCAS ‘04 0.18µm CMOS 3 6.5 1.9 15 8.9 29

ISSCC ‘03 0.25µm CMOS 2.2 14.9 3 16.1 23.5 54

51
AMSC
De-Embedding the NF of LNA

Fig 1 shows the simplified small signal model of LNA. RL is the load
impedance of LNA presented by the LC resonant circuit at the
output, R is the external resistor connected to improve the gain and
50Ω is the resistance of the port.

Fig 1: Small Signal Model

52
AMSC

For numerical analysis a value of RL=150Ω and

R=75Ω are used below.
From Table 3 in the paper, the measured gain at
the point VLNA shown in Fig 1 is 10.5dB for
R=75Ω and NF is 2.95dB. Hence

NF = 1 +
2
V measured −in
2.95
= 10 10 = 1.972
(1)
V502 Ω

53
AMSC Noise Analysis at output:

Fig 2: Noise Analysis

2 2
Fig 2 shows the model used for noise analysis. i LNA and i RL
are the noise currents due to input transistor and the load resistance (RL) respectively.
2
i LNA + i RL
2
is reflected to the output port to generate
2
v LNA _ out

54
AMSC

The resistors R and 50Ω generate an output

noise voltage at the node ‘OUT’ given by
⎡ 1 ⎛ R+R ⎞
2
⎛ 50 ⎞
2⎤
2
V add = 4 KT ⎢ ⎜⎜ L
⎟⎟ 50 2 + R⎜⎜ ⎟⎟ ⎥
⎢ 50 ⎝ R + R L + 50 ⎠ ⎝ R + R L + 50 ⎠ ⎥⎦ (2)
⎣
⎡⎛ R + R ⎞
2
R * 50 ⎤
= 4 KT * 50 ⎢⎜⎜ L
⎟ + ⎥
⎢⎝ R + R L + 50 ⎟⎠ (R + R L + 50) ⎥⎦
2
⎣
= 4 KT * 50 * (0.72 )

The output noise measured at the node ‘OUT’ is the sum of noise contributed
by the LNA and the output resistive network formed by R and 50Ω and is given
as follows.

55
 AMSC

2
⎛ 50 ⎞
2
V measured − out = V LNA
2
_ out *⎜ ⎟ + V add
2
(3)
⎝ R + 50 ⎠
2
⎛ 50 ⎞
= V LNA
2
_ out *⎜ ⎟ + 4 KT * 50 * 0.72 ( from (2))
⎝ R + 50 ⎠

The overall gain of LNA for R=75Ω is given as follows.

Vout V LNA _ out Vout
Overall Gain = = *
Vin Vin V LNA _ out
V LNA _ out
= 10.5 dB = 3.35
Vin
Vout 50
= = 0.4
V LNA _ out 50 + 75
Overall Gain( Av ) = 3.35 * 0.4 = 1.34

56
 AMSC

Total input measured noise is given as follows.

2
V measured − out
−in =
2
V measured
Av2
4 KT * 50 * 0.72
= V LNA
2
−in + ( from (3))
Av2
2
Where V LNA−in is the total input referred noise contribution of LNA and RL alone.

.
Let V n250 = 4 KT * 50 Hence total input referred noise contribution of LNA and the load resistor alone is given by
2
⎡ 2.95 ⎤ V n50 * 0.72
2
V LNA −in = V n250 ⎢10 10 − 1⎥ − ( from (1))
⎣ ⎦ Av2
= V n250 (0.9 − 0.4 )
De-embedded NF = 1+0.5=1.76dB
= V n250 (0.5)

57
AMSC Conclusion

• A highly Linear LNA using a non-linearity

cancellation technique has been proposed
• Theoretical analysis using Volterra series has
been done to corroborate the idea
• The LNA has been designed and fabricated in
TSMC 0.35µm technology
• An IIP3 of +21dBm has been experimentally
achieved

58