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I CG =C CG *dV CE /dt
Miller Capacitor CCG
S2
RDRIVER RG
+HVDC
RGATE
RGATE
To Driver
To Driver
+_
Gate Capacitor CG
Figure 3. Negative Supply Voltage
2
Active Miller Clamp Solution
To avoid both efficiency loss due to CG and additional How it works: During turn-off, the gate voltage is moni-
cost for the negative supply voltage, another measure tored and the clamp is activated when the gate voltage
to prevent the unwanted IGBT turn-on is proposed by goes below 2 V (relative to VEE). The clamp voltage is
shorting the gate-to-emitter path. This can be achieved typically VOL + 2.5 V for a Miller current up to 1100 mA.
by an additional transistor between the gate and
emitter. This ‘switch’ shorts the gate-emitter region after
a threshold is reached. The occurring currents across the
Miller capacitance are shunted by the transistor instead
of flowing through the output driver pin, Vout (Pin 11).
This technique is called Active Miller Clamp.
Figure 4 shows the ACPL-332J internal block diagram.
13
VCC2
UVLO
6, 7 D
ANODE R
I 11
5, 8 VOUT
CATHODE V
LED1 DESAT
E
14
R
DESAT
9, 12
VEE
SHIELD
VCLAMP
2 10
VCC1 VCLAMP
LED2
3 VE
FAULT 16
1, 4 15
VS VLED
SHIELD
Figure 4. ACPL-332J Block Diagram; Active Miller Clamp Feature Circled in Red
3
Figures 5 to 7 show possible application circuits using Avago’s Active Miller Clamp.
Application Note: If Active Clamp is not used, connect VCLAMP to VEE
Figure 5 is the recommended circuit for gate driver design with Miller Clamp (VCLAMP pin).
1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15 CBLANK
0.1µF RF DDESAT
+
_ 3 FAULT DESAT 14
100 Ω
CF
4 VS VCC2 13
5 CATHODE VEE 12
+
_ + HVDC
RG +
6 ANODE VOUT 11 VCE
R Q1 -
3-PHASE
7 ANODE VCLAMP 10 RPULL--DOWN AC
+
_ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
Figure 5. IGBT Driver with Single Power Supply, Desaturation Detection and Active Miller Clamp
Figure 6 shows the driver circuit using a negative gate driver for a high-power application. In such circumstances, the
Miller clamp feature would not be required and hence Pin 10 is connected to pin 9, VEE.
1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15
3 FAULT DESAT 14
4 VS VCC2 13
0.1µF Optional R2
5 CATHODE VEE 12
+_ + HVDC
Optional R1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN _+ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
Figure 6. IGBT Driver with Negative Gate Drive for High-power Application
4
Figures 7a and 7b show a dual power supply with an The Clamp threshold voltage is relative to the VEE voltage.
external buffer configuration. The external buffer stage If VEE is 0 V, the clamp threshold is 2 V. If VEE is -5 V, then
is required when the IGBT gate current requirement goes the clamp threshold is -3 V (threshold is 2 V relative to the
beyond the driver IC capability. Miller Clamp function is VEE voltage)
normally not used when a negative voltage supply is
For Figure 7, an optional resistor R1 may be added
provided. However, there are two possible circuit config-
to reduce the current drawn from the driver. This will
urations that use the clamp pin:
increase turn-on/off times of the IGBT. If not required, R1
1. Use the clamp pin as a secondary gate discharge path should be shorted. Optional resistor R2 can be added to
(Figure 7a) allow both the driver and buffer to provide current to the
2. Use the clamp pin to control an additional PNP IGBT. R2 can be open circuited to prevent current being
transistor to sink current. Connecting the Clamp drawn from the driver to the IGBT.
DIRECTLY to the IGBT gate is not advisable for a high-
power IGBT application as the internal clamp MOSFET
is only rated up to 1.5 A. (Figure 7b)
1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15
3 FAULT DESAT 14
4 VS VCC2 13
0.1µF Optional R2
5 CATHODE VEE 12
+_ + HVDC
Optional R1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN
- _+ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
Figure 7a. Large IGBT Driver with Negative Gate Drive, External Buffer for High Current and Active Clamp as Secondary Gate Discharge
1 VS VE 16
0.1µF 0.1µF
2 VCC1 VLED 15
3 FAULT DESAT 14
4 VS VCC2 13
0.1µF Optional R2
5 CATHODE VEE 12
+_ + HVDC
Optional R1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN +_
+
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
R3
Figure 7b. Large IGBT Gate Drive with Negative Gate Drive, External Buffer for High Current and Active Clamp to Control Secondary Discharge Path For High
Power Application
5
Conclusion
Avago Technologies gate optocouplers have a Miller
Clamp function that controls the Miller current during
a high dV/dt situation and keeps the IGBT totally off. It
provides cost savings by eliminating the use of a negative
supply voltage and additional capacitors that reduces
driver efficiency.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved.
AV02-0072EN - July 21, 2010