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Hewlett-Packard Company

Ken Boorom, M.S. 382


P.O. Box 15
Boise, Idaho 83707-0015
Phone: 208-396-7905
Fax: 208-396-5433

Joan Lynch
Managing Editor, EDN
275 Washington St
Newton, MA 02458

October 15, 1998

Dear Ms. Lynch:

Thank you for the information regarding my submission of an article to EDN.

I have enclosed an article entitled, “SPICE Simulations can Help Engineers Understand
Signal Integrity Issues in High-Speed Digital Designs.”

The article provides useful information to the majority of engineers in the field who do
not understand signal integrity in high-speed digital systems.

Feel free to contact me with questions or concerns.

Best Regards,

Ken Boorom
M.S.E.E./B.S.E.E. Stanford University
SPICE Simulations Can Help Engineers
Understand Signal Integrity Issues in High-
Speed Digital Systems

As consumers demand higher speed computing systems, engineers


must raise clock rates to squeeze more performance from their designs.
Higher clock rates mean faster slew rates, and shorter setup and hold.
This, coupled with the trend toward 3.3 Volt logic, makes it essential to
understand transient switching behavior on digital busses.
Engineers sometimes take a trial-and-error approach to fixing transmission line problems that come up
in high speed digital circuits. They experiment with serial termination, parallel termination, or both on the
same interconnecting trace.

There is a better way. SPICE tools allow an engineer to perform simple simulations with various
termination and bus topologies. The simulations work equally well at 10 Mhz or 10 Ghz. They don’t need
exotic high frequency fixturing. They can provide the engineer with a “seat-of-the-pants” understanding
of the behavior of a high speed digital bus. More complex (and expensive) signal integrity tools are
available for exotic and critical applications, where the training and purchase costs are justified.

One such SPICE tool is OrCad’s Pspice. The tool supports the functionality of the original SPICE, and
lets you build circuits with a Graphical User Interface, so you don’t have to memorize SPICE syntax. It
also has a built in graphing waveform function. An evaluation version is available from OrCad’s web site
at: http://www.orcad.com

The interface allows an engineer to perform "what if" scenarios, varying circuit parameters to
understand the effect on the circuit's behavior. The ability to vary a parameter can provide an important
qualitative understanding of a circuit's behavior.

A high-speed digital bus can be modeled with the tool by drawing its equivalent circuit, as shown in
Figure 1.

Figure 1

Any one of the digital interconnects on the left can be modeled as the circuit on the right. The
circuit includes the driver voltage and rise time (Vsrc), the source impedance (Rsrc), any series
impedance added by the designer to match the driver’s impedance to the transmission line
(Rseries), the transmission line, and any terminating capacitance/resistance added by the
designer to terminate the line. By varying the values of the components, different experiments can
be performed. Performing the experiments prior to board layout using a tool like SPICE can
reduce project costs and lead times.
is more realistic, because control signals in digital
@ A Glance circuits are typically active high due to the improved
noise margins.
Easy-to-use PC-based SPICE tools, like PSpice,
can provide useful insights into the behavior of
termination schemes in high-speed digital Several different termination schemes can be
interconnects. As signal rise times are reduced to compared by varying the values of Rseries, Cterm
allow for faster clock speeds, it becomes more and Rterm. If your SPICE tool does not accept 0 or
important for engineers to understand these effects. infinite as a component value, a suitably large or
small number may be substituted:
Figure 2 shows the parameters you will need to
Termination Rseries Cterm Rterm
know to model the circuit.
None 0 0 Infinite
Series 46 Ohms 0 Infinite
Figure 2 Parallel AC 0 10 pF 70 Ohms
Series + Parallel 46 Ohms 10 pF 70 Ohms
Parameter Source Value Once the values are entered, a simulation canbe
Name performed with a single mouse click. Figure 4 shows
Driver Output Manufacturer data 24 Ohms the voltage that would be seen at a device close to
Impedance or experiments the driver. Series termination is the winner here,
Driver Rise Function of driver 0.259 producing the fastest rise-time with the least
Time strength and nsec overshoot.
capacitance seen
at driver Figure 3
Input Mfg Data or Infinite
Impedance of experiments
Driven
Device
Transmission PCB Manufacturer. 24 Ohms
Line Varies with trace
Impedance width. Typical
values for 4-layer
board are 70 Ohms
for 5 mil trace, 58
Ohms for 8-mil
trace.
Transit Time Divide trace length 0.83ns
by speed of wave
in transmission
line, which This graph compares the voltages seen by a
depends on the device close to the driver for the different
board’s dielectric termination schemes. The serially terminated
coefficient. transmission line shows the fastest setting
characteristics, while the unterminated line
Once the circuit model is complete, values shows the most overshoot. Both lines using
must be provided for the components in the parallel termination require a long setting line for
model. These values reflect the physical the series capacitor to charge.
characteristics of the PC board, and the
components that are mounted on it. A fast At high speeds, the location of a device on a
rise time of 0.259 nsec was used to illustrate transmission line can influence both the timing and
the differences between the termination the shape of the transient switching waveform seen
schemes. at its inputs. Figure 4 shows the voltages that
appear at the end of the transmission line. In these
cases, note that the range of the voltages exceeds
For simplicity, the case where signal goes from
those seen in Figure 2.
LOW to HIGH is examined. The HIGH to LOW case
Figure 4
Figure 5

Devices farther from the driver will see different


signal waveforms. This graph shows the impact
of various termination schemes on the waveform
seen at the end of a transmission line. Note that
the overshoot for the unterminated transmission
line is more severe at the end of the transmission
line.
PSpice allows you to display the driver current
required to perform the switching, which can give
Modeling Ground Bounce you an idea of the impact of the termination
scheme on ground-bounce. Note that while a
Driver current can also be measured during the serial termination improves switching speed and
simulation. Driver current is important because rapid reduces ground-bounce, parallel terminations
changes in the current cause ground bounce. reduce ground-bounce at the expense of speed.
Ground bounce happens when a high frequency The unterminated line will alternately dump
current must be sunk to ground through a finite current onto the ground, and require positive Vcc
inductance, such as a bond wire, or packaging lead. current during switching.

Ground-bounce is most pronounced on falling


It is the high frequency components of the driver
transitions, since the digital circuit must sink current
current that are of the greatest concern, because the
into the ground to discharge the interconnecting tract
inductive impedance of the ground path increases
and its loads. On rising edges, the voltage source
linearly with frequency. SPICE includes a Fourier
sees most of the noise. Ground-bounce is more
Analysis feature which can be used to show the
serious than power supply bounce because logic
frequency components of the signals listed above.
circuits reference ground, so changes in the ground
Figure 6 shows such a graph.
can change the perceived value of a logic signal.
This can lead high logic levels to be perceived as low
Note that it is not the highest value that is relevant
logic, which can cause spurious clocking and other
here, but the weighted product of the magnitude and
problems.
the frequency.
Figure 4 shows the driver current for the various
Serial termination comes out a clear winner here.
termination schemes – a positive value in the graph
In comparing the parallel termination to the no
represents a current that would flow into the ground
termination, the parallel termination shifts the spectra
plane. Note that the currents shown are for one
to a lower frequency, but does not diminish its
driver only – consider the effects of driving 8 or 32
magnitude.
signals simultaneously.
It is interesting to note that the addition of parallel
termination to a system with series termination will
result in greater ground bounce. This shows why it’s
important to have an understanding of how
termination schemes work – it’s possible to have too
much of a good thing.

Figure 6

A Fourier Analysis of the switching current can


be a guide in evaluating ground-bounce. Since
all current must reach ground through an
inductive impedance, termination schemes that
produce switching currents with strong high
frequency components can be expected to
exacerbate ground-bounce. In this comparison,
serial termination comes out the clear winner –
the series resistor at the driving source limits the
source’s drive current and reduces ground-
bounce.

References:

1996 Altera Databook, Altera Corporation. San


Jose, CA, 408-894-7000

Johnson, Howard. High Speed Circuit Design: A


Handbook of Black Magic. Prentice Hall Inc.,
1993. ISBN 0-13-395724-1

Author’s Biography

Ken Boorom works for Hewlett-Packard’s


Laserjet Solutions Group in Boise, ID, where he
is responsible for ASIC and circuit board
qualification. He holds Bachelor’s and Master’s
Degrees from Stanford University.