HCS12 µController

DR. Salim Al-Wasity

 ❖ Mainframe computers, workstations, and personal
computers (PC):
 After power is turned on, the processor starts to execute the
program from the BIOS (nonvolatile memory), which performs
the system initialization.
 After system initialization is completed, the processor loads
INTRODUCTION additional programs such as Windows operating system into the
main memory (RAM) for execution.

❖ Embedded systems:
 After power-up, the processor starts to execute all their
programs from the nonvolatile memory.
THE CIRCUIT OF THE PROGRAM COUNTER

The program counter consists of D-type flip-flops and other additional logic gates as
shown in figure 1.
 The D value may be transferred to Q on either the rising or the falling edge (but not both
edges) of the CLK input.
 The CLK signal is the clock input signal.
 The Q signals of all the flip-flops of the program counter determine the address of the
next instruction to be fetched.
 The set and reset inputs are active low and cannot be low at the same time.
➢ When set is low, the Q signal is forced to 1.

➢ When reset is low, the Q signal is forced to 0.

Figure 1. Block diagram of a D

flip-flop with a set and reset
 A block diagram of the program counter (PC) of an 8-bit microcontroller is
shown in figure 2. It allows the PC to be:
 Forced to 0
 Incremented by 1
 Incremented by a field in the instruction register (IR)
 Loaded with a jump target

THE CIRCUIT OF
THE PROGRAM
COUNTER

Figure 2. A simplified block diagram of the program counter (PC) of an 8-bit microcontroller
THE CIRCUIT OF THE
PROGRAM COUNTER

Forced to 0: Whenever power is

turned on to the microcontroller,
the PC is forced to 0 (via reset)
and the instruction fetch will
start from address 0.
THE CIRCUIT OF THE
PROGRAM COUNTER

Incremented by 1: If the instruction

being executed is not a program
flow control instruction, then the
PC is simply incremented by 1
after each instruction byte is
fetched.
THE CIRCUIT OF THE
PROGRAM COUNTER

Incremented by a field in the IR: If

the instruction being executed is a
conditional branch instruction and
the branch condition is true, then
the branch signal will be 1, the sum
of the current PC and branch offset
will be loaded into the PC, and
instruction execution will continue
from that address
THE CIRCUIT OF THE
PROGRAM COUNTER

Loaded with a jump target: If the

instruction being executed is a jump
instruction, then the jump value will
be 1 and Jump target value will be
loaded into the PC.
INSTRUCTION EXECUTION PROCESS

To have a better understanding of how the µprocessor/µcontroller read and execute instructions, we
assume that we have:
 An 8-bit µprocessor X with:
 An 8-bit accumulator (A)

 A 16-bit pointer register (ptr) used to point to the data memory

 A memory data register (MDR) to hold the data received from/ to be written to data memory.

 A separate data and program memory with 64KB each.

 An instruction opcode of 1-byte (it is always the first byte of the instruction)
INSTRUCTION EXECUTION PROCESS

 An example of the instruction set shown in table-1 below.

Assembly Instruction Machine Code Address Meaning

ld 0x20,#00 75 20 00 0x0000 place 0 in data memory located at address 0x20
ld 0x21,#20 75 21 14 0x0003 place 20 in data memory located at address 0x21
ld ptr,#0x2000 90 20 00 0x0006 load 0x2000 into the register ptr
loop ld A,@ptr E0 0x0009 load the memory contents pointed to by ptr into A
and A,#0x03 54 03 0x000A and the value 0x03 with A and leave the result in A
bnz next 70 02 0x000C branch if the result in A is not 0
inc 0x20 05 20 0x000E increment the memory location at 0x20 by 1
next: dbnz 0x21,loop D5 21 0A 0x0010 decrement the memory location at 0x21 and branch if the result is not 0
ld 0x20,#00 (Machine code 75 20 00)

1. The value in the PC (0x0000) is placed on the address bus of the

program memory with a request to read the contents of that CPU
location.
Program Memory Program Memory
2. The 8-bit value at the location 0x0000 is the instruction opcode data bus address bus
0x75. At the end of this read cycle, the PC is incremented to 0x75 75 0x0000
0x0001. The opcode byte 0x75 is fetched. Figure 3 shows the
0x20 20 0x0001
opcode read cycle.
0x00 00 0x0002
3. Control unit recognizes that this version of the ld instruction
75
requires one read cycle to fetch the direct address and another PC status
cycle to read the data operand. These 2 bytes are stored 21
Before read 0x0000
immediately after the opcode byte. Two more read cycles to 14 After 1st read 0x0001
program memory are performed to access the data memory 90 After 2nd read 0x0002
address 0x20 and 0x00. After these two read cycles, the PC is After 3rd read 0x0003
20
incremented to 0x0003.
Program Memory

Figure 3. Instruction 1-opcode read cycle

ld 0x20,#00 (Machine code 75 20 00)

4. Control unit places 0x0020 on the data memory address bus and
the value 0x00 on the data memory data bus to perform a write CPU
operation. The value 0x00 is to be stored at data memory location
0x0020, as shown in Figure 4.

0x00 00 0x20
Data Memory xx Data Memory
data bus address bus
xx
xx
xx
xx
PC status
xx Before read 0x0003
xx After read 0x0003

Data Memory

Figure 4. Instruction 1-data memory write cycle

ld 0x21,#20 (Machine code 75 21 14)

CPU CPU

Program Memory Program Memory

data bus address bus
75 00
20 PC status 0x20 20 0x21
Before read 0x0003
00 xx
After 1st read 0x0004 Data Memory Data Memory
0x75 75 0x0003 data bus xx address bus
After 2nd read 0x0005
0x21 21 0x0004 After 3rd year 0x0006 xx
0x14 14 0x0005 xx
PC status
90 xx Before read 0x0006
20 xx After read 0x0006

Program Memory Data Memory

Figure 5. Instruction 1-opcode read cycle Figure 6. Instruction 1-data memory write cycle
ld ptr,#0x2000 (Machine code 90 20 00)

1. The value in the PC (0x0006) is placed on the program memory ptr: 0x2000

address bus with a request to read the contents of that location. CPU
2. The 8-bit value at the location 0x0006 is the instruction opcode Program Memory Program Memory
0x90. At the end of this read cycle, the PC is incremented to data bus address bus
0x0007. The opcode byte 0x90 is fetched. Figure 7 shows the 75
opcode read cycle. PC status
20
3. The control unit recognizes that this instruction requires two more Before read 0x0006
00
read cycles to the program memory to fetch the 16-bit value to be After 1st read 0x0007
75 After 2nd read 0x0008
placed in the ptr register. These 2 bytes are stored immediately
after the opcode byte. The control unit continues to perform two 21 After 3rd read 0x0009

more read cycles to the program memory. At the end of each read 14
cycle, the processor X stores the received byte in the ptr register 0x90 90 0x0006
upper and lower bytes, respectively. After these two read
0x20 20 0x0007
operations, the PC is incremented to 0x0009.
0x00 00 0x0008
Program Memory
Figure 7. Instruction 1-opcode read cycle
ld A,@ptr (Machine code E0)

1. The value in the PC (0x0009) is placed on the program memory

address bus with a request to read the contents of that location. CPU
2. The 8-bit value at the location 0x0009 is the instruction opcode Program Memory Program Memory
0xE0. At the end of this read cycle, the PC is incremented to data bus address bus
0x000A. The opcode byte 0xE0 is fetched as shown in figure 8. 75
PC status
20
Before read 0x0009
00
After read 0x000A
75
21
14
90
20
00
0xE0 E0 0x0009

Program Memory

Figure 8. Instruction 1-opcode read cycle

ld A,@ptr (Machine code E0)

3. The control unit recognizes that the current instruction requires

performing a read operation to the data memory with the address
specified by the ptr register. The processor places the 16-bit value
ptr: 0x2000
of the ptr register on the data memory address bus and indicates
CPU
this is a read operation. A: ED

4. The data memory returns the contents to the processor and the Data Memory Data Memory
processor places it in accumulator A. The process is shown in data bus address bus
figure 9. 00
0x20 20
xx
xx
xx
ED 0x2000
xx PC status
xx Before read 0x000A

Data Memory After read 0x000A

Figure 9. Instruction 1-opcode read cycle

and A,#0x03 (Machine code 54 03)

1. The value in the PC (0x000A) is placed on the program memory

address bus with a request to read the contents of that location. CPU
2. The 8-bit value at the location 0x000A is the instruction opcode Program Memory
0x54. At the end of this read cycle, the PC is incremented to Program Memory address bus
0x000B. The program memory returns the opcode byte 0x54 to the data bus
E0
CPU.
0x54 54 0x000A
3. The control unit recognizes that the current instruction requires 03
0x03 0x000B
performing a read operation on the program memory to fetch the
70
operand for the AND operation. It then places the PC value on the
program memory address bus again with a read request. 02
05 PC status
4. The program memory returns the value 0x03 to the CPU. The PC is A ED
20 Before read 0x000A
incremented to 0x000C.
&& After 1st read 0x000B
D5
5. The CPU then performs an AND operation on the contents of B 03 After 2nd read 0x000C
accumulator A and the value 0x03 and places the result in A. 21
A 01
0A

Program Memory

Figure 10. Instruction 1-opcode read cycle

bnz next (Machine code 70 02)

1. The value in the PC (0x000C) is placed on the program memory address bus with a request to read the contents of that location.

2. The 8-bit value at the location 0x000C is the instruction opcode 0x70. At the end of this read cycle, the PC is incremented to
0x000D. The program memory returns the opcode byte 0x70 to the CPU.

3. The processor recognizes that this is a conditional branch instruction and it needs to fetch the branch offset from the program. So
it places the PC value (0x000D) on the program memory address bus with a read request. At the end of this read cycle, the
processor increments the PC to 0x000E.

4. The program memory returns the branch offset 0x02 to the CPU. The CPU checks the contents of accumulator A to determine
whether the branch should be taken. Let’s assume that A contains zero and the branch is not taken. The PC remains at 0x000E. If
A contains a nonzero value, the next instruction will be skipped.
inc 0x20 (Machine code 05 20)

1. The value in the PC (0x000E) is placed on the program memory address bus with a request to read the contents of that location.

2. The 8-bit value at the location 0x000E is the instruction opcode 0x05. At the end of this read cycle, the PC is incremented to
0x000F. The program memory returns the opcode byte 0x05 to the CPU.

3. The processor recognizes that it needs to increment a data memory location; this requires it to fetch an 8-bit address from the
program memory.

4. The processor places the value in the PC on the program memory address bus with a read request. At the end of the read cycle,
the PC is incremented to 0x0010 and the value 0x20 is returned to the CPU.

5. The processor places the value 0x20 on the data memory address bus with a request to read the contents of that location. The
data memory returns the value of that memory location at the end of the read cycle, which will be placed in the MDR.

6. The processor adds 1 to the MDR.

7. The processor places the contents on the data memory data bus and places the value 0x0020 on the data memory address bus
and indicates this is a write cycle. At the end of the cycle, the value in the MDR is written into the data memory location at 0x20.
dbnz 0x21, loop (Machine code D5 21 0A)

1. The value in the PC (0x0010) is placed on the program memory address bus with a request to read the contents of that location.

2. The 8-bit value at the location 0x0010 is the instruction opcode 0xD5. At the end of this read cycle, the PC is incremented to
0x0011. The program memory returns the opcode byte 0xD5 to the CPU.

3. The CPU recognizes that it needs to read a data memory address and a branch offset from the program memory.

4. Processor X performs two more read operations to the program memory. The program memory returns 0x21 and 0x0A. At the
end of these two read cycles, the PC is incremented to 0x0013.

5. Processor X places 0x21 on the data memory address bus with a read request. At the end of the read cycle, the value of the data
memory location at 0x21 is returned to the CPU which will be held in the MDR.

6. Processor X decrements the contents of the MDR. The contents of the MDR are then placed on the data memory data bus.
Processor X also places the address 0x21 on the data memory address bus with a write request to store the contents of the MDR
in data memory.

7. If the value stored in the MDR is not zero, processor X adds 0x0A to the PC and places the result in the PC (this causes a branch
behavior). Otherwise, the PC is not changed.