L4938N/ND

® L4938NPD

DUAL MULTIFUNCTION VOLTAGE REGULATOR

. STANDBY OUTPUT VOLTAGE PRECISION 5V

. ± 2%
OUTPUT 2 TRACKED TO THE STANDBY OUT-

. PUT
OUTPUT 2 DISABLE FUNCTION FOR
)
. STANDBY MODE
VERY LOW QUIESCENT CURRENT, LESS
t ( s
. THAN 250µA, IN STANDBY MODE
OUTPUT 2 VOLTAGE SETTABLE FROM 5 TO
d u c PowerDIP
(12+2+2)
SO20
(12+4+4)
PowerSO20

.. 20V
OUTPUT CURRENTS : I01 = 50mA, I02 = 500mA
r o s ) ORDERING NUMBERS: L4938N (PDIP)

. VERY LOW DROPOUT (max 0.4V/0.6V)

OPERATING TRANSIENT SUPPLY VOLTAGE
t e P c t ( L4938ND (SO)
L4938NPD (PSO20)

. UP TO 40V
POWER-ON RESET CIRCUIT SENSING THE
l e d u
. STANDBY OUTPUT VOLTAGE

b
POWER-ON RESET DELAY PULSE DEFINED s o
P r o DESCRIPTION

. BY THE EXTERNAL CAPACITOR

O
EARLY WARNING OUTPUT FOR SUPPLY UN-
- t e
The L4938N is a monolithic integrated dual voltage
regulators with two very low dropout outputs and ad-

. DERVOLTAGE

( s )
THERMAL SHUTDOWN AND SHORT CIRCUIT
s o l e ditional functions such as power-on reset and input
voltage sense. They are designed for supplying mi-
PROTECTIONS
c t b
crocomputer controlled systems specially in auto-
motive applications.

d u
PIN CONNECTION (top view)
- O
r o s )
e P c t (
l e t POWERDIP

d u SO20 PowerSO20

s o r o
O b N.C.

e
1
P 16 SI
N.C.
C7
1
2
20
19
SI
VS1
GND 1 20 GND

t
N.C. 2 19 N.C.
CT 2 15 VS1

e
EN 3 18 VS2 VS2 3 18 VO2

o
GND l
EN 3
4
14
13
VS2
GND
GND 4 17 GND VS1 4 17 ADJ

s
GND 5 16 GND SI 5 16 VO1

O b GND
RES
SO
5
6
7
12
11
10
GND
VO2
VO2
GND
GND
RES
6
7
8
15
14
13
GND
GND
VO2
N.C.
CT
EN
6
7
8
15
14
13
SO
RESET
N.C.
VO1 8 9 ADJ SO 9 12 VO2 N.C. 9 12 N.C.

D95AT156
VO1 10 11 ADJ GND 10 11 GND
D93AT004 D95AT169A

April 1999 1/12

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
 L4938N - L4938ND - L4938NPD

BLOCK DIAGRAM

VS1 VO1

1.23V
REFERENCE
REG1

( s )
VS2
c t VO2

d u
EN

r o s ) ADJ

REG2

e P c t (
l e t d u
1.23V

s o 2µ r o CT

O b e P RES

- l e t
s )
RESET
( o
2.0V

c t b s
u
SO
SI
d - O
r o s )
SENSE
1.23V

e P c t (
(optional)
GND

l e t d u D94AT143A

s o r o
O b
THERMAL DATA

e P
Symbol

l e t
Rthj-case
Parameter
Thermal Resistance Junction-Case Max.
Powerdip
14
PowerSO20
<2
SO20
–
Unit
°C/W

s o
Rthj-amb Thermal Resistance Junction-Ambient Max. 90 – 20 °C/W

O b

2/12
 L4938N - L4938ND - L4938NPD

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VS DC Supply Voltage 28 V
Transient Supply Voltage (T < 1s) 40 V
Tj, Tstg Junction and Storage Temperature Range –55 to 150 °C
ISI Sense Input Current (VSI ≤0.3V or VSI > VS) ±1 mA
IEN Enable Input Current (VEN ≤0.3V) ±1 mA
VEN Enable Input Voltage VS
VRES, VSO Reset and Sense Output Voltage 20 V
IRES, ISO Reset and Sense Output Current 5 mA
PD Power Dissipation

( s ) 875 mW
Note : The circuit is ESD protected according to MIL–STD–883C.

c t
d u
APPLICATION CIRCUIT
r o s )
e P c t (
l e t d u
s o r o
O b e P
-VS1

l e t VO1

(
CS

s ) o
CO1

c t b s
d u - O REFERENCE
REG1
1.23V

r o s ) VO2

e P c t ( VS2
ADJ

l e t d u
EN

REG2
CO2

s o r o CT
CT

O b e P 1.23V
2µ RES

l e t 2.0V
RRES

VO1

s o RESET
RSO

b
SI
SO

O SENSE
(optional)
1.23V
GND

D94AT144A

CS ≥ 1µF ; C01 ≥ 6µF ; C02 ≥ 10µF, ESR < 10Ω at 10KHz

3/12
 L4938N - L4938ND - L4938NPD

ELECTRICAL CHARACTERISTICS (VS = 14V; –40°C ≤ TJ ≤ 125°C unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VS Operating Supply Voltage 25 V
VO1 Standby Output Voltage 6V ≤ VS ≤ 25V 4.90 5.00 5.10 V
1mA ≤ IO1 ≤ 50mA
VO2 - VO1 Output Voltage 2 Tracking Error 6V ≤ VS ≤ 25V –25 +25 mV
(note 1) 5mA ≤ IO2 ≤ 500mA
Enable = LOW
IADJ ADJ Input Current IO1 = 1mA; IO2 = 5mA –1 0.1 1 µA
VDP1 Dropout Voltage 1 IO1 = 10mA 0.1 0.25 V

)
IO1 = 50mA 0.2 0.4 V
VIO1 Input to Output Voltage
Difference in Undervoltage
VS = 4V, IO1 = 35mA 0.4

t ( s V

Condition

u c
VDP2 Dropout Voltage 2 IO1 = 100mA
IO1 = 500mA
o d
0.2
0.3
0.3
0.6
)
V
V
VIO2 Input to Output Voltage VS = 4.6V, IO1 = 350mA
r 0.6
s V
Difference in Undervoltage
Condition
t e P c t(
VOL 1.2 Line Regulation 6V ≤ VS ≤ 25V
IO1 = 1mA; IO2 = 5mA
l e d u 20 mV

VOLO1 Load Regulation 1 1mA ≤ IO1 ≤ 50mA

s o r o 25 mV
VOLO2 Load Regulation 2
b
5mA ≤ IO2 ≤ 500mA

e P 50 mV

-O t
ILIM1 Current Limit 1 VO1 = 4.5V 55 100 200 mA
VO1 = 0V (note 2)
) le 25 50 100 mA

s so
ILIM2 Current Limit 2 VO2 = 0V 550 1000 1700 mA
IQSB
t ( b
Quiescent Current Standby Mode IO1 = 0.3mA; TJ < 100°C
(output 2 disabled)
c VEN ≥ 2.4V

d u VS = 14V
- O 210 290 µA
µA
o VS = 3.5V 340 850

r (t s)
IQ Quiescent Current IO1 = 50mA 30 mA

e P c
IO1 = 500mA

ENABLE
e t u
VENL

s ol r o d
Enable Input LOW Voltage
(output 2 active)
–0.3 1.5 V

O b VENH

e P
Enable Input HIGH Voltage 2.4 7 V
VENhyst
IEN
l et
Enable Hysteresis
Enable Input Current 0V < VEN < 1.2V
30
–10
75
–1.5
200
–0.5
mV
µA

s o 2.5V < VEN < 7V –1 0 +1 µA

O b

4/12
 L4938N - L4938ND - L4938NPD

ELECTRICAL CHARACTERISTICS (continued)

RESET

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VRt Reset Low Threshold Voltage Vo1 -0.4 4.7 Vo1 -0.1 V
VRth Reset Threshold Hysteresis 50 100 200 mV
tRD Reset Pulse Delay CT = 100nF; tR > 100µs 55 100 180 mV
tRR Reset Reaction Time CT = 100nF 1 10 50 µs
VRL Reset Output LOW Voltage RRES = 10KΩ to V01 0.4 V
VS = 1.5V

(s)
ILRES Reset Output HIGH Leakage VRES = 5V 1 µA
VCTh Delay Comparator Threshold 2.0 V
VCTh, hyst Delay Comparator Threshold
Hysteresis
100

u ct mV

SENSE
o d )
VSlth Sense Threshold Voltage

e Pr
1.16 1.23

c t(
1.35 s V
VSlth, hyst
VSOL
Sense Threshold Hysteresis
Sense Output LOW Voltage VSI = 1,16V; VS ≥ 3V
l e t 40 100

d u
200
0.4
mV
V
RSO = 10KΩ to V01

s o r o
ILSO Sense Output Leakage VSO = 5V; VSI ≥ 1.5V

O b e P 1 µA

2 : Foldback characteristic
- le t
Note : 1 : VO2 connected to ADJ.VO2 can be set to higher values by inserting an external resistor divider.

( s ) o
FUNCTIONAL DESCRIPTION
c t b s The current consumption of the device (quiescent

d u
The L4938N is based on the STMicroelectronics
modular voltage regulator approach. Several out-
- O current) is less than 250µA when output 2 is dis-
abled (standby mode). The dropout voltage is con-

r o
standing features and auxiliary functions are pro-
s ) trolled to reduce the quiescent current peak in the

e P
vided to meet the requirements of supplying the mi-
croprocessor systems used in automotive applica-
ct ( undervoltage region and to improve the transient
response in this region.
tions.
l e t d u
Furthermore the device is suitable also in other ap-
The quiescent current is shown in fig. 2 as a function
of the supply input voltage 2.
o r o
bs
plications requiring two stabilized voltages.
OUTPUT 2 VOLTAGE

O e P
The modular approach allows other features and
The output 2 regulator uses the same output struc-

l e
STANDBY REGULATOR
t
functions to be realized easily when required.
ture as the standby regulator, but rated for an output
current of 500mA.

s o
The standby regulator uses an Isolated Collector The output 2 regulator works in tracking mode with

O b
Vertical PNP transistor as the regulating element.
This structure allows a very low dropout voltage at
currents up to 50mA. The dropout operation of the
standby regulator is maintained down to 2V input
supply voltage. The output voltage is regulated up
to the transient input supply voltage of 40V. This fea-
ture avoids functional interruptions which could be
generated by overvoltage pulses.
The typical curve of the standby output voltage as a
function of the input supply voltage is shown in fig. 1.
the standby output voltage as a reference voltage
when the output 2 programming pin ADJ is con-
nected to VO2. By connecting a resistor divider R1,
R2 to the pin ADJ as shown in fig. 3, the output volt-
age 2 can be programmed to the value :
VO2 = VO1 (1 + R1/R2)
The output 2 regulator can be switched off via the
Enable input.
If a fixed 5 regulation is required ADJ Pin has to be
connected to V02 Pin.
5/12
 L4938N - L4938ND - L4938NPD

Figure 1 : Output Voltage vs. Input Voltage.

( s )
c t
d u
r o s )
e P c t (
l e
Figure 2 : Quiescent Current vs. Supply Voltage.
t d u
s o r o
O b e P
- l e t
400µ
( s ) o
c t b s
d u - O
r o
200µ
s )
e P c t (
l e t d u
s o r o
O b e P
e t
Figure 3 : Programmable Output 2 Voltage with External Resistors.
l
s o
O b

6/12
 L4938N - L4938ND - L4938NPD

RESET CIRCUIT occurs. The nominal reset delay is generated for

The block circuit diagram of the reset circuit is shown
in fig. 4. The reset circuit supervises the standby out-
put voltage. The reset threshold of 4.7V is defined
by the internal reference voltage and the standby
output divider.
The reset pulse delay time tRD, is defined by the
charge time of an external capacitor CT :
CT x 2V
tRD =
2µA
The reaction time of the reset circuit depends on the
discharge time limitation of the reset capacitor CT
and is proportional to the value of CT.
The reaction time of the reset circuit increases the
d u
noise immunity. In fact, if the standby output voltage
r o nected to GND. In this case the St-by quiescent cur-
standby output voltage drops longer than the time
necessary for the complete discharging of the ca-
pacitor CT. This time is typically equal to 50µs if
CT = 100nF. The typical reset output waveforms are
shown in fig. 5.
SENSE COMPARATOR
This circuit compares an input signal with an internal
voltage reference of typically 1.23V. The use of an
external voltage divider makes the comparator very
flexible in the application. This function can be used
to supervise the input voltage - either before or after
s )
the protection diode - and to give additional informa-
(
c
ings.t
tion to the microprocessor such as low voltage warn-
If this feature is not used SI and SO have to con-

s )
rent (14V) increases from 290µA to 300µA.
drops below the reset threshold for a time shorter

e P
than the reaction time tRR, no reset output variation
c t (
l
Figure 4: Block Diagram of the Reset Circuit. e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

7/12
 L4938N - L4938ND - L4938NPD

Figure 5 : Typical Reset Output Waveforms.

( s )
c t
d u
r o s )
1.5V

e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

8/12
 L4938N - L4938ND - L4938NPD

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 20.0 0.787

( s )
E 8.80 0.346

c t
e 2.54 0.100

d u
e3 17.78 0.700
r o s )
F 7.10
e
0.280P c t (
I 5.10
l e t
0.201
d u
L 3.30
s o Powerdip
0.130
r o 16
O b e P
Z 1.27

- l t
0.050

e
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

9/12
 L4938N - L4938ND - L4938NPD

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.6 0.142 MECHANICAL DATA
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004
b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013
D (1) 15.8 16 0.622 0.630
D1 9.4 9.8 0.370 0.386
E 13.9 14.5 0.547 0.570

)
e 1.27 0.050
e3
E1 (1) 10.9
11.43
11.1 0.429
0.450

t
0.437
( s
E2 2.9
c
0.114
u
E3
G
5.8
0
6.2
0.1
0.228
0.000
o d 0.244
0.004
)
H 15.5 15.9 0.610
P r 0.626
( s
h 1.1

t e t
0.043
c
JEDEC MO-166
L
N
0.8 1.1 0.031
10˚ (max.)
l e d u
0.043

S
o PowerSO20
8˚ (max.)

s r o
T 10

O b P
0.394

e
(1) "D and F" do not include mold flash or protrusions.

- Critical dimensions: "E", "G" and "a3"

l e t
- Mold flash or protrusions shall not exceed 0.15 mm (0.006").

-
( s ) o
c t b s
N

d u N

- O R

r o s ) a2 A
c

e P b

c t ( DETAIL A
e DETAIL B
E
a1

l e t d u e3
DETAIL A

o o
H lead

b s P r D

O t e a3 slug

o l e DETAIL B

s
20 11 0.35
Gage Plane

b
-C-

O
S SEATING PLANE
L
G C
BOTTOM VIEW (COPLANARITY)
E2 E1

E3

1 10

PSO20MEC
D1
h x 45

10/12
 L4938N - L4938ND - L4938NPD

mm inch
DIM. OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

( s )
c t
E 7.4 7.6 0.291 0.299

d u
e 1.27 0.050
r o s )
H 10 10.65 0.394

e P 0.419
c t (
h 0.25 0.75 0.010
l e t d
0.030u
s o r o
L 0.4 1.27
b
0.016

O e P 0.050
SO20
K 0˚ (min.)8˚ (max.)
- l e t
( s ) o
c t b s
d u - O L

r o s ) h x 45˚

e P c t (
l e t d u
A

s o B
r o e K A1 C

O b e P H

l e t D

s o
O b 20 11

1 0
1

SO20MEC

11/12
 L4938N - L4938ND - L4938NPD

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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