mm 40 60 80 100 120

40
16. Deep Submicron Issues

J. A. Abraham

Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M, VLSI I
Fall 2010
80
October 25, 2010

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 1 / 23
 Ideal Transistor I-V

mm 40 60 80 100 120

Shockley first-order transistor models

40

0  Vgs < Vt cutoff

 
Vds
Ids = β Vgs − Vt − 2 Vds Vds < Vdsat linear

 β (V − V )2

Vds > Vdsat saturation
60 2 gs t

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 1 / 23
 Ideal nMOS I-V Plot

180 mm 40
nm TSMC process 60 80 100 120

40
Ideal Models
β = 155(W/L) µA/V 2
Vt = 0.4 V
V
60DD = 1.8 V

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 2 / 23
 Simulated nMOS I-V Plot

180 mm
nm TSMC process
40 60 80 100 120
BSIM3 3V3 SPICE models

40
What differs?
Less ON current
No square law
60
Current increases in
saturation

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 3 / 23
 Velocity Saturation

We assumed carrier velocity ∝ E-field

mm 40 60 80 100 120
ν = µElat = µVds /L

Carriers scatter off atoms

40 reaches ν
Velocity sat
Electrons: 6 − 10 × 106
cm/s
Holes: 4 − 8 × 106 cm/s
60model
Better

µElat
ν= Elat
=⇒ νsat = µEsat
1 + 80
Esat

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 4 / 23
 Velocity Saturation I-V Effect

mm 40 ON current
Ideal transistor 80 V 2
60 increases with 100 120
DD

W (Vgs − Vt )2 β
Ids = µCox = (Vgs − Vt )2
L 2 2
40
Velocity-saturated ON current increases with VDD

Ids = Cox W (Vgs − Vt )νmax

Real
60 transistors are partially velocity saturated
Approximate with α-power law model
α
Ids ∝ VDD

80 1 < α < 2 determined empirically

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 5 / 23
 α-Power Model


mm 400

 60Vgs < Vt 80 cutoff 100 120
Vds
Ids = Idsat V Vds < Vdsat linear
 dsat
Idsat Vds > Vdsat saturation


40

β
Idsat = Pc (Vgs − Vt )α
2

= Pν (Vgs − Vt )α/2
Vdsat60
α, β, Pc and Pν are
parameters determined
empirically from a curve-fit of
80
I-V characteristics

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 6 / 23
 Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
mm Region between
40
n and p with no carriers
60 80 100 120
Width of depletion Ld region grows with reverse bias
Lef f = L − Ld
Shorter Lef f = more current
Ids increases with Vds
40 Even in saturation

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 7 / 23
 Channel Length Modulation I-V

β
(Vgs − Vt )2 (1 + λVds )
I =
mm 2 60 40ds 80 100 120
λ = channel length modulation coefficient
Not feature size
Empirically fit to I-V characteristics
40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 8 / 23
 Body Effect
Vt : gate voltage necessary to invert channel
Increases if source voltage increases because source is
mm 40 60 80 100 120
connected to the channel
Increase in Vt with Vs is called the body effect
Body Effect Model
40 p p 
Vt = Vt0 = γ φs + Vsb − φs

φs = surface potential at threshold

φ60s = 2νT ln( NnAi )
Depends on doping level NA
As well as intrinsic carrier concentration ni
γ = body effect coefficient
80 √
tox p 2qSi NA
γ= 2qSi NA =
ox Cox
ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 9 / 23
 OFF Transistor Behavior
What about current in cutoff?
Simulated results
mm 40 don’t match
60 measurements
80 100 120
What differs?
Current doesnt go to 0 in cutoff

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 10 / 23
 Leakage Sources

Subthreshold conduction
mm Transistors
40 can’t abruptly
60 turn ON or
80OFF 100 120
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
40 Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source of leakage in
modern transistors

Subthreshold
60 Leakage
Subthreshold leakage is exponential with Vgs
Vgs −Vt
 −Vds

Ids = Ids0 e nνT
1−e νT
, Ids0 = βνT2 e1.8
80
n is process dependent, typically 1.4 – 1.5
ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 11 / 23
 Other Leakage Sources
Drain-Induced Barrier Lowering (DIBL)
Drain Voltage40also affects60Vt (Vt0 = Vt80− ηVds )
mm 100 120
High drain voltage causes subthreshold leakage to increase

Junction Leakage
40
Reverse-biased
 V p-n junctions have some leakage
D
ID = IS e νT − 1

Is depends on doping levels

60 As well as area and perimeter of diffusion regions
Typically < 1 f A/µm2

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 12 / 23
 Gate Leakage

Carriers may tunnel thorough very thin gate oxides

mm 40 60 80 100 120
Predicted tunneling current (from Song, 2001)

Negligible for older

processes
40
Becoming critically
important for nanoscale
transistors
However,
60 use of metal
gates and rare-earth
dielectrics (Hf) may
reduce this significantly
80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 13 / 23
 Temperature Sensitivity
Increasing temperature
Reduces mobility
mm Reduces 40
Vt 60 80 100 120
ION decreases with temperature
IOF F increases with temperature

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 14 / 23
 So What?

mm 40 60 80 100 120

So what if transistors are not ideal?

They still behave like switches, and isn’t that enough for
40 digital logic?
But these effects matter for . . .
Supply voltage choice
Logical effort
Quiescent power consumption
60 Pass transistors
Temperature of operation

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 15 / 23
 Parameter Variations

Transistors have uncertainty in parameters

mm Process: 40
Lef f , Vt , tox 60
of nMOS and80pMOS 100 120
Vary around typical (T) values

40

Fast (F)
Lef f : short
Vt : low
60 tox : thin
Slow (S): opposite

80
Not all parameters are independent for nMOS and pMOS
ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 16 / 23
 Environmental Variation

mm 40 60 80 100 120

VDD and T also vary in time and space

Fast:
40 VDD : high
T : low
Corner Voltage Temperature
F 1.98 0℃
T 60 1.8 70℃
S 1.62 125℃

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 17 / 23
 Process Corners
Process corners describe worst case variations
mm If a design
40works in all60
corners, it will
80probably work
100 for any 120
variation
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
40
Voltage
Temperature

Important Corners
60
Some critical simulation corners include
Purpose nMOS pMOS VDD Temp
Cycle time S S S S
Power F F F F
80
Subthreshold leakage F F F S
Pseudo-nMOS S F ? ?
ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 18 / 23
 Causes of Variations?

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 19 / 23
 Features Smaller than Wavelengths
What is drawn is not what is printed on silicon
mm 40 60 80 100 120

40

60

80

Source: Raul Camposano, Synopsys

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 20 / 23
 Random Dopant Fluctuations

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 21 / 23
 Dynamic Temperature Variations

Thermal Map – 1.5 GHz Itanium Chip

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 22 / 23
 Dynamic Voltage and Power Variations

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 16. Deep Submicron Issues J. A. Abraham, October 25, 2010 23 / 23