Computer Hardware Engineering (IS1200) Computer Organization and Components (IS1500)

1
Computer Hardware Engineering (IS1200)

Computer Organization and Components (IS1500)
Fall 2017
Lecture 7: Combinational Logic
Optional for IS1200, compulsory for IS1500
Fredrik Lundevall
Slides by David Broman and Fredrik Lundevall
Part I Part II Part III

David Broman Gates and Building Blocks: Multiplexers, Logisim
dbro@kth.se Boolean Algebra Decoders, and Adders Demo
Slides version 2.0
Course Structure
Module 1: C and Assembly
Module 4: Processor Design
Programming
LE1 LE2 LE3 EX1 LAB1 LE9 LE10 EX4 S2 LAB4
LE4 S1 LAB2
Module 2: I/O Systems Module 5: Memory Hierarchy
LE5 LE6 EX2 LAB3 LE11 EX5 S3
Module 3: Logic Design PROJ Module 6: Parallel Processors

(IS1500 only) START and Programs
LE7 LE8 EX3 LD-LAB LE12 LE13 EX6 S4
Proj. Expo LE14

Gates and Building Blocks: Multiplexers, Logisim
Boolean Algebra Decoders, and Adders Demo
3
Abstractions in Computer Systems

Computer
Computer System
System Networked Systems and Systems of Systems
Application
Application Software
Software
Software
Operating
Operating System
System
Instruction
Instruction Set
Set Architecture
Architecture Hardware/Software Interface
Microarchitecture
Microarchitecture
Logic
Logic and
and Building
Building Blocks
Blocks Digital Hardware Design
Digital
Digital Circuits
Circuits
Analog
Analog Circuits
Circuits
Analog Design and Physics
Devices
Devices and
and Physics
Physics

Agenda
Part I
Gates and Boolean Algebra
Part II Part III

Building Blocks: Multiplexers, Logisim Demo
Decoders, and Adders

5
Part I
Gates and Boolean Algebra

6
Logic Gates (1/3)
AND, OR, NOT, and BUF
A A
AND Y OR Y
B A B Y B A B Y
0 0 0 0 0 0
0 1 0 0 1 1
This kind of table is 1 0 0 1 0 1
called a truth table. 1 1 1 1 1 1
NOT A Y BUF A Y
A Y A Y
0 1 Looks like not, 0 0
The small circle (called a
1 0 but has no circle. 1 1
bubble) inverts the signal.
Buffer. Logically the
NOT is also called an same as a wire. Important
inverter. because of technology limitations.
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The output of a CMOS gate

Transistors are used as on/off switches in digital circuits.
Supply voltage, logic "1": +3.3 Volts Channel, open or closed

depending on control input.
P-channel MOS transistor
Turning on the upper
transistor connects
Control input. A logic "1" input supply voltage to output.
turns off the P-channel MOS transistor.
Output
Turning on the lower
A logic "1" input turns on transistor connects
the N-channel MOS transistor. ground to output.
N-channel MOS transistor
Ground, logic "0": 0 Volts

8
Logic Gates (2/3)
NAND, NOR, XOR, and XNOR
A A
NAND Y NOR Y
B A B Y B A B Y
0 0 1 0 0 1
0 1 1 0 1 0
NOT AND. Note the 1 0 1 NOT OR. 1 0 0
Small bubble at the end. 1 1 0 1 1 0
A A
XOR Y XNOR Y
B A B Y B A B Y
0 0 0 0 0 1
0 1 1 0 1 0
Exclusive OR, 1 0 1 Exclusive NOT OR. 1 0 0
pronounced “ex-or”. 1 1 0 1 1 1

9
Logic Gates (3/3)
Multi-Input Logic Gates
Gates can be generalized to have more than two inputs. For instance:
A
XOR3 B Y
AND3 C
Exclusive OR gate with 3 inputs.
AND gate with 3 inputs.
A B C Y
An N-input XOR
0 0 0 0
gate is a parity
gate. The output
0 0 1 1
is 1 when an odd 0 1 0 1
number of inputs 0 1 1 0
NOR5
are 1. 1 0 0 1
1 0 1 0
NOT OR gate with 5 inputs. 1 1 0 0
1 1 1 1

10
E
Combinational Circuit
1 0 This circuit is
A=1 combinational because its
1 outputs depend only on its
Y =1
inputs. The circuit is
B=0
0 memoryless, that is, it has
1
C=1
1 no memory.
We will
introduce
memory in
0 1 Lecture 8
A=0 1
0 Y =1
1 Observe that this (rather
B=1 0 useless) circuit always
C=1
1 outputs 1. As a logic formula,
this is called a tautology.

11
E
Problematic Circuits
Unstable circuit.
What is the value of Q?
Q
Answer: it oscillates. This circuit is
called a ring oscillator.
Illegal value (X)

What is the value of Q?
A=0
Answer: Q = X, called an unknown or illegal
Q value. For example, when a wire is driven to
B=1 both 0 and 1 at the same time.
This situation is called contention

(and can damage the transistors in the gates).

12
Floating Values and Tristate Buffers
The output of a tri-state™ (or three-state) buffer has a high

impedance if the output enable signal E is not active.
E A Y
E 0 0 Z
A Y 0 1 Z
1 0 0
1 1 1
Commonly used in buses to When the enable signal The output floats
connect multiple chips. As long is not active, the output when both output
as only one buffer at a time is is said to be floating transistors are
enabled, contention is avoided. (using symbol Z). turned off.

13
Boolean Algebra (1/4)
Truth Tables and Sum-of-Products Form
We can create a boolean expression
A B C Y from the truth table
The AND of two or more
0 0 0 0 variables is called a product.
0 0 1 0
0 1 0 1 ABC + ABC + ABC AND can be written
0 1 1 0 using “no space” or
1 0 0 0 using a dot, e.g. A•B•C
1 0 1 1 The line over a variable
0 means that the inverse OR is written using
1 1 1
(complement) of the the + symbol.
1 1 1 0
variable is used (NOT).
Sometimes a prime is This form is called
used instead: sum-of-products
A truth table with some A'BC' + AB'C + ABC' (surprise!)
(random) output.

14
Boolean Algebra (2/4) E
Some Theorems
Theorem Dual Name
Exercise:
A•1 = A A+0 = A Identity Derive the simplest
A•0 = 0 A+1 = 1 Null Element form of expression
A•A = A A+A =A Idempotency BA + AB + A
A=A Involution Solution:

A•A = 0 A+A = 1 Complements BA + AB + A
A•B = B•A A+B = B+A Commutativity = AB + AB + A Commutativity
(A•B)•C = (A+B)+C = = A(B+B) + A Distributivity

Associativity
A•(B•C) A+(B+C) = A•1 + A
Complements
(dual)
(A•B)+(A•C)= (A+B)•(A+C)= Distributivity =A+A Identity
A•(B+C) A+(B•C) Indempotency
Note! Not as traditional algebra = A (dual)

15
De Morgan’s Theorem
Theorem Dual
A1 • A2 • A3 … = A1 + A2 + A3 … =
(A1 + A2 + A3 …) (A1 • A2 • A3 …)
Augustus De Morgan,
The law shows that these gates are equivalent British mathematician and
logician (1806 – 1871).
A A A A
B
Y = Y
B
Y = Y
B B
AB = A + B = Y A+B = A B = Y
Important law. For CMOS logic, NAND and NOR But how can we know
gates are preferred over AND and OR gates. that this theorem is true?

16
Proof by Perfect Induction
Perfect Induction = Proof by Exhaustion = Proof by Cases
Prove the De Morgan’s Note that these two

Theorem for three variables columns are equal
ABC = A + B + C
A B C ABC A+B+C
0 0 0 1 1
Proof by perfect induction.
0 0 1 1 1
Exhaustively show all cases
in a truth table. 0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0

17
Part II
Building Blocks:
Multiplexers, Decoders,
and Adders

18
Abstractions in Computer Systems

Computer
Computer System
System Networked Systems and Systems of Systems
Application
Application Software
Software
Software
Operating
Operating System
System
Instruction
Instruction Set
Set Architecture
Architecture Hardware/Software Interface
We can combine
Microarchitecture
Microarchitecture logic gates and form
digital building
Logic
Logic and
and Building
Building Blocks
Blocks Digital Hardware Design blocks
Digital
Digital Circuits
Circuits
Analog
Analog Circuits
Circuits
Analog Design and Physics
Devices
Devices and
and Physics
Physics

19
Combinational Blocks (1/3) E
Multiplexers
The control signal S
What is this? It’s a 2:1 Multiplexer. selects which input bit
that is sent to the output.
S D1 D0 Y S
0 0 0 0 2 bits for the
data input D0 0
0 0 1 1 Y 1 output
D1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 One possible
D0
1 1 0 1 implementation.
1 1 1 1 S Y Convince
yourself of its
D1 correctness!

20
Combinational Blocks (2/3) E
Multiplexers
A multiplexer can be seen as a simple A 4:1 multiplexer can be defined
switch, selecting which signal that should hierarchically.
pass through the block.
S1 S0 S1 S0
S0
D0 D0 00
D1 D1 01
D0 0
Y Y S1
D2 D2 10 D1 1
D3 D3 11
0
S0 Y
1
4:1 multiplexer (4 inputs, 1 output).
D2 0
What is the output signal Y for the D3 1
4:1 multiplexer with these inputs?
D0 = 1, D1 = 0, D2=1, D3=0,
S1 = 1, S0 = 0 Answer: Y = 1
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Combinational Blocks (3/3)
Decoders
A decoder has N inputs and 2N outputs.
Asserts exactly one output.
Decoder A1 A0 Y3 Y2 Y1 Y0
A0
00 Y0 0 0 0 0 0 1
01 Y1 0 1
A1 10 Y2
0 0 1 0
11 Y3 1 0 0 1 0 0
1 1 1 0 0 0
2:4 decoder (2 inputs, 4 output).
Note that only one

signal is 1 on each
row. This is called
one-hot.

22
Arithmetic Circuits and Numbers (1/3) E
Half and Full Adders
A half adder has a carry out signal. A full adder has
A B
both carry out and
carry in signals.
Cout + Cin
A B How can we add
bigger numbers? S
Cout + Idea: Chain A B Cin Cout S
S adders together… 0 0 0
0 0 1
A B Cout S 0 1 0
0 1 1
0 0 0 0
1 0 0
0 1 0 1
1 0 1 Exercise:
1 0 0 1 1 1 0 Complete the
1 1 1 0 1 1 1 truth table

23
Arithmetic Circuits and Numbers (1/3) E
Half and Full Adders
A half adder has a carry out signal. A full adder has
A B
both carry out and
carry in signals.
Cout + Cin
A B How can we add
bigger numbers? S
Cout + A B Cin Cout S
Idea: Chain
S adders together… 0 0 0 0 0
0 0 1 0 1
A B Cout S 0 1 0 0 1
0 1 1 1 0
0 0 0 0
1 0 0 0 1
0 1 0 1
1 0 1 1 0 Exercise:
1 0 0 1 1 1 0 1 0 Complete the
1 1 1 0 1 1 1 1 1 truth table

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Arithmetic Circuits and Numbers (2/3)
Carry Propagate Adders
An N-bit carry propagate adder (CPA) Three common implementations

sums two N-bit inputs. of CPAs are:
Note the notation • Ripple-carry adder

A B Simple but slow.
N N for an N-bit bus.
• Carry-lookahead adder
Cout + Cin Faster, divides into blocks.
N
See course book • Prefix adder
S (advanced part) Even faster. Used in
today's computers.
32-bit ripple-carry adder
A31 B31 A30 B30 A1 B1 A0 B0
Cout + + + Cin
C30 C29 C1 C0 +
S31 S30 S1 S0
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Arithmetic Circuits and Numbers (3/3)
Subtract
Subtract is simple to implemented with a We can easily create a circuit where

carry propagate adder (CPA): K = 0 results in A + B and
Invert input signal B and set Cin = 1. K = 1 results in A - B
K
B B 0
N
1
A
N N A N
N
Cout + Cin = 1 Cout +
N
Coming up… N
S S
In lecture 9, we will generalize this idea
Note that setting carry in to 1 into an Arithmetic/Logic Unit (ALU), one
adds 1 to A + B. of the main components of a processor.
26
Part III
Logisim Demo

27
Logisim
Free graphical digital circuit simulator. Graphical Model Canvas

Used in the LD-LAB and in LAB4. Both for construction and simulation
Explorer Pane
Building blocks
and gates
Attribute Table
Configure
different
components

28
Some Different Notations in Logisim

Blue wire:
Adder (different symbol 4:1 1 bit floating
Splitter of bits
than in text books) Constant Multiplexer signal
Number
Dark green wire:
1 bit signal with value 0.
1 bit
input Decoder
2:4
Bright green wire:

1 bit signal with value 1 Orange write:
Incorrect bit width
1 bit output

29
Hardware Description Languages
Logisim is a simple graphical design

and simulation environment for
educational purposes.
For those who are interested,
see Harris & Harris (2012),
chapter 4. This is not part of
Professional hardware designers work in
the course.
textual Hardware Description Languages (HDL).
The two most commonly used HDLs in industry are:

• System Verilog. Used a lot in the USA. C-like syntax.
• VHDL. Used more in Europe. Ada-like syntax.

30
Reading Guidelines
Module 3: Logic Design
Lecture 7: Combinational Logic Design

• H&H Chapters 1.5, 2.1-2.4, 2.6, 2.8-2.9
Lecture 8: Sequential Logic Design

• H&H Chapters 3.1-3.3 (not 3.2.7),
3.4.1-3.4.3, 5.2.1-5.2.2, 5.5.5
Reading Guidelines
See the course webpage
for more information.

31
Summary
Some key take away points:
• Combinational logic design: Output is directly

dependent on input. There is no memory.
• Important components to remember: multiplexer,

decoder, and adder.
• Next lecture is about sequential logic design; circuits

with memory.
Thanks for listening!


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1

Computer Hardware Engineering (IS1200)

Part I Part II Part III

Module 2: I/O Systems Module 5: Memory Hierarchy

LE5 LE6 EX2 LAB3 LE11 EX5 S3

Module 3: Logic Design PROJ Module 6: Parallel Processors

Proj. Expo LE14

Part I Part II Part III

Abstractions in Computer Systems

Part I Part II Part III

Part II Part III

Part I Part II Part III

Part I Part II Part III

The output of a CMOS gate

Supply voltage, logic "1": +3.3 Volts Channel, open or closed

Ground, logic "0": 0 Volts

Part I Part II Part III

Part I Part II Part III

Part I Part II Part III

Part I Part II Part III

Illegal value (X)

This situation is called contention

Part I Part II Part III

Floating Values and Tristate Buffers

The output of a tri-state™ (or three-state) buffer has a high

Part I Part II Part III

Part I Part II Part III

A•A = A A+A =A Idempotency BA + AB + A

A=A Involution Solution:

(A•B)•C = (A+B)+C = = A(B+B) + A Distributivity

Part I Part II Part III

Part I Part II Part III

Perfect Induction = Proof by Exhaustion = Proof by Cases

Prove the De Morgan’s Note that these two

Part I Part II Part III

Part I Part II Part III

Abstractions in Computer Systems

Part I Part II Part III

Part I Part II Part III

Note that only one

Part I Part II Part III

Part I Part II Part III

Part I Part II Part III

An N-bit carry propagate adder (CPA) Three common implementations

Note the notation • Ripple-carry adder

Subtract is simple to implemented with a We can easily create a circuit where

Part I Part II Part III

Free graphical digital circuit simulator. Graphical Model Canvas

Part I Part II Part III

Some Different Notations in Logisim

Bright green wire:

Part I Part II Part III

Hardware Description Languages

Logisim is a simple graphical design

The two most commonly used HDLs in industry are:

Part I Part II Part III

Module 3: Logic Design

Lecture 7: Combinational Logic Design

Lecture 8: Sequential Logic Design

Part I Part II Part III

Some key take away points:

• Combinational logic design: Output is directly

• Important components to remember: multiplexer,