Course Title: Computer architecture

Course Code: CSE211

Assignment-CT3

Submitted By:

Name: Md Ali Sami Submitted To:

Name: MR. SYED AHSANUL KABIR

Student ID:183002109
Dept. of CSE GREEN UNIVERSITY OF
BANGLADESH
Department: CSE

Section: A

Submission Date: 10 /06 / 2020

1. A non-pipeline system takes 50 ns to process a task. The same task can be processed
In a six-segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of
The pipeline for 100 tasks. What is the maximum speedup that can be achieved?

Solve:

Total Number of tasks n = 100

Time taken by non-pipeline Tn = 50 ns

Time period of 100 tasks = ntn

= 100 x 50 = 5000 ns

Number of segment pipeline K = 6

Time period of 1 clock cycle = 10 ns

Total time required = (k + n - 1) tp

= (6 + 100 - 1)10

= 1050 ns

Speed up ratio S = 5000/1050

= 4.76

the maximum speedup that can be achieved S max = k = 6.

2. The outputs of four registers, Ro, R1, R2, R3, are connected through 4-to-1-line
Multiplexers to the inputs of another register, X. Each register is eight bits long. The
Required transfers are dictated by four timing variables To through T3 as follows:
To: X+RO T z: XR1 T2: X+ R2 ,T3:X+ R3.The timing variables are mutually exclusive, which
means that only one variable is Equal to 1 at any given time, while the other three are equal to 0.
Draw a block diagram showing the hardware implementation of the register transfers. Include
the Connections necessary from the four timing variables to the selection inputs of the
Multiplexers and to the load input of register X.

Solved:
T0,T1,T2,T3 four timing variable include 4:2 encoder to connect with two 4:1 mux which
load X register.

3. Design a 4-bit combinational circuit incremented by including a control input X. When

X=0, the circuits increments by one, but when X=1, the circuit increments by two.
Solve:
Fig. 4 bit synchronous binary counter.
4. The following page reference changes occur during a given time interval.
4 2 0 1 2 6 1 4 0 2 3 5 7
Determine the four pages that are resident in main memory after each page reference
Change if the replacement algorithm used is

(a) FIFO
4 2 0 1 2 6 1 4 0 2 3 5 7

4 4 4 1 1 1 1 1 0 0 0 5 5
2 2 2 2 6 6 6 6 2 2 2 7
0 0 0 0 0 4 4 4 3 3 3
H H

(b) LRU
4 2 0 1 2 6 1 4 0 2 3 5 7
 4 4 4 1 1 1 1 1 1 2 2 2 7
2 2 2 2 2 2 4 4 4 3 3 3
0 0 0 6 6 6 0 0 0 5 5
H H

(c) OPT.
4 2 0 1 2 6 1 4 0 2 3 5 7

4 4 4 1 1 1 1 4 4 4 4 5 5
2 2 2 2 6 6 6 6 6 3 3 3
0 0 0 0 0 0 0 2 2 2 7
H H H

5. Draw a diagram showing the structure of a four-dimensional hypercube network. List

All the paths available from node 7 to node 9 that use the minimum number of
Intermediate nodes.
6. Construct a diagram for a 4X4 omega switching network. Show the switch setting
Required to connect input 3 to output 1.
Fig. omega switching network

7. Specify a pipeline configuration to carry out the operation ((A *Bi) + (C*D)]. List the
Contents of all registers in the pipeline for i = 1 through 6. Also draw the space time
Diagram for pipeline.