UKSim 2009: 11th International Conference on Computer Modelling and Simulation

Design and Implementation of a 64-bit RISC Processor using VHDL

Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin1, Pranav Bhasker, Ishita Verma
Department of Electronics and Communication Engineering,
1
Department of Computer Science and Engineering Engineering,
Jaypee University of Information Technology,
Waknaghat, Solan, 173215, HP, INDIA
rohit.sharma@juit.ac.in

Abstract— In the present paper, we present the design
and implementation of a 64-bit reduced instruction set
(RISC) processor with built-in-self test (BIST) features. A
built-in self-test (BIST) or built-in test (BIT) is a
mechanism that permits a machine to test itself. Key
features of the design including its architecture, data
path, and instruction set are presented. The design is
implemented using VHDL and verified on Xilinx ISE
simulator. The processor is designed keeping in mind
specific applications. The proposed design may find
applications where automation and control is required.
Illustrations highlight the typical use of our processor in
bottling plants and control of robotic movements using
exhaustive simulations. Future applications may include
its use in vending machines, ATMs, mobile phones, and
portable gaming kits.
exhaustive set of test patterns is developed. A scheme
for meaningfully interpreting and understanding of the
test outputs is designed. The processor has been
designed keeping in mind specific applications where
automation and control is required. Some these
applications include vending machines, bottling plants,
control of robotic movements, and automatic teller
machine (ATM). The proposed design has 33
instructions set with MICA architecture. The design is
implemented on Xilinx ISE simulator and programmed
using VHDL.

Keywords-RISC, BIST, BIT, VHDL

I. INTRODUCTION
In today’s Integrated Circuits (ICs), Built-In-Self
Test (BIST) is becoming increasingly important as
designs become more and more complicated [1-5].
Keeping the structural fault coverage high along with
maintaining an acceptable design overhead is critical.
It is important to achieve a high level of reliability with
minimum cost and time. It is with this goal in mind
that BIST has become a major design consideration in
Design-For-Testability (DFT) methods. BIST is
beneficial in many ways: First, it can reduce
dependency on external Automatic Test Equipment
(ATE). In addition, BIST can provide at speed, in
system testing of the Circuit-Under-Test (CUT). This
is crucial to the quality component of testing. BIST can
overcome pin limitations due to packaging, make
efficient use of available extra chip area, and provide
more detailed information about the faults present. A
generic approach to BIST is shown in Fig 1. On a very
basic level, BIST needs a stimulus (the Test Pattern
Generator - TPG), a circuit to be tested (CUT) and a
way to analyze the results (ORA). Additionally, there
may be compression schemes for the TPG and the
ORA [4-5].
In this paper, a 64 bit RISC processor with limited
functionality is designed with an architecture that
supports BIST. The ALU is analyzed and an
Figure 1. A general schematic of BIST
The organization of the paper is as follows: In
section 2, we present the detailed design, architecture,
data path and instruction set of the proposed design.
Simulation results are also provided in this section. In
section 3, we discuss the potential applications of our
processor. In that its application in bottling plant and
control of robotic movement is discussed. The paper
concludes in section 4.
II. DESIGN
The instruction set, architecture, and data path are
discussed here. The processor is designed considering
MICA architecture and is implemented using VHDL.
The architecture of the ALU consists of two parts, the
Operation Architecture, which does the actual
operation of the ALU, and the Testing Architecture,
which comes into play only during testing. The
Operation Architectures consists of a five units, 4-bit
Carry Look Ahead adder (CLA), and a 4-bit AND, OR,
XOR and INVERTER gates. There is a PreCLA to
prepare the inputs based on the arithmetic operation to
be done. There is a MUX which uses the select pins to
select one of the results from the above five units. The
Testing Architecture has a ROM which has the

978-0-7695-3593-7/09 $25.00 © 2009 IEEE 568

DOI 10.1109/UKSIM.2009.30
 Figure 2. 64 Bit RISC Processor Architecture [5]

Figure 3. Data path for 64-bit RISC Processor [5]

discovered test patterns stored in. There is an address The data path and the architecture for the proposed
decoder to select which of the test patterns will be design are shown Fig. 2 and 3, respectively. TABLE 1
applied. There is a TestMUX, which depending on the gives the salient technical features of the proposed
value on the TestMode pin will present the test pattern processor. TABLE 2 provides detailed explanation of
or the actual inputs to be operated upon, to the the entire instruction set
Operation Architecture.

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 .TABLE 1 SALIENT FEATURES OF THE PROPOSED DESIGN

Features of the proposed design

Architecture MICA
Instructions 33
Instruction register 32 bit
Address counter 32 bits
Data memory 64 bits
Data bus 64 bits
Address bus 32 bits

TABLE 2 INSTRUCTION SET FOR THE 64-BIT RISC PROCESSOR

Instructions
ADD - Arithmetic Addition
1
2 IAND - Logical AND
3 SKIPZ – Skip on Zero
Usage: LTR src; Loads the current task register with the value specified in
4 LTR - Load Task Register (286+ privileged)
Description
Usage: ADD dest, src; Adds "src" to "dest" and replacing the original
contents of "dest". Both operands are binary.
Usage: AND dest, src; Performs a logical AND of the two operands
replacing the destination with the result.
Usage: skipz, Skips one clock cycle when data entered is zero.
"src".

Usage: LSL dest, src; Loads the segment limit of a selector into the
5 LSL - Load Segment Limit (286+ protected) destination register if the selector is valid and visible at the current privilege
level. If loading is successful the Zero Flag is set, otherwise it is cleared.
INOT - One's Complement Negation (Logical Usage: NOT dest; Inverts the bits of the "dest" operand forming the 1s
6
NOT) complement.
Usage: NEG dest; Subtracts the destination from 0 and saves the 2s
7 NEG - Two's Complement Negation
complement of "dest" back into "dest".
Usage: POP dest; Transfers word at the current stack top (SS: SP) to the
POP - Pop Word off Stack
8 destination then increments SP by two to point to the new stack top. CS is
not a valid destination.
Usage: PUSH src
PUSH immed (80188+ only); Decrements SP by the size of the
9 PUSH - Push Word onto Stack
operand (two or four, byte values are sign extended) and transfers one word
from source to the top (SS: SP).
SETS - Set if Signed (386+) Usage: SETS dest; Sets the byte in the operand to 1 if the Sign Flag is set,
10
otherwise sets the operand to 0.
Usage: ROL dest, count; Rotates the bits in the destination to the left
ROL - Rotate Left
11 "count" times with all data pushed out the left side re-entering on the right.
The Carry Flag will contain the value of the last bit rotated out.
Usage: ROR dest, count; Rotates the bits in the destination to the right
ROR - Rotate Right
12 "count" times with all data pushed out the right side re-entering on the left.
The Carry Flag will contain the value of the last bit rotated out.
Usage: SAL dest, count
SAL/SHL - Shift Arithmetic Left / Shift Logical
13 SHL dest, count; Shifts the destination left by "count" bits with
Left
zeroes shifted in on right. The Carry Flag contains the last bit shifted out.
Usage: SAR dest, count; Shifts the destination right by "count" bits with the
14 SAR - Shift Arithmetic Right current sign bit replicated in the leftmost bit. The Carry Flag contains the last
bit shifted out.
Usage: SETC dest; Sets the byte in the operand to 1 if the Carry Flag is set,
15 SETC - Set if Carry (386+)
otherwise sets the operand to 0.
Usage: SETO dest; Sets the byte in the operand to 1 if the Overflow Flag is
16 SETO - Set if Overflow (386+)
set, otherwise sets the operand to 0.
17 STC - Set Carry Usage: STC; Sets the Carry Flag to 1.
Usage: STI; Sets the Interrupt Flag to 1, which enables recognition of all
STI - Set Interrupt Flag (Enable Interrupts) hardware, interrupts. If an interrupt is generated by a hardware device, an End
18
of Interrupt (EOI) must also be issued to enable other hardware interrupts of
the same or lower priority.

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 Usage: SUB dest, src; The source is subtracted from the destination and the
19 SUB - Subtract
result is stored in the destination.
Usage: VERR src; Verifies the specified segment selector is valid and is
20 VERR - Verify Read (286+ protected) readable at the current privilege level. If the segment is readable, the Zero
Flag is set, otherwise it is cleared.
21 CLC - Clear Carry Usage: CLC; Clears the Carry Flag.
Usage: XOR dest, src; Performs a bitwise exclusive OR of the operands and
22 IXOR - Exclusive OR
returns the result in the destination
Usage: dest, sre; Performance a logical NAND of the two operands replacing
23 INAND –Logical NAND
the destination with the result.
Usage: ADD dest, src; Adds "src" to "dest" and replacing the original
ADDI – Add Immediate
24 contents of "dest" Both operands are binary. It performs immediate addition
i.e. takes half clock cycle than in add. Operation.
Usage: HLT; Halts CPU until RESET line is activated, NMI or maskable
HLT - Halt CPU
25 interrupt received. The CPU becomes dormant but retains the current CS: IP
for later restart.
26 SKIPN – Skip on Neg. Usage: skipn; Skips one clock cycle when NEG instruction is executed.
Usage: VERW src; Verifies the specified segment selector is valid and is
27 VERW - Verify Write (286+ protected) ratable at the current privilege level. If the segment is writable, the Zero Flag
is set, otherwise it is cleared.
28 CLR- Clear Usage: clr; It clears every flag used in processor.
Uses: ld dest; Transfer data at the current address to the destination then
29 LD – Loads Data from Address
increments address to the point of new address.
30 ST- Stores Data to Address Usage: st src; Transfers data from destination to the given address.
Usage: SAL dest, count
ISLL - Shift Logical Left
31 SHL dest, count; Shifts the destination left by "count" bits with
zeroes shifted in on right. The Carry Flag contains the last bit shifted out.
Usage: dest, src; Jumps the pointer from source to destination. Mainly used in
32 JAL – Jump and Link
selection of the desired register at the moment
Usage: br dest; Responsible for disabling the write enable for registers.
33 BR – Branch

Address and data to that address is shown by add [95:0]

(i.e 64 bit data and 23 bit address). ‘data [63:0}’ represents
the output data after all operations has been performed by
the processor. If we want to read the data from an address
then ‘rd’ is set to ‘1’ and for writing ‘wr’ is set tp ‘1’. ‘verr’
is to verify read operation and ‘verw’ is to verify write
operation. If at any point interrupt flag is set to ‘1’ then
computer is in state of halt and ‘hlt’ is set to ‘1’.

III. APPLICATIONS
The proposed processor has been designed for
applications where control of movements and automation is
important.
Figure 4. Simulation for 64-bit RISC Processor

Fig. 4 gives the simulated output obtained on the
XILINX ISE simulator. This 64 bit RISC processor works
on two clock cycles. ‘xclk’ is the external clock which is
always equal to one. ‘clk’ is the clock which triggers the
inputs and gives us the desired output. ‘rxdat’ triggers the
state of the registers except for segment registers and ‘txdat’
states the triggered state of register after data is passed
through registers. Similarly ‘rxstb’ triggers the state of
segment register and ‘txstb’ states the triggered state of
segment register after data is passed through segment
registers.
A. BOTTLING PLANT
Bottles start filling from the right side and boxes start to
move from the left side. Here four tracks of bottles are used
simultaneously therefore packing is made of four bottles.
When bottle reaches to the fourth position, box moves to the
first position. After that, bottle is dropped in the box and
hence, box moves one position ahead. In this way, when box
is at the fifth position, signal ‘lb’ is set to ‘1’ indicating to
lift the box.

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a. Flowchart c. Simulation Results

Figure 6 Simulation result of bottling plant

B. CONTROL OF ROBOTIC MOVEMENTS

When the forward button is pressed the robot moves in
Figure 5. Flowchart for Bottling Plant forward position and forward acknowledgement ‘fack’ is
sent to the user. When the downward button is pressed robot
In flow chart ‘a’ shows position of bottle and ‘b’ shows moves in backward position and backward
position of box. Following is the algorithm: acknowledgement ‘back’ is sent to the user. When both
buttons are pressed simultaneously then there is no
acknowledgement (i. e. robot remains still).
b. Algorithm
a=1, b=7, weight=0 a. Algorithm
loop a till a=8 fwd, fwdnew, bkwd, bkwdnew clk
a=a+1; wait for 15 secs If fwd=1 then
If (a=4) then loop fwd till fwd=0
drop bottle in box If fwd=1 then
a=a-1; robot moves forward
End If; End If;
If (a=5) then If fwd=0 then
report error in bottle machine report error in forward movement of
End If; robot
End loop; End If;
loop b till b=5 clk= clk+1;
b=b+1; wait till weight=1; fwd= fwdnew;
If (b=5) then End loop;
given signal to left box; End If;
b=b-1; If bkwd= 1 then
End If; loop bkwd till bkwd= 0
If (b=6) then If bkwd= 1 then
report error in packing machine robot moves backward
End if; End If;
End loop; If bkwd= 0 then
report error in backward movement
of robot
End If;
clk= clk+1;
bkwd= bkwdnew;
End loop;
End If;

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b. Simulation Results
Fig. 7 shows the simulated results obtained using XILINX
ISE simulator. The three conditions of forward, backward
and simultaneous movements are shown here by markers at
3 respective positions.
Figure 7. Simulation result
IV CONCLUSION
A 64-bit RISC processor with 33 instruction set has been
designed. Every instruction is executed in two clock cycles.
The design is verified through exhaustive simulations.
Some of the applications are presented. In the near future
more applications like the ATMs, mobile phones; portable
gaming kits can be implemented.
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