2018 3rd International Conference on Integrated Circuits and Microsystems

A 10 GS/s, 3-Bit ADC with Novel Decoder in SiGe BiCMOS Technology

Yu Shen3, Yi Zhang1, 2,3,4*, Lei Yang1,5, Yanhui Yang3, Yufeng Guo1,3, Xiaopeng Li1,5, Youtao Zhang1,5
1
National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology, Nanjing, 210023,
China
2
State Key Laboratory of Millimeter Waves, Nanjing, 210096, China
3
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and
Telecommunications, Nanjing, 210023, China
4
Post-Doctoral Research Center, JiangSu HengXin Technology Co., Ltd, Yixing, 214222, China
5
Nanjing GB Electronics Co., Ltd, Nanjing, 210016, China
*e-mail: nyzhangyi@njupt.edu.cn

Abstract—This paper presents a design of 10-GS/s, 3-bit
analog-to-digital converter in a 0.13 μm SiGe BiCMOS
technology for optical communication application. This fully
differential flash ADC includes a wide-bandwidth
track-and-hold amplifier, a high-resolution comparator array
and a novel differential decoder. By using our novel differential
decoder, this ADC design achieves better than 2.8 effective bits
for lower input frequencies and 2.5 effective bits for 1 GHz
input frequency at a sampling rate of 10 GS/s. This ADC
consumes 1.6 W with a 10 GS/s clock rate, while operating
from -5/-3.3 V power supplies and its core area is only occupies
1×1.2 mm2.
Keywords-flash ADC; SiGe BiCMOS; differential decoder;
10 GS/s
simulated results of this flash ADC is shown in Section IV.
The conclusions are drawn in Section V.
II. FLASH ADC ARCHITECTURE
As shown in Fig. 1, the proposed flash ADC consists of a
THA, a voltage comparator array with 7 comparators, a
thermometer-to-binary decoder and a differential resister
ladder. All the circuit modules adopt fully differential logic
to reduce common-mode noise and other parasitic effects.
The final output of the flash ADC are 3-bit binary
differential signals.
Vin_P/N Vi_P/N
THA

I. INTRODUCTION 7/8*Vref V[7]_P/N

With the rapid development of mobile communication 1/8*Vref

and optical communication, the speed of signal processing 6/8*Vref V[6]_P/N

becomes faster and faster, which will make a massive 2/8*Vref
requirement in the market for the ultra-high-speed ADCs.
5/8*Vref Bit2_P/N
High-performance ultra-high-speed ADCs increase the V[5]_P/N

amount of information that digital systems can acquire, 3/8*Vref

thereby increasing the competitiveness of the system. The Resister 4/8*Vref Comparator V[4]_P/N
Bit1_P/N

Ladder Decoder
Array
research of this ultra-high-speed ADC with a sampling rate 4/8*Vref
Bit0_P/N
of 10 GS/s is of great significance for mobile communication 3/8*Vref V[3]_P/N
and optical communication. 5/8*Vref
This paper describes a 3-bit 10-GS/s flash ADC designed 2/8*Vref V[2]_P/N
in a 0.13μm SiGe BiCMOS technology. The flash ADC 6/8*Vref
architecture was chosen to achieve the maximum sampling 1/8*Vref V[1]_P/N
frequency for the design, the SiGe heterojunction bipolar 7/8*Vref
transistors (HBTs) was chosen for improving the high-speed
performance of circuit. A wide-bandwidth track-and-hold Figure 1. Simplified block diagram of 3-bit flash ADC
(THA) with capacitor bandwidth enhancement method was
applied to achieve a wide input ADC bandwidth. The III. MODULE CIRCUIT DESIGN
high-resolution comparator is the most important part since it A. THA Module
determines the speed of the ADC. It adopts fully differential
The block diagram of the THA is shown in Fig. 2 and it
architecture of differential input signals and differential
consists of an input buffer, a track-and-hold stage, and an
reference voltage signals. The decoder includes a
output buffer. A common method to suppress the input
bubble-correct module, a XOR-gate-array module and a fully
feedthrough [1], is to connect a capacitance equal to
differential ROM-decoder module.
base-emitter capacitance of the switch between input buffer
This paper is organized as follows. In Section II, the
and hold capacitance. Two operation modes of the THA are
architecture of the flash ADC is presented. The details of
controlled by the track-and-hold stage, which are track mode
module circuit design are discussed in Section III. The
and hold mode respectively. In this THA module, the

978-1-5386-8311-8/18/$31.00 ©2018 IEEE 196

capacitor bandwidth enhancement method is proposed and 60.0
implemented to increase the bandwidth. THA with conventional output buffer@0.6Vpp
Fig. 3 presents the transistor-level schematic diagram of THA with modified output buffer@0.6Vpp
the output buffer in this work. In this design, the output
buffer is an important module for the THA. The performance 55.0
requirements for the output buffer are low harmonic
distortion, good isolation with the subsequent circuits and

SFDR(dB)
enough driving ability for the subsequent circuits.
As shown in Fig. 3, the front differential output signals 50.0
enter into the base of npn25 and npn26 respectively, and
npn21, npn22 follow the emitter signals that could change
the potential and increase the bandwidth of the output buffer.
The emitter-degeneration resistor (R4) between npn21 and 45.0
npn22 improves the linearity of the output buffer whose 0.0 1.0 2.0 3.0 4.0 5.0
Fin(GHz)
value needs to be determined according to the specific circuit
structure and other design requirements. In addition, bias Figure 4. SFDR of the THAs with respect to different input frequency
circuit of npn23 and npn24 is simplified to reduce the
number of transistors, which is helpful for decreasing the 5.0
Conventional
area of layout. Modified
Compared to the conventional output buffer in [2], the 0.0

capacitor (C2) in Fig. 3 is very critical for improving input 3dB Bandwidth(conventional):33GHz
bandwidth. As the value of the capacitor (C2) increases, the -5.0 3dB Bandwidth(modified):38GHz
bandwidth of the THA increases. However, the linearity of
Gain(dB)
the THA decreases when the value of capacitor (C2) -10.0

increases. So the value of capacitor (C2) need to take a

trade-off between the bandwidth and the linearity of the -15.0
THA. It is appropriate to determine the capacitance value of
C2 as 30 fF in this work. -20.0

-25.0
-1 0 1 2 3 4 5 6 7 8 9 10 11
10 10 10 10 10 10 10 10 10 10 10 10 10
Freq(Hz)

Figure 5. Frequency response of the THAs

Fig. 4 shows the simulated SFDR of THAs with two

different output buffers for a differential 0.6Vpp sine-wave
input. The simulated 3dB bandwidth is shown in Fig. 5. It is
Figure 2. THA block diagram
shown that 3dB bandwidth of the THA with a modified
output buffer is 38 GHz which is increased by 5 GHz. The
results of post-layout simulation show that total harmonic
R3 R3 distortion (THD) performance is better than -50 dB with a
Pout_p Pout_n 0.6Vpp input signal when the input frequency is up to 3 GHz.
D21
R6 R6
THA performances have been improved compared to the
npn23 npn24 state-of-the-art. In particular, a wide bandwidth up to 38
GHz is obtained when a novel output buffer is used in the
D22 THA.
TABLE I. PERFORMANCES COMPARISON OF STATE-OF-THE-ART THAS
D23
Pin_p npn25 npn26 Pin_n Reference [3] [4] [5] [6] This work
R5 Process CMOS CMOS InP SiGe SiGe
Sample Rate(GS/s) 1 16 30 2.5 10
npn21 -5V npn22 BW(GHz) NA 19.3 25 26 38
Vsupply(V) 1.8,3.3 3 5.5 4 -5
Input(Vpp) 0.4 NA 0.6 0.5 0.6
R4
THD(dB)@Fin(GHz) -60@0.8 -37@6 -59@1 -52@10 -55.8@1
Power(mW) 258 192 420 830 586
C2 2
R1 R2 R2 R1 Size( mm ) 1.5*1.4 0.36 1.1*0.7 0.7*0.8 0.33*0.21

-5V -5V In Table I, a comparison with other works previously

published is presented, in particular considering similar
Figure 3. Modified output buffer

197
sampling rates to have a reasonable contrast of the various
performance of circuits. Compared to other works, the input
bandwidth in this work is obviously larger than other works
and the THD performance in this work is better than other
works.
B. Comparator Module
In this paper, an ECL-structured dynamic latching
voltage comparator is used, which consists of an innovative
two-stage preamplifier circuit, a simple latch circuit, and an
output buffer circuit. The schematic of the comparator is
shown in Fig. 6.
(a)
(b)
Figure 6. The comparator including (a) two-stage preamplifier circuit (b)
latch and output buffer circuit
Figure 7. The input signals in the critical condition
In this comparator, the front of the voltage comparator
typically uses a preamplifier to increase the speed. The
one-stage amplifying circuit tends to have a small bandwidth
in order to obtain a high gain, and the multi-stage amplifying
circuit can obtain a higher gain with a suitable bandwidth.
198
Considering speed and power consumption, a two-stage
preamplifier circuit is usually used in [7].
Fig. 7 shows the input signals and Fig. 8 shows the
results in the critical condition which the reference DC
voltage is very close to the peak of the input sine signal at a
sampling rate of 10 GS/s.
Figure 8. Results in the critical condition
The preamplifier circuit in this paper is formed by
two-stages preamplifier circuit. The first stage amplifying
circuit is a fully differential Gilbert Cell structure, and the
second stage amplifying circuit is a common-emitter
differential amplifier structure. Compared with the
traditional two-stage preamplifier circuit in [7], the structure
of the first-stage amplifying circuit in this work is well
matched with the fully differential THA, which decreases the
complexity of design of the flash ADC and reduces the
power consumption of the flash ADC circuit.
The results of post-layout simulation show that input
sensitivity of the comparator is better than 1mV for 1 GHz
input frequency at a sample rate of 10 GS/s, while the delay
of signal transmission is lower than 45 ps.
C. Decoder Module
The output of the comparators is converted to binary
code by a thermometer-to-binary decoder, which consists of
a bubble-correct module, a XOR-gate-array module and a
fully differential ROM-decoder module. The simple
implementation of thermometer-to-binary decoder is based
on ROM-decoder structure [8][9]. The block diagram of
thermometer-to-binary decoder is shown in Fig. 9 and a
novel differential ROM-decoder module in this work is
shown in Fig. 10.
The function of the ROM-based decoder is to convert the
one-hot code obtained by the XOR gate array into the binary
code. The format of the 3-bit ROM-based decoder in this
paper is similar to a ROM of 8-bit input and 3-bit output, and
the conversion table of one-hot to binary code is shown in
Table II.
The input signals of the 3-bit ROM-based decoder
proposed in this paper is the 7 single-ended output signals
(m1~m7) of the XOR gate array and a control signal (m_ctrl)
provided by the single-ended signal (Va[1]_N) of the least
significant bit (LSB) output of the bubble-correct module.
This control signal (m_ctrl) is always logic ‘0’ when the
other 7 single-ended signals are one-hot codes. When the 7 TABLE II. CONVERSION OF 8-BIT ONE-HOT TO BINARY CODE
single-ended output signals are all logic ‘0’, the control One-hot Code Binary Code
signal becomes logic ‘1’. The main function of this control m_ctrl m7 m6 m5 m4 m3 m2 m1 Bit2_P Bit1_P Bit0_P

signal is to make this differential ROM-based decoder 0 0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 0 1 0 0 1 0
converting correctly when the other 7 single-ended signals 0 0 0 0 0 1 0 0 0 1 1
are all logic ‘0’. The three control transistors marked with a 0 0 0 0 1 0 0 0 1 0 0
red square in Fig. 10 make an important role in ROM-based 0 0 0 1 0 0 0 0 1 0 1
decoder. 0 0 1 0 0 0 0 0 1 1 0

The input signals of the common 3-bit ROM-based 0 1 0 0 0 0 0 0 1 1 1

1 0 0 0 0 0 0 0 0 0 0
decoder are 7 single-ended signals, which needs to be
compared with a reference voltage in order to obtain logic IV. SIMULATION RESULTS
level. So the traditional structure makes the ROM-based
decoder more sensitive to noise signals. The flash ADC in this work was implemented in a
This paper proposes a structure of the differential 0.13μm SiGe BiCMOS technology. Fig. 11 shows the layout
ROM_based decoder, which includes 8 single-ended input of the flash ADC. The area of the layout is 1×1.2 mm2. The
signals. The differential circuit determines that the logic of a output signal of the ADC in time domain was transformed
certain input signal is not compared with a certain voltage into frequency domain by Fourier transformation. From the
level, but the other signals of 8 single-ended input signals. signal spectrum spurious free dynamic range (SFDR) and
So the advantages of the ROM-based decoder in this work total harmonic distortion (THD) were calculated in Matlab.
are reducing the sensitivity to noise, improving the reliability In Table III, a summary of the simulated ADC
of the decoder and decreasing the power consumption. performance is presented. From the Table III, it is obviously
V[7]_P/N Va[7]_P/N
m7
that the static and dynamic performance of the flash ADC in
V[6]_P/N Va[6]_P/N
m6
this work meets the specifications of the ADC design.
V[5]_P/N Va[5]_P/N
XOR- m5 Bit2_P/N
Bubble ROM
V[4]_P/N gate
Thermometer Correct Va[4]_P/N Decoder Bit1_P/N
Array m4
Code Binary Code
V[3]_P/N Va[3]_P/N
m3 Bit0_P/N

V[2]_P/N Va[2]_P/N
m2

V[1]_P/N Va[1]_P/N
m1

m_ctrl=Va[1]_N

Figure 9. The block diagram of decoder in this work

Figure 11. Layout core of the flash ADC

TABLE III. SUMMARY OF THE SIMULATED ADC PERFORMANCE

Sampling frequency (fs) 10 GS/s

Differential input range 1.6 Vpp-diff
Resolution 3 bit
ENOB >2.5-bit
DNL/INL +/- 0.18/0.2 LSB
SFDR at fin=1GS/s 26.8 dB
SNDR at fin=1GS/s 16.7 dB
Supply voltage -5/-3.3 V
Power dissipation 1.6 W
Layout Core size 1mm×1.2 mm
Technology 0.13μm SiGe BiCMOS

V. CONCLUSION
In this work we have presented a flash ADC working at
10 GS/s. The proposed capacitor method in the THA module
Figure 10. The ROM-based decoder module of the decoder improve the bandwidth, and the novel differential

199
ROM-based decoder improves the reliability of the decoder
and decreases the power consumption. The results of
post-layout simulation show that THD performance is better
than -17.3 dB with a 1.6 Vpp-diff input signal when the input
frequency is up to 1 GHz. The static and dynamic
performance of the flash ADC meets the requirements of the
ADC design. In particular, a wide-bandwidth THA and a
novel differential ROM-based decoder are described in
detail.
ACKNOWLEDGMENT
The research was supported by National Natural Science
Found (NSF No. 61804081, 61828401, 61571235,
61604082), Open project of State Key Laboratory of
Millimeter Waves (No. K201727), Open project of National
and Local Joint Engineering Laboratory of RF Integration
and Micro-assembly Technology (No. KFJJ20170203) and
Scientific Research Foundation of Nanjing University of
Posts and Telecommunications (NUPTSF No. NY215138).
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