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DESCRIPTION (continued)
results in reduced audible motor noise, increased step accuracy, Special power-on sequencing is not required.
and reduced power dissipation.
The A4982 is supplied in two surface mount package, the ET, a
Internal synchronous rectification control circuitry is provided 5 mm × 5 mm, 0.90 mm nominal overall package height QFN
to improve power dissipation during PWM operation. Internal package, and the LP package, a 24‑pin TSSOP. Both packages have
circuit protection includes thermal shutdown with hysteresis, exposed pads for enhanced thermal dissipation and are lead (Pb)
undervoltage lockout (UVLO), and crossover-current protection. free (suffix –T), with 100% matte tin plated leadframes.
Selection Guide
Part Number Package Packing
A4982SETTR-T 32-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel
A4982SLPTR-T 24-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel
2
Allegro MicroSystems
955 Perimeter Road
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
0.22 µF 0.1 µF
DAC OUT1A
OUT1B
PWM Latch
Blanking OCP
Mixed Decay SENSE1
STEP
DIR Gate
Drive DMOS Full Bridge RS1
VBB2
RESET
Control
Translator
MS1 Logic
OUT2A
MS2 OCP
OUT2B
PWM Latch
ENABLE Blanking SENSE2
Mixed Decay
SLEEP
RS2
DAC
VREF
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
*In still air. Additional thermal information available on Allegro Web site.
5.5
5.0
4.5
4.0
3.5 (R
Power Dissipation, PD (W)
θJ
(R A =
3.0 θJ
28
A = ºC
31 /W
ºC )
2.5 /W
)
2.0
1.5
1.0
0.5
0.0
20 40 60 80 100 120 140 160 180
Temperature (°C)
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
tA tB
STEP
tC tD
MS1, MS2,
RESET, or DIR
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
Functional Description
Device Operation. The A4982 is a complete microstepping Low Current Microstepping. Intended for applications
motor driver with a built-in translator for easy operation with where the minimum on-time prevents the output current from
minimal control lines. It is designed to operate bipolar step- regulating to the programmed current level at low current steps.
per motors in full-, half-, quarter-, and sixteenth-step resolution To prevent this, the device can be set to operate in Mixed decay
modes. The currents in each of the two output full-bridges and all mode on both rising and falling portions of the current waveform.
of the N-channel DMOS FETs are regulated with fixed off-time This feature is implemented by shorting the ROSC pin to ground.
PWM (pulse width modulated) control circuitry. At each step, In this state, the off-time is internally set to 30 µs.
the current for each full-bridge is set by the value of its external
current-sense resistor (RS1 and RS2), a reference voltage (VREF), Reset Input ( R̄¯ Ē
¯ S̄
¯ Ē
¯ T̄
¯ ). The R̄¯ Ē¯ S̄¯ Ē¯ T̄¯ input sets the translator
and the output voltage of its DAC (which in turn is controlled by to a predefined Home state (shown in Figures 10 through 13) and
the output of the translator). turns off all of the FET outputs. All STEP inputs are ignored until
¯ Ē
the R̄ ¯ S̄¯ Ē
¯ T̄
¯ input is set to high.
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in Figures 10
through 13), and the current regulator to Mixed decay mode for Step Input (STEP). A low-to-high transition on the STEP
both phases. When a step command signal occurs on the STEP input sequences the translator and advances the motor one incre-
input, the translator automatically sequences the DACs to the ment. The translator controls the input to the DACs and the direc-
next level and current polarity. (See Table 2 for the current-level tion of current flow in each winding. The size of the increment is
sequence.) The microstep resolution is set by the combined effect determined by the combined state of inputs MS1 and MS2.
of the MSx inputs, as shown in Table 1. Direction Input (DIR). This determines the direction of rota-
When stepping, if the new output levels of the DACs are lower tion of the motor. Changes to this input do not take effect until the
than their previous output levels, then the decay mode for the next STEP rising edge.
active full-bridge is set to Mixed. If the new output levels of the Internal PWM Current Control. Each full-bridge is con-
DACs are higher than or equal to their previous levels, then the trolled by a fixed off-time PWM current control circuit that limits
decay mode for the active full-bridge is set to Slow. This auto- the load current to a desired value, ITRIP . Initially, a diagonal pair
matic current decay selection improves microstepping perfor- of source and sink FET outputs are enabled and current flows
mance by reducing the distortion of the current waveform that through the motor winding and the current sense resistor, RSx.
results from the back EMF of the motor. When the voltage across RSx equals the DAC output voltage, the
Microstep Select (MS1 and MS2). The microstep resolu- current sense comparator resets the PWM latch. The latch then
tion is set by the voltage on logic inputs MS1 and MS2, as shown turns off either the source FET (when in Slow decay mode) or the
sink and source FETs (when in Mixed decay mode).
in Table 1. MS1 has a 100 kΩ pull-down resistance, and MS2 has
a 33.3 kΩ pull-down resistance. When changing the step mode, The maximum value of current limiting is set by the selection of
the change does not take effect until the next STEP rising edge. RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
If the step mode is changed without a translator reset, and abso-
ITripMAX (A), which is set by
lute position must be maintained, it is important to change the
step mode at a step position that is common to both step modes in ITripMAX = VREF / ( 8 RS) ×
order to avoid missing steps. When the device is powered down,
or reset due to TSD or an overcurrent event the translator is set to where RS is the resistance of the sense resistor (Ω) and VREF is
the home position which is by default common to all step modes. the input voltage on the REF pin (V).
7
Allegro MicroSystems
955 Perimeter Road
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
Missed
Step
Mixed Decay
No Missed
ILOAD 500 mA/div. Steps
Figure 3: Continuous Stepping Using Automatically-Selected Mixed Stepping (ROSC pin grounded)
8
Allegro MicroSystems
955 Perimeter Road
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
The DAC output reduces the VREF output to the current sense a fixed off-time cycle. After the fixed off-time expires the driver
comparator in precise steps, such that turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
Itrip = (%ITripMAX / 100) × ITripMAX is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in Figure 5.
(See Table 2 for %ITripMAX at each step.)
If the driver is operating in Mixed decay mode, it is normal for
It is critical that the maximum rating (0.5 V) on the SENSE1 and
the positive current to spike, due to the bridge going in the for-
SENSE2 pins is not exceeded.
ward direction and then in the negative direction, as a result of the
Fixed Off-Time. The internal PWM current control circuitry direction change implemented by the Mixed decay feature. This
uses a one-shot circuit to control the duration of time that the is shown in Figure 6. In both instances the overcurrent circuitry is
DMOS FETs remain off. The off-time, tOFF , is determined by the protecting the driver and prevents damage to the device.
ROSC terminal. The ROSC terminal has three settings:
Charge Pump (CP1 and CP2). The charge pump is used to
▪ ROSC tied to VDD — off-time internally set to 30 µs, decay generate a gate supply greater than that of VBB for driving the
mode is automatic Mixed decay except when in full step where source-side FET gates. A 0.1 µF ceramic capacitor, should be
decay mode is set to Slow decay connected between CP1 and CP2. In addition, a 0.1 µF ceramic
▪ ROSC tied directly to ground — off-time internally set to capacitor is required between VCP and VBB, to act as a reservoir
30 µs, current decay is set to Mixed decay for both increasing for operating the high-side FET gates.
and decreasing currents.
▪ ROSC through a resistor to ground — off-time is determined Capacitor values should be Class 2 dielectric ±15% maximum,
by the following formula, the decay mode is automatic Mixed or tolerance R, according to EIA (Electronic Industries Alliance)
decay for all step modes. specifications.
tOFF ≈ ROSC ⁄ 825
VREG (VREG). This internally generated voltage is used to
Where tOFF is in µs.
operate the sink-side FET outputs. The nominal output voltage
Blanking. This function blanks the output of the current sense of the VREG terminal is 7 V. The VREG pin must be decoupled
comparators when the outputs are switched by the internal current with a 0.22 µF ceramic capacitor to ground. VREG is internally
control circuitry. The comparator outputs are blanked to prevent monitored. In the case of a fault condition, the FET outputs of the
false overcurrent detection due to reverse recovery currents of the A4982 are disabled.
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (µs), is approximately Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
tBLANK ≈ 1 µs
specifications.
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is Enable Input ( Ē¯ N̄¯ Ā¯ B̄¯ L̄¯ Ē¯ ). This input turns on or off all of the
shorted to ground, the driver will protect itself by sensing the FET outputs. When set to a logic high, the outputs are disabled.
overcurrent event and disabling the driver that is shorted, protect- When set to a logic low, the internal control enables the outputs as
ing the device from damage. In the case of a short-to-ground, the required. The translator inputs STEP, DIR, MS1, and MS2, as well
¯ Ē
device will remain disabled (latched) until the S̄ L̄ ¯ Ē
¯ P̄¯ input goes as the internal sequencing logic, all remain active, independent of
high or VDD power is removed. A short-to-ground overcurrent ¯ N̄¯ Ā¯ B̄¯ L̄
the Ē ¯ Ē
¯ input state.
event is shown in Figure 4. Shutdown. In the event of a fault, overtemperature (excess TJ)
When the two outputs are shorted together, the current path is or an undervoltage (on VCP), the FET outputs of the A4982 are
through the sense resistor. After the blanking time (≈1 µs) expires, disabled until the fault condition is removed. At power-on, the
the sense resistor voltage is exceeding its trip value, due to the UVLO (undervoltage lockout) circuit disables the FET outputs
overcurrent condition that exists. This causes the driver to go into and resets the translator to the Home state.
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
VSTEP
100.00
70.71
See Enlargement A
IOUT 0
–70.71
–100.00
Enlargement A
toff
tFD tSD
IPEAK
Slow Decay
Mixed Decay
IOUT
Fa
st
De
ca
y
Symbol Characteristic
toff Device fixed off-time
IPEAK Maximum output current
tSD Slow decay interval
tFD Fast decay interval
IOUT Device output current
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
Application Layout
Layout. Typical application circuits and layouts are shown in The two input capacitors should be placed in parallel, and as
Figures 8 (LP package) and 9 (ET package).The printed circuit close to the device supply pins as possible. The ceramic capaci-
board should use a heavy groundplane. For optimum electrical tor (CIN1) should be closer to the pins than the bulk capacitor
and thermal performance, the A4982 must be soldered directly (CIN2). This is necessary because the ceramic capacitor will be
onto the board. On the underside of the A4982 package is an responsible for delivering the high frequency current components.
exposed pad, which provides a path for enhanced thermal dissipa- The sense resistors, RSx , should have a very low impedance
tion. The thermal pad should be soldered directly to an exposed path to ground, because they must carry a large current while
surface on the PCB. Thermal vias are used to transfer heat to supporting very accurate voltage measurements by the current
other layers of the PCB. sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
In order to minimize the effects of ground bounce and offset to accurately measure the current in the windings. The SENSEx
issues, it is important to have a low impedance single-point pins have very short traces to the RSx resistors and very thick,
ground, known as a star ground, located very close to the device. low impedance traces directly to the star ground underneath the
By making the connection between the pad and the ground plane device. If possible, there should be no other components on the
directly under the A4982, that area becomes an ideal location for sense circuits.
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
Solder
A4982
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
OUT2B
C3 C6
GND
U1
A4982 GND
C4 GND CP1
GND C3
CP2 ENABLE
OUT2A OUT2B
C5 R4 VCP
C4 VBB2
PAD C6
ROSC R5 VREG SENSE2
C5
OUT1A MS1 OUT2A
R4
C1 MS2
GND OUT1A
RESET
SENSE1
ROSC R5
ROSC VBB1
OUT1B SLEEP
OUT1B
VDD
GND GND GND C1 STEP DIR
BULK GND REF GND C2
CAPACITANCE
C2 VDD VBB
VDD VBB
12
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955 Perimeter Road
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
GND R4 R5
GND
C7
R4 R5
OUT2A
OUT1A
SENSE2
SENSE1
VBB
RESET
SLEEP
ROSC
VREG
GND
VDD
VCP
MS1
MS2
R3
C1
C3
C4
GND C1 VDD
C5
ROSC
C4
C5 ROSC VDD
GND
8V 40 V
PGND GND
8V
STEP
VBB MS1 VBB
VREG SENSE VREG MS2 OUT
DIR DMOS
ENABLE Parasitic
DMOS RESET 8V
10 V DMOS
Parasitic
SLEEP Parasitic
GND GND GND GND GND
13
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
RESET
STEP
STEP 100.00
Mixed*
100.00
Mixed* 70.71
–70.71 –70.71
–100.00 –100.00
*With ROSC pin tied to GND *With ROSC pin tied to GND
DIR= H DIR= H
Figure 10: Decay Mode for Full-Step Increments Figure 11: Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
Mixed*
38.27
Phase 1
Slow Mixed Slow Mixed Slow
IOUT1A
0.00
Direction = H
Home Microstep Position
(%) –38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71 Mixed*
38.27 Slow
Phase 2
Mixed Slow Mixed Slow Mixed
IOUT2B
0.00
Direction = H
(%) –38.27
–70.71
–92.39
–100.00
DIR= H
Figure 12: Decay Modes for Quarter-Step Increments
14
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
STEP
100
96
88
83
77
71
63
56
47
Mixed*
38
29
20
Phase 1
IOUT1A 10
Slow Mixed Slow Mixed
Direction = H 0
(%) –10
–20
–29
–38
Home Microstep Position
–47
–56
–63
–71
–77
–83
–88
–96
–100
100
96
88
83
77
71
63
56
47
38
Mixed*
29
Phase 2 20
Slow
IOUT2B 10
Mixed Slow Mixed Slow
Direction = H 0
(%) –10
–20
–29
–38
–47
–56
–63
–71
–77
–83
–88
–96
–100
DIR= H
Figure 13: Decay Modes for Sixteenth-Step Increments
15
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955 Perimeter Road
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
Pin-out Diagrams
ET Package LP Package
SENSE2
SENSE1
OUT2A
OUT1A
NC
NC
NC
NC
CP1 1 24 GND
CP2 2 23 ENABLE
32
31
30
29
28
27
26
25
VCP 3 22 OUT2B
OUT2B 1 24 OUT1B
VREG 4 21 VBB2
NC 2 23 NC
VBB2 MS1 5 20 SENSE2
3 22 VBB1
NC 4 21 NC MS2 6 PAD 19 OUT2A
PAD
ENABLE 5 20 DIR RESET 7 18 OUT1A
GND 6 19 GND ROSC 8 17 SENSE1
CP1 7 18 REF SLEEP 9 16 VBB1
CP2 8 17 STEP
VDD 10 15 OUT1B
STEP 11 14 DIR
10
12
13
14
15
16
11
9
REF 12 13 GND
VCP
RESET
SLEEP
VREG
MS1
MS2
ROSC
VDD
17
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
32
1.00
1
1
2 A 2
1
3.40
33X D C
SEATING
0.08 C PLANE 5.00
18
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
0.65
7.80 ±0.10 0.45
4° ±4
24
+0.05
0.15 –0.06
B
3.00 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 3.00 6.10
A (1.00)
1 2
4.32
0.25
1.65
4.32
24X C SEATING PLANE
SEATING
0.10 C PLANE C PCB Layout Reference View
GAUGE PLANE
+0.05
0.25 –0.06 0.65
1.20 MAX For Reference Only; not for tooling use
0.15 MAX (reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
19
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
DMOS Microstepping Driver
A4982 with Translator and Overcurrent Protection
Revision History
Number Date Description
4 March 21, 2012 Update example layout
5 May 7, 2014 Revised Fixed Off-Time section and Figure 10
6 April 2, 2020 Minor editorial updates
20
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com