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Mohamed Sathak A J College of Engineering
Siruseri IT Park, OMR, Chennai - 603103.
Assessment - I Exam
Date /Time Max. Marks 50 Marks
Subject with Code EC 8552 - computer architecture and Time 90 minutes
organization
Branch ECE Year/Semester III/V
Course Objectives
The Student should be able
S. No. Course Objective
1 To make students understand the basic structure and operation of digital computer
2 To familiarize with implementation of fixed point and floating-point arithmetic operations
3 To study the design of data path unit and control unit for processor
4 To understand the concept of various memories and interfacing
5 To introduce the parallel processing technique
Course Outcomes:
On Completion of the course the students will be able to
CO No. Course Outcome
1 Describe data representation, instruction formats and the operation of a digital computer
2 Illustrate the fixed point and floating-point arithmetic for ALU operation
3 Discuss about implementation schemes of control unit and pipeline performance
4 Explain the concept of various memories, interfacing and organization of multiple processors
5 Discuss parallel processing technique and unconventional architectures
(OR)
(b) 1 K2 13
Explain in detail, the performance of a computer
9 (a) 1 K2 13
Explain in detail, the technologies for building processor
and memory.
OR
(b) 1 K3 13
Write short notes on Logical and control operations with
examples
Part c (1x10=10marks) CO BT Univ.QP Marks
level Reference Alloted
10. (a) Write a MIPS code for following C statements 1 K6 3+3+4
i) f = (g+h) – (i+j)
ii)g = h + A[8]
iii)A[12] = h+A[8]
Assume corresponding registers in MIPS
OR
(b) 1 K2 10
Explain in detail, the Addressing & Addressing Modes.