Introduction to:

Microprocessors (EEE-347)
Embedded Systems Development (CNG 336)

Lecture Notes
Dr. Gürtaç Yemişçioğlu
Spring 2019
METU Northern Cyprus Campus

References:
Main Textbook: M. A. Mazidi, S. Naimi, & S. Naimi, “The AVR Microcontroller and Embedded Systems: Using
Assembly and C” (International Ed.), Pearson, 2014
Auxiliary Textbooks: Barry B. Brey, “The Intel Microprocessors” (7th/8th Ed.), Prentice Hall, 2006/2014
Other: ATmega128 Datasheet
 Intro. to MCU Architecture &
Programming

Lectures 3-5

Reading:
Mazidi: Chapter 2 & 3

Ali Muhtaroğlu 2
Outline

• First: Short review of IC technology, CMOS, chip

specifications, hardware/software terminology
• Common Microcontrollers and AVR product families
• AVR ATmega128 package, pins and architectural overview
• Simple instructions and assembly programs
• Data address space
• Introduction to ALU operations and Status Register
• Assembler and assembler directives
• Program Memory and instruction fetch
• RISC (vs. CISC) architecture features
3
Integrated Circuit (IC) Technology (short review)

Chip= Integrated Circuit

Silicon containing the circuit patterns is called a die.

A collection of dies are manufactured together on a wafer of silicon.

Latest processors are manufactured on 18 inch (450 mm) wafers.

The die is packaged before being integrated into the system for
thermal and mechanical protection, and for ease of integration
(e.g. socketing or soldering.) In some special applications where
silicon is integrated to the circuit board the package may be
skipped.

Typical packages are plastic or ceramic, and have different

characteristics depending on the required size,
mechanical/electrical/thermal performance, and cost.
4
Transistor Technology (short review)
• Transistors made from semiconductor material are used to build digital
logic gates (NAND, NOR, INV, etc.), which in turn are used as building
blocks for complex functions.
• Complimentary Metal Oxide Semiconductor(CMOS) transistors act like
voltage controlled switches, and are most common for digital designs due
to low power requirement, high noise immunity, and ease of design. They
contain both P- and N-channel transistors as shown.
• CMOS gates are sensitive to electrostatic discharge (zap) – handle your
parts with care in the lab
VDD

S
G
P-channel
D
Vin Vout
D

G N-channel
S

5
Transistor Technology (short review)

• Dynamic power consumed by an IC component can in general be

approximated as: C. Vdd2.f
where
C : Internal circuit capacitance that is switched high and low
Vdd : Supply voltage
f : Switching frequency
CMOS static power is a function of leaking currents when transistors are
idle but otherwise powered up. This can be even a stronger function of Vdd
(cubic or more).

• Therefore many mobile (low power) requirements tend to push the supply
voltages lower over time. Lower supply voltage helps power, but hurts
noise immunity.

6
Chip Specifications (short review)

• Architectural specs
Operating modes, memory size, programming model, instruction set, etc.
– will be covered in detail for ATMega128

• Electrical specs
– Supply voltage and power
• e.g. Max VDD = 6 V, IDD,max = 400 mA, Imax,per_IOpin= 40 mA

– DC specs
• VOL, VOH, VIL, VIH, Pin leakage, …

– AC specs
• Setup, Hold, Valid times, Min and Max clock periods, strobe timing, …

• Refer to ATMega128 Datasheet

7
Hardware/Software Terminology (short review)

SYSTEM
Hardware Software

Architecture OS, User Interface,

SOFTWARE ABSTRACTION LEVELS

HARDWARE ABSTRACTION LEVELS

Logic Apps, menus

Circuits Application
Development
Patterns on Silicon Tools
and PCB Materials
like FR-4 (Flame Source Code
Retardant Wowen Object Code
Glass Reinforced Machine Code
Epoxy Resin
Bit Streams
8
Code or Macrocode (short review)
• Assembly Language: Unlike high level languages, like C, Pascal, etc.,
assembly language is specific to a particular micro-
controller/microprocessor architecture since it uses mnemonics that
directly represent the instruction set.

• A high level programming language is typically much easier to follow than

an assembly language. On the other hand a good assembly coder can
potentially write more efficient code than can be done in a high level
language, which is limited by the “translating wisdom” of the compilers.

• A program written in assembly or high level language is called a source

code. A program converted to machine readable bit streams (hex or
binary) is called an object code or machine code.

• A compiler is required to convert high level code to object (machine)

code; or an assembler converts a source assembly code to object code.

• Efficiency in coding refers to the number of machine instructions required

to perform a given task, which may be done by one program.
9
Microcode or Microprogram (short review)

• Each instruction is executed by the CPU through a sequence

of well-defined steps.

• The recipe of execution per instruction is stored in the CPU’s

control sequencer, and is called the Microcode or
Microprogram. A microprogram is written during the design
phase of the chip and is normally not accessible afterward.

• The available hardware resources combined with the

efficiency in microcode determines the number of clock
cycles each instruction takes to execute.

10
Most common microcontrollers

• 8-bit microcontrollers
– AVR
– PIC
– HCS12
– 8051

• 32-bit microcontrollers
– ARM
– PIC32

11
AVR product families

• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287

12
AVR product families – part numbers

ATmega128

Atmel Mega
Flash =128K
group

ATtiny44 AT90S4433

Atmel
Tiny Flash =4K Atmel Classic
Flash =4K
group group

13
AVR product families

• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287

SOIC Small outline integrated circuit QFN Quad-flat no-leads

PDIP Plastic dual in-line package MLF Micro leadframe
TQFP Thin quad flat package CBGA Ceramic ball grid array
LQFP Low profile quad flat package 14
AVR product families

• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287

SOIC Small outline integrated circuit QFN Quad-flat no-leads

PDIP Plastic dual in-line package MLF Micro leadframe
TQFP Thin quad flat package CBGA Ceramic ball grid array
LQFP Low profile quad flat package 15
AVR product families

• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287

SOIC Small outline integrated circuit QFN Quad-flat no-leads

PDIP Plastic dual in-line package MLF Micro leadframe
TQFP Thin quad flat package CBGA Ceramic ball grid array
LQFP Low profile quad flat package 16
AVR product families

• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287

SOIC Small outline integrated circuit QFN Quad-flat no-leads

PDIP Plastic dual in-line package MLF Micro leadframe
TQFP Thin quad flat package CBGA Ceramic ball grid array
LQFP Low profile quad flat package 17
ATmega128 Package and Pinout

64-lead TQFP
Thin quad flat pack

64-pad QFN/MLF
Quad-flat no-leads
or
Micro leadframe

Note second and third functions on some pins

18
ATmega128 Pin Descriptions
Pin Function
1st Function: I/O port with internal pull-up resistors (selected per bit)
Port A[7:0]
Alt. Function: Address low byte and data lines for external memory interface, AD[7:0]
Port B[7:0] 1st Function same. Alt. Function (depending on pin): Output Compare, PWM, SPI
Port C[7:0] 1st Function same. Alt. Function: Address high byte for external memory interface, A[15:8]
1st Function same. Alt. Functions (depending on pin): Timer/counter/USART clocks,
Port D[7:0]
timer/counter input capture, external interrupt inputs or UART and TWI signals
1st Function same. Alt. Functions (depending on pin): Timer/counter/interrupt/USART/
Port E[7:0]
UART/programming data/analog comparator input
1st Function same. Alt. Functions (depending on
Port F[7:0]
pin): ADC analog inputs, JTAG interface
1st Function same. Alt. Function (depending on
Port G[4:0] pin): Oscillator, External address latch enable, data
read/write controls
VCC/GND Digital Supply Voltage
RESET Active low reset with 1.5 µs required pulse width
XTAL 1/2 External oscillator pins
AVCC & AREF Supply voltage for Port F and ADC & ADC reference

PEN Active low enable for SPI serial programming mode

19
AVR internal architecture

RAM EEPROM Timers

PROGRAM
ROM

Program
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Note Harvard Architecture

20
ATmega128 Architectural Overview
• Low-power 8-bit 16 Mhz microcontroller
• RISC Architecture (more on this later)
• 133, mostly single-cycle instructions
– Most instructions follow a single 16-bit
word format
• 128 KB Flash, 4KB EEPROM, 4KB internal
SRAM
• 32 x 8-bit register file
– ALU can directly operate on these
registers and store the result back to the
register file
– Six of the 32 (R26-R31) can pair up to be
used as three 16-bit registers X, Y, Z e.g.
as memory address pointers
• Status register
– Information on most recently executed
arithmetic instruction e.g. Overflow, zero,
negative, etc.
• Many special and peripheral features 21
ATmega128 Architectural Overview
• Low-power 8-bit 16 Mhz microcontroller
• RISC Architecture (more on this later)
• 133, mostly single-cycle instructions
– Most instructions follow a single 16-bit
word format
• 128 KB Flash, 4KB EEPROM, 4KB internal
SRAM
• 32 x 8-bit register file
– ALU can directly operate on these
registers and store the result back to the
register file
– Six of the 32 (R26-R31) can pair up to be
used as three 16-bit registers X, Y, Z e.g.
as memory address pointers
• Status register
– Information on most recently executed
arithmetic instruction e.g. Overflow, zero,
negative, etc.
• Many special and peripheral features 22
ATmega128 Architectural Overview
• Low-power 8-bit 16 Mhz microcontroller
• RISC Architecture (more on this later)
• 133, mostly single-cycle instructions
– Most instructions follow a single 16-bit
word format
• 128 KB Flash, 4KB EEPROM, 4KB internal
SRAM
• 32 x 8-bit register file
– ALU can directly operate on these
registers and store the result back to the
register file
– Six of the 32 (R26-R31) can pair up to be
used as three 16-bit registers X, Y, Z e.g.
as memory address pointers
• Status register
– Information on most recently executed
arithmetic instruction e.g. Overflow, zero,
negative, etc.
• Many special and peripheral features 23
ATmega128 Architectural Overview
• Low-power 8-bit 16 Mhz microcontroller
• RISC Architecture (more on this later)
• 133, mostly single-cycle instructions
– Most instructions follow a single 16-bit
word format
• 128 KB Flash, 4KB EEPROM, 4KB internal
SRAM
• 32 x 8-bit register file
– ALU can directly operate on these
registers and store the result back to the
register file
– Six of the 32 (R26-R31) can pair up to be
used as three 16-bit registers X, Y, Z e.g.
as memory address pointers
• Status register
– Information on most recently executed
arithmetic instruction e.g. Overflow,
zero, negative, etc.
• Many special and peripheral features 24
ATmega128 Architectural Overview
• Low-power 8-bit 16 Mhz microcontroller
• RISC Architecture (more on this later)
• 133, mostly single-cycle instructions
– Most instructions follow a single 16-bit
word format
• 128 KB Flash, 4KB EEPROM, 4KB internal
SRAM
• 32 x 8-bit register file
– ALU can directly operate on these
registers and store the result back to the
register file
– Six of the 32 (R26-R31) can pair up to be
used as three 16-bit registers X, Y, Z e.g.
as memory address pointers
• Status register
– Information on most recently executed
arithmetic instruction e.g. Overflow, zero,
negative, etc.
• Many special and peripheral features 25
AVR’s CPU

• AVR’s CPU
– ALU
– 32 General Purpose registers
(R0 to R31)
R0
– PC register R1
ALU
– Instruction decoder R2

…
SREG: I T H S V N Z C
R15

CPU R16
R17

…
PC

R30
Instruction decoder
R31
Instruction Register
registers

26
Some simple instructions
1. Loading values into the general purpose registers
LDI (Load Immediate)
• LDI Rd, k
– Its equivalent in high level languages:
Rd = k (where Rd is a variable)

• k : An 8 bit value
(00-FF in hex, 0-255 in decimal)
Rd is any of the upper 16 registers, R16-R31 R0
R1
ALU
R2
• Example:

…
– LDI R16, 53 SREG: I T H S V N Z C
R15
• R16 = 53 CPU R16
R17
– LDI R19, 132

…
PC
– LDI R23, 0x27 Instruction decoder
R30
R31
• R23 = 0x27 Instruction Register
registers

27
Some simple instructions
2. Arithmetic calculation

• There are some instructions for doing

Arithmetic and logic operations; such as:
ADD, SUB, MUL, AND, etc.

• ADD Rd, Rs
– Rd = Rd + Rs
R0
R1
Example: ALU
R2
– ADD R25, R9

…
SREG: I T H S V N Z C

• R25 = R25 + R9 R15

– ADD R17, R30 CPU R16

R17

…
PC
• R17 = R17 + R30
R30
Instruction decoder
R31
Instruction Register
registers

28
A simple program

• Write a program that calculates 19 + 95

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20

R0
R1
ALU
R2

…
SREG: I T H S V N Z C
R15

CPU R16
R17

…
PC
R30
Instruction decoder
R31
Instruction Register
registers

29
A simple program

• Write a program that calculates 19 + 95 + 5

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
LDI R20, 5 ;R20 = 5
ADD R16, R20 ;R16 = R16 + R20

Note the second solution uses fewer registers

30
Some simple instructions
2. Arithmetic calculation

• SUB Rd, Rs
– Rd = Rd – Rs

Example:
– SUB R25, R9
• R25 = R25 - R9 R0
R1
ALU
– SUB R17, R30 R2

…
• R17 = R17 - R30 SREG: I T H S V N Z C
R15

CPU R16
R17

…
PC
R30
Instruction decoder
R31
Instruction Register
registers

31
Some simple instructions
2. Arithmetic calculation

• INC Rd
– Rd = Rd + 1
Example:
– INC R25
• R25 = R25 + 1

• DEC Rd R0
R1
ALU
– Rd = Rd - 1 R2

…
Example: SREG: I T H S V N Z C
R15
– DEC R23
• R23 = R23 - 1
CPU R16
R17

…
PC
R30
Instruction decoder
R31
Instruction Register
registers

32
Data Address Space

8 bit General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM

Program CPU Data

Bus Bus address bus
data bus
control bus
Data
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

33
Data Address Space

8 bit General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM

Program CPU Data

Bus Bus address bus
data bus
control bus
Data
Bus

Address Address Address

Name Name
Interrupt Name Other
I/O Mem. OSC
I/O Mem. I/O Ports
Mem.
$00 $20 TWBR $16 $36 Unit
PINB $2B $4B OCR1AH Peripherals
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
$03 $23 TWDR $19 $39 PINA $2E $4EI/O TCCR1B
$04 $24 ADCL $1A $3A DDRA $2F PINS
$4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
$06 $26 ADCSRA $1C $3C EECR OCDR
$1D $3D EEDR $31 $51
$07 $27 ADMUX OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 $29 UBRRL $1F $3F EEARH $33 $53 TCCR0
$0A $2A UCSRB UBRRC $34 $54 MCUCSR
$20 $40
$0B $2B UCSRA UBRRH $35 $55 MCUCR
$0C $2C UDR $21 $41 WDTCR $36 $56 TWCR
$0D $2D SPCR $22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD $27 $47 ICR1H $3C $5C OCR0
$13 $33 PINC $28 $48 OCR1BL $3D $5D SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
34
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

LDS (LoaD direct from data Space) STS (STore direct to data Space)

LDS Rd, addr ;Rd = [addr] STS addr,Rd ;[addr]=Rd

where addr is between 0000-FFFF hex where addr is between 0000-FFFF hex

Example: Example:

LDS R1, 0x100 STS 0x100, R15 ; [0x100] = R15

35
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Example: Write a program that stores 55 into location 0x120 of RAM.

Solution:
LDI R20, 55 ;R20 = 55
STS 0x120, R20 ;[0x120] = R20 = 55

36
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Example: Write a program that copies the contents of location 0x120

of RAM into location 0x121.

Solution:
LDS R20, 0x120 ;R20 = [0x120]
STS 0x121, R20 ;[0x121] = R20 = [0x120]

37
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Example: Add contents of location 0x130 to contents of location

0x135 and store the result in location 0x313.
Solution:
LDS R20, 0x130 ;R20 = [0x130]
LDS R21, 0x135 ;R21 = [0x135]
ADD R20, R21 ;R20 = R20 + R21
STS 0x313, R20 ;[0x313] = R20
38
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Example: What does the following instruction do?

LDS R20, 2

Answer:
It copies the contents of R2 into R20; as 2 is the address of R2.

39
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A UCSRB
CPU Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Example: Store 0x53 into the SPH register.

The address of SPH is 0x5E

Solution:
LDI R20, 0x53 ;R20 = 0x53
STS 0x5E, R20 ;SPH = R20

40
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS
IN (IN from IO location)

IN Rd, IOaddress ;Rd = IO(Address)

where Address: $00 - $3F
Example:
IN R1, 0x3F ;R1 = SREG
IN R17, 0x3E ;R17 = SPH

41
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A UCSRB
CPU Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS
OUT (OUT to IO location)

OUT IOAddr,Rd ;IO(Address) = Rd

where Address: $00 - $3F

Example:
OUT 0x3F, R12 ;SREG = R12
OUT 0x3E, R15 ;SPH = R15
42
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS

Using Names of IO registers

SPH and SREG are defined
in m128def.inc
Example: through assembler
OUT SPH,R12 ;OUT 0x3E,R12 directive .EQU:
IN R15, SREG ;IN R15,0x3F .EQU SPH=0x3E
.EQU SREG=0x3F

43
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H

8 bit $03
$04
$23
$24
TWDR
ADCL
$19
$1A
General
$39
$3A
PINA
RAM
DDRA
$2E
EEPROM
$2F
$4E
$4F
TCCR1B
Timers
TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
Purpose
$1C $3C EECR
$06
PROGRAM $26 ADCSRA OCDR
$07 $27 ADMUX Registers
$1D $3D EEDR $31 $51
ROM OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
$09 Program
$29 UBRRL $1F $3F EEARH
$0A $2A
CPU
UCSRB
Data $33 $53 TCCR0
Bus Bus
$20 $40
UBRRC $34 $54 MCUCSR
address bus
$0B $2B UCSRA UBRRH $35 data
$55 bus
MCUCR
$0C $2C UDR $21 $41 WDTCR $36 control
$56 bus
TWCR
$0D $2D SPCR Data
$22 $42 ASSR $37 $57 SPMCR
$0E $2E SPSR Bus
$23 $43 OCR2 $38 $58 TIFR
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
$12 $32 PORTD Interrupt Other
OSC $27 $47 ICR1H Ports
$3C $5C OCR0
$13 $33 PINC $28 Unit OCR1BL
$48 $3D $5D
Peripherals
SPL
$14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
$15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG
I/O
PINS
Example: Write a program that adds the contents of the PINC IO
register to the contents of PIND and stores the result in location
0x100 of the SRAM

Solution:
IN R20,PINC ;R20 = PINC
IN R21,PIND ;R21 = PIND
ADD R20,R21 ;R20 = R20 + R21
STS 0x100,R20 ;[0x100] = R20 44
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Address Name Address Name Address Name

I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
R0 $01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L

ALU R1 $02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B
R2 $04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
…

$06 $26 ADCSRA $1C $3C EECR OCDR

$1D $3D EEDR $31 $51
$07 $27 ADMUX
SREG: I T H S V N Z C $1E $3E EEARL
OSCCAL
$08 $28 ACSR $32 $52 TCNT0
R15

CPU
$09 $29 UBRRL $1F $3F EEARH $33 $53 TCCR0
R16 $0A $2A UCSRB
$20 $40
UBRRC $34 $54 MCUCSR
$0B $2B UCSRA UBRRH $35 $55 MCUCR
R17 $0C $2C UDR $21 $41 WDTCR $36 $56 TWCR
$0D $2D SPCR $22 $42 ASSR $37 $57 SPMCR
…

PC $0E
$0F
$2E
$2F
SPSR
SPDR
$23 $43 OCR2 $38 $58 TIFR
$24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
R30 $11 $31 DDRD $26 $46 ICR1L
Instruction decoder $12 $32 PORTD $27 $47 ICR1H
$3B $5B GICR
R31 $13 $33 PINC $28 $48 OCR1BL
$3C $5C OCR0
$3D $5D SPL
Instruction Register $14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
registers $15 $35 PORTC $2A $4A OCR1AL $3F
$3E $5F
$5E SREG

45
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Example: Show the status of the C, H, and Z flags after the addition
of 0x38 and 0x2F in the following instructions:
LDI R0 0x38
R16, ;R16 = 0x38
ALU R1
LDI R17,
R2 0x2F ;R17 = 0x2F
…

ADD R16, R17 ;add R17 to R16

SREG: I T H S V N Z C
R15

CPU Solution: R16

$38
R17
1
0011 1000
+ $2F 0010 1111
…

PC
$67 0110 0111 R16 = 0x67
R30
Instruction decoder C = 0 because there is no carry beyond the D7 bit.
R31
H = 1 because there is a carry from the D3 to the D4 bit.
Instruction Register
registers
Z = 0 because the R16 (the result) has a value other than 0 after the addition.

46
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Example: Show the status of the C, H, and Z flags after the addition
of 0x9C and 0x64 in the following instructions:
R0
LDI R20, 0x9C
ALU R1
LDI
R2 R21, 0x64
…

ADD R20, R21 ;add R21 to R20

SREG: I T H S V N Z C
R15

CPU Solution: R16

R17
$9C
1
1001 1100
…

PC + $64 0110 0100

$100
R30 1 0000 0000 R20 = 00
Instruction decoder
C = 1 because there is a carry beyond the D7 bit.
R31
H = 1 because there is a carry from the D3 to the D4 bit.
Instruction Register
registers
Z = 1 because the R20 (the result) has a value 0 in it after the addition.

47
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Example: Show the status of the C, H, and Z flags after the (unsigned)
subtraction of 0x23 from 0xA5 in the following instructions:
R0
LDI R20, 0xA5
ALU R1
LDI
R2 R21, 0x23
…

SUB R20, R21 ;subtract R21 from R20

SREG: I T H S V N Z C
R15

CPU Solution: R16

R17
$A5 1010 0101
…

PC - $23 0010 0011

$82
R30 1000 0010 R20 = $82
Instruction decoder
C = 0 because R21 is not bigger than R20 and there is no borrow from D8 bit.
R31
Z = 0 because the R20 has a value other than 0 after the subtraction.
Instruction Register
registers
H = 0 because there is no borrow from D4 to D3.

48
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Example: Show the status of the C, H, and Z flags after the (unsigned)
subtraction of 0x73 from 0x52 in the following instructions:
R0
LDI R20, 0x52
ALU R1
LDI
R2 R21, 0x73
…

SUB R20, R21 ;subtract R21 from R20

SREG: I T H S V N Z C
R15

CPU Solution:
R16
$52
R17
- $73
0101 0010
0111 0011
…

PC
$DF 1101 1111 R20 = $DF
R30
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
Instruction decoder
R31
Z = 0 because the R20 has a value other than zero after the subtraction.
H = 1 because
Instruction Register there is a borrow from D4 to D3.
registers

49
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Example: Show the status of the C, H, and Z flags after the

subtraction of 0x9C from 0x9C in the following instructions:
R0
LDI
R1 R20, 0x9C
ALU
R2
LDI R21, 0x9C
…

SREG: I T H S V N Z C SUB R20, R21 ;subtract R21 from R20

R15

CPU Solution: R16

R17
$9C 1001 1100
…

PC - $9C 1001 1100

$00
R30 0000 0000 R20 = $00
Instruction decoder
C = 0 because R21 is not bigger than R20 and there is no borrow from D8 bit.
R31
Z=
Instruction Register 1 because the R20 is zero after the subtraction.
registers
H = 0 because there is no borrow from D4 to D3.

50
Status Register (SREG)

SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

R0
ALU R1
R2
…

SREG: I T H S V N Z C
R15

CPU R16
R17
…

PC
R30
Instruction decoder
R31
Instruction Register
registers

51
Assembler
• A source file (.asm) is created in ASCII format by the programmer using a text editor
• The object file (.obj) generated by the assembler is used by the simulator/emulator to
debug and verify the code (e.g. in Atmel Studio)
• The map file (.map) generated by the assembler contains the mapping of the labels
used in the program to actual values
• The list file (.lst) optionally generated by the assembler is useful for debug, since it
shows both the source and binary code, memory locations used by the program, etc.
• Hex (.hex) file and eeprom (.eep) file generated by the assembler are used to
configure the FLASH program memory and EEPROM data memory respectively
EDITOR
PROGRAM
myfile.asm
Assembly
ASSEMBLER
PROGRAM

assembler

myfile.eep myfile.hex myfile.map myfile.lst myfile.obj

Machine
Language DOWNLOAD TO DOWNLOAD TO
AVR’s EEPROM AVR ’s FLASH
52
Assembler Directives
.EQU and .SET

• .EQU name = value

– Assigns a value to a label, which cannot be reassigned
– Example:
.EQU COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28

• .SET name = value

– Assigns a value to a label, which can be reassigned later
– Example:
.SET COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
LDI R21, COUNT ;R21 = 0x19

53
Assembler Directives
.INCLUDE
• .INCLUDE “filename.ext”
– Tells assembler to start reading and assembling source code
from a specified file (until the end-of-file or ‘EXIT’ directive
encountered)

54
Assembler Directives
.INCLUDE
• .INCLUDE “filename.ext”
– Tells assembler to start reading and assembling source code
from a specified file (until the end-of-file or ‘EXIT’ directive
encountered)

M128def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words

Program.asm
.INCLUDE “M128DEF.INC”
LDI R20, 10
OUT SPL, R20

55
Assembler Directives
.ORG

• .ORG address
– Changes the memory location counter within a code (flash) segment
(after .CSEG), or a data (SRAM) segment (after .DSEG), or an EEPROM
segment (after .ESEG)
– Default location counter for the code and EEPROM segments are 0
– Default location counter for the data (SRAM) segment is the address
immediately following the extended I/O address space i.e. 0x100
00 E205

Program.asm 01 0000
02 0000
.ORG 0
03 0000
LDI R16, 0x25
.ORG 0x7
assembler 04 0000

LDI R17, 0x34 05 0000

LDI R18, 0x31 06 0000
07 E314
08 E321
09 0000
0A 0000 56
Assembler - Example

; AVR Assembly Language Program to Add Some Data.

; store SUM in SRAM location 0x300.
.EQU SUM = 0x300 ; SRAM loc $300 for SUM

.ORG 00 ; start at address 0

LDI R16, 0x25 ; R16 = 0x25
LDI R17, $34 ; R16 = 0x34
LDI R18, 0b00110001 ; R18 = 0x31
ADD R16, R17 ; add R17 to R16
ADD R16, R18 ; add R18 to R16
LDI R17, 11 ; R17 = 0x0B
ADD R16, R17 ; add R17 to R16
STS SUM, R16 ; save the SUM in loc $300
HERE: JMP HERE ; stay here forever

57
Assembler – Map File (.map)
for the previous example
EQU SUM 00000300
CSEG HERE 00000009

58
 Assembler – List File (.lst)
for the previous example
Source
Code ; AVR Assembly Language Program to Add Some Data.
Instruction ; store SUM in SRAM location 0x300.
Address
.DEVICE ATMega128
Machine
Instructions .EQU SUM = 0x300 ; SRAM loc $300 for SUM

.ORG 00 ; start at address 0

000000 e205 LDI R16, 0x25 ; R16 = 0x25
000001 e314 LDI R17, $34 ; R16 = 0x34
000002 e321 LDI R18, 0b00110001; R18 = 0x31
000003 0f01 ADD R16, R17 ; add R17 to R16
000004 0f02 ADD R16, R18 ; add R18 to R16
000005 e01b LDI R17, 11 ; R17 = 0x0B
000006 0f01 ADD R16, R17 ; add R17 to R16
000007 9300 0300 STS SUM, R16 ; save the SUM in loc $300
000009 940c 0009 HERE: JMP HERE ; stay here forever

Memory use information (in a different but similar format)

Memory Use information:
22 bytes used in .cseg ; 0 bytes used in .dseg ; 0 bytes used in .eseg
59
Flash memory – CPU interface

16-bit

RAM EEPROM Timers

PROGRAM
Flash ROM ALU

PC: Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

60
Flash memory – CPU interface

16-bit

RAM EEPROM Timers

PROGRAM
Flash ROM ALU

PC: Data
16bit

16bit CPU Bus

Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

61
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 0 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

62
Fetching Instructions using Program Counter

00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 0 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

63
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 1 Data
CPU Bus
Instruction dec.
Program
Bus E205

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

64
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 1 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

65
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 2 Data
CPU Bus
Instruction dec.
Program
Bus E314

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

66
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 2 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

67
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 3 Data
CPU Bus
Instruction dec.
Program
Bus E321

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

68
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 3 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

69
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 4 Data
CPU Bus
Instruction dec.
Program
Bus 0F01

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

70
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 4 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

71
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 5 Data
CPU Bus
Instruction dec.
Program
Bus 0F02

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

72
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 5 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

73
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 6 Data
CPU Bus
Instruction dec.
Program
Bus E01B

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

74
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 6 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

75
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 7 Data
CPU Bus
Instruction dec.
Program
Bus 0F01

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

76
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 7 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

77
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 8 Data
CPU Bus
Instruction dec.
Program
Bus 9300

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

78
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300
0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 8 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

79
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 9 Data
CPU Bus
Instruction dec.
Program
Bus 0300

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

80
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A
Flash0009
ROM ALU

PC: 9 Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

81
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: A Data
CPU Bus
Instruction dec.
Program
Bus 940C

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

82
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
0009
ROM ALU

PC: A Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

83
Fetching Instructions using Program Counter

00 E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: B Data
CPU Bus
Instruction dec.
Program
Bus 0009

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

84
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Done 85
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 1
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Done 86
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 1
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Done 87
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute1
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Done 88
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute1
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Done 89
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Instruct
Fetch 2
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
Instruct 1 PINS

Done 90
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Instruct
Fetch 2
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
Instruct 1 PINS

Done 91
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute2
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
Instruct 1 PINS

Done 92
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute2
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
Instruct 1 PINS

Done 93
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 3
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 94
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 3
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 95
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute3
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 96
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
Instruct 4
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute3
Instruct
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 97
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 4
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Instruct 3 Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 98
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 4
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Instruct 3 Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 99
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute4
Instruct Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Instruct 3 Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 100
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute4
Instruct Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Instruct 3 Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 101
Fetch and execute cycles
in simple multi-cycle organization
00 E205
Waiting to be fetched 01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Instruct 4 Interrupt Other

OSC Ports
Instruct 3 Unit Peripherals
Instruct 2
I/O
Instruct 1 PINS

Done 102
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Done
103
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 1
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Done
104
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 1
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Done
105
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 2
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruct 1 Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Done
106
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 2
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute1
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Done
107
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch3
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruct 2 Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Instruct 1 Done
108
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
Instruct 4 03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 3
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute2
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
Instruct 1 Done
109
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 4
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute3
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

Instruct 2 I/O
PINS
Instruct 1 Done
110
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 4
Instruct 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute3
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

Instruct 2 I/O
PINS
Instruct 1 Done
111
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute4
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 3
Instruct 2 I/O
PINS
Instruct 1 Done
112
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute4
Instruct Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals
Instruct 3
Instruct 2 I/O
PINS
Instruct 1 Done
113
Fetch and execute cycles
in pipeline organization (ATmega128)
00 E205

Waiting to be fetched 01 E314

02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
Instruct 4 OSC Ports
Unit Peripherals
Instruct 3
Instruct 2 I/O
PINS
Instruct 1 Done
114
How to speed up the CPU
• Increase the clock frequency
– Dynamic Power Dissipation increases linearly with frequency: CV2f
– More power consumption & more heat
– CMOS Static Power Dissipation (Leakage) increases exponentially with
Temperature

• Increase both supply voltage and clock frequency

– Even worse than just frequency
– Dynamic Power Dissipation grows quadratically with Voltage: CV2f
– Even more power consumption & even more heat
– CMOS Static Power Dissipation (Leakage) increases exponentially with
Voltage as well; so compounded effect of voltage and temperature

• Change the architecture

– Pipelining – note this by itself may still have some impact on dynamic
power due to increased device capacitance switching
– RISC (Reduced Instruction Set Computing)
115
Changing the architecture
RISC vs. CISC

• CISC (Complex Instruction Set Computer)

– Put as many instruction as you can into the CPU

• RISC (Reduced Instruction Set Computer)

– Reduce the number of instructions, and use your facilities in a
more proper way.

116
RISC architecture

• Feature 1: regular (fixed) instruction sizes

– RISC processors have a fixed instruction size. It makes the

task of instruction decoder easier.
• In AVR the instructions are 2 or 4 bytes.

– In CISC processors instructions have different lengths

• E.g. in 8051
– CLR C ; a 1-byte instruction
– ADD A, #20H ; a 2-byte instruction
– LJMP HERE ; a 3-byte (long jump) instruction

117
RISC architecture

• Feature 2: reduced number of simple instructions

– Pros: Reduces the number of used transistors

– Cons:
• Can make the assembly programming more difficult
• Can lead to using more memory

118
RISC architecture

• Feature 3: limit the number of addressing modes

– Advantage
• Hardwiring from instruction register to datapath

– Disadvantage
• can make the assembly programming more difficult

119
RISC architecture

• Feature 4: Load/Store architecture

– ALU operations are simple and are always between registers
– Use simple dedicated load/store instructions for register-
memory transfers (which should be less frequent than ALU
operations)

LDS R20, 0x200

LDS R21, 0x220 RAM EEPROM Timers
ADD R20, R21
STS 0x230, R20 PROGRAM
Flash ROM ALU

PC: Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

120
RISC architecture

• Feature 5 (Harvard architecture): separate buses for

opcodes and operands

– Advantage: opcodes and operands can go in and out of the

CPU together.

– Disadvantage: leads to more cost in general purpose

computers - but less of an issue with Moore scaling.

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

121
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20, R21
ADD R20,R21 ; R20 = R20 + R21
LDS R20, 0x100

Fetch

Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

122
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20, R21
ADD R20,R21 ; R20 = R20 + R21

LDS Fetch
R20, 0x100

Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

123
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20, R21
ADD R20,R21 ; R20 = R20 + R21

LDS Fetch
R20, 0x100

Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

124
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20,R21 ; R20 = R20 + R21

ADDFetch
R20, R21

Execute
LDS R20, 0x100

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

125
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20,R21 ; R20 = R20 + R21

ADDFetch
R20, R21

Execute
LDS R20, 0x100

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

126
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20,R21 ; R20 = R20 + R21

Fetch

Execute
ADD R20, R21

LDS R20, 0x100

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

127
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20,R21 ; R20 = R20 + R21

Fetch

Execute
ADD R20, R21

LDS R20, 0x100

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

128
RISC architecture

LDS R20, 0x100 ; R20 = [0x100]

ADD R20,R21 ; R20 = R20 + R21

Fetch

Execute

ADD R20, R21

LDS R20, 0x100

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

129
RISC architecture

• Feature 6: Common cases are fast

– e.g. operations between general purpose registers

– more than 95% of instructions are executed in 1 machine

cycle

130
RISC architecture

• Feature 7: High user accessible register count

– RISC processors have at least 32 registers.

– Decreases the need for stack and memory usages.

– In AVR there are 32 general purpose registers (R0 to R31)

131