VLSI Assignment

Ans 1.
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 The problem can be overcome using NORA logic, nMOS and pMOS transistor networks are
alternatively used. The output of an nMOS block is HIGH during precharge, which cannot
turn a pMOS transistor ON. Similarly, the output of an pMOS block is LOW during precharge,
which cannot turn a nMOS transistor ON.

Ans 8.
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VLSI Design Styles

Several design styles can be considered for chip implementation of specified

algorithms or logic functions. 

1. Field Programmable Gate Array (FPGA)

Fully fabricated FPGA chips contains ten thousand to more than a million logic
gates with programmable interconnection. Programmable interconnections are
available for users or designers to perform given functions easily. There are I/O
blocks, which are designed and numbered according to function. For each
module of logic level composition, there are CLB’s (Configurable Logic
Blocks).

2.  Gate Array Design

In view of the fast prototyping capability, the gate array (GA) comes after the FPGA.
While the design implementation of the FPGA chip is done with user programming,
that of the gate array is done with metal mask design and processing. It requires a
two-step manufacturing process: The first phase, which is based on generic (standard)
masks, results in an array of uncommitted transistors on each GA chip. These
uncommitted chips can be stored for later customization, which is completed by
defining the metal interconnects between the transistors of the array.
 3. Standard Cell Based Design
A standard cell-based design requires development of a full custom mask set. The
standard cell is also known as the polycell. In this approach, all of the commonly
used logic cells are developed, characterized and stored in a standard cell library.
A library may contain a few hundred cells including inverters, NAND gates, NOR
gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate type can be
implemented in several versions to provide adequate driving capability for different
fan-outs.
4. Full Custom Design
In a full-custom design, the entire mask design is made new, without the use of any
library. The development cost of this design style is rising. Thus, the concept of
design reuse is becoming famous to reduce design cycle time and development
cost.
The hardest full custom design can be the design of a memory cell, be it static or
dynamic. For logic chip design, a good negotiation can be obtained using a
combination of different design styles on the same chip, i.e. standard cells, data-path
cells, and programmable logic arrays (PLAs).

Ans 10.

(a) CAD Technology:

Computer-aided design (CAD) is a computer technology that designs a product
and documents the design's process. CAD may facilitate the manufacturing
process by transferring detailed diagrams of a product’s materials, processes,
tolerances and dimensions with specific conventions for the product in question.
It can be used to produce either two-dimensional or three-dimensional diagrams,
which can then when rotated to be viewed from any angle, even from the inside
looking out. A special printer or plotter is usually required for printing professional
design renderings.

(b) Design Quality:

(c) Techniques for reducing leakage current:
Leakage currents can be reduced through on-chip impedance termination circuits. An on-
chip impedance termination circuit includes a network of resistors and transistors formed
on an integrated circuit. The termination circuit is coupled to one or more IO pins. The
transistors can be turned ON and OFF to couple or decouple subsets of the resistors
from the IO pins. The bodies of transistors 305-306 are coupled to a supply voltage to cut
off leakage current. By pulling the body of these transistors to a supply voltage, the
transistor's drain/source-to-body diodes turn OFF preventing unwanted leakage current.
Also, by moving the source/drain/body node of transistors 301-304 to Node 2, leakage

currents through transistors 301-304 are eliminated.

(d) Adiabatic logic circuits:
Adiabatic logic is the term given to low power electronics circuits that implement
reversible logic. Adiabatic logic is commonly used to reduce the energy loss
during the charging and discharging process of circuit operations. Adiabatic logic
is also known as energy recovery or charge recovery logic. The adiabatic logic
structure dramatically reduces power dissipation. The adiabatic switching
technique can achieve very low power dissipation but at the expense of
complexity.