Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

Number of samples 3.84 Msps

Attenuation level requirement Minimum 33dB

Number of samples/slot 2560samples/frame

Roll off factor α 0.22

The table 3.2 gives us the specifications of the 3G filter and a decimator which can be
implemented

Table 3.2 :Specification of 3G FIR Filter and Decimator

Parameter Value

Decimation Factor 4, 8

Roll Off factor 0.22

Cut Off Frequency 1.92MHz

Sample Frequency 15.36MHz, 30.72MHz

Filter Length 65, 129

The specifications of the Filter and Decimator considered for this project is shown in the
table 3.3

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

Table 3.3: Specifications of the Filter and Decimator considered for this project

Parameter Value

Decimation Factor 4

Roll Off factor 0.22

Cut Off Frequency 1.92MHz

Sample Frequency 15.36MHz

Filter Length 65

The HPF filters the low frequency components thereby allowing the noise component of the
decimated signal. This signal along with the FIR filter output is input to the control unit. The
control unit calculates the SNR and controls the FIR filter taps accordingly. Such an
operation ensures optimum usage of the filter.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

CHAPTER 4

4 DESIGN AND IMPLEMENTATION

This chapter gives an insight on the proposed architecture blocks, the hardware software
requirements and the implementation description of FIR filter and decimator.

4.1 Description of blocks of the proposed architecture

The proposed architecture shown in figure 3.4 consists of the decimator, FIR filter,
High Pass Filter, Signal Power Measurement units and a control unit.

4.1.1 Decimator

Decimation is a technique for reducing the number of samples in a discrete-time

signal. The element which implements this technique is referred to as a decimator. The most
immediate reason to decimate is simply to reduce the sampling rate i.e by removing the
interpolated ‘0’s, at the output of one system so a system operating at a lower sampling rate
can input the signal.

The existing architecture places the decimator at the output of the filter, whereas the
proposed architecture places it before the FIR which allows only the required components
through it, thereby improving the performance of the filter.

The decimator can be modeled by using the following algorithm:

Algorithm for Decimator modeling :

1. Obtain the clock for the Decimator which is quarter of the original clock.

2. This clock is applied to the decimator which outputs the data at the rising edge of this
new clock.

3. Enable the reset of the decimator, which initializes it to a initial value.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By
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4. Once the reset is disabled, apply the input value to the decimator.

5. Vary the input values to verify the working of the decimator

4.1.2 FIR Filter

A finite impulse response [FIR] filter is a filter structure that is used to implement
almost any sort of frequency response digitally. A fir filter is usually implemented using a
series of delays, multipliers and adders to create the filter’s output.

The filter can be modeled using the equation:

where α (roll off factor) = 0.22

Tc is the sample duration = 0.26042µs

Using this equation we obtain the coefficients of the filter

Table 4.1 Coefficient table of the FIR filter

Slno Coefficient Value Slno Coefficient Value

1 h1,h65 0.001191428 18 h18 ,h48 0.001152062

2 h2,h64 0.000185011 19 h19,h47 0.007466688

3 h3,h63 0.001579242 20 h20,h46 0.013084682

4 h4,h62 0.001803047 21 h21,h45 0.00954521

5 h5,h61 0.000542837 22 h22,h44 0.003722408

6 h6,h60 0.001256441 23 h23,h43 0.019308718

7 h7,h59 0.002070439 24 h24,h42 0.025115184

8 h8,h58 0.001082773 25 h25,h41 0.012377001

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By
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9 h9,h57 0.000979401 26 h26,h40 0.016316573

10 h10,h56 0.002281221 27 h27,h39 0.044815069

11 h11,h55 0.001404123 28 h28,h38 0.049948612

12 h12.h54 0.001231202 29 h29,h37 0.014330881

13 h13,h53 0.003359618 30 h30,h36 0.061652241

14 h14,h52 0.00258634 31 h31,h35 0.156280539

15 h15,h51 0.001353721 32 h32,h34 0.234653662

16 h16,h50 0.005711588 33 h33 0.265028175

17 h17,h49 0.006359228

Figure 4.1 shown below is the block diagram for an FIR filter of length N. The delay
result in operating on prior input samples. The h kvalues are the coefficients used for
multiplication, so that the output at time n is the summation of all the delayed samples
multiplied by the appropriate coefficients.

Figure 4.1: FIR filter of length N

Now considering the existing architecture of the FIR along with the decimator
wherein the decimator is placed after the FIR filter.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

We shall consider a 65 tap FIR filter and a decimator with decimation factor as 4

Y0=x0 X h0

The decimator with decimation

Y1=x1 X h0 + x0 X h1
factor 4 selects every 4th sample of
Y2=x2 X h0 + x1 X h1 + x0 X h2 the FIR output

Y3=x3 X h0+x2 X h1+x1 X h2+x0 X h3

Y4=x4 X h0 + x3 X h1 + x2 X h2 + x1 X h3 + x0 X h4

Figure 4.2: Block diagram of an FIR filter followed by a decimator

Where

xn{ n=1,2,3,.....} is the input to the filter

yn {n=1,2,3,......} is the output of the filter

hn {n=1,2,3,...65} are filter coefficients

Considering the example as x1,x2,x3,x4 as the inputs , as shown in the figure above,
the outputs of the filter are y0,y1,y2,y3,y4. The decimator allows every 4th sample to pass
through it. Therefore, the output of the decimator will have y0, y4.

Though the number of outputs at the decimator is one fourth the number of outputs of
the FIR, the single filter still has to process all samples irrespectively. This increases the
requirement of processing speed, in turn increasing the power consumed by it.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

This problem can be overcome by placing the decimator prior to the filter, where it
allows every fourth sample input to it, thereby decreasing the requirement of the processing
speed and achieving low power working of the filter.

Input Output
Decimator FIR Filter

Y0=x0 X h0

Y1=x4 X h0 + x0 X h1

Figure 4.3: Block diagram of an decimator followed by a FIR filter

This architecture shown in figure 4.3, however introduces a problem where the filter
receives only the fourth samples, whereas the proper working of the filter requires the
previous set of samples too.

This shows that the placement of the decimator without any modification of the above
shown architecture will lead us to wrong results. Hence modifications are necessary to obtain
correct solution. Therefore the modification of the above architecture is shown in figure 4.4.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

X1
X4 X3 X2
Delay Delay Delay

D D D D

FIR 1 FIR 2 FIR 3 FIR 4

𝑌 = 𝑥 × ℎ +𝑥 ×ℎ +𝑥 ×ℎ +𝑥 × ℎ + ⋯𝑥 ×ℎ

Figure 4.4 :Modified architecture of the filter-decimator combination

The 65 tap filter is divided as four filter banks and has a decimator prior to each filter.

From the table 3.4, we can see the symmetrical characteristic of the filter with the symmetry
of the coefficient values.

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

We can utilize the symmetry property of the coefficients to fold the filter, thereby
reducing the requirement of multipliers to half.

Table 4.2: Arrangement of coefficients to achieve optimization

h1 h5 h9 h13 h17 h21 h25 h29 h33 h37 h41 h45 h49 h53 h57 h61 h65

h2 h6 h10 h14 h18 h22 h26 h30 h34 h38 h42 h46 h50 h54 h58 h62

h3 h7 h11 h15 h19 h23 h27 h31 h35 h39 h43 h47 h51 h55 h59 h63

h4 h8 h12 h16 h20 h24 h28 h32 h36 h40 h44 h48 h52 h56 h60 h64

Table 4.2 shows a unique way of arrangement of the coefficients. The coefficients are filled
row wise.

Where the four rows show the arrangement of coefficients to obtain FIR 1,2,3,4
Therefore,
FIR 1 contains coefficients: h1,h5, h9, h13, h17, h21,h25, h29, h33, h37, h41, h49, h53, h57,
h61, h65

FIR 3 contains coefficients : h3, h7, h11, h15, h19, h23, h27, h31, h35, h39, h43, h47, h51,
h55, h59, h63

By grouping the coefficients in a apt manner we can reduce the FIR 2 and FIR 4 filters as
one filter bank named FIR 2,4

FIR 2 4 contains coefficients :h2, h6, h10, h14, h18, h22, h26, h30, h34, h38, h42, h46, h50,
h54, h58, h62, h4, h8, h12, h16, h20, h24, h28, h32, h36, h40, h44, h48, h52, h56, h60, h64
The overall architecture shown in figure 4.4 can be modified as shown in figure 4.5

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 Design of a Low Power Reconfigurable FIR filter for 3G wireless Application-By Nischita

This arrangement is shown in figure 4.5.

X1
X4 X3 X2

Delay Delay Delay

D D D D

FIR 1 FIR 3 FIR 2, 4

𝑌 = 𝑥 × ℎ +𝑥 ×ℎ +𝑥 ×ℎ +𝑥 × ℎ + ⋯𝑥 ×ℎ

Figure 4.5: Optimized architecture of the Figure 4.4

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