XU Yong Ping
Dept of Electrical and Computer Engineering
Email: elexuyp@nus.edu.sg
Outline
1. Module organization
2. Project Introduction
3. AtoD Conversion Basics
4. Successive Approximation ADC
5. Bandgap reference
6. Noise analysis
1
1. Module organization
Aims
Through the design of a prototype IC chip
To provide the opportunity for students to apply
fundamentals and theory to the real life problems
To improve students’ analytical and problem solving
skills
Expose students to commercial integrated circuit
design flows and teamwork
To introduce mixedsignal circuit design, in particular,
ADCs and DACs
2
Lectures and Labs (1)
Semester 1:
Familiarization
with EDA tools Chip design
2 weeks 11 weeks
4 ~ 5 weeks
Tapeout
23 weeks
Design presentation
Presentation from each group Assessment
3
2. Project introduction
Scope
Specifications
Project schedule and execution
Assessment
Refer to the handout for more details
The scope
ECG (Electrocardiogram) signal acquisition system
Bias Voltage
circuit Reference
4
Specifications
System and analog
Technology: 0.35μm CMOS
System supply voltage: 3V
System bandwidth: 0.5 – 150Hz
Amplifier gain: 200
Input referred noise: <10 μV (0.5150Hz)
Input signal amplitude: up to 5 mVpp
Commonmode input range: ±0.5V
DC offset rejection: > ±50 mV
CMRR (instrum. amplifier): > 50dB
Power consumption: As low as possible
ADC
Resolution: 10 bits
Sampling frequency 500Hz
Output format: Binary coded
DNL and INL: < 2 LSB
Load capacitance: 2.5pF@ADC output
With onchip reference
End of conversion (EOC)
EE4410 – Integrated circuit and system design – Xu YP 9
Week 0
Introduction to module and project
Grouping and lab schedule
Week 1 – 6
Lectures and chip design (lab)
Week 7 – 11
Chip design (lab)
5
Assessment
Individual
Subsystem design 35%
Subsystem performance 20%
Chip design presentation 10%
Team
Overall chip design 15%
Overall chip performance 15%
Report writing 5%
3. AtoD conversion
Qantization
Sample & hold
Antialiasing filter
vin n
Sample
Antialiasing
&hold
Quantization vo
6
Quantization and noise
Quantization noise:
Analog input Digital output
3bit ADC ADC
Theoretical ADC Vin Dout
transfer characteristic
111
Center point A full scale (FS) analog signal is converted
110 Midstep Value
into 2n discrete levels which correspond to
Digital output code
+1/2 LSB
The quantization error is bounded between
Analog input ±0.5LSB, that is
0 1 2 3 4 5 6 7
Δ Δ
1/2 LSB
− ≤ eq (n) ≤
2 2
EE4410 – Integrated circuit and system design – Xu YP 13
If assuming that eq(n) is equally distributed (equal Assuming that the signal is a fullscale sinusoidal
probability density) over the range of (Δ/2, Δ/2), as wave with an amplitude of A, the signal power for
shown below, an nbit ADC is
P(e) A2 (FS 2 )2
Ps = =
1/Δ 2 2
The signaltoquantization noise ratio (SQNR) is
e Ps
−Δ/2 0 Δ/2 SQNR(dB) = 10 ⋅ lg
Pn
and is not correlated with the signal, the ⎡⎛ A2 ⎞ ⎛ Δ2 ⎞⎤
quantization noise power (the variance) is = 10 ⋅ lg ⎢⎜⎜ ⎟⎟ ⎜ ⎟⎥
⎜ 12 ⎟
⎣⎝ 2 ⎠ ⎝ ⎠⎦
Pn = σ e2 =
Δ2
e 2 p (e)de =
1 Δ2 2
e de =
Δ2 ⎡ (FS 2)2
≈ 10 ⋅ lg ⎢
(FS 2 ) ⎤⎥
n 2
∫ ∫
Δ −Δ 2 ⎣⎢ ⎦⎥
−Δ 2 12 2 12
≈ 6.02n + 1.76dB
7
Sampling and aliasing
xa(t) – Continuoustime signal with bandwidth of B
xa (t) Xa (ω)
ms(t) – Periodic sampling function.
xo(t) – Sampled version of xa(t), xo(t)=xa(t).ms(t)
t ω τ ∞
⎛ nπτ ⎞
2π/ωs 0 ωs 2ωs 3ωs X o (ω) = ∑m X n a ( ω − nω s ) mn = Sa⎜⎜ ⎟⎟
τ Ts n = −∞ ⎝ TS ⎠
xo (t) Xo (ω)
Sample ωs
≥ 2 B (No aliasing)
2π
xa (t) xo (t) ωs
< 2 B ' (Aliasing occurred)
2π
ms (t)
t ω
0 ωs 2ωs 3ωs
8
Gain and offset errors
Gain error (1 ¾ LSB)
101 101
100 100
000 000
0 1 2 3 4 5 6 7 (FS) 0 1 2 3 4 5 6 7 (FS)
Analog input Analog input
The gain error is the difference between its actual Offset error (¾ LSB)
and ideal FS value. It may be expressed in terms
of LSB or in the percentage of the FS value. In The offset error is defined as the amount of the
this example, the gain error is negative. analog value shifted from zero when the digital
output code is zero. It may be expressed in terms
For the actual ADC transfer characteristic, the full of LSB or in the percentage of the FS value.
scale point can be determined by either the
endpoint or the best fit line.
EE4410 – Integrated circuit and system design – Xu YP 17
½ LSB
Digital output code
101 101
½ LSB
100 100
¼ LSB
011 011
 ¼ LSB
¾ LSB
010 010
¼ LSB ¼ LSB
001 001
½ LSB
¼ LSB
000 000
0 1 2 3 4 5 6 7 (FS) 0 1 2 3 4 5 6 7 (FS)
Analog input Analog input
9
Signaltonoise and distortion ratio
Power spectral density (dB) In this example, when the power spectral
density is used,
Signal tone
Ps
Spurious tones
SINAD(dB ) = 10 lg
Pn
S2
Harmonics
= 10 lg
H 22 + H 32 + N 2
Noise floor where
Noise floor
DR Peak SNR
f
0dB Signal bandwidth
DR
Input amplitude
120dB Max. input (0dB)
10
Effective number of bits (ENOB) and
effective resolution bandwidth (ERBW)
Effective number of bits (ENOB): Effective resolution bandwidth (ERBW) [1]
Measured SNR n
ENOB: n – 0.5 (3dB)
SINAD(dB) − 1.76
ENOB(bit ) =
6.02
ref2 = 8
ref3 = 12
3. X > 12? Yes 12 < X < 16
12 X 16
"1" is assigned to bit 2
ref4 = 14
4. X > 14? No 12 < X < 14
X "0" is assigned to bit 1
12 14
ref5 = 13
5. X > 13? Yes 13 < X < 14 "1" is assigned to bit 0 (LSB) and the digital output is 01101.
~ 14 − 13
x = 13 + = 13.5 ⇒ Error = 13.5 − 13.7 = −0.2
2
14 − 13 1
Error (max) = ± = ±0.5 ⇒ ± LSB
2 2
EE4410 – Integrated circuit and system design – Xu YP 22
11
System architecture
Comparator
Vin,ana
S/H +
 Vref
CLK
Error
Dout 0.5Vref
1 0 1 1 0 0 1 Dout
CLK Register
SAR
S.Conv 0
1 2 3 4 5 6 7
# of successive approximation
S.conv
Comparator
Vin,ana
S/H + k=0

CLK
k = k+1
Vref DAC
Bit(nk) = 1 no
Dout yes
n  k = 0? E.conv
no
SAR
S.Conv
Bit(nk) = 0
12
Successive approx. Register (SAR)
Example:
*Johns & Martin, Analog Integrated Circuit Design, First edition, John Wiley & Sons, 1997
Vout
n1
2 C 2C C C
n2
2 C
n −1
2k C
Vout = ∑ Dk ⋅ Vref
k =0 2n C
Vref
Dn1 Dn2 D1 D0
13
SAADC based on charge scaling
V ref V ref
D2 D1 D0 D2 D1 D0
D1 = 1, D2,0 = 0 D2,1 = 1, D0 = 0
Vo Vo
2C C C 2C C C
3V ref
S1 V ref S1 3C
Vo =
C
⋅ V ref = Vo = ⋅ V ref =
4C 4 4C 4
Vref
Vref
D2 D1 D0
D2 D1 D0
14
SAADC based on charge redistribution
reset
Capacitor array DAC
(Ctotal = 2nC) Vtop
Dbit,out
2n1C 2C C C Comparator
2n2C
from SAR
Vin
Vref
Vin
Vref
Vref
2
Vref
Vin
Vi ,comp = −Vin + >0
reset 2 reset
n1 ⇒ Dn −1 = 0 n2
2 C 2 C
Vi,comp Vi,comp
Vref Vref
Dn1 Dn1
n2
n1 Vin Vref 3(2 )C Vin Vref
2 C Comparator Comparator
2 4
Vref
Vi ,comp = −Vin + Vi ,comp = −Vin +
Vref
2 4
EE4410 – Integrated circuit and system design – Xu YP 30
15
Capacitance mismatch error
Assume that the unit capacitor, C, has a mismatch of ΔC.
Worstcases INL:
( )
INL max = 2 n −1 C + ΔC max,INL − 2 n −1 ⋅ C = 2 n −1 ⋅ ΔC max,INL
C LSB
ΔC max,INL ≤ for INL <
2n 2
Worstcases DNL:
DNLmax = ( 2 n − 1) ⋅ ΔC max,DNL
1 C LSB
ΔC max,DNL ≤ ⋅ for DNL <
2n − 1 2 2
16
Commercial Successive approx. ADCs
Resolution: 12b
Conv. Time: 1.6μS
Throughput: 100kSPS
Supply: +2.7 to 5.25V
Power dissipation:
0.9mW@100kSPS and 3V
Resolution: 10b
Conv. Time: 20μS
Supply: +5V and 12V
Power diss.: 325mW
Comparator
Ideal comparator Nonideal comparator
V0 V0
V0 V0
Vop+ Vop Vop
Low gain
+
Vin V0 High gain
 0
Vin Vin
0
Vin = V+ − V− Vop Vin
0
0 Vref
Minimum resolved Hysteresis
Infinite gain ⎧Vop + ← (Vin > 0) ⎧Vop ← (Vin > Vref ) input voltage
V0 = ⎨ V0 = ⎨
No hysteresis ⎩Vop − ← (Vin < 0) ⎩ 0 ← (Vin < Vref )
Effect of nonidealities:
V0 V0 Limited slew rate Low gain reduces the
resolution.
Vop Vop
Nonzero offset
Vin Zero rise and Vin introduces error.
Vref fall time Hysteresis introduces
Vref
No input offset Zero offset error, but increases the
Nonzero offset noise immunity.
t t Slew rate limits the
0 0 speed.
17
Highgain amplifier as a comparator
Avo
Avo ⋅ ω3dB = ωu
Highgain Amplifier as a comparator Acl ⋅ ω3dB −cl = ωu
Acl=1/β
V0
0dB ω
Vop+ ω3dB ω3dBcl ωu
+
Vin A V0
ideal low gain

Vin V0
high gain
ΔV0
AV = slope =
Vop ΔVin Vfinal

A(s)
−1 ⎛ v (t ) ⎞ − 1 ⎛ vin (t ) β − v0 (t ) ⎞
Vo(s) t settle = ln⎜1 − 0 ⎟= ln⎜ ⎟⎟
ω3dB ⎜⎝ vin (t ) β ⎟⎠ ω3dB ⎜⎝ vin (t ) β ⎠
Av 0
Openloop: Av (s ) = (1) Expected output Settling error
1 + s ω3dB
For the settling error less than 1%,
V0 (s ) Av (s )
Closedloop: Acl (s ) = = (2)
Vin (s ) 1 + βAv (s ) 4.6 4.6
t≈ or t≈
ω3dB −cl ωBW
Substitute (1) into (2),
ωu ωu
Acl (s ) = = (βAV 0 >> 1) ωBW = ω3db (Openloop)
s + βωu s + ω3dB −cl = ω3dBcl (Closeloop)
= ωu (Unitygain)
18
Nonlinear settling time – slew rate
Nonlinear settling is a large signal behavior. Smallsignal model or analysis is
therefore not valid.
Transistors are operated in nonlinear regions (triode or cutoff)
The nonlinear settling time is determined by the slew rate
Slew rate indicates how fast the output signal reaches its final value under large
signal condition.
Vin 
I0 A2 Vo
+
 VC + I0 CL
M1 M2 CC
I0
 Vo
A2
I0 +
M3 M4 dVC dV0 dVC I
CC = I0 SR = = = 0
dt dt dt CC
gm 2 I 0 ⋅ ωu
Since ωu = SR ==
CC g m2
Regenerative comparator
Regenerative latch
Regenerative latch and metastability:
Preamplifier
CL CL
+
A Latch V0

CLK
ΔVinitial/final
Vfinal
Drive + Regenerative
Vin A V0
circuit  latch
Valid logic high
CLK
Preamplifier
acts as a buffer Vinitial
19
Examples
Regenerative comparator 1
φ1 = 0 > Track phase
The drain voltage of M12 and M13. is equal to VDD and Q
M12 M13 = 0. The drain voltage of M6 and M7 is ground.
Vibias M5 φ1 φ1
M14 M15
Q φ1 = 1 > Latch phase
M2
Vip M1 Vin φ1 The drains of M6 and M7 are discharged initially through
Qn
D1 M10 M8 and M9. The discharge currents depend on the input
M11
signal. After the discharge starts, an ΔVinitial is
D2 M8 M9 developed across the latch and regenerative process
M3 M4 follows.
M6 M7
Examples (cont’d)
M8 M9 M4
Vbias M3 φ1 M6 M8 M9
M5 M7
To SR latch
M1 M2 φ2
Vin φ1
M1 M2 V0
Vin
M12 M12
Preamplifier Latch
Preamplifier Latch
φ1 = 1 and φ2 = 0 > Latch phase. Comparator 3 has less kickback noise, but slightly
The latch regenerates from ΔVinitial to a full digital high power consumption due to the static current
output. in the latch during track phase.
20
Sample and hold circuits
Sample and hold
vin Sample vo
& hold
clk
Ideal Nonideal
Vo Vo
Vin Vin
h
s s h
t3 t t
0 t1 t2 0
vdd vdd  vT
Vo
C
t
0
Vin
PMOS: VT < Vin ≤ Vdd
t GND
0
Clk GND vT
s h s h s
C
t
0
21
On resistance of switch
Ron
1 NM OS
NMOS: Ron ,n = → ∞, when Vin = Vdd − VT
W
μ n Cox (VDD − Vin − Vth )
L
1 0 V DD − VT
PMOS: Ron , p = → ∞, when Vin = VT Vin
W Ron
μ n Cox (Vin − Vth )
L
PM OS
V0
Ron actual
vin vo
h t h t h t h t
t
Firstorder settling:
⎛ v (t ) ⎞ ⎛ 1 ⎞
t settle = − Ron C ln ⎜⎜ 1 − 0 ⎟⎟ = Ron C ln ⎜⎜ ⎟⎟
⎝ v in (t ) ⎠ ⎝ settling error ,% ⎠
Fast settling requires small Ron and C
⎛ 1 ⎞
C ln ⎜⎜ ⎟⎟
or t settle = ⎝ settling error ,% ⎠
W Signal dependent
μ n C ox (Vclk − Vin − VT )
L
EE4410 – Integrated circuit and system design – Xu YP 44
22
S/H errors and remedies
Clock feedthrough
Charge injection
Droop (Voltage on holding capacitor)
Aperture time and error
Clock feedthough
vdd
ΔV C gs
0
ΔV = VDD
Clk C gs + C L
Cgd Cgs
 Clock feedthrough is caused by parasitic capacitance
vin vo in MOSFET.
C  Independent of input voltage.
 Only introduces constant DC offset or Pedestal error.
Remedies:
vdd
vdd
 Use dummy transistor Clk Clk
0 0
 Use complementary switch
 Use differential structure Cgd Cgs Cgd/2 Cgs/2
vin vo
Δq Δq/2 Δq/2
C Dummy
transistor
(half size of the switch)
23
Channel charge injection
vdd
Clk
Charges in the channel exit from source and drain, and
0
are injected onto signal source and the sampling
capacitor, causing an error in the voltage across the
vin vo capacitor.
Δq Δq C
Psub
⎛ WLC ox
V0 = Vin ⎜ 1 −
⎝ 2C
⎞ WLC ox
⎟−
⎠ 2C
[ (
V DD − Vth 0 + γ 2φB + VSB − 2φ B )]
⎛ WLC ox
= Vin ⎜ 1 −
⎝ 2C
⎞ WLC ox
⎟−
⎠ 2C
γ 2φB + Vin −
WLC ox
2C
(
VDD − Vth 0 + 2φ B )
[6]
Linear Nonlinear DC offset
Remedies:
Same remedies for clock feedthrough can be used to reduce the charge injection.
24
Droop
Clk
vin
v0
CL RL
n n
Psub Leakage
Leakage
S/H circuits
Openloop S/H circuits
25
Closedloop S/H circuit 1
φ1
φ2

φ1 vo
 A
A +
vin +
Track
Hold

 (vin) A vo
 A vo +
A +
vin +
C
C
φ1 C

+ φ2 A vo
A +
vin 
Track (φ 1) Hold (φ 2)
C
C 
 A vo
+ A vo +
A +
vin 
C
Signal dependent charge injection is eliminated Clk
Since one terminal of the switch is at ground or
Virtual ground.

WLC ox (V DD − Vth )
1
Δq = Δq +
2
26
Bottomplate sampling S/H circuit
φ1 φ1
SW1
φ2
vin vo vin vo
Δq1 Δq2 Δq 1 Δq 2=0
C t C
φ1
SW2 I c=0
φ2 φ2
t
5. Bandgap reference
Outline
Bandgap voltage reference
PTAT current source
Design issues
27
Bandgap voltage reference
Temperature independent voltage source
+
k1 Vref = k1V1 + k2V2
k2
V1 ∂V1 ∂T > 0
With properly chosen k1 and k2,
reference voltage, Vref, can be made
independent of the temperature, that
V1 has a positive V2 ∂V2 ∂T < 0
is,
temperature coefficient.
dVref ∂V1 ∂V
= k1 + k2 2 = 0
V2 has a negative dT ∂T ∂T
temperature coefficient
IC
VBE = VT ln At room temperature, T=3000K,
IS
Eg
ln − (4 + m ) T − VT
VT I 0 V
=
T IS T kT 2
VBE − (4 + m )VT − E g q
= Note that the temperature coefficient of VBE depends on
T
the temperature.
where assumed that IC is constant and independent
of temperature.
EE4410 – Integrated circuit and system design – Xu YP 56
28
Voltage source with positive TC
R2
Vref = VT ln n + VT ln n + VBE 2
R3
R1 R2
⎛ R ⎞
b  = ⎜⎜1 + 2 ⎟⎟VT ln n + VBE 2 (1)
a + ⎝ R3 ⎠
+
R3
Vref (Positive TC) (Negative TC)

Q1(AE) Q2 (n x AE) ∂Vref ∂VBE 2 ⎛ R2 ⎞ VT
For zero TC of Vref, = + ⎜⎜1 + ⎟⎟ ln n = 0
∂T ∂T ⎝ R3 ⎠ T
⎛ R2 ⎞
or (
⎜⎜1 + ⎟⎟VT ln n = − VBE 2 − (4 + m )VT − E g q ) (2)
Va = Vb , R1 = R2 , Vref = VR2 + VR3 + VBE 2 ⎝ R3 ⎠
Vref = (4 + m )VT + E g q
VBE1 − VBE 2 1
I R3 = = VT ln n
R3 R3
When T = 0,
R2
VR2 = I R2 ⋅ R2 = I R3 ⋅ R2 = VT ln n Vref = E g q Bandgap voltage reference
R3
29
BJTs in CMOS technology
C E B
p+ p+ n+
Vertical PNP transistor nwell
psubstrate
C E B
p+ p+ p+ n+
Lateral PNP transistor nwell
psubstrate
VGS +
−
A IR I 0 = IR
+

Q1 Q2
Area=A Area=nA
30
Bandgap voltage reference using PTAT
IR
+ R2

Vref V ref = I R 2 ⋅ R 2 + V BE 3 = VT ln n + V BE 3
R1
R1
R2
Q2(nxAE)
Q1(AE) Q3
Vref
R1
R2
Q2(nxAE)
Q1(AE) Q3
Design issues
31
Collector current variation
I0
I0 VT ln n
R ΔVBE=VTlnn IC = I R = PTAT
R
Q1(AE) Q2(nxAE)
∂VBE ∂VT I C ⎛ 1 ∂I S 1 ∂I C ⎞
= ln + VT ⎜⎜ − ⎟⎟
∂T ∂T IS ⎝ I S ∂T I C ∂T ⎠
∂VT I C VT ∂I S VT
= ln − +
∂T I S I S ∂T T
VBE − (3 + m)VT − Eq q
=
T
Opamp offset
VDD
R1 R2
VGS +
b 
−
+
a +
+
R3 Vos
Vref A IR

+

+
Q1(AE) a b
Q2 (n x AE)
Vos R1
ΔVBE
Q1(AE) Q2(nxAE)
V R 3 = V BE 1 − V os − V BE 2 = VT ln n − V os
⎛ R ⎞
V ref = ⎜⎜ 1 + 2 ⎟⎟ (VT ln n − V os ) + V BE 2
⎝ R3 ⎠
IR =
1
(VT ln n + Vos )
R1
32
Feedback polarity
R2
R1 R2
b 
R3
a + b
+ 
R3 Vref
Vref 1/gm2 a
+
 1/gm1
Q1(AE) Q2 (n x AE)
VBE2 R1
VBE1
Feedback coefficients:
R3 + 1 g m 2 1 g m1
βN = βP =
R3 + 1 g m 2 + R 2 R1 + 1 g m1
A (V BE 1 − V BE 2 − β PV BE 1 + β N V BE 2 )
V ref = Positive feedback if βP > βN
1 − A (β P − β N )
Startup problem
The circuit has two equilibrium points. It may not start operation
itself if all nodes have zero initial voltage
Rc
M6
R1
M5
Q1 Q2
Startup circuit
33
6. Noise analysis
Noise definition
Noise presentation in time domain
Noise presentation in frequency domain
Noise measures
Noise models
Example
Noise definition
34
Noise presentation in timedomain
Vn2,rms
Normalized noise power: Pn = = Vn2,rms
1Ω
noise
Pn = I n2, rms × 1Ω = I n2, rms
t
1 T 1 T
Average noise power: Pn ,av = Tlim
→∞ T ∫
0
vn2 (t )dt Pn ,av = lim
T →∞ T ∫
0
in2 (t )dt
1/ 2
⎡1 T ⎤
1/ 2
⎡ ⎤ 1
I n, rms = ⎢ ∫ in2 (t )dt ⎥
T
rms noise voltage or current:Vn,rms = ⎢T ∫0 vn (t )dt ⎥
2
⎣ ⎦ ⎣T 0 ⎦
V2n,rms(f ) and I2n,rms (f ) are the power spectral density (V2/Hz or A2/Hz)
Resolution BW
1 2 3 4 5 6
n
35
Equivalent noise bandwidth (1)
White noise
Vni(f ) H(s)
[
Vno ( f ) = H ( j 2πf ) V ( f )
2 2
ni ]
1/ 2
V2 nw
Filtered out
White noise f0 f
π
Equivalent noise bandwidth: feq = f0
2
EE4410 – Integrated circuit and system design – Xu YP 71
V
P
f3
f2
f1
f0
t
0
36
Time vs frequency domain (2)
37
Noise summation
1 T
[Vn1(t ) + Vn 2 (t )]2dt
T ∫0
Vn1(t)
Vno2 ,rms =
Vn0(t)
2 T
Vn2(t)
= Vn21,rms + Vn22,rms + ∫ Vn1 (t ) ⋅Vn 2 (t )dt
T 0
= Vn21,rms + Vn22,rms
Noise measures
Input referred noise (equivalent input noise)
v0
= Av
RS
In1
vin
Vs Vin In2 Vn2 V0
v0 Zin
= Av = Av ,ov
Zin
Vn1
vs Rs + Zin
Noise equivalent circuit: Input referred noise
RS Vn,rms RS
Vn,th Vni
Input In,rms Noiseless circuit Output Input Zin Noiseless Output Vno
Vs Vs circuit
38
Input referred noise (2)
RS Vn,rms RS
Vn,th In,rms Vni1 Zin Noiseless Vno Vni Vni1 Zin Noiseless
circuit circuit
vn0 = Av ,ovvni
2
2
vno
vni2 = 2
= vn2,th + vn2,rms + in2,rms Rs2 = 4kTRs Δf + vn2,rms + in2,rms Rs2
Av ,ov
⎡P ⎤ ⎡V 2 ⎤ ⎡V ⎤
SNR(dB) = 10 log⎢ s ⎥ or SNR(dB) = 10 log⎢ s2,rms ⎥ = 20 log⎢ s,rms ⎥
⎣ Pn ⎦ V
⎣ n,rms ⎦ ⎣Vn,rms ⎦
NF describes how much the noise has increased through the circuit under evaluation.
⎛ A v ⎞ ⎛ v2 + v2 + i2 R2 ⎞
NF (dB) = 10 log
(SNR)i
NF ( dB ) = 10 log⎜⎜ v ,ov ni ⎟⎟ = 10 log⎜⎜ n ,th n ,rms2 n ,rms s ⎟⎟ > 1
(SNR)o
or
⎝ Av ,ov vn ,th ⎠ ⎝ vn ,th ⎠
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Noise models
Noise in resistors
4kT
I n2, r ( f ) =
R R
In,r
2
I nr , rms = 4kTΔf R I nr ,rms = (4kTΔf R )1/ 2
kT/C noise
Vnr2 ( f ) = 4kTR
R
R C Vn20,rms Vnr(f) C Vn20,rms 1 jωC
H ( jω ) =
R + 1 jωC
1 ∞ 1 ∞ 4kTR ⋅ (1 RC )2 dω = kT
∫0 Vn (ω ) ⋅ H ( jω ) dω = ∫0
2
Vn20,rms = 2
kT/C
2π 2π ω + (1 RC )2
2 C
4kTR
Recalculate the total noise power using the equivalent noise bandwidth:
f0 feq
f
f0 =
1 π π 1 1
3dB frequency: Equivalent noise bandwidth: f eq = f0 = =
2πRC 2 2 2πRC 4 RC
1 kT
Vn20, rms = 4kTR ⋅ f x = 4kTR ⋅ = Independent of R
4 RC C
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Diode
The noise source in a diode or PN junction is shot noise, caused by random passage of
individual charge carriers across a potential barrier. Shot noise is a random noise and white.
kT i(t) P(i)
rD = In,d (t)
qI D
rD In,D ID
t Idiode
ID
Bipolar transistor
I nc2 2qI C kT ⎛ 1 ⎞
vni2 = + 4kTrb = ⋅ + 4kTrb = 4kT ⎜⎜ + rb ⎟⎟
g m2 g m qI C ⎝ 2 gm ⎠
Vnb2 ( f ) = 4kTrb
I nc2 ⎛ KI IC ⎞
I ni2 = I nb
2
+ I nf2 + = 2q⎜⎜ I B + B + ⎟
β ( f ) 2 ⎟⎠
fcnr is correlated with the 1/f corner frequency
β ( f )2 ⎝ f
K is a constant related to the process
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MOS transistor (1)
⎧ 1 Triode
⎪
γ = ⎨2 3 Strong − inversion
⎪1 2 Weak − inversion
⎩
*Christian C. Enz and Yuhua Cheng, “MOS transistor modeling for RF IC design,” IEEE Journal of SolidState Circuits, vol. 35, pp. 186  201, February 2000.
Flicker noise:
K – processdependent constant
K W – channel width
Vnf2 ( f ) =
WLCox f L – channel length
Cox – unit gate capacitance
Vnf2 ( f ) Vni2 ( f )
I d2 ( f )
1 K
Vni2 ( f ) = 4kTγ + *Only channel thermal noise and flicker
g m WLCox f noise are considered.
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MOS transistor (3)
ω 2Cgs2
2
ing = 4kTg ng g ng ≈ At strong inversion
5g m i2ng Gng C gs
Operational amplifier
Noiseless
in2
v n2 A
+
in+2
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Example 1 – Cascode amplifer (1)
A cascode amplifer is shown in the figure below. Calculate the total output noise power at dc
and the inputreferred noise. Ignore the flicker noise and assume that gm1 = gm2 = gm, rds1 =
rds2 =rds, RL<<rds and gmrds>>1.
= g m1 (rds1 rin 2 ) ≈
(ii) Calculate Vno1 due to Vn1 v gs 2 g m1
Av1a = =1
rds2 vn 1 gm 2
ix ⎛ v +v ⎞
vno1 = −⎜⎜ g m 2 vgs 2 + no gs 2 ⎟⎟ ⋅ RL
+ rds1  gm2vgs2 + ⎝ rds 2 ⎠
vgs2 RL
vn1
vno1 (1 + g m 2 rds 2 )RL
gm1vn1 vno1
 + 
Av1b = = ≈ − g m 2 RL
vgs 2 rds 2 + RL
rin2
vno1
Av1 = = Av1a ⋅ Av1b ≈ − g m 2 RL
DC gain from Vn1 to Vn01: vn1
vx − ix RL
ix = g m 2 v x + Output noise power due to vn1:
rds 2
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Example 1 – Cascode amplifer (3)
⎛ v −v ⎞
(iii) Calculate Vno2 due to Vn2 vno 2 = −⎜⎜ g m vgs 2 + no 2 1 ⎟⎟ RL (E3)
⎝ rds ⎠
rds2
Substituting (E1) and (E2) into (E3),
+ vgs2 
⎛R ⎞
+ + gm2vgs2
+ vno 2 ≈ −⎜⎜ L ⎟⎟ ⋅ vn 2 (g r >> 2 )
m ds
vn2 rds1 v1
RL vno2 ⎝ rds ⎠
  
v R
Av 2 = no 2 ≈ L
vn 2 rds
DC gain from Vn2 to Vno2 :
⎛ v −v ⎞
v1 = (g m rds vgs 2 + vno 2 ) (E1)
1
v1 = ⎜⎜ g m v gs 2 + no 2 1 ⎟⎟rds
⎝ rds ⎠ 2
rds vn 3
vno 3 =
R ⎛ 1⎞ 1
RL 1 + L − ⎜⎜ g m + ⎟⎟ RL ⋅
rds ⎝ rds ⎠ g m rds
 +
rds vgs2 gm2vgs2
+ v ≈ vn 3
no3
vn3 
+

vno 3
Av 3 = ≈1
vn 3
DC gain from Vn3 to Vno3 :
⎛ v +v ⎞ R ⎛ 1⎞
vno 3 = vn 3 − ⎜⎜ g m v gs 2 + no 3 gs 2 ⎟⎟ RL = vn 3 − L vno 3 − ⎜⎜ g m + ⎟⎟ RLv gs 2 (E5)
⎝ rds ⎠ rds ⎝ rds ⎠
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Example 1 – Cascode amplifer (5)
2
vno = vno
2
1 + vno 2 + vno 3
2 2
vn20 vn20 4kTRL 2
vni2 = 2 = 2 ≈ + 4kT
2
vno1 2 vno 2 2
2
v
2
AV g m RL ( g m RL )2 3g m
= vn 1 + vn 2 + no 3 vn23
v n1 vn 2 vn 3
⎡ ⎛R ⎞ ⎤
2
From RL
= ⎢(g m RL ) + ⎜⎜ L ⎟⎟ ⎥ ⋅ 4kT
2 1
+ 4kTRL
2
⎢⎣ ⎝ ds ⎠ ⎥⎦
r 3 gm From input transistor
≈ (g m RL ) 4kT
2 1
+ 4kTRL
2
3 gm
Vno2 can actually be ignored.
⎛ 2 ⎞
= 4kTRL ⎜1 + g m RL ⎟
⎝ 3 ⎠
Since 2/3gmRL >> 1, the noise from the input transistor is the dominant noise source.
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