COMPUTER TECHNOLOGY • First Generation - Vacuum tube - 1945-1955
central nervous system of the
Computer
 a device made up of a combination of
electronic and electromechanical components
that performs high-speed calculations and
other processing operations on input data.
 a machine for manipulating data according to
a list of instructions.
Embedded computer
 the most common form of computer in use
today is by far the. Embedded computers are
small, simple devices that are often used to
control other devices
THE EVOLUTION OF COMPUTER
ENIAC (Electronic Numerical Integrator And
Computer)
• Eckert and Mauchly from University of
Pennsylvania
• To be used for trajectory tables for weapons in
WWII
• Started 1943 and finished 1946
Too late for war effort but used until 1955
• Occupied about 15,000sq. ft. of floor spaces
and weighed 30 tons
• 18,000 vacuum tubes
• Run program one at a time
• First large scale computer
• Decimal (not binary)
• 20 accumulators of 10 digits
• Programmed manually by switches
• 140 kW power consumption
• 5,000 additions per second
Generations of Computer
• Zeroth Generation - Mechanical computers
– 1642-1945
• Second Generation - Transistor - 1955-1965
• Third Generation – Integrated circuits
• Small scale integration - 1965 - 1980
 Up to 100 devices on a chip
• Medium scale integration - 1968
 100-3,000 devices on a chip
• Large scale integration - 1971
 3,000 - 100,000 devices on a chip
• Fourth Generation - Very large scale
integration - 1980 to date
 100,000 - 100,000,000 devices on a chip
• Ultra large scale integration
 Over 100,000,000 devices on a chip
COMPONENTS OF THE COMPUTER SYSTEM
1. Hardware – refers to the physical components
of the system.
2. Software – refers to the program
Types of softwares:
1. system software – ex. DOS,
Windows2000, UNIX
2. application software – ex. MSWord,
PhotoShop
3. Firmware – software implanted into the
hardware
4. Dataware – refers to all the data needed in
data processing
5. Liveware / peopleware – refers to the user
Central Processing Unit (CPU) – the brain of the
computer
Performs the following
a. input operation
b. processing operation
c. output operation
Components of a CPU:
A. Arithmetic Logic Unit (ALU) – takes care of
arithmetic operations and logical data
comparisons.
B. Control Unit (CU)
-
computer
- directs the sequence of
operation
C. Memory Unit (MU)
- these are registers
(temporary storage devices)
- program instructions,
addresses, and data are
stored here
Microprocessor – CPU in a single chip
Advantages of Computer Data Processing
1. more rapid data processing
2. more accurate data processing
3. more automatic data processing
4. more economical data processing
Capabilities of Computers
1. perform certain logic operations
2. provide new time dimensions
3. store and retrieve information
4. control error
5. check itself
Limitations:
1. dependence on prepared instructions
2. inability to derive meaning from objects
3. inability to generate information on its own
ANALOG AND DIGITAL SYSTEM
Analog systems – contain devices that manipulate
physical quantities that are represented in analog
form.
Digital systems – combination of devices designed to
manipulate physical quantities or information that are
represented in digital form; that is, they take on only
discrete values.
NUMBER SYSTEMS COMMONLY USED IN  Expand each base 8 number to its 3- Straight Binary Coding
DIGITAL TECHNOLOGY bit binary equivalent. - when the decimal number is represented by its
d. Base 16 to Base 2 equivalent binary number.
A. Decimal Number System (Base 10)  Expand each base 4 number to its 4-
B. Binary Number System (base 2) bit binary equivalent. Types of Binary Coding:
C. Octal Number System (Base 8) e. Base 8 to Base 16 A. Binary Coded Decimal Code (BCD)
D. Hexadecimal Number System (Base 16)  Base 8 to Base 2 to Base 16  It represents each digit of a decimal number
f. Base 16 to Base 8 by its binary equivalent
Methods of Conversion:  Base 16 to Base 2 to Base 8  It is a decimal system with each digit
3. Mathematical operation encoded in binary equivalent.
1. Mathematical Method (applied to any base n The general procedure to perform any  The weights are 8 4 2 1.
conversion) mathematical operation is to convert the
a. Base n to Base 10 number from the given base to decimal and B. Excess-3 Code
 use Positional Value Method then do the operation and convert it back to  The excess-3 code for a decimal number is
b. Base 10 to Base n the given base. performed in the same manner as in BCD
 Case 1: for integers/whole numbers 4. Complements. Commonly used to represent except that 0011 (or 3) is added to each
only negative numbers in most computer systems. decimal digit before encoding it in binary.
Successively divide the given base They are used in digital computers for  Unweighted code (the bit positions do not
10 number by n until the quotient is simplifying subtraction operation and for have any specific weight assigned to them).
zero. The remainder forms the logical manipulations.  Used in some old computers.
answer. Read it from the last a. r's complement Decimal BCD Excess-3
remainder going back to the first. Given a positive number N in base r 0 0000 0011
 Case 2: for fractional numbers only. with an integer part of n digits, the r’s 1 0001 0100
Successively multiply the given base complement of N is defined as 2 0010 0101
10 number by n until the product is  (rn)10 – N for N is not equal to zero 3 0011 0110
zero or depending on the number of  0 for N = 0 4 0100 0111
decimal places required. The integer b. (r-1)'s complement 5 0101 1000
part in the product forms the answer. Given a positive number N in base r 6 0110 1001
Read it from the first to the last. with an integer part of n digits and 7 0111 1010
c. Base m to Base n fractional part of m digits, the (r-1)’s 8 1000 1011
 Base m to Base 10 to Base n complement of N is defined as 9 1001 1100
2. Shortcut method conversion  (rn – rm)10 – N
Limitation: for binary, octal, hexadecimal
conversions only C. Gray Code (Reflected Code)
Digital Systems which includes computers use
a. Base 2 to Base 8  Belongs to a class of codes called minimum-
signals that have two distinct values and circuit
 Group by 3, start from the radix point change-codes, in which only one bit in the
elements that have two stable states; hence, data is
and get its equivalent. code group changes when going from one
represented by a series of 1s and 0s.
b. Base 2 to Base 16 step to the next.
 Group by 4, start from the radix point  Classified as an unweighted code.
CODES
and get its equivalent. The term used when numbers, letters, or words Decimal Binary Gray Code
c. Base 8 to Base 2 are represented by a special group of symbols. 0 0000 0000
1 0001 0001
 2 0010 0011  Named after Emile Baudot, pioneer in  Example: Either “it has rained” OR “someone
3 0011 0010 telegraph printing splashed water”, “must be tall” AND “good vision”.
4 0100 0110  5 bits character code  A tool used for the analysis and design of digital
5 0101 0111  Also called telex code systems
6 0110 0101  Primarily used for low-speed teletype Note: Boolean constants and variables are
7 0111 0100 equipment allowed to have only two possible values, 0 or 1.
8 1000 1100  Uses figure shift and letter shift
9 1001 1101 Example: A – 11000; dash(-) – 11000 Three basic operations:
10 1010 1111 Q – 11101; one(1) – 11101 1. Logical Addition (OR operation)
11 1011 1110 Note: Figure shift – 11111 0+0=0 1+0=1
12 1100 1010 Letter shift – 11011 0+1=1 1+1=1
13 1101 1011
14 1110 1001 B. Internal Code – 6 bits 2. Logical Multiplication (AND operation)
15 1111 1000 0•0=0 1•0=0
C. ASCII (American Standard Code for 0•1=0 1•1=1
D. Others Information Interchange) code – 7bit code and
a. 8 4 -2 -1 has a form; b7 b6 b5 b4 b3 b2 b1 b0 3. Logical Complementation or Inversion (NOT
 negative weighted code Example: A – 11000001 operation)
b. 2 4 2 1 and 5043210 0’ = 1 1’ = 0
 also weighted codes D. EBCDIC code
 Extended BCD Interchange Code Postulates and Theorems of Boolean Algebra
The BCD is both a code and a direct binary  8 bits character codes X+0 = X X•1=X
conversion, as long as the numbers are from 0 to 9.  being used by IBM computer X+X’ = 1 X•X’=0
 has a form; b0 b1 b2 b3 b4 b5 b6 X+X = X X•X=X
The excess-3, 2421 and the 84-2-1 are self X+1 = 1 X•0=0
complementary code, that is, the 9’s complement of ERROR DETECTION CODES X+Y = Y + X X•Y=Y•X
the decimal number is easily obtained by changing  Parity Bit – extra bit included with a message X+(Y+Z) = (X+Y) X(YZ)=(XY)Z commutative law
the 1s to 0 and 0s to 1. to make the total number of 1s either odd or +Z X+YZ=(X+Y)(X+Z) associative law
even. X(Y+Z)=XY+XZ X(X+Y)=X law of absorption
The biquinary code has an error-detection properties. Note: even parity – number of 1s is even X+XY=X (XY)’=X’+Y’ De Morgan’s
odd parity – number of 1s is odd (X+Y)’=X’+Y’ theorem
Alphanumeric Code
BOOLEAN ALGEBRA Types of Boolean Expressions:
 A binary code of group of elements consisting
a. Sum-of-Product Term Expression (SOP)
of the ten decimal digits, the 26 letters of the
alphabet, and certain number of special  May be defined with a set of elements and a set of  Sum of the product terms corresponding to an
symbols such as the dollar sign, etc. output of 1.
operators.
Product Term – product of the input variables where
 named after George Boole who used it to study the variable with the value of zero is complemented.
Different types: human logical reasoning – calculus of proposition.
A. Baudot Code  Events : true or false b. Product-of-Sum Term Expression (POS)
 Developed by Thomas Murry, French
 Connectives : a OR b; a AND b, NOT a  Product of the sum terms corresponding to an
postal engineer.
output of 0.
 Sum Terms – sum of the input variables where the A A' A A B A+B
A A' A+B
variable with the value of one is complemented. B
0 1 0 0 0
A A'
1 0 A  0 1 1
Truth Table B 1 A+B
- Provides a listing of every possible combination of 1 0 1
inputs and its corresponding outputs.  Application of the Inverter: complement. 1 1 1
Binary number
No. of possible combinations = 2n 1 1 0 1 0 0 0 1
Where n = no. of input variables
The NAND Gate
Methods of simplifying Boolean Expression:
 The NAND Gate
KARHAUGH MAP
- provides a simple straight forward procedure for A
B (A.B)'  A
B
(A.B)'
minimizing Boolean functions and is regarded as a
pictorial form of a truth table. 0 0 1 0 1 1 1 0 A B (A.B)'
- is first proposed by Veitch and slightly modified by 1’s Complement
Karnaugh. It is also known as “Veitch diagram”. 0 0 1
A &
The AND Gate B
(A.B)'
0 1 1
Objective in k-mapping:  The AND Gate
A A B A.B 1 0 1
1. To have the most number of members in a A.B 1 1 0
B 0 0 0
group.
2. To have the least number of groups. Grouping A & 0 1 0 
should be a factor of 2”. B A.B
1 0 0
1 1 1 NAND Negative-OR
Tabulation method - also called the Quine-McCluskey
method of simplifying Boolean expressions especially
concerning more than 5 variables. The NOR Gate
 The NOR Gate
LOGIC CIRCUITS The AND Gate
 Application of the AND Gate
A
B (A+B)'  A
B
(A+B)'

Logic Gates 1 sec

Electronic circuits which combine digital signals A B (A+B)'
according to the Boolean algebra A 1 0 0 1
(A+B)'
B
A A 0 1 0
The Inverter
 The Inverter Enable 1 0 0
Enable 1 1 0
1 sec 
The OR Gate
NOR Negative-AND
 The OR Gate
 x'
Analysing Logic Circuit x
The XOR Gate  When a logic circuit is provided, we can x+y
 The XOR Gate analyse the circuit to obtain the logic expression.
A A B AB  Example: What is the Boolean expression of y
AB y'
B F4?
0 0 0
A' ((xx)'(yy)')' = (x'y')' idempotency
0 1 1 B' F4
A =1 = x''+y'' DeMorgan
B AB 1 0 1 C = x+y involution
1 1 0
F4 = (A'B'+C)' = (A+B).C' NOR Gate
 NOR gate is also self-sufficient.
The XNOR Gate Universal Gates: NAND and NOR  Can be used to implement AND/OR/NOT.
 The XNOR Gate  AND/OR/NOT gates are sufficient for building  Implementing an inverter using NOR gate:
A A B (A  B) ' any Boolean functions. x x'
B (A  B)'  However, other gates are also used because:
0 0 1
(i) usefulness
0 1 0 (ii) economical on transistors (x+x)' = x' (T1: idempotency)
A =1
B (A  B)' 1 0 0 (iii) self-sufficient  Implementing AND using NAND gates:
1 1 1 x
x'
NAND/NOR: economical, self-sufficient
XOR: useful (e.g. parity bit generation) x.y
NAND Gate
Drawing Logic Circuit  NAND gate is self-sufficient (can build any y
y'
 When a Boolean expression is provided, we logic circuit with it).
can easily draw the logic circuit.  Can be used to implement AND/OR/NOT. ((x+x)'+(y+y)')'=(x'+y')' idempotency
 Examples:  Implementing an inverter using NAND gate: = x''.y'' DeMorgan
(i) F1 = xyz' (note the use of a 3-input AND gate) = x.y involution
x x'
x  Implementing OR using NAND gates:
y F1
(x.x)' = x' (T1: idempotency) (x+y)'
z' x
z x+y
 Implementing AND using NAND gates: y
(ii) F2 = x + y'z (can assume that variables and (x.y)'
their complements are available) x
x.y ((x+y)'+(x+y)')' = ((x+y)')' idempotency
(iii) F3 = xy' + x'z y = (x+y) involution
x xy'
y' ((xy)'(xy)')' = ((xy)')' idempotency
= (xy) involution Implementation using NAND gates
F3
 Possible to implement any Boolean
x'  Implementing OR using NAND gates: expression using NAND gates.
z x'z Procedure:
 (i) Obtain sum-of-products Boolean expression:
e.g. F3 = xy'+x'z
(ii) Use DeMorgan theorem to obtain expression
using 2-level NAND gates
e.g. F3 = xy'+x'z
= (xy'+x'z)' ' involution
= ((xy')' . (x'z)')' DeMorgan
x (xy')'
y'
F3
x'
z (x'z)'
F3 = ((xy')'.(x'z)') ' = xy' + x'z
Implementation using NOR gates
 Possible to implement boolean expression
using NOR gates.
Procedure:
(i) Obtain product-of-sums Boolean expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain expression
using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')' DeMorgan
x (x+y')'
y'
F6
x'
z (x'+z)'
F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)
Implementation of SOP Expressions
 Sum-of-Products expressions can be
implemented using:
 2-level AND-OR logic circuits
 2-level NAND logic circuits
 AND-OR logic circuit
A  NOR-NOR circuit (by circuit transformation):
B
F = AB + CD + E a) add double bubbles
C b) changed AND-with- inverted-inputs to NOR &
F bubbles at inputs to their complements
D
A
E
B
 NAND-NAND circuit (by circuit transformation) C
a) add double bubbles G
D
b) change OR-with- inverted-inputs to NAND &
bubbles at inputs to their complements
E
A
B
A
C
F B
D
C
E G
D
E'
A
B Positive & Negative Logic
 In logic gates, usually:
C  H (high voltage, 5V) = 1
F
D  L (low voltage, 0V) = 0
 This convention – positive logic.
E'  However, the reverse convention, negative
logic possible:
Implementation of POS Expressions  H (high voltage) = 0
 Product-of-Sums expressions can be  L (low voltage) = 1
implemented using:  Depending on convention, same gate may
 2-level OR-AND logic circuits denote different Boolean function.
 2-level NOR logic circuits  A signal that is set to logic 1 is said to be
 OR-AND logic circuit asserted, or active, or true.
A  A signal that is set to logic 0 is said to be
B
G = (A+B).(C+D).E deasserted, or negated, or false.
C  Active-high signal names are usually written in
D
G uncomplemented form.
 Active-low signal names are usually written in
E complemented form.
Positive & Negative Logic  This name is come from the fact that two half adder Full-adder
Positive logic: can implement a full adder. A B Carry-in SUM Carry-out
0 0 0 0 0
 Using SOP method, we get
Active High: 0 1 0 1 0
0: Disabled  SUM S = A’B + AB’ 0
Enable 1 0 1 0
1: Enabled  CARRY C = AB 1 1 0 0 1
 We can use Ex-OR gate to implement the circuit for 0 0 1 1 0
Negative logic: SUM, or using a combination of AND, OR and NOT 0 1 1 0 1
1 0 1 0 1
Active Low: gates, or using NAND gates only, or using NOR 1 1 1 1 1
0: Enabled gates only
Enable
1: Disabled Half-Subtractor
Half -adder
A B SUM CARRY
Combinational Logic Circuit 0 0 0 0
 Consists of several logic gates interconnected and 0 1 1 0
the output depends on the combination of logic 1 0 1 0
levels present at the inputs. 1 1 0 1
 Only the current inputs will affect the output logic
state.
 There is no feedback path in the circuit. A
B S The circuit has two outputs labeled DIFF and
A logic circuit design procedure may be carried out in BORROW. A truth table for the circuit looks like:
a step-by-step approach as follows: C
1) Obtain a verbal description of a problem with   A     B     DIFF     BORROW  
clearly defined logic definitions.
Full-adder 0 0 0 0
2) Prepare a logic truth table (or Boolean equation in
some cases) from verbal descriptions.  Similar to half-adder, but the addition involves three
variables A, B and a ‘Carry-In’ 1 0 1 0
3) Map from truth table (or Boolean equation) onto K-
Map.  If Augend and Addend are both 1 digit long, a half
0 1 1 1
4) Obtain simplified logic expression from the map. adder can complete the addition process.
5) Manipulate to desired logic form if necessary (as  However, if they are TWO or more digits long, full- 1 1 0 0
for NAND or NOR gates implementation) adder is needed.
6) Draw a logic circuit diagram.  So, half-adder can only be used for the addition of
7) Construct the circuit and make improvement or the LSB. Full-Subtractor
modification if necessary. Ci

Half-adder A S
 A combinational circuit that perform the addition of B
C
two Boolean variables.
 Generate the results ‘SUM’ and ‘CARRY’ according o

to the truth table shown.

The final truth table for a full subtractor looks like:  It steers one of 2n inputs to a single output line,  Pulse-triggered
using n selection lines. Also known as a data  latches
selector.  ON = 1, OFF = 0
  A     B     BORIN     D     BOROUT    Edge-triggered
 flip-flops
0 0 0 0 0 Demultiplexer  positive edge-triggered (ON = from 0 to 1;
 Given an input line and a set of selection lines, OFF = other time)
0 0 1 1 1 the demultiplexer will direct data from input to a  negative edge-triggered (ON = from 1 to 0;
selected output line. OFF = other time)
0 1 0 1 0
Sequential Logic Circuit LATCHES
0 1 1 0 0
 Usually consists of Combinational logic circuit and 1. S-R Latch
storage devices.  Complementary outputs: Q and Q'.
1 0 0 1 1
 The output is a function of both current and pass  When Q is HIGH, the latch is in SET state.
logic levels of the inputs.  When Q is LOW, the latch is in RESET state.
1 0 1 0 1
 The inputs can be from external or internal  For active-HIGH input S-R latch (also known as
feedback. NOR gate latch),
1 1 0 0 0
R=HIGH (and S=LOW)  RESET state
1 1 1 1 1 There are two types of sequential circuits: S=HIGH (and R=LOW)  SET state
 synchronous: outputs change only at specific time both inputs LOW  no change
 asynchronous: outputs change at any time both inputs HIGH  Q and Q' both LOW
Decoders (invalid)!
 Convert binary information from n input lines Multivibrator: a class of sequential circuits. They can  Drawback of S-R latch: invalid condition exists and
to (max. of) 2n output lines. be: must be avoided.
 Known as n-to-m-line decoder, or simply n:m  bistable (2 stable states) S R Q Q'
or nm decoder (m  2n).  monostable or one-shot (1 stable state)
No change. Latch
 astable (no stable state) 0 0 NC NC
Encoder remained in present state.
 Encoding is the converse of decoding. Bistable logic devices: latches and flip-flops. 1 0 1 0 Latch SET.
 Given a set of input lines, where one has been Latches and flip-flops differ in the method used for 0 1 0 1 Latch RESET.
selected, provide a code corresponding to that line. changing their state.
 Contains 2n (or fewer) input lines and n output 1 1 0 0 Invalid condition.
lines. Memory Elements
 Implemented with OR gates.  Memory element: a device which can
remember value indefinitely, or change value on 2. Gated D Latch
Multiplexer command from its inputs.  Make R input equal to S'  gated D latch.
 A multiplexer is a device which has  Flip-flops are memory elements that change  D latch eliminates the undesirable condition of
(i) a number of input lines state on clock signals. invalid state in the S-R latch.
(ii) a number of selection lines  Clock is usually a square wave.
(iii) one output line
 When EN is HIGH,
 Two types of triggering/activation:
 D=HIGH  latch is SET
 pulse-triggered
 D=LOW  latch is RESET
 edge-triggered
 Characteristic table:  T flip-flop: single-input version of the J-K flip  Fan-out: Fan-out of a gate is the maximum
EN D Q(t+1) flop, formed by tying both inputs together. number of inputs that the gate can drive.
 Speed-power product (SPP): product of
1 0 0 Reset the propagation delay time and the power
Characteristic table.
1 1 1 Set T CLK Q(t+1) Comments dissipation.
0 X Q(t) No change
0  Q(t) No change
When EN=1, Q(t+1) = D 1  Q(t)' Toggle

Latch circuits are not suitable in synchronous logic

circuits. Integrated Circuit Logic Families
 Some digital integrated circuit families: TTL, DOS (Disk Operating System)
CMOS, ECL.  Serves as an interface between the user and
FLIP-FLOPS
 TTL: Transistor-Transistor Logic. the hardware and another software.
 Flip-flops: synchronous bistable devices
 Output changes state at a specified point on a  Uses bipolar junction transistors
 Consists of a series of logic circuits:
Terms:
triggering input called the clock.
standard TTL, low-power TTL, Schottky 1. Booting – starting-up the computer
 Change state either at the positive edge (rising
TTL, low-power Schottky TTL, advanced 2. File – named collection of data or program
edge) or at the negative edge (falling edge) of the
Schottky TTL, etc. 3. Filename – alphanumeric character that are
clock signal.
used to identify a file.
 S-R, D and J-K edge-triggered flip-flops. Note the
4. Home – first row and fist column of the screen.
“>” symbol at the clock input. TTL Series Prefix Example of
5. Syntax – format/rule for typing a command
Designation Device
6. Cursor – blinking light in the screen.
J-K Flip-flop Standard TTL 54 or 74 7400 (quad
 J-K flip-flop: Q and Q' are fed back to the NAND gates)
Multimedia
pulse-steering NAND gates. Low-power 54L or 74L 74L00 (quad
 Refers to the technology that presents
TTL NAND gates)
 No invalid state. information in more than one medium,
Schottky TTL 54S or 74S 74S00 (quad
 Include a toggle state. NAND gates)
including text, graphics, animation, video,
 J=HIGH (and K=LOW)  SET state music and voice.
Low-power 54LS or 74LS 74LS00 (quad
 K=HIGH (and J=LOW)  RESET state Schottky TTL NAND gates)
 both inputs LOW  no change Multimedia Computer
 both inputs HIGH  toggle (change state)  Powerful microcomputers that include sound
 CMOS: Complementary Metal-Oxide capability, run CD-ROM disks and allow the
Semiconductor. user to play games or perform interactive
Characteristic table:  Uses field-effect transistors
J K CLK Q(t+1) Comments tasks.
 ECL: Emitter Coupled Logic.
0 0  Q(t) No change  Uses bipolar circuit technology. Internet
0 1  0 Reset  Has fastest switching speed but high
1 0  1 Set  simply called "the Net"
power consumption.
1 1  Q(t)' Toggle  Access is not restricted to anyone
 Performance characteristics
 Propagation delay time.  A public and global communication network
T Flip-flop  Power dissipation. that provides direct connectivity to anyone via
a Local Area Network (LAN) and an Internet
Service provider (ISP)
  A network of networks in which users at any  Hypertext Transfer Protocol  It is totally self-governing
one computer can get information from any  the set of rules for exchanging files (text,
other computer (and sometimes talk directly to graphic images, sound, video, and other Services offered in the Internet
users at other computers) multimedia files) on the World Wide Web  Send/receive messages – email, SMS, MMS
 Exchange ideas with other people – Usenet
Intranet TCP/IP  Copy files – File Transfer Protocol (FTP)
 a corporate LAN and/or Wide Area Network  Transmission Control Protocol/Internet
(WAN) that is secured behind company’s
 Run a remote computer – Telnet
Protocol
firewalls and it uses Internet technologies  Dig directories – Gopher
 basic communication language or protocol of
 intranet uses TCP/IP, HTTP, and other  Search/browse documents, virtually visit
the Internet
Internet protocols and in general looks like a libraries – world wide web
private version of the Internet E-mail
Common search engines:
 electronic mail 1. Yahoo
Extranet
 the exchange of computer-stored messages 2. Google
 refers to an intranet that is partially accessible by telecommunication
to authorized outsiders 3. Yehey
 format: username@subdomains.domains 4. Alta Vista, etc.
World Wide Web (www)  the internet uses a method known as Domain
Names System (DNS) Download – file is transferred from a remote computer
 all the resources and users on the Internet that to your computer.
are using the Hypertext Transfer Protocol  the name consists of 3 elements:
1. user name Upload - file is transferred from a remote computer to
(HTTP) your computer.
 "The World Wide Web is the universe of 2. sub domain
network-accessible information, an 3. domain
embodiment of human knowledge."
A domain represents/identifies a type of organization.
URL (Uniform Resource Locator) A sub domain further narrow down the address to
 is the address of a file (resource) accessible division, departments or offices.
on the Internet
 the resource can be an HTML page, an image Possible domains:
file, a program such as a common gateway Code Organization Type
interface application or Java applet, or any edu Educational or research institution
other file supported by HTTP gov Government or nonmilitary
mil Military
 contains:
com Commercial entity
o the name of the protocol required to
net Network access provider
access the resource org Other organizations
o domain name that identifies a specific
computer on the Internet Who Governs the Internet?
o hierarchical description of a file location
 No governmental body, either local, national or
on the computer international governs or rules the content of
the Internet.
HTTP