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EE537- Spring 2020

Digital Integrated Circuit Design


Instructor: Engr. Dr. Nasir Mohyuddin
Homework # 3, Due on 20th April 2020, Online Submission by 10:00pm PST

Problem # 1
Does the following design implement a 4-input AND (with inputs a, b, c, and d, and output O/P? If
not, explain the reason using an example combination of input values and detailed waveforms.

Problem # 2
Using DOMINO logic, design the following logic circuits:
a) Y = A + BCD + E
b) Y = AB  CD

Problem # 3
In the circuit below, if the inverter's threshold is 3.1 volts, and Vdd = 5 volts, how large can C1 be
without creating problems due to charge-sharing?

1
Problem # 4
In the following FFs, identify the transistors which have impact on the setup and hold times, and clock-
to-Q delay. Which FF can get negative hold time?

ckbar VDD VDD ckbar VDD VDD


stage 1 stage 2 stage 3 stage 4
M5 M7
D Q
VDD VDD VDD VDD
M6 M8
M4 M9
M1 ck M7 M10
1 2 ck ck
D Q ck ck
ck M2 M5 ck M8
M11
ck
M3 M6 M9
ckbar ckbar

(a) Positive edge-triggered flip-flop in TSPC (b) Negative-edge triggered master-slave flip-flop

Problem # 5
Consider the following figure where S1 and S2 are two PMOS switches used to connect capacitor C
to one of the two power supplies. The power supplies are ideal and as shown in the figure their output
voltages are Vf and Vi. Initially both switches are OFF.

a) Calculate the amount of energy that is dissipated when charging C that is initially charged to a
level of Vi to Vf by closing switch S1. Next, we open S1 and close S2 to discharge this capacitor
back to Vi level. Calculate the energy that is dissipated during this ‘falling’ transition. (Hint:
energy is only consumed in the two transistor switches; this energy dissipation may be
calculated by integrating the product of current thru the switch and voltage across the switch
during the transition time.)
b) Calculate the energy which is extracted from power source Vf as C is charged from Vi to Vf.
Next calculate the energy which is dumped into power source Vi as C is discharged from Vf to
Vi.
c) Calculate the change in stored energy of the capacitor during each of these two transitions. Is
the law of conservation of energy met for each half of the switching cycle i.e., is the energy
that is extracted from Vf equal to the sum of energies dissipated in the first switch plus change
in the stored energy of the capacitor during a rising output transition AND is the change in the
stored energy of the capacitor during a falling output transition equal to energy dissipated in
the second switch plus the energy that is returned to the power source Vi?