SUMMARY OF LECTURE 1 (WEEK

3)
Create a switch model for nFET with characteristics given below:

L*=0.5um, Lo=0.05um, Vth=0.6, Kx*=150u A/V2, Cox=2.7fF/um2, Cj=0.86fF/um2, Cjsw=0.24fF/um2

Solution:

Step 1: L= L*-2Lo

So, L = 0.5 – 2*(0.05)

L = 0.4um

Step 2: Linear Resistance

Rn=1/(Bn*(VGSN – VTH)

By putting Bn = Kr* *(W/L) we can find Rn

So,

Rn = 1/[(5/0.4)*(150 x 10-6 )*(3.3-0.60]

Rn = 197.5 Ohms

Step 3: Gate capacitance

CG= Cox * AG

Whereas AG=W*L*

So, CG= 0.5*2.7*5

CG=6.75fF

If gate capacitance is known then we can find out C GD and CGS which is ½ of CG

Hence, CGD and CGS = 3.375fF

Step 4: Junction capacitance

Cn= (Cj * Abot) + (Cjsw* Psw)

By putting formulas of Psw /Abot and by putting their values we get:

Cn=16.98fF

Step 5: FINAL DRAIN CAPACITANCE

Cs = CGS + CSB

CD = CDG + CDB
CD = Cs =20.36fF

If we want to see the geometry of Pmos we can say that it’s kind of similar with Nmos but
complimentary while the gate capacitance is similar to Nmos hence we can say the length/
width and side capacitances are same for nmos and pmos. For electrical properties, we change
all voltage terminals as well as current directions for Pmos. V SGp and VSDp instead of VSGn and VSDn
while VTp is negative and VTn is positive. Hole charge carrier or charges Qh forms a channel which
create a current flow from source to drain. When V SGp <= |VTp| then there will be no channel
hence the device will be in the cut off region while when V SGp > |VTp| and VSDn > 0 then a channel
is formed which will result in the flow of current from source to drain, that channel vanishes
when VSDp = Vsat.

For current in saturation region:

IDp= (Bp/2) *(VSGp - |VTp|2)

BP = Kp* *(W/L)
Kp*=upCox

The saturation point:

Vsat= VSGp - |VTp|

The sizing of Pmos is a bit same while since the motilities differ hence their ratio will be to 2 to 3 so
widths are needed to adjusted to get results as desired.

If we have to reduce the size of Mosfets we do scaling which is a process of reducing the width and
length by factor S. While the aspect ratio will remain same but the gate area A G will reduce by S2.. The
thickness of oxide (Tox) is reduced by S then following thing happens:

1. Oxide capacitance Cox is increased by S.

2. The gate capacitance CG is reduced by S.

3. K will increases by S while trans-conductance B will also increases.

4. Drain and source resistance will decrease by S.

By decreasing voltage with S resistance will not change while drain current ID will reduce by S and power
P will also reduce by S2 which can be called as motivating factor for voltage reduction for small Mosfets.