ASSIGNMENT # 4

Q. No. 1: Consider an inverter circuit that has FET Aspect Ratios of (𝑊𝐿)=6 and (𝑊𝐿)𝑝=8 in a process
where 𝑘𝑛′=150 𝜇𝐴/𝑉2, 𝑘𝑝′=62 𝜇𝐴/𝑉2, 𝑉𝑇𝑛=0.7𝑉 and 𝑉𝑇𝑛=−0.85𝑉, 𝑉𝐷𝐷=3.3𝑉 and total output
capacitance to be 𝐶𝑜𝑢𝑡=150𝑓𝐹.

a. Compute Rise Time, Fall Time and maximum operating frequency.

b. What happens to maximum frequency when the aspect ratios are reduced to half i.e. 𝑊2 and 𝐿2

SOLUTION:

GIVEN:

𝑘𝑛*=150 𝜇𝐴/𝑉2

𝑘𝑝*=62 𝜇𝐴/𝑉2

𝑉𝑇𝑛=0.7𝑉

𝑉𝑇𝑛=−0.85𝑉

𝑉𝐷𝐷=3.3𝑉

𝐶𝑜𝑢𝑡=150𝑓𝐹.

Part a:

For the Rise Time,

Consider PFET resistance:

Rp=1/[Bn*(VDD – |VTp|)]

Rp=1/[(62*10-6)*(8)*(3.3-0.85)]

Rp= 822.9 ohms

So,
Tp = Rp * Cout

Tp = 822.9 * 150 * 10-15

Tp = 123.43 ps

tr = 2.2 Tp

tr = 2.2 * 123.43

tr = 271.55 ps
For the Fall Time,

Consider NFET resistance

Rn=1/[Bn*(VDD – VTn )]

Rn=1/[(150*10-6)*(6)*(3.3-0.70)]

Rn=427.35 ohms

So, discharge time constant will be

Tn = Rn * Cout

Tn = (150*10-6) * 427.35 ohms

Tn = 64.1 ps

tf = 2.2 Tn

tf = 2.2 * 64.1 ps

tf = 141 ps

For Maximum Frequency:

Fmax = 1/ (tf + tr)

Fmax = 1/ (141 ps + 271.55 ps)

Fmax = 2.42 GHz

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Q. No. 2: In our CMOS Circuits, at no load capacitance, prove why we have 𝑡𝑟0> 𝑡𝑓0. Support
your answer with proper derivations.

SOLUTION:

As total output capacitance is:

Cout = CFET + CL

We know that “CFET” represents the parasitic capacitances of the transistors while C L is the capacitance
with external load.

So,

Rise and fall equation are

tr = 2.2 * Rp * Cout

tf = 2.2 * Rn * Cout

Hence under no load condition i.e. CL is equal to zero the inverter drives its capacitances such that
Cout = CFET

So,

tr0 = 2.2 * Rp * Cout

tf0 = 2.2 * Rn * Cout

As we know that
*
Kn = un (eox/tox)

Kp*= up (eox/tox)

But we also know that

un > u p

So,
*
Kn > Kp*
Hence,

Bn > B p
* *
Because Bn = Kn *(W/L) while Bp = Kp *(W/L)

So,

Rn=1/[Bn*(VDD – VTn )]and Rp=1/[Bn*(VDD – |VTp|)] hence by the above conditions Bn > Bp so we can say that
Rp > R n .

Recalling the rise and fall time equations, which are as follows:

tr0 = 2.2 * Rp * Cout

tf0 = 2.2 * Rn * Cout

We can say that by above conditions seen through derivations that is Rp > Rn , hence tr0 > tf0 .

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Q. No. 3: Consider a function given by

_________

𝑓= 𝑥∙(𝑦+𝑧)

Design its CMOS circuit highlighting all capacitances. Find “Worst Case” rise and fall times of the
function.
Solution:

From De Morgan’s law we can say that

_____

f = x+(y.z)

The aspect ratios are critical parameters that effect

the rise and fall time, which is generated by PFET
and NFET respectively. Assuming that all have same
width and length, i.e. all are of same size. Hence the
worst case will lie in when x = 1 but only if one of the
other inputs is also one resulting in 2 FET series pair
that will handle discharge of the capacitor.

Cout = CFET + CL Hence,

Tn = Rn * Cn + 2 Rn * Cout

Hence fall time will be,

tr = tro + αo CL

where αo is the slope.

The rise time is given by the PFET if aspect ratio are

i.e. that they are all of same size. So series chain
gives a time constant

Tp = Rp*Cp +2RpCout

The worst case rise time is

tr = to + ao * CL

where ao is the slope.

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Q. No. 4: Design clocked CMOS logic for NAND and NOR gates. Also design layout of the C2MOS
designs.

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Q. No. 5:Revise lecture of inverter switching characteristic, and find the output capacitance (𝐶𝑜𝑢𝑡) of
first inverter, which is driving an inverter with 𝐶𝑖𝑛=32.4 𝑓𝐹, with 𝐶𝑀𝑂𝑆=52.34 𝑓𝐹.

Given:

𝐶𝑖𝑛=32.4 𝑓𝐹

𝐶𝑀𝑂𝑆=52.34 𝑓𝐹.

To Find:

Cout

Solution:

As the output capacitance is

Cout = 𝐶𝑖𝑛 + 𝐶𝑀𝑂𝑆

Cout = 32.4 + 52.34

Cout = 84.7 x 10 -15 F