Datapath Design
Fixed-point arithmetic
Basic adders
 Half-adder
 Full-adder – also called 1-bit
adder
 Serial Adder – the least
expensive circuit in terms of
hardware cost for adding two n-
bit binary numbers
- Slow but circuit
size is very small
High level view of a serial adder
that has D F/F as the carry store. One sum bit
and carry is generated per clock cycle.
 Parallel Adders - in one clock
cycle add all bits of two n-bit
numbers as well as an external
carry-in signal.
Ripple-carry adder –
type of parallel adder.
connecting full adders one full
adders to generate 1 on its
carry signal.
Subtracters
-implemented using two’s
complementation.
Overflow
-Arithmetic operation exceeds the
standard word size n
Carry-lookahead adders
-a high-speed adder
-compute the input carry needed by
stage directly from carry like signals.
2 auxiliary signals for carry-lookahead adder
1.) generate
2.) propagate
Methods of handling carry signals in the two
main combinational adder designs
1. Ripple Carry propagation
i. Lowest cost adders
and can easily
provide access to
the internal signal
needed by the
flags.
2. Carry-lookahead
i. Fast, expensive and
impractical because
of complexity of its
carry-generation
logic.
Multiplication – usually implemented by some
form of addition.
Two multiplication algorithms for twos-
complement numbers
 Robertson’s Algorithm – will
perform multiplication
depending on the case occur.
 Booth’s Algorithm - treats
positive and negative operands
uniformly, no special actions
are required for negative
numbers.
Combinational array multiplier – can multiply
large scale of numbers
Several division difficulties
 Quotient overflow – two large to be
placed for the answer
 Divided by zero error – when a number
is divided to zero
Division by repeated multiplication- division
is performed efficiently and low cost.
Floating-point Arithmetic

Basic Operations
Difficulties On implementing floating point
arithmetic
1. Exponent biasing
If biased exponents are added
or subtracted using fixed-point arithmetic in the
course of a floating-point calculation, the
resulting exponent is doubly biased and must
be corrected by subtracting the bias.
3. Overflow and Underflow
A floating point operation
causes overflow if the result is too large or too
small to be represented. However, the
exponent overflows or underflows, an error
signal indicating floating-point overflow or
underflow is generated.
4. Guard Bits
To preserve accuracy during floating-
point calculations, one or more extra bits called
guard bits are temporarily attached to the right
end of the mantissa.
Pipeline Processing
Pipeline processing
- A general technique for increasing processor
throughput without requiring large amount of
extra hardware.
- Applied to design of complex datapath units
such as multipliers and floating-point adders.
- Also used to improve the overall throughput of
an instruction set processor.
Introduction
Stages or segments – a pipeline processor consist of
a sequence of m data-processing circuits, which
collectively perform a single operation on a stream of
data operands passing through them.
Structure of Pipeline Processor:
 Si contains multiword input register or latch Ri
and a datapath circuit Ci that is usually
combinational.
 Ri holds partially processed results as they move
through the pipeline and they also serve as
buffers that prevent neighboring stages from
interfering w/ 1 another.
 A common clock causes Ri to change state
synchronously.
 Each Ri receives a new set of input data D(i-1)
from the preceding stage S(i-1) except for Ri
whose data is supplied from an external source.
 D(i-1) represent the results computed by C(i-1)
during the preceding clock period.
 Once D(i-1) has been loaded into Ri, Ci
proceeds to use D(i-1) to compute the new data
set Di.
 Thus in clock period, every stage transfers it
previous results to the next stages and
computes a new set of results.
Advantage: A m-stage pipeline can simultaneously
process up to m independent set of data operands.
T – pipeline’s clock period
mT – Delay or latency of the pipeline
1/T – Pipeline’s throughput
CPI = 1
Latency
• For a non-pipelined processor:
NmT
• For a pipelined processor:
[m+(N-1)]T
Where: N = number of Tasks
m = number of stages
T = pipeline’s clock period
Addition of two normalized floating-point numbers x
and y can be implemented using: Four-step sequence
Four-step sequence:
1) compare the exponents
2) align the mantissas
3) add the mantissas
4) normalize the result
Normalization is done by counting the number k of
leading zero digits of the mantissa (or leading ones in
the negative case), shifting the mantissa k digit
position to normalize it and making a corresponding
adjustment in the exponent.
Four-stage floating-point adder pipeline:
 Suppose that x has a normalized floating
point representation (Xm, Xe) where Xm is
mantissa and Xe is exponent w/ respect to
some base B=2K
 In the first step of adding x=(Xm, Xe) to
y=(Ym, Ye) which is executed by S1 of the
pipeline, Xe and Ye are compared by
subtracting the exponents, which requires a
fixed point adder.
 S1 identifies the smaller of the exponents
say Xe whose mantissa Xm can then be
modified by shifting in the second stage S2
of the pipeline to form a new mantissa x’m
that makes (x’m, xe) = (xm, xe)
 In the third stage, the mantissa X’m and Ym
are added. This can produce an
unnormalized result.
 Hence, the result is normalized.
Operation of the four-stage floating-point adder
pipeline:
 Illustrates the behavior of the adder pipeline
when performing a sequence of N floating-
point additions of the form xi+yi for the case
N=6
 At any time, any the four stages can contain
a pair of partially processed scalar operands
(xi, yi).
 The buffering of the stages ensures that Si
receives as input the results computed by
stage S(i-1) during the preceding clock
period only.
 If T is the pipeline’s clock period, then it
takes 4T to compute the single sum xi+yi or
in other words, pipeline’s delay is 4T
 4T is the time required to do one floating-
point addition using a nonpipelined
processor plus the delay due to the buffer
registers.
 Once all four stages of the pipeline have
been filled w/ data, a new sum emerges from
the last stage of the pipeline S4 every T
seconds.
 Consequently, N consecutive additions can
be done in time (N+3)T, implying that the
four-stage pipeline’s speedup is
_<Pipeline Design:
 Find a suitable multistage sequential
algorithm to compute the given function.
 This algorithm’s steps which are
implemented by the pipeline stages should
be balanced that they should have roughly
the same execution time.
Fast buffer registers
- placed between the stages to allow all necessary
data-items (partial or complete results) to be
 transferred from stage to stage without
interfering w/ 1 another
- buffers are designed to be clocked at the
maximum rate that allows data to be transferred
reliably between stages.

Pipelined version of the floating-point adder:

 Shows a register level design of a floating-

point adder pipeline based on the
nonpipelined design and employing a four
stage organization
 The main change is the inclusion of the
buffer registers to define and isolate the four
stages.
 Thus the circuit is an example of
multifunction pipeline that can be configured
as either a floating-point adder or as one-
stage fixed point adder

Tc = max{Ti} + TR
For i = 1,2,…m

Where: Tc = minimum clock period

max{Ti} = delay between the
emergence of the
results
from the Pipeline
Throughput:
• Pipelined Processor:

• Non-pipelined Processor:

Feedback:
- The usefulness of a pipeline processor can
sometimes be enhanced by including feedback
paths from a stage output to the primary inputs
of the pipeline.
- It enables the result computed by certain stages
to be used in a subsequent calculations by the
pipeline