CHAPTER 5
Control Design
5.1 Basic Concepts
5.1.1 Introduction
Parts of digital system:
(1) datapath – is a network of
functional and storage units
capable of performing certain
(micro) operations on data
words
(2) control unit – selects the
functions to be performed at
specific times and route the
data through appropriate parts
of the datapath unit
Register File for temporary storage of
operands, two functional units F1 and F2
responsible for data processing and mux to
allow data to be steered through DP. Typical
functional units are ALU, a shifter or a
multiplier. Control unit receives external
instructions or commands which is converted
to control signals.
Multicycle operations
Single-cycle execution is a central goal of
RISC design.
Single precision floating point = 4 bytes
Double-precision floating point = 8 bytes
microprogram – an associated set of
microinstructions in digital computers
microinstructions – control the CPU at
a very fundamental level of hardware
circuitry
Implementation Method
(1) Hardwired – views the
controller as a sequential logic
circuit or fsm that generates
specific sequences of control
signals in response to externally
supplied instructions.
– designed with the usual
goals of minimizing the number
of components used and
maximizing the speed of
operation
(2) Microprogrammed control unit
– built around a storage unit
called control memory, where
all the control signals are stored
in a programlike format
resembling
Control Memory – stores set of
microprograms designed to implement or
emulate the behavior of the given instruction
set.
Microprogramming makes control unit design
more systematic by organizing signals into
formatted words (microinstructions).
On the negative side, microprogrammed
control unit is more costly to manufacture
than hardwired due to the presence of
control memory and its access circuitry.
Microprogrammed also tend to be slower
because of the extra time required to fetch
microinstructions from control memory.
Hardwired control units use RISC, the reason
it has fast instruction set.
Pipelining is a relatively low-cost way of
increasing a processor’s throughput by
decomposing its operation into a sequence of
relatively independent steps.
5.1.2 Hardwired Control
Design Methods
Method 1: Classical Method – attempts to
minimize the amount of hardware by using
only flip-flops to realize a P-state
circuit
Method 2: One-hot Method – simplifies CU
design and debugging
State Tables
Moore machine – output signal values
depend on the current state and independent
of the input
Mealy machine – contrast with Moore
Example: GCD processor
GCD is performed by continuous subtraction
of the smallest value until reached the last
number that can be the difference and that
would be the greatest common denominator.
GCD procedure suggests datapath unit DP
that contains pair of register XR and YR to
store corresponding variables, we don’t need
a register TEMPR since we can r/w with the
same clock cycle. Load XR and Load YR to
load each register independently. We have
swap to route the outputs of XR and YR and
final signal subtract to assume control in
subtraction XR:=XR-YR. Input signals are
asynchronous to reset signal.
Classical Method
1 Construct a P-Row state table that defines
the desired input-output behavior
2 Select the minimum number p of D-type
flip-flop and assign a p-bit binary code to
each state
3 Design a combinational circuit C that
generates the primary output signals {zi}
and secondary outputs {Di} that must be
applied to the flip-flops
Defined states:
S0 = 0 0 – Begin
S1 = 0 1 – Swap
S2 = 1 0 – Sub
S3 = 1 1 – End
One-hot method
Binary state assignment always contains a
single 1 – the “hot” bit – while all the
remaining bits are 0.
1 Construct a P-row state table that defines
the desired input-output behavior
2 Associate a separate D-type flip-flop Di
with each state Si and assign the P-bit one-
hot binary code to each state
3 Design a combinational circuit that
generates the primary and secondary output
signals {Di} and {zk} respectively. Di+ is
defined by the logic equation
 Defined states:
S0 = 0 0 0 1 – Begin
S1 = 0 0 1 0 – Swap
Microassembler is necessary to
translate microprograms into executable
programs that can be stored in the control
memory.

S2 = 0 1 0 0 – Sub
Control unit organization
S3 = 1 0 0 0 – End
Microinstruction’s two parts:

1 Control fields that specify the control

5.1.3 Design Examples
CPU Control Unit
DPU – datapath unit designed to
execute the set of 10 basic single-address
signals to be activated
2 Address fields that contains the address in
the CM of the next microinstruction to be
executed

PCU – program control unit is CMAR – control memory address register

responsible for managing the control signals
linking PCU to the DPU, as well as the control
signals between the CPU and external
memory M.

RISC processors are usually designed so that

all instruction execution times are equalized
to one CPU clock period Tc in length, making
the cycles associated with the register-
transfer operations into subcycles of Tc.

5.2 Microprogrammed Control

5.2.1 Basic concepts

Microprogramming is a method of
control-unit design in which the control
signal selection and sequencing information
is stored in a ROM or RAM called control
memory, CM. Microinstruction length is determined by
three factors:
Microinstructions activates the control
signals at any time which is fetched from CM 1 The maximum number of simultaneous
in much the same way an instruction is microoperations that must be specified, that
fetched from main memory. is, the degree of parallelism required at the
microoperation level
Microprogram is a set of related
microinstructions. 2 The way in which the control information is
represented or encoded
Emulator is the set of microprograms
that interpret a particular instruction set or 3 The way in which the next microinstruction
machine language. address is specified
Control memories are usually ROMs, so their Horizontal microinstructions (fig5.28):
contents cannot be altered on-line. But CM
can be a r/w memory or RAM. WCM or 1 long formats
writable control memory would have a
2 ability to express a high degree of
number of “fascinating possibilities” but
parallelism
doubted that its cost could be justified. WCM
allows us to change a processor’s instruction 3 little encoding of the control
set by changing the microprograms that information
interpret the instruction set.
Allows no encoding of control information

Specifies many microoperation

Dynamically microprogrammable if the
control memory contents can be altered
under program control, e.g. WCM
Vertical microinstructions (fig5.27):

1 short formats
Parallelism in microinstructions
2 limited ability to express parallel
Microinstruction formats take microoperations
advantage of the fact that, at the
microprogramming level, many operations 3 considerable encoding of the control
can be performed in parallel. information

Allows encoding of control information

Specify only one microoperation (no

parallelism)

Microinstruction addressing

µPC, microprogram counter is the primary

source of microinstruction address and can
also be used as CMAR

Horizontal vs. Vertical

Microoperation timing Control-field encoding

A single clock signal synchronizes the control We can state optimization problem that aims
signals, and its period can be the same as to minimize the total size of control fields
the microinstruction cycle period; this mode needed to implement a particular set of
of control has been termed monophase. microinstructions:

Control unit organization

Design of a typical microprogrammed control

unit using the microinstruction format:
5.2.3 CPU Control Unit
1 a condition-select field specifies the
external condition to be tested in the case of Basic Emulator
conditional branch microinstructions
Extensions
2 an address field contains the next-address
field to be used when a branch condition is Microprogram sequencers
satisfied. A microprogram counter µPC
provides the next microinstruction address Nanoprogramming
when no branching is needed.

3 the rest of the microinstruction specifies in

5.3 Pipeline Control

5.3.1 Instruction Pipelines

Instruction Pipeline is a multifunction,

reconfigurable pipeline designed to speed up
a computer’s performance by efficiently
overlapping the processing of instructions.

Pipeline structure
encoded or unencoded format the control Simplest instruction pipeline:
signals that are activated to perform the
desired microoperations Fetch Stage S1:

µPC – microprogram counter, source of

microinstructions; buffer register
5.2.2 Multiplier Control Unit
CM – control memory, stores
Microprogram structure microinstructions

Execute Stage S2:

µIR – microinstruction register, buffer

register

decoders – extract control signals from

the microinstructions

logic – choosing for branch addresses

Multistage pipelines
Four-stage pipeline:
1 IF: instruction fetching and decoding
using the I-cache
2 OL: operand loading from the D-cache to
RF
3 EX: data processing using the ALU and
RF
4 OS: operand storing to the D-cache from
RF
5.3.2 Pipeline Performance
Performance measures
A pipeline’s performance can be measured
by its throughput in terms of millions of
instructions executed per second or MIPS.
Space-time diagram is an illustration that
shows the utilization of each pipeline stage
as a function of time. In general, a space-
time diagram for an m-stage pipeline has the
form of mxn grid, where n is the number of
clock cycles to complete the processing of
some sequence of N instructions of interest.
The ratio of the unshaded area to the total
area of a space-time diagram for an m-stage
pipeline is defined as the efficiency or
utilization E(m) of the pipeline.
Optimizing m
An easy way to improve a pipeline’s
performance is to increase the number of
stages m.
Pipeline’s performance/cost ratio PCR
5.3.3 Superscalar Processing
Microprocessors reach performance levels
greater than one instruction per cycle by
fetching, decoding and executing several
instructions concurrently; which is called
superscalar.
The PCU of a superscalar computer machine
is responsible for determining where each
instruction can be executed and for providing
it with access the resources it needs. The
factors that need to be taken into account
for the said part of the machine to do its
task are:
1 Instruction type. For example, a
floating-point add instruction has to be
issued to a floating-point E-unit and not to
an integer E-unit
 2 E-unit availability. An instruction can
be issued to a pipelined E-unit only if no
collisions will result, as determined by the
pipeline’s reservation table

3 Data dependencies. To avoid

conflicting use of registers, data-dependency
constraints among the operands of the active
instructions must be satisfied

4 Control dependencies. To maintain

high performance levels, techniques are
needed to be reduce the impact of branch
instructions on pipeline efficiency

5 Program order. Instructions must

eventually produce results in the order
specified by the program being executed.
The results may be computed out-of-order
internally to improve the CPU’s performance