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EE2361 Spring 2002 - Extension

Midterm Exam 1
Problem 1: (Short answers)
a) What's the difference between the operand `à,x'' and the operand
``[a,x]''
The operand `à,x'' is an indexed operand with effective address
given by the sum of accumulator and index register
while ``[a,x]'' is an indirect operand whose address is contained at
memory locations given by adding to .
c) How many bus cycles does the instruction ``dex'' require to fetch
and execute?
Answer: the reference manual says 1.
c) How many bus cycles does the instruction ``des'' require to fetch
and execute?
Answer: the reference manual says 2.
For the rest of this problem, you are given the following facts:
Memory location $820 contains the bit pattern %10101100.

Memory location $821 contains the bit pattern %00101110.
Accumulator contains the bit pattern %01010110.
Accumulator contains the bit pattern %11101010.
d) If represents a signed number, what number (in decimal,

sign-magnitude notation) does it represent?
Answer: convert to hex: $56 and then to decimal: 86.
(Since the MSB is , it's a positive number.
e) Suppose the instruction `àdda $820'' is executed.
What will the contents of and the CCR be after the instruction?
Answer: = 2 and N = 0, Z = 0, V = 0, C = 1.
f) Suppose now that ``subb $821'' is executed. What will
be the contents of and the CCR after the instruction?

Answer: = $BC N = 1, Z = 0, V = 0, C = 0.
g) What unsigned number does the register represent after
both instructions have executed?
= $2BC represents 512+176+12 = 700.
Problem 2: Processor registers are as shown:
A B D X Y SP PC CCR
$AA $BB $AABB $CCDD $EEFF $5678 $1234 --0000
Describe what memory locations or processor registers are affected and how they are affected when the
instruction ``staa 1,x-'' is executed. Answer: The effective address is $CCDD, which will contain $AA after the
instruction. The register will be decremented by one after it is used in computing the effective address, so it
will be $CCDC. The CCR register will be changed only by the N flag being set. Problem 3: Memory contents and
procesor registers are as shown:
The
will be $CCDC. The CCR register will be changed only by the N flag being set. Problem 3: Memory contents and
procesor registers are as shown:
A B D X Y SP PC CCR
$122A $00
$122B $11
$122C $22
$122D $33
$122E $44
$122F $55
$1230 $66
$1231 $77
$1232 $88
$1233 $99
$1234 $AA
The sequence of instructions below is executed:
0800 36 psha
0801 34 pshx
0802 35 pshy
0803 16 09 00 jsr $900
In the above description of memory and register contents, write in any values changed by the above sequence of
instructions. Answer: The first instruction, psha, changes the SP register to $1233 and writes the value of
into that location in memory, changing it to $AA. It also changes the PC, incrementing it by 1. The second
instruction decrements the SP by 2, making it $1231 and writes $CCDD into memory location $1231 as a word,
making memory location $1231 $CC and $1232 $DD. It also increments the PC. The third instruction
decrements the SP by 2, making it $122F and writes $EEFF into that memory as a work, making $122F $EE and
$1230 $FF. It also increments the PC. the jsr instruction pushes the return address, which is $806, onto the
stack, decrementing it by 2 and making memory locations $122D and $122E contain $08 and $06 respectively.
It also loads the PC with the value $806. None of the instructions changes the CCR bits, so the final state of the
PC is:
A B D X Y SP PC CCR
$AA $BB $AABB $CCDD $EEFF $122D $0900 --0000
And the memory locations now contain:
$122A $00
$122B $11
$122C $22
$122D $08
$122E $06
$122F $EE
$1230 $FF
$1231 $CC
$1232 $DD
$1233 $AA
$1234 $AA
$1234 $AA
Problem 4: Consider the following program.
program: ;this subroutine is supposed to count the number

;of 1 bits in a sequence of bytes. The first
;byte is at memory location pointed to by x.
;the last byte is at memory location pointed to by y.
pshy ;put y where we can compare it to x.
pshd
ldx #0 <-- Problem 1
nbyte:
ldaa 1,x+ ; 2 bytes
cpx 0,sp ;check if done 2 bytes <-- Problem 2
bmi done ; 2 bytes
ldab #8 ; 2 bytes
bcloop: ;this is going to count the number of bits in a byte
lsra ; 1 byte
bcs ibit ; 2 bytes
decb ; 1 byte
bne bcloop ; 2 bytes
bra nbyte ; 2 bytes
ibit: ;increment the number of bits
inc 1,sp ; 2 bytes <--- Problem 3
bcc nxt ; 2 bytes
inc 0,sp ; 2 bytes
nxt:
decb ; 1 byte
bne bcloop ; 2 bytes
bra nbyte ; 2 bytes
done: puld
rts ;returns with d containing the number of 1 bit
a) This program, as written, will not work. I've made an

error or two. List them.
Ans: Problem 1: the ldx will wipe out the value of x. We need a
counter to hold the number of bits found, and it appears to
be the intent of the author to hold these bits in x, but
x is already used for the address of the byte-array.
Problem 2: 0,sp contains the saved value of , not .
is at 2,sp.
Problem 3: It appears now to be the author's intent to have
the bit counter at 0,sp, but that's where is stored!

Remember, as an assembly-language author, you are
responsible for all variables, where they are kept, and how
they are used.
The corrected subroutine should have zeroed instead of x,

and the ibit should have been simply iny. Alternatively,
we could zero before pushing it on the stack and left the

ibit as it is.
b) Hand-assemble the last 5 instructions.
decb, puld, and rts will present no problems, as they are
just look-ups into the reference manual. However, for the
just look-ups into the reference manual. However, for the
two branch instructions, we need to calculate the offsets
which will be taken. Count the bytes of machine code. There
are 17 bytes from where the PC will be after the bne bcloop
back to bcloop. Therefore, the displacement will be -17.
That's the two's complement of %00010001, or $EF. Similarly,
there are 27 bytes from where the PC is after the bra nbyte
back to nbyte, so the displacement will be $E5.
Here's the machine code:
53
26 EF
20 E5
3A
3D
Here's the final, tested, version of the program:
bitctr: ;this subroutine is supposed to count the number

;of 1 bits in a sequence of bytes. The first
;byte is at memory location pointed to by x.
;the last byte is at memory location pointed to by y.
pshy ;put y where we can compare it to x.
ldy #0 ;this will be our counter
nbyte:
ldaa 1,x+ ;get the next byte;
cpx 0,sp ;check if done by comparing x and the saved val of y
bhi done ;we are done if x after increment is bigger than end
ldab #8 ;8 bits per byte
bcloop:
lsra ;counting bits in a byte. Shift into Carry flag
bcc nibit ;was it a 1? If so, we'll increment our counter
iny ;increment the number of bits
nibit:
decb ;otherwise, no increment.
bne bcloop ;all 8 bits counted?
bra nbyte ;get next byte
done:
tfr y,d
puly
rts ;returns with d containing the number of 1 bits
Problem 6: In class we wrote the most efficient memory copy subroutine for copying a number of bytes (the
number in register ) located in memory (address in register ) to destination (address in register ) as
long as the memory didn't overlap. When the memory regions overlap, we needed a routine (label ``deep
trouble'') which copied the memory in reverse order. Write this routine. As you will recall, is located at the
top of the stack. Your program will have to restore the stack before finishing, and will need to do a return
instruction. When the memory regions overlap, we have to copy from the end of the memory backwards to avoid
having the data at the end of of the source being overwritten by the stuff being copied in. To copy the bytes
backward we just do:
deeptrouble:
pshd ;save d
addd 2,sp ;d = y + d
tfr d,y ;y = y + d
ldd 0,sp ;recover d
ldd 0,sp ;recover d
stx 2,sp ;put x on stack
addd 2,sp ;d = x + d
tfr d,x ;x = x + d
puld ;pop x off
puld ;recover d
bmclp:
movb 1,x-,1,y-
addd #-1,d
bpl bmclp
rts
done:
puld
rts
Here's a full version of memcpy. I've changed the logic a little, so it isn't exactly what we did in class. It isn't as
efficient, because we're copying bytes instead of words.
memcpy:
pshd
pshx
cpy 0,sp ;compare x and y (y - x)
beq done ; x = y. Don't copy
bpl trouble ;if y > x, a possible overlap exists
falsealarm:
pulx
puld
mclp:
movb 1,x+,1,y+
addd #-1
blo mclp
rts
trouble:
addd 0,sp ; so d = x + d
pshd
cpy 0,sp ;compare x + d and y
puld
bpl falsealarm ;x + d <= y
deeptrouble:
ldd 2,sp ;recover d
pshy
addd 0,sp ;d = y + d
tfr d,y ;y = y + d
ldd 4,sp ;recover d
addd 2,sp ;d = x + d
tfr d,x ;x = x + d
puld ;pop x off
puld ;pop y off
puld ;recover d
bmclp:
movb 1,x-,1,y-
addd #-1,d
bpl bmclp
rts
done:
pulx
puld
rts
About this document ...

2002-03-20

Midterm Exam 2
Problem 1: The state of the CPU is:
A B D X Y SP PC flags: S X H I N Z V C
$01 $75 $0175 $abcd $374A $7FE $800 0 0 0 0 0 0 0 1
The following sequence of instructions is executed (note that the jsr instruction results in in non-sequential
operation.)
...
$800 pshd ;SP = SP - 2, D --> $7fc
$801 pshx ;SP = SP - 2, D --> $7fa
$802 movw #$2354,-2,sp ;trick: this will be overwritten
$808 jsr subrtn ;SP = SP - 2, PC --> $7f8
$80b ...
$80b ...
subrtn: ;the address of this subroutine is $920
pshc ;SP = SP - 1, ccr --> $7f7
psha ;SP = SP - 1, a --> $7f6
pshy ;SP = SP - 2, Y --> $7f4
Fill in the following ``Stack Frame'' appropriately. Indicate the addresses of each location on the stack, the
contents, and the initial and final places the stack pointer points to.
address data
$7ec
$7ee
$7f0
$7f2
$7f4 $374a saved Y
$7f6 $0101 saved ccr, saved a
$7f8 $080b return address
$7fa $abcd saved X
$7fc $0175 bottom of stack - D
Problem 2: Hand-assemble the instruction ``movb $900,-2,x''.
$18 $09 $1e $09 $00
Problem 3: Assume that the counter-timer is set up to run at a clock of 500KHz (after the pre-scaler). Suppose
that you cannot use channel 7 (it's being used for some other purpose.) Assuming that channel 1 is already set
up to generate interrupts on output compare, write an interrupt service routine to increment a 32-bit counter
value at memory location $900 (through $903) each 10 msecs. Solution: a 500KHz clock will have 2000 cycles
in 10 msecs. Channel 1 won't automatically retrigger, so we have to use the `òn-the-fly'' method to change
the output compare on each interrupt to 2000 more than the current tcnt. We do this first so that the timing
won't be off any more than necessary. We also have to explicitly clear the interupt flag.
ISR:
ldd tcnt ;get current count
addd #2000 ;the count will be this in 10msecs
std tc1 ;store to the output compare for ch1
std tc1 ;store to the output compare for ch1
inc $903 ;a 32-bit counter is trivial.
bne done ;we just increment each byte, starting
inc $902 ;at the least-significant, and only
bne done ;bump the next byte if we get overflow,
inc $901 ;indicated by a zero when we bump.
bne done
inc $900
done
movb #2,TFLAG1 ;write a 1 to the flag reg to clear the
;interrupt bit.
rti
Problem 4: Describe the sequence of microprocessor events which take place when an interrupt (IRQ) occurs.
Assume that the I bit in the CCR is 0 initially. Solution: The CCR is saved to a temporary register, and then the I
bit in the CCR is set. The CCR, D, X, SP, and PC (which contains the address of the next instruction) are placed
on the stack. Note that the CCR is written as a 16 bit thing, so the stack remains aligned. The appropriate word
in the interrupt vector table is then read and placed in the PC. This will cause the next instruction to be executed
to be the one at the address contained in that vector. Assume that the X and I bits in the CCR are 0, and the
instruction
orcc #$50
is executed. Describe the contents of the CCR after this instruction.

Solution: The CCR I bit will be set, but the X bit cannot be set through software, and will remain clear.
Problem 5: Following is a before-and-after snapshot of the processor state, upon execution of the instruction
between them:
Before:
$01 $75 $0175 $abcd $374A $7FE $800 0 0 0 0 0 0 0 1
dbeq a,foo
(Assume that the label ``foo'' refers to an instruction at address $840.)

After:
$01 $75 $0175 $abcd $374A $7FC $810 0 1 0 0 0 0 0 0
There is at least one error in the `àfter'' snapshot (such as bits that are set that shouldn't be, register values
which are wrong). Find and explain as many errors as you can. Solution: The following errors exist:
The X bit cannot be set.

The A register is decremented by dbeq, so A should be 0.
The D register should reflect this.
The C bit shouldn't be affected.
The PC should be $840, as the branch will be taken.
The SP should not be affected.
Problem 6: Suppose that we wish to create voltages from 0 to 10 volts using a Digital-to-Analog convertor with
a precision of .1 volts or better. a) Can we do this with an 8-bit DAC? Solution: Yes, .1 volts is 1 percent, and
we can do 1/128 at least.
b) What bit pattern would correspond to an output voltage of 4.3 volts ?
Solution: I get $6E. ((255-0)*4.3/10 = 109.65, or 110. Convert to hex.)
2002-05-10
2002-05-10

Midterm Exam 1
Problem 1: (Short answers)
Suppose accumulator contains the bit pattern %1101001001011001, memory location $800 (considered as
the address of a sixteen bit number) contains $1234. Also suppose that the CCR register contains %00001111.
a) Considered as representing a signed number, what number does
register represent?
soln: contains . This means that it represents a
negative number (since it's signed.) To find that number, find

its magnitude, which is the decimal value represented by the 2's
complement, , or 32 + 14, or 46. The answer is -46.
b) Considered as representing an unsigned number, what number does
register represent?
soln: 13*16 + 2 = 208 + 2 = 210.
c) Considered as representing a signed number, what number does
register represent?
soln:
d) Suppose that `àdda $800'' is executed. What will the contents
of and the CCR be after the instruction?

soln: adda $800 is an 8-bit operation with an extended operand.
The operand is the contents of memory location $800, which
(considered as an 8-bit quantity) is $12. Therefore, we must
add $12 to $D2. The result: = $E4 (no carry, no overflow.)

This result is not zero but is negative. The adda instruction
modifies all four of the CCR bits we know about (as well as the
H bit which is for BCD add.) The answer is %00001000. This is
correct for H as well as N, Z, V, and C. (there is no carry out
of the low-order nybble.)
f) Suppose that `àddd #$800'' is executed. What will
be the contents of and the CCR after the instruction?
soln: This is a 16-bit add with $D259 and $0800 going into .
The answer: = $DA59 (so = $59), CCR = %00001000.

Problem 2: Processor registers are as shown:
A B D X Y SP PC CCR
$AA $BB $AABB $0802 $0802 $0802 $1234 --0000
Suppose that memory locations $7FE through $804 contain data as follows:
address data
$7FE $0001
$800 $0010
$802 $0100
$804 $1000
Describe what memory locations or processor registers are affected and how they are affected when the
instruction ``movw 2,x-,2,-y'' is executed. Do this by crossing out any changed values above and writing in the
correct values above or to the right of the original values.
Solution: X and Y are both decremented by 2 by this instruction. X is decremented after the move, so the
Effective Address of the source operand is $802, and the operand is $0100 (16 bit, since this is a movw
instruction.) The Y register is decremented before the move, so the Effective Addresss of the destination is
$800, which memory location will be over-written by the value $0100. In addition, the PC will be changed.
movw is a two-byte instruction and the indexed addressing modes for both source and destination will require
each a post-byte, for a total of four bytes. PC will contain $1238 after the instruction.
Problem 3: Hand assemble the following assembly-language fragment:
org $200 ___________________

number dw 0 ___________________
org $300 ___________________
prog ldd number ___________________
ldx #number ___________________
bra prog ___________________
I've placed a line to the right of each statement, whether it will produce any code or data or not. Your job is to
put the hex values (or binary, if you choose) in the spaces provided. You can assemble this yourself with your
assembler to see what the answer is. I will discuss the problem at a higher level. What is required is to
understand what lines produce code and which do not. The `òrg'' lines produce no code. The ``dw'' line does
cause the assembler to produce data (16 bits of 0), which is put in memory at memory location $200, and the
label ``number'' is then given the value $200. The ``ldd number'' produces three bytes of instruction data, 1
byte of opcode and then the value $200 (which is 16 bits.) Similarly, ``ldd #number'' produces three bytes of
data, 1 byte of opcode and 2 bytes of instruction data (again, $200.). The ``bra'' instruction produces two bytes
of instruction, 1 byte of opcode and 1 byte which is the value to be added to the PC. The branch is taken relative
to the value of the PC at the end of the instruction, which is $308, and the destination address is $300, so the
value of the byte should be or $f8.
Problem 4: Memory contents and procesor registers are as shown:

A B D X Y SP PC CCR
$122A $00
$122B $11
$122B $11
$122C $22
$122D $33
$122E $44
$122F $55
$1230 $66
$1231 $77
$1232 $88
$1233 $99
$1234 $AA
The sequence of instructions below is executed:
0800 36 psha
0801 34 pshx
0802 35 pshy
0803 16 09 00 jsr $900
In the above description of memory and register contents, write in any values changed by the above sequence of
instructions. Solution: You can simulate this, so there's no solution necessary, but I will comment about what
happens. First, psha is an 8-bit stack push, which decrements the stack pointer by 1 and writes the value in
to the location pointed to by SP. This would make ($1233) = $AA and SP = $1233. Similarly, the pshy
instruction decrements the stack and writes to the memory location pointed to by the stack, but this is a
16-bit quantity, so ($1231) = $CC and ($1232) = $DD, and SP = $1231. The same thing happens again, with
in pshy: ($122f) = $EE, ($1230) = $FF. We must also figure out what happens to the PC during this process.
The psha, pshx, and pshy are 1-byte instructions, so each increments the PC by 1. Finally, the jsr $900
instruction would push the address of the next instruction, which would be $806, on the stack, which would
make ($122d) = $08 and ($122e) = $06, and then set the PC to $900.
Problem 5: Consider the following program.
;this subroutine counts all occurrences of the value

;in the A register in an array whose starting address
;is in the X register and whose ending address is in
;the Y register and returns the number of times the
;value was found in the D register.
;Only the A register and the CCR are left altered.
countbytes:
pshy ;put Y where we can compare it with X
ldd #0 <<<<<<< ERROR! destroys the A register.
pshd ;initialize count to 0
cbyte:
cmpa 1,x+ <<<<< ERROR! changes X, which we have *not* saved!
bne notfound
puld
addd #1
pshd
notfound:
cpx 0,sp ;compare x with the saved value of Y
<<<<<< ERROR! this compares X with D, not Y, which is at 2,sp.
blo done ;unsigned compare. Are we done?
<<<<<< ERROR! wrong comparison. I think it should be bge.
<<<<<< In any case, this will *not* work.
bra cbyte
done: puld
<<<<<< ERROR! Stack discipline violation! We pushed Y, we'd
<<<<<< better pul it before we call rts.
rts ;returns with d containing the number of times
<<<<<< better pul it before we call rts.
rts ;returns with d containing the number of times
I was in a hurry when I wrote it, and when I simulated it it didn't work, so it must have at least one error. List all
the problems you can find with this subroutine. Solution: look for the in the above...
Problem 6: a) Hand-execute the following subroutine and determine the value returned in the A register if the
value in the A register is $12 to start:
subroutine_X:
pshb
tfr a,b
lsrb
andb #$55
anda #$55
aba
tfr a,b
lsrb
lsrb
andb #$33
anda #$33
aba
tfr a,b
lsrb
lsrb
lsrb
lsrb
aba
anda #$0f
pulb
rts
Solution: 2
b) What does this program do? (hint: try a couple of more values for A, such as $35, and $ff.) I'm not looking for
``pushes b on the stack, then, ...'' - I want you to tell me what I'll get out if I put an arbitrary value in. I'll give
you this for nothing: it changes only the A register and the CCR. Yes, there's a simple, short answer.
If you run $35 and $ff through, you'll find that the subroutine returns 4 for $35 and 8 for $ff. This is the
number of ``1'' bits in the number in the register as a binary number.
c) Suggest a way to make the program faster. Unfortunately, there is no `àndd'' instruction, so we cannot
speed up the and instructions, and the rest are pretty much unimprovable as well. There is a way to speed this
program up, however, at (hint, hint) the cost of increased space. Here's the solution:
table db 00, 01, 01, 02, 01, 02, 02, 03,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 04, 05, 05, 06, 05, 06, 06, 07,
db 01, 02, 02, 03, 02, 03, 03, 04,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 04, 05, 05, 06, 05, 06, 06, 07,
db 02, 03, 03, 04, 03, 04, 04, 05,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 04, 05, 05, 06, 05, 06, 06, 07,
db 03, 04, 04, 05, 04, 05, 05, 06,
db 04, 05, 05, 06, 05, 06, 06, 07,
db 04, 05, 05, 06, 05, 06, 06, 07,
db 05, 06, 06, 07, 06, 07, 07, 08
subroutine_X:
pshx
ldx #table
ldaa a,x
pulx
rts

Charles Rennolet 2003-02-23
Department of Electrical and Computer Engineering
EE2361 - Introduction to Microcontrollers - Fall 2002
Name (printed) _____________________________
Signature: _____________________________
Student ID# _____________________________
Final Examination
Closed Book & Crib Sheet
December 17, 2002
SOLUTIONS
• Your printed name, signature and ID # is required.
• Show all your work. Results without justification will lose points.
• Circle or clearly label your final answers. Problems with conflicting answers will receive no
credit.
• Be prepared to show two forms of photo identification.
8 problems
1. Number Conversions - 2 parts
2. Arithmetic - 4 parts
3. Programming - 2 parts
4. ATD - 3 parts
5. Serial Port - 3 parts
6. Timer - 2 parts
7. Fuzzy Logic - 2 parts
8. Memory Timing - 3 parts
1. Number conversions
a) Convert the decimal number -185 into a 16-bit signed binary number.
185
92 1
46 0
23 0
11 1
5 1
2 1
1 0
1
0000000010111001 = $00B9 = 11x16 + 9 = 185
1111111101000110 + 1
1111111101000111
b) Convert the signed binary number 11011010 to a decimal number.
$DA
$25+1 = $26
2*16 + 6 = 38
-38
c) Compute the two's complement of the 8-bit two's complement number $B5.
$B5 => $4A + 1 = $4B

d) Perform the arithmetic operations on the two’s complement and signed binary numbers. In
each case, indicate whether or not signed overflow occurs.
a) $88CD + $F781
$88CD + $F781 = $804E

This adds two negative numbers and produces a negative result, so there is no signed
overflow.
b) $8333 - $7FF6
$8333 - $7FF6 = $033D

This subtracts a positive number from a negative number and produces a positive result, so signed
overflow has occurred.
c)
01101010
+ 01001101
10110111
This adds two positive numbers and produces a negative result, so there is signed overflow..
d)
01101010
- 10101110
01010001
+ 00000001
01010010
+ 01101010
10111100
This adds two positive numbers and produces a negative result, so there is signed overflow..
3. Programming problems.
a) Give the addressing mode and the effective address for the instruction,
staa $3,y Assume the Y index register contains $1991.
EA = $0003+(Y) = $1994, (indexed)
b) Write a program to move 96 bytes from location $900 to location $1000. Include the use of a
loop. and both index registers. Skip the ORG and EQUATES.
PROG: EQU $800

org PROG
loop: ldaa !48

ldx #$900
ldy #$1000
movw $2,x+,$2,y+
dbne a,loop
nop
4. The ATD is to perform the following sampling.
continuous conversion
channels 4-7
32 Total Conversion Time ATD clock periods
0.571 MHz ATD clock
a) What binary code must be loaded into ATDCTL5 ?
ATDCTL5, #%00110100
b) What binary code must be loaded into ATDCTL4 ?
ATDCTL4, #%11000110
c) What register will contain the result for Channel 6?
ADR2H
d) Write a single line of code which will wait for the conversion to be completed.
spin: brclr ATDSTAT, %10000000,spin
e) If VRH = 5.0v and VRL = 0v, what hex value is returned when the ATD system converts 1.25
volts assuming an 8-bit conversion?
(256 – 1)steps * resolution = (5 – 0)

138 $8A
1.25 = steps
5 255
steps = 64 = $40
5. SC0 is to be used to transmit and receive characters.
1 start, 9 data and 1 stop bit
odd parity
9600 Baud.
a) What binary value must be loaded into register SC0CR2?
bset SC0CR2,%00001100 ; TxRx enable
b) What binary value must be loaded into register SC0CR1?
%00010011 ; mode, parity, odd
c) Write the 1 line of code needed in order to wait for a character to be received.
spin: brclr SC9SR1,%00100000,spin
d) What register must be loaded with the BAUD rate (assume a 16-bit value)?
SC0BDH or SC0BDH and SC0BDL
e) Write the 1 line of code needed in order to wait for a character to be transmitted.

6. The Input Capture capability of the Timer is to be used to find the times of the rising and falling
edges of a periodic waveform.
first edge
second edge
a) What binary value must be loaded into what register in order to set up to capture the time of
the rising edge of the waveform being input to Channel 5 of PORTT?
%00000100 TCTL3
b) What binary value must be loaded into what register in order to set up to capture the time
of the falling edge of the waveform being input to Channel 5 of PORTT?
%00001000 TCTL3
c) Write the 1 line of code needed to wait for the rising edge of the waveform.
spin1: brclr TFLG1,%00100000,spin1

7. Fuzzy Logic
a) An input to a fuzzy controller whose membership function includes the one shown below is
$50. What is the truth value of the function in decimal?
192
b) Apply the rule evaluation process to the following table of truths for the Robot and determine
final truth values for the rules LS.
Rule Right Sensor Left Sensor Truth Rule Current Final

1 0 32 0 LM 0 0
2 16 32 16 LM 0 16
3 22 15 15 LS 0 15
4 55 30 30 LS 15 30
5 70 0 0 LM 16 16
6 55 40 40 LS 30 40
LS = 40
8. Given the timing diagram below for a memory system and HC12 determine the following,
a) tcs access available
b) toe available
c) taddr access available
33, 55, 70 t1st = 100 ns t2nd = 100 ns
ECLK
37 = tdcoder 22 (if needed) + tAND 15 ns

Address
tAV >0 tAH 20 ns
tADDR access available
R/notW tRWV 20
notWE = !(ECLK*R/notW)
tOE available
NAND 15 ns
notCS = !(ECLK*A13) 37 = tdcoder 22 (if needed) + tAND 15 ns
tCS access available tDSR 30 ns

Data
1. _______ (12 points)

2. _______ (12 points)
3. _______ (12 points)
4. _______ (12 points)
5. _______ (12 points)
6. _______ (12 points)
7. _______ (12 points)
8. _______ (12 points)
+ 4 points
Total ________ (100)

EE 2361 Lab 6 James Lamberg
04/03/03 #2485126
Interfacing a Digital to Analog Converter
James Lamberg
University of Minnesota Microcontrollers Lab 032
Objective
In this lab, we wired a circuit and wrote a program to send a 400Hz signal to a speaker. It
is the first lab of a sequence that is part of a larger project called the voice encryption
system. We built the digital to analog conversion section during this lab. The program
generated sent a saw-tooth signal through Port, A which was wired to the speaker.
Steps and Explanation: just divide the time to get to the peak by
Our first task was to complete the the step time to get 2.5ms/0.096ms≈26
pre-lab. This gave us a good idea of cycles. Therefore, we used 26 or $1A
what we would have to do in this lab. for the number of steps.
Next, we wired the circuit using Since we used Port A, we need to
the schematic given to us. This set Port A as an output port and assign
schematic can be found as Attachment the necessary data direction register
#1 which also includes the block (DDRA). We then loaded into
diagram of the circuit. The block accumulator B $1A which would count
diagram consists of the 68HC12A4EVB from 26 down to 0. During this time, we
connected to a Burr-Brown 811 Digital incremented A and stored it into Port A.
to Analog Converter (DAC) via Port A This would increase the value of Port A
(PA0-PA7). This connects to an by 1 each time, simulating the rising
Amplifier circuit then to a 3KHZ cutoff edge of the sawtooth wave.
Filter then finally to the speaker for Next, we decremented B and
output. The amplifier is meant to branched to the same instruction if not
attenuate the circuit so its gain is less equal to 0. This simulated the falling
than 1. edge of the sawtooth wave. Then we
Our next step was to write the branched always back to the point where
program. We checked the we load accumulator B with $1A. This
documentation to ensure the MCLK bus cycle gave a sawtooth output on Port A.
clock for the HC12 was 8 MHz before The code is attached as Attachment #2.
we began. We then needed to calculate When the circuit was wired
how many cycles it would take to reach correctly, the output from Port A went
the peak of the sawtooth wave. With a into the DAC and was converted to an
clock frequency of 8MHz, we get analog signal. It was then attenuated and
1/8MHz or T=0.125µs for the period. A filtered before reaching the speaker. We
frequency of 400Hz gives 1/400Hz or were able to confirm a correct audible
T=2.5ms for the period. Our branch tone coming from the speaker. This
command would take 3 cycles with showed that our program and circuit
2^8=256 bits. Using our data for the were working correctly. We also used
waveform we get an oscilloscope to measure ∆T=2.64ms
256*3*0.125µs=0.096ms. This is the and 1/∆T≈378.788Hz which ensured our
time for each step in the waveform. To output was correct.
determine how many steps we take, we
04/03/03 #2485126
Problems Encountered: this wave to a speaker. This required
We encountered a couple careful wiring and some computation to
problems during this lab. At first we ensure the software would output a
were unable to wire the circuit correctly. 400Hz wave. After completing all the
After investigating our circuit we were parts we were able to hear the 400Hz
able to determine where we made sawtooth wave though the speaker and
mistakes. We simply corrected these view it on an oscilloscope.
wiring errors to fix the problem.
Next, we needed to calculate the References:
number of steps needed. We were M68HC12 & HXC12 Microcontrollers,
initially lost but then easily solved our CPU12 Reference Manual by Motorola,
problem using the pre-lab work that we Rev. 3, 5/2002
had already done.
After fixing these problems our 68HC12 Microcontroller, Theory and
sound came out clear and we had no Applications by Daniel J. Pack and
further trouble. Steven F. Barrett, Prentice Hall 2002
Conclusion: 68HC12 Micro-Controller Board

In this lab we were able to Development Environment by P & E
program a 400Hz sawtooth wave in Microcomputer Systems
Assembly and interface a DAC to output
04/03/03 #2485126
Attachment #1
04/03/03 #2485126
Attachment #2
;************************
; James Lamberg
; 03/13/2003
; 400Hz sawtooth wave
; Lab #6
;************************
DDRA equ $0002

PORTA equ $0000
org $0800
ldaa #$00FF
staa DDRA
ldaa #$0000
staa PORTA
begin: ldab #$001A ;acccum B counts from 26 to 0 for 26 steps

inca
staa PORTA ;increases Port A each loop to increase tone
loop: dbne B,loop ; decrements accum B until B is 0

bra begin ; cycles again, creating continuous sawtooth
04/17/03 #2485126
Serial Communications
James Lamberg
Objective
In this lab, we wired a circuit and wrote a program to utilize the serial port on the
68HC12A4EVB. It is the second lab of a sequence that is part of a larger project called
the voice encryption system. We built the bi-directional communications portion
throughout this lab using the Serial Communications Interface (SCI). The program
generated a saw-tooth signal that was sent over using a serial port from one HC12 to
another HC12, which used the circuit (ATD Conversion) to output the 400HZ signal to a
speaker.
program to send the letter “A” from
Steps and Explanation: HyperTerminal and see if we received
Our first task was to complete the the letter in the form of $41. For this
pre-lab. This gave us a good idea of program we needed to initialize Port A
what we would have to do in this lab. and set the baud rate for the SCI. We
Next, we wired the circuit using then set the correct bits in the SCI
the schematic given to us. This registers and continually polled for data.
schematic can be found as Attachment We found that this program did in fact
#1 which also includes the block receive an “A” (and any other byte) from
diagram of the circuit. The block HyperTerminal. The code is included as
diagram consists of the 68HC12A4EVB Attachment #3.
connected to a Burr-Brown 811 Digital The program was then easy. We
to Analog Converter (DAC) the serial setup the same registers for the sending
port. This connects to an Amplifier program. We set the baud rate to be
circuit then to a 3KHZ cutoff Filter then very high, at 38400. We disabled
finally to the speaker for output. The interrupts then cleared the TDRE flag.
amplifier is meant to attenuate the circuit We then polled until this flag was set,
so its gain is less than 1. There is also a which would tell us that we have sent
sending 68HC12A4EVB, which successfully. We then implemented the
generates the sawtooth wave. same code from the previous lab to make
Our next step was to write the the sawtooth wave.
test program. This program would send The next step was to make the
the letter “A” to the HyperTerminal receiving program. Again, we set the
program that is included with Microsoft same registers as we did for the
Windows. We did this by writing bits to HyperTerminal program. We set the
certain SCI registers, enabling the items baud rate to be the same, 38400, so there
we wanted. We then moved a byte, “A” would be no problems. We then
or $41, to the SCI Data Register and disabled interrupts and initialized Port A
continued writing the byte. We checked by writing $FF to DDRA and $00 to
HyperTerminal and found that it did in PORTA. Next, we cleared the RDRF
fact show the letter “A” repeatedly on flag and continuously polled until the
the screen. This code is included as flag was set, telling us that data
Attachment #2. We then wrote a test receiving has been successful. We then
04/17/03 #2485126
sent this information to the circuit to be
outputted to the speaker. Conclusion:
When the circuit was wired In this lab we were able to make
correctly, the output from Port A went a sending and receiving program for
into the DAC and was converted to an HyperTerminal. This sent a byte, letter
analog signal. It was then attenuated and “A”, to HyperTerminal and back to the
filtered before reaching the speaker. We 68HC12A4EVB. We then implemented
were able to confirm a correct audible our 400Hz sawtooth code from last lab.
tone coming from the speaker. This We made a sending program with the
showed that our program and circuit sawtooth that sent data via the Serial
were working correctly. We also used Communications Interface (SCI) to
an oscilloscope to measure ∆T=2.64ms another 68HC12A4EVB. We then made
and 1/∆T≈378.788Hz which ensured our a program that received this data and
output was correct. sent it as output to Port A. This was
then sent to a DAC then a filter to output
Problems Encountered: this wave to a speaker. This required
We encountered a few problems careful wiring and some computation to
during this lab. At first we were unable ensure the software would output a
to wire the circuit correctly. After 400Hz wave. After completing all the
investigating our circuit we were able to parts we were able to hear the 400Hz
determine that the wiring to the HC12 sawtooth wave though the speaker and
was incorrect and we were able to easily view it on an oscilloscope.
correct the problem.
Next, we needed to calculate the References:
number of steps needed. Since this M68HC12 & HXC12 Microcontrollers,
program was similar to the last lab, we CPU12 Reference Manual by Motorola,
were able to use the same formula. Rev. 3, 5/2002
The last problem was that the
wave was not very “crisp” on the 68HC12 Microcontroller, Theory and
oscilloscope. This may have been a Applications by Daniel J. Pack and
baud rate problem or a wiring problem. Steven F. Barrett, Prentice Hall 2002
It was likely a wiring problem and took
some troubleshooting to correct. After 68HC12 Micro-Controller Board
correction, the wave was slightly better Development Environment by P & E
but still not perfect. Microcomputer Systems
04/17/03 #2485126
Attachment #1
04/17/03 #2485126
05/01/03 #2485126
Sampling Voice from a Microphone

James Lamberg
Objective
In this lab, we wired a circuit and wrote a program to utilize the serial port on the
68HC12A4EVB. It is the third lab of a sequence that is part of a larger project called the
voice encryption system. We used the Serial Communications Interface (SCI) to send an
audio signal from one HC12 to another HC12 then to a speaker. The sending program
sent and audio signal via the SCI, converting it to a digital signal using the Analog to
Digital Converter (ATD). The receiving program sent this signal through an ATD chip,
which was then send to a speaker. The overall design is shown in a flow chart as
Attachment #1.
successfully. We also set a delay for the
Steps and Explanation: ATD to stabilize. We then implemented
First, we wired the circuit using the same code to send the audio signal.
the schematic given to us. This The next step was to make the
schematic can be found as Attachment receiving program. Again, we set the
#1 which also includes the block same registers as we did for Lab 7. We
diagram of the circuit. The block set the baud rate to be the same,
diagram consists of the 68HC12A4EVB 250,000bps, so there would be no
connected to a Burr-Brown 811 Digital problems. We then disabled interrupts
to Analog Converter (DAC) the serial and initialized Port A by writing $FF to
port. This connects to an Amplifier DDRA and $00 to PORTA. Next, we
circuit then to a 3KHZ cutoff Filter then cleared the RDRF flag and continuously
finally to the speaker for output. The polled until the flag was set, telling us
amplifier is meant to attenuate the circuit that data receiving has been successful.
so its gain is less than 1. There is also a We then sent this information to the
sending 68HC12A4EVB, which we circuit to be outputted to the speaker.
wired for sending the audio signal. This When the circuit was wired
circuit needed to amplify the (+/-) correctly, the output from Port A went
250mV audio signal to a 0-5V signal so into the DAC and was converted to an
that the ATD could use it. We did this analog signal. It was then attenuated and
by building the circuit show in filtered before reaching the speaker. We
Attachment #2. were able to confirm an audio signal that
Since we had written most of the was similar to the one being sent. This
program in Lab 7, there wasn’t much showed that our program and circuit
more to do. We setup the same registers were working correctly. We also used
for the sending program. We set the an oscilloscope to view both the analog
baud rate to be very high, at 250,000bps and digital signals on either end. We
by writing a $02 into the Baud Rate compared the two and determined that
Control Register. We disabled interrupts the signal was in fact being sent.
then cleared the TDRE flag. We then
polled until this flag was set, which Problems Encountered:
would tell us that we have sent
05/01/03 #2485126
We encountered a couple and Analog to Digital Converter (ATD).
problems during this lab. At first we We made a receiving program that used
were unable to wire the sending circuit the SCI to received data and sent it as
correctly. After investigating our circuit output to Port A. This was then sent to a
we were able to determine that the DAC then a filter to output this wave to
wiring to the HC12 was incorrect and we a speaker. This required careful wiring
were able to easily correct the problem and to ensure that we would get the same
by changing to the correct port. audio signal back. After completing all
Next, we needed to calculate the the parts we were able to hear the sent
number of steps needed. Since this audio signal though the speaker and see
program was similar to the last lab, we the signal on the oscilloscope.
were able to use the same formula.
The last problem was that the References:
audio signal was not very clear. We M68HC12 & HXC12 Microcontrollers,
attempted to fix this by correcting CPU12 Reference Manual by Motorola,
wiring, but then realized that it was just Rev. 3, 5/2002
noise. With some minor adjustments we
were able easily recognize the signal. 68HC12 Microcontroller, Theory and
Applications by Daniel J. Pack and
Conclusion: Steven F. Barrett, Prentice Hall 2002
In this lab, we were able to
utilize 2 HC12s to send an audio signal. 68HC12 Micro-Controller Board
We made a sending program using the Development Environment by P & E
Serial Communications Interface (SCI) Microcomputer Systems
05/01/03 #2485126
Attachment #1
05/01/03 #2485126
Attachment #2
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/Decrypt.txt
;**********************
;
; Lab 3
; Decrypt RC4
; Lamberg, Sullivan
; Feb. 12th, 2003
;
;***********************
PROGRAM EQU $0800

INDEXES EQU $0AFE
KEY_TABLE EQU $0B00
STRING EQU $0A50
MASK EQU $20
org INDEXES
;**********************
; Variables Declared
Xindex ds 1 ;declare One Byte at $AFE for Xindex
Yindex ds 1 ;declare One Byte at $AFF for Yindex
org STRING
;**********************
; String initalization
plain_text db 'This is the secret to encode:RC4'
cipher_text ds $20
decode_text ds $20
org PROGRAM
;***************
; INIT Variables
lds #$0AFD ;set stackpointer
;***************
; MAIN Program
jsr init_array ;Jump to subroutine (jsr) init_array for key_table init

clra ;Clear accum A (clra); define my counter
perm1: psha ;put counter on the stack; permutate key_table 255 times
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/Decrypt.txt (1 of 4) [06Nov07 22:48:13 ]

jsr get_key ;get a key, do the mix

pula ;pull counter back off the stack
inca ;increment the counter
bne perm1 ;branch to perm 255 times, then encrypt the string
ldx #plain_text ;Load Index Register X; set X index register to location of plain_text
ldy #cipher_text ;Load Index Register Y; set Y index register to location to store cipher_text
encrypt: psha ;Push accum A (psha) onto the stack;
jsr get_key ;Jump to subroutine get_key; new key is now in accum B
pula ;Pull accum A (pula) get accum A off stack
eorb A,X ;exclusive or accum B (eorb); This instruction is kind of complex
;it is an accumulator index offset instruction. X+A is the address
;of the byte to eor with accum B, the result is stored in accum B
stab A,Y ;Store accum B (stab) in cipher_text memory
inca ;Increment A (inca) A++
cmpa #MASK ;Compare A (cmpa) Compares the counter in accum A to the bit-mask
;and sets the Condition Code Register (CCR) accordingly. The mathmatical
;operation performed by this instruction can be found in the Ref Manual.
bne encrypt ;Branch not equal (bne); stops encrypt loop when counter is equal to MASK.
;*****************
; Decryption Code Here

perm2: psha ;put counter on the stack; permutate key_table 255 times
bne perm2 ;branch to perm 255 times, then encrypt the string
ldx #cipher_text ;Load Index Register X; set X index register to location of plain_text
ldy #decode_text ;Load Index Register Y; set Y index register to location to store cipher_text
decrypt: psha ;Push accum A (psha) onto the stack;

stab A,Y ;Store accum B (stab) in decode_text memory
bne decrypt ;Branch not equal (bne); stops decrypt loop when counter is equal to MASK.

nop ;leave instruction for breakpoint
;
;
; subroutines follow
;
;
init_array: movw #$0000,INDEXES ;Move word (movw); clear Xindex, Yindex

ldaa #$00 ;Load accum A (ldaa); init counter variable
ldx #KEY_TABLE ;Load Idex Register X (ldx) init X = key_table
;for (a = 0; a < 256; a++) key_table[a] = a;
init_loop: staa A,X ;key_table[A] = A
inca ;A++
bne init_loop ;8 bit auto mod 256, fall through when A = 0
rts ;return from subroutine
get_key: ;get_key is a destructive routine of accumulators A:B

;assumes global definition of Xindex, Yindex, and INDEXES
;returns new key in accumulator B
pshx ;push X on stack
ldx #KEY_TABLE ;load X with location key_table
ldd INDEXES ;load accum D (ldd); loads A with Xindex; B with Yindex
inca ;add 1 to Xindex (if overflow mods); x=(x+1)%256
addb A,X ;add key_table[x] to b (if overflow mods); y=(y+key_table[x])%256
staa Xindex ;store Xindex value in memory
stab Yindex ;store Yindex value in memory
;prepare to swap
;swap
ldaa A,X ;accum A <- index[x]
ldab B,X ;accum B <- index[y]
staa B,X ;index[y] <- accum A
stab A,X ;index[x] <- accum B
aba ;accum A <- (A + B); (key_table[x] + key_table[y])%256

ldab A,X ;accum B <- index[accum A]; key_table[A]

clra ;clear accum A

pulx ;restore X index register
nop ;breakpoint to stop program

end

EE 2361 - Introduction to Microcontrollers
Spring Semester 2003
Discussion Problem Set 10
Monday, April 7
Assume a clean HC12 (no built-in ISR’s)
1) Write a subroutine to catch the timer count when the falling edge of a pulse occurs. Use the Input
Capture Edge Bit mechanism of the HC12. Use an interrupt service routine so that the HC12 can do
other work while waiting for the falling edge. Use Channel 1.
INIT_GET_FALLING:
PROG EQU $800
STACK EQU $7FFF
TIOS EQU $80 ; Timer I/O select, 8 bits, 1 per channel,
TSCR EQU $86 ; Timer control, bit-7 Timer Enable TEN,
TFLG1 EQU $8E ; Timer interrupt flag 1 register, 1 bit per chn
TC1 EQU $92 ; Input Capture/Output Compare register #1
TMSK1 EQU $8C ; Timer mask register, enable interrupts
TEN: EQU %10000000 ; Timer enable bit
C1 EQU %00000010 ; Channel 1
EDG1F EQU %00001000 ; Edge1 falling
TCTL4 EQU $8B ; Timer Control 4
FIRST EQU $900
ISR_T1_FALL EQU $6000 ; arbitrary location for ISR
INT_T1 EQU $FFEC ; FFEC will hold address for ISR
ORG PROG
sei ; disable interrupts
; assumes STACK is set by main program
; lds #STACK
ldd #ISR_T1_FALL ; get address of ISR
std INT_T1 ; store ISR address as interrupt vector for T1
bset TSCR,TEN ; Enable the timer system
bclr TIOS,C1 ; Reset TIOS bit-1 to enable input capture
ldaa #EDG1F ; Initialize IC1 for falling edge
staa TCTL4
ldaa #C1 ; Reset IC1 Flag
staa TFLG1
staa TMSK1 ; enable T1 interrupt
cli ; enable interrupts
rts
; ISR for processing falling edge
ORG ISR_T1_FALL ; start of ISR
ldd TC1 ; get the count that was latched
std FIRST ; save it
ldaa #C1 ; Reset the flag
staa TFLG1
rti
2) Write a subroutine to generate the leading edge of the pulse waveform in Problem 1 when the timer
counter is $01FF. Use the Output Compare mechanism of the HC12. Use an interrupt so that the
HC12 can do other work while waiting to generate the rising edge. Use Channel 1.
INIT_GEN_RISING:
PROG EQU $800
STACK EQU $7FFF
C1 EQU %00000010 ; Channel 1
OHC1 EQU %00001100 ; set channel 1 output o a “1”
TCTL2 EQU $89 ; Timer Control 2
COUNT EQU $01FF
ISR_T1_GEN EQU $7000 ; arbitrary location for ISR
ORG PROG
sei ; disable interrupts
; assumes STACK is set by main program
; lds #STACK
ldd #ISR_T1_GEN ; get address of ISR
bset TIOS,C1 ; Set TIOS bit-1 to enable output compare
ldd #COUNT ; load count to compare into TC1
std TC1
ldaa #OHC1 ; Initialize IC1 to generate rising edge
staa TCTL2
staa TFLG1
staa TMSK1 ; enable T1 interrupt
cli
rts
; ISR for cleaning up after generating rising edge
ORG ISR_T1_GEN ; start of ISR
ldaa #C1 ; Reset the flag
staa TFLG1
rti
Monday, April 14
1) Write a program (skip the equates) which uses the timer and polling to perform the
following:
a) Initialize the timer. Generate a “0” output levell on PT4 and a “1” output level on PT5
at the same time when the TCNT=$011F. Clear the flags.
bset TIOS,%00110000 ; set PT5 & PT4 to be outputs

ldaa #%00001110 ; prepare to set PT5 “1”, PT4 “0”
; not sure timer can process 2 channels at same time
staa TCTL1 ; setup TCTL1
ldaa #%11111111 ; prepare to clear all the flags
staa TFLG1 ; clear flag register
ldd #$011F ; prepare to set count to compare
std TC4 ; set count to compare for Ch4
std TC5 ; set count to compare for Ch5
bset TSCR,%10000000 ; turn on the timer
spin brclr TFLG1,%00110000,spin ; wait for TCNT=$011F
ldaa #%11111111 ; prepare to clear the flag register
staa TFLG1 ; clear the flag register
b) Initialize the timer. Detect a falling edge input signal on PT6 followed by detecting a
rising edge input signal on PT2. Clear the flag.
bclr TIOS,%11111111 ; set all channels to be inputs

ldaa #%00100000 ; prepare to detect falling edge on PT6
ldaa #%11111111 ; prepare to clear all the flags
staa TFLG1 ; clear flag register
bset TSCR,%10000000 ; turn on the timer
spin1 brclr TFLG1,%01000000,spin1 ; wait for falling edge on PT6
ldaa TFLG1,%01000000 ; prepare to clear the flag
staa TFLG1 ; clear the flag
ldaa #%00010000 ; prepare to detect rising edge on PT2
spin2 brclr TFLG1,%00000100,spin2 ; wait for rising edge on PT2
bset TFLG1,%00000100 ; clear the flag
Note that two methods were used to clear the flag bits in the above problems, bset and ldaa/staa.
In each method a “1” is written to the bits that need to be reset (cleared to “1”).
On problem 1b, there could be a problem if the pulse on PT2 is too short. In that case, there
would not be enough time to reconfigure for a falling edge on PT2. Probably better is to
configure for any edge on PT2 and then check to see that PT2 is 0 before starting.
2) Describe how we could use the use the timer to count the number of rising edges of a signal
during the period of a positive pulse input to PT2.
Setup Pulse Accumulator (PA) to detect rising edges on PT7
Clear PA counter
Setup timer to detect rising edges on PT2
Turn on timer
Wait for rising edge on PT2
Turn on the PA
Wait for falling edge on PT2
Transfer count in PA to D register
Monday, April 28 Solutions
1) You are in a boat and are attempting to cross directly to the opposite shore of a flowing river. You
are controlling the tiller so that the boat is pointed up river. As you change the motor speed your boat
will strike either up or down river from the target. Then you must change the tiller direction (UP
RIVER ANGLE = system output) to point the boat a little less up river. You have sensors that can
measure how much off of the target you are (DISTANCE) and can calculate the rate of drift away
from target (RATE).
up river
down river
river flow
a) Create 5 input membership names for each of the two System Inputs (just names of sets, not
values)
DISTANCE - LARGE DOWN, MEDIUM DOWN, ZERO, MEDIUM UP, LARGE UP
RATE - DOWN FAST, DOWN MEDIUM, ZERO, UP MEDIUM, UP FAST
b) Create a set of five Fuzzy Output memberships which describe the amount of angle which should
be applied (relative to the starting angle).
MUCH LESS, LESS, SAME, MORE, MUCH MORE
c) Create a set of Rules which relate the Fuzzy Input membership sets and Fuzzy Output
memberships.
Distance \ Rate Down Fast Down Zero Up Medium Up Fast

Medium
Large Down MM MM MM M S
Medium Down MM M M S L
Zero M M S L ML
Medium Up M S L ML ML
Large Up S L ML ML ML
2) Which of the following are System Input, Fuzzy Input, a Fuzzy Output minimum, Fuzzy Output, and
System Output.
a) Hot membership when temperature=100 degress.
b) Temperature recorded on thermometer.
c) Run fan at 80 rpm.
d) Value for HIGH FAN speed when HOT and HUMID for TEMP=100 degress and
HUMIDITY=98%.
e) Final value for HIGH FAN speed.
a. Fuzzy Input b. System Input c. System Output d. Fuzzy Output MIN e. Fuzzy Output
Monday, May 5
Prepare to make a memory timing analysis by filling in the propagation delay times in the table below using
the data sheets provided on the web (link on Memory timing line):
tPH, tPL or tPD for CL = 50pf VCC = 4.5 volts
Backroom Specials 250C -550C to1250C
NAND 30 45
NOT 28 33
AND 30 45
DECODER 42 60
Fill in the timing information in the table below using the SRAM (55ns parts) data sheet:
Address change max 55
Output enable max 25
Chip enable tACE max 40
Pulse width tPWE min 30
Chip select tSCE min 40
A memory design like the one given in the Timing Note has been constructed using the chips given above.
Fill in the memory timing for the two temperature conditions in the tables below:
nanoseconds after the rising edge of the ECLK (50% point)
250C -550C to1250C
READ Time when output data of memory chip becomes 55 55
from valid due to Address change
memory Margin available for Address change 125 same
chip –30tDSR
–55add
= 40
Time when output data of memory chip becomes +30nand +45nand
valid due to Output Enable +25oe +25oe
= 55 = 70
Margin available for Output Enable 125 125
– 30tDSR –30tDSR
–55 -70
= 40 = 25
Time when output data of memory chip becomes 42decoder 60decoder
valid due to Chip Select +30and +45and
+40tace +40tace
= 112 = 145
Margin available for Chip Select 125 125
–30 tDSR –30 tDSR
– 112 –145
= -17 = - 50
nanoseconds
250C -550C to1250C
WRITE Time left over (margin) between pulse 125 125
to memory width needed to write data to the -(28not-20rwch) –(33not-20rwch)
chip memory chip and the falling edge of the –30nand -45 nand
ECLK. –30tPWE –30tPWE
Note: this ignores the extra margin = 57 = 37
available due to propagation delays.
Time left over (margin) between the 125 125
chip select time needed and the falling – 42decoder – 60 decoder
edge of the ECLK. – 30and –45 and
Note: this ignores the extra margin –40tSCE –40tSCE
available due to propagation delays. = 13 = -20
• timing for HCT CMOS (not the Backroom Special)
t1st 125ns t2nd 125ns
ECLK
Address (input to memory

chip, direct from HC12)
memory chip address access time, tADDR, (time when memory chip output data
becomes valid after input address change) must be less than 125–30 = 95 ns.
This assumes chip select and output enable are already set .
R/notW tRWV 20
memory chip output enable access time, tOE , (time when

NAND 15 ns memory chip output data becomes valid after notOE input to
notOE = !(ECLK*(R/notW)
chip changed) must be less than 125–30–15 = 80 ns.
37 = tdcoder 22 (if needed) + tAND 15 ns (A13*ECLK)

notCS = !(ECLK*A13)
tDSR 30 ns
Data
memory chip select access time, tCS, must be less than

which is 125-30-37 = 58ns (output data becomes stable
following chip select input to memory chip going low). Data from memory chip
must be stable before this time
ECLK
Address
tRWV 20 required
R/notW
NOT 15
tRWH 20
!R/notW
tDSW 30 ns
Data tDHW 20 ns
NAND 15
pulse width, tWP, to write the memory chip must be less
notWE = !(ECLK*!R/notW) than 125–15 = 110ns
37 = tdcoder 22 (if needed) + tAND 15
notCS = !(ECLK*A13) memory chip select time, tCSW , must be less than 125-37 = 88
EE 2361 Spring 2003
Discussion 1
Week of January 26th
6 problems - Solutions
1. Convert the signed binary number 10101101 to a decimal number. Then convert
10101101 to Hex and convert the Hex number to a decimal number.
01010010
+1
01010011
1*20 + 1*21 + 1*24 + 1*26 = 1 + 2 + 16 + 64 = 83 → -83
$AD
FF
- AD
52
+ 1
$53
3*160 + 5*161 = 3 + 80 = 83 → -83
2. Convert the following decimal number -1297 into the following:

a) 16-bit two’s complement binary
0 ← 1 ← 2 ← 5 ← 10 ← 20 ← 40 ← 81 ← 162 ← 324 ← 648 ← 1297 / 2

↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 0 0 0 1 0 0 0 1
10100010001
Extend to 16 bits
0000010100010001
1111101011101110
+1
1111101011101111
FAEF
b) Hex (directly)
0 ← 5 ← 81 ← 1297 / 16
↓ ↓ ↓
5 1 1
FFFF
- 0511
FAEE
+1
FAEF
3. Convert each of the following signed hex numbers to decimal numbers.

a) $D5EC
$FFFF
-D5EC
2A13
+1
2A14
2*163 + 10*162 +1*161 + 4*160 + = 8192 + 2560 + 16 + 4 = 10772 → -10772
b) $AC93
$FFFF
-AC93
536C
+1
536D
5*163 +3*162 + 6*161 + 13*160 = 20480 + 768 +96 +13 = 21357 → -21357
4. Sign-extend the signed hex or binary numbers to 16-bit signed-hex or 16-bit signed
binary numbers.
a) E FFFE
b) 3FE 03FE
c) 2 0002
d) ED2 FED2
e) 10110 1111111111110110
f) 011100001111 0000011100001111
5. Perform the binary arithmetic operations on these signed binary numbers and indicate
if overflow occurs. For the subtraction operations perform the operation directly and
then repeat it by taking the 2’s complement and adding the operands.
a) 01111101
+ 11001110
01001011 No
b) 10101011
- 11011010
11010001 No
10101011
00100101
1
11010001
c) 01011110
+ 01010101
10110011 Yes
d) 01101010
- 01101101
11111101 No
01101010
10010010
1
11111101
6. Perform the indicated 16-bit arithmetic operations on the signed-hex numbers and
indicate if overflow occurs.
a) DFE2
+ B427
9409 No
b) 3ECD
- B0F2
8DDB Yes
c) 8EB3
- 93D7
FADC No
d) D008
+ 100A
E012 No
e) E0FD
+ 4E2A
2F27 No
EE 2361 Spring 2003
Discussion 2
Week of February 2nd
5 problems - solutions
1. Give the addressing mode and the effective address for each of the instructions. Use the instruction
LEAS to verify your answer for the indexed instructions. For each indexed instruction assume A=5,
B=20, x=1000 and y=2000 before the instruction is executed.
Instruction Address Mode Effective Address X or Y register after

staa 4,+y indexed, preincrement 2004 2004
staa $7,x+ indexed, postincrement 1000 1007
staa A,y indexed, register 2005 2000
staa D,y indexed, register 2520 2000
2. For each of the instructions find the corresponding object code for the instruction and determine the
amount of time it takes to execute the program. Assume that one cycle lasts 125 nanoseconds. Use
Tables from the CPU12 Reference Manual, instructions for timing and A-3 for postbyte.
Instruction Object Code # Cycles Time - ns

staa 4,-x 6A 2C 2 250
staa 4,y+ 6A 73 2 250
staa -4,y 6A 5C 2 250
3. List the contents of A and B for each step of the program.
prog equ $800

base equ $900
mary equ $950
org prog
ldaa jane
ldab jane+1
aba
ldd dave
addd dave+1
ldd base
aba
jane DB $56,$67
dave DW $89,$01,$23,72
org base
DB $12,$34
Solution
prog equ $800
base equ $900
mary equ $950
org prog
ldaa jane ; a = 56
ldab jane+1 ; b = 67
aba ; a = BD
ldd dave ; d = 0089
addd dave+1 ; 0089+8900 = 8989
ldd base ; d = 1234
aba ; 12 + 34 = 46
jane DB $56,$67
dave DW $89,$01,$23,72 ; loads memory with 0089000100230072
org base
DB $12,$34
4. Convert the decimal number -614 to hex. Check the answer by converting back to decimal.
16x30 = 480
16x8=128
614-608 = 6
0 ← 2 ← 38 ← 614 / 16
↓ ↓ ↓
2 6 6
FFF
-266
1. D99
+1
D9A
2*162 +6*161 + 6*160 = 512

+96
+6
614
5. Perform subtraction operations on the signed-hex numbers and determine values of NZVC bits.
Perform the subtraction by taking the complement of the 2nd operand and adding. Do not perform the
subtraction directly.
a) DE3F - E0F2
DE3F
1F0D
1
FD40 NZVC=1001
b) 8EB3 - 43D7
8EB3
BD28
1
4ADC NZVC=0010
c) BE – 34 (8-bit signed numbers)
BE
CB
1
8A NZVC=1000
EE 2361 Spring 2003
Discussion 3
Week of February 9th
For the program listing is given below:
1. In what memory locations is data1 stored? List the locations and contents of each
location.
$5000:5009 $5A,$29,$58,$90,$BE,$67,$4E,$2D,$EC,$34
2. In what memory locations is data2 stored? List the locations and contents of each
location.
$5010:5007 $C7,$E2,$E4,$5C,$AB,$47,$E4,$B6
3. How would you find out where data3 is stored?

Assemble the program, look for the data in memory near $800 and read the
memory locations.
4. What memory locations are read and what values get loaded in the X, Y, and A
registers by the instructions ldy, ldx and ldaa which are just before pshy?
Y = 2958 ; from $5001:5002
X = 90BE ; from data1+3, $5003:5004
A = E2 ; from data2+1, $5011
5. What are the contents of the Stack, SP and D after puld is executed?
D Y SP FE FF
2958 1000
pshy 2958 0FFE 29 58
puld 2958 2958 1000 29 58
6. What are contents of A, B, and NZVC after each of these instructions are executed
and what operand is being read from memory by each instruction?
operand A B NZVC
29 58
suba data3+2 56 D3 58 1001
addd data1 5A29 2D 81 0001
nega 2D D3 81 1001
nega
overflow – set only if A=$80
carry – set always unless A=$00
7. What is happening in these lines of code?
ldx #data1 ; start of data
ldy #ndata1 ; number of data
ldd #$0
std rslts1
std rslts1+2 ; clear memory locations
clc
clv ; initialize C & V
loop1: ldd rslts1 ;
addd !2,x+ ; need 2 because we are adding words
std rslts1 ; store addition in rslts1
dbne y,loop1 ; have all the data been added?
8. What value gets stored in rslts1?

$5A29
$5890
$B2B9
9. What value gets stored in rslts2?

$B2B2
PROGRAM
prog: equ $800
data1: equ $5000
ndata1: equ !2
data2: equ $5010
ndata2: equ !3
rslts1: equ $5030
org data1
db $5A,$29,$58,$90,$BE,$67
dw $4E2D,$EC34
org data2
fdb $C7E2,$E45C,$AB47
fcb $E4,$B6
org rslts1
ds !16
org prog
lds #$1000
ldy $5001
ldx data1+3
ldaa data2+1
pshy
puld
suba data3+2
addd data1
nega
; next part
ldx #data1
ldy #ndata1
ldd #$0
std rslts1
std rslts1+2
clc
clv
loop1: ldd rslts1
addd !2,x+
std rslts1
dbne y,loop1
tab
std rslts2
swi
data3: db $4,$A1,$56,$EF
rslts2: ds $4
EE 2361 Spring 2003
Discussion 4
Week of February 16th Solutions
1) Convert the binary fraction to decimal. Repeat using hex arithmetic.

0.1010 1000
=1*2-1 + 0*2-2 + 1*2-3 + 0*2-4 + 1*2-5
= 0.5 + 0.125 + 0.03125
= 0.65625
10*16-1 + 8*16-2
= 0.625 + 0.03125
= 0.65625
2) What will the register contents of the HC12 registers abxy after the following instructions are
executed.
a) IDIV where D=!734 and X=!21
before division
D=$02DE
X=$0015
after division
734/21 = 34.952
34x21 = 714
734 – 714 = remainder of 20 or $14
X=!34 = $0022
D=$0014
b) IDIV where D=!20 and X=!21

before division
D=$0014
X=$0015
after division
X=$0000 ; the result is less than 1 so X=0
D=$0014
c) IDIVS where D= -!734 and X= !21

D= -!34 = $FD22
X= $0015
after division registers should have,
X= complement of $22 = $FFDE
D= complement of $14 = $FFEC
(my simulator does not produce this result so I’m not positive it is accurate,
instead IDIVS treats the numerator as an unsigned number)
d) FDIV where D= !21 and X= !734

21/734 = .028610354
running a program gave the results,
X= $.0753
D= $0006
Use calculators and check the results.
X = $0753
= 0*16-1 + 7*16-2 + 5*16-3 + 3*16-4
= 0.02734375 + 0.001220703 + 0.000045776
= 0.028610229
734*0.028610229 =20.99990809
21 - 20.99990809 = 0.00009191 (remainder should be)
D=$0006
6*16-4 = 0.000091552 which is close and may be limited by calculator
Another run using D=!210 = $00D2 and X=!734 gave the result
X=$493E
= 4*16-1 + 9*16-2 + 3*16-3 + 14*16-4
= 0.25 + 0.03515625 + 0.000732421 + 0.000213623
= 0.286102294
734*0.286102294 = 209.9990838
210 - 209.9990838 = 0.0009162 (remainder should be)
D=$003C
= 0*16-1 + 0*16-2 + 3*16-3 + 12*16-4
= 0.000732421 + 0.000183105
= 0.000915526 which again is close
3) Write a program which checks unsigned integer and fractional division results. Using the
emul instruction.
PROG: EQU $0800

RAM: EQU $0900
ORG PROG
; integer divide
ldd NUM16
ldx DEN16
idiv
stx QUO16
std REM16
; fractional divide
ldd NUM16F
ldx DEN16F
fdiv
stx QUO16F
std REM16F
; check integer with emul
ldd DEN16
ldy QUO16
emul
addd REM16
subd NUM16
beq next
nop
next nop
; check fractional with emul
ldd DEN16F
ldy QUO16F
emul
addd REM16F
bcc cont ; branch if no carry to pass on to upper 16 bits of result
iny ; add carry from lower 16-bit sum
cont tfr y,d ; move high-order part of result to D
subd NUM16F ; compare with numerator
beq end
nop
end nop
ORG RAM
NUM16: DW !734
DEN16: DW !21
NUM16F: DW !21
DEN16F: DW !734
QUO16: ds !2
REM16: ds !2
QUO16F: ds !2
REM16F: ds !2
Monday, February 24
1. Assume that all maskable and non-maskable interrupts are enabled and suppose
the contents of memory at $FFF0:FFF7 are $0A, $80, $0A, $60, $0A, $40, $0A,
and $20. A partial table of interrupts is
Interrupt Vector
Priority Type
Source Address
5 SWI nonmaskable $FFF6:FFF7
6 XIRQ pin nonmaskable $FFF4:FFF5
7 IRQ pin maskable $FFF2:FFF3
Real Time
8 maskable $FFF0:FFF1
Interrupt
What information is pushed onto the stack and into what memory locations when
the swi instruction executes?
7FF7: CCR
7FF8: B
7FF9: A
7FFA: XH
7FFB: XL
7FFC: YH
7FFD: YL
7FFE: RTNH
7FFF: RTNL
8000:
Which, if any, bits are set or cleared in the CCR.

None set or cleared.
What is the address of the next instruction that will be executed?

$0A20
Suppose that during the execution of the swi instruction an IRQ interrupt arrives,
what happens?
Nothing SWI has higher priority
2. Write a complete M68HC12 program in assembly language for an interrupt

occurring on the external IRQ source. The interrupt vector is to be at
$FFF2:FFF3. When the interrupt occurs the ISR is to increment an 8-bit memory
location COUNT starting from $00. The foreground job is to be a spin loop SPIN
bra SPIN. Assume
a. The D-bug 12 monitor is not installed.

b. The interrupt vector is $E000.
c. RAM is available between $0800 and $0F00
; IRQ interrupt
PROG: EQU $800
STACK: EQU $8000
COUNT: EQU $900
org $FFF2
FDB IRQ_INT ; after assembly, (FFF2:FFF3) =
$E000
org PROG
lds #STACK
lda #$0
std COUNT
SPIN: bra SPIN
org $E000 ; object code created starting at

$E000,
IRQ_INT: nop ; A7
inc COUNT ; 72 09 00
rti ; 0B
3. Write a program to raise the ATD interrupt to the highest priority.
; HPRIO change
PROG: EQU $800
STACK: EQU $8000
HPRIO: EQU $1F
ATD: EQU $D2
org PROG
ldd #ATD
std HPRIO
nop
Monday, March 3
Solutions
1) An analog signal has a spectrum (frequency content) that includes frequencies as high as 4
KHz. What is the minimum ATD sampling rate adequate to allow reconstruction of the
signal? If the spectrum increases to 6 KHz what sampling rate is required.
8 KHz, 12 KHz
2) If the sampling rate of an ATD converter is 6.8 KHz what is the highest frequency an input
signal can contain. What if the sampling rate is increased to 7.6 KHz?
3.4 KHz, 3.8 KHz
3) An ATD converter system converts each analog sample to a 12-bit, unsigned binary value.
What is the resolution of the converter if VRH and VRL are 5 volts and 1.5 volts.
Resolution = (5 – 1.5) / (212) = 0.8545 mv
4) If a 14-bit ATD converter is used at a sampling frequency of 9 KHz how many bits of binary
data are generated per second?
9000 x 14 = 126,000
5) What is the dynamic range of an 8-bit ATD converter, 10-bit ATD converter, and 12-bit
ATD converter.
DR(dB) = 20 log(2b) = 20b log2 = 20b x 0.301 = 6.02b
8-bit DR = 44.24 dB 10-bit DR = 60.2 dB 12-bit DR = 72.24 dB
6) What can be done to prevent aliasing?

Sample at 2x highest freq in signal.
Limit signal bandwidth using a low pass filter and prevent freq > ½ sampling freq from
passing.
7) What is the highest frequency the HC12 can accurately sampled on a channel if it is programmed to
do a sequence of four conversions of channels 4-7, the P-clock frequency be 8 MHz, the prescaler is
set equal to 00101, SMP1=1, and SMP0=1.
Prescaler = 00101, Divisor = (5 + 1)( 2) = 12

ATD Clock = 8 MHz / 12 = 0.667 MHz
ATD Clock period = 1 / 0.667 MHz = 1.5 usec
SMP1 = 1 and SMP2 = 1
Total conversion ATD clocks = (16+16) ,
Total conversion time = 32 x 1.5 usec = 48 usec
Sampling freq = 1 / 48 usec = 20.833 KHz
Highest signal freq that can be sampled without distortion if continuous sampling was being
done on one channel = 20.811 KHz / 2 = 10.417 KHz
Given that 4 channels are being sampled the highest frequency = 10.417 / 4 = 2.6 KHz
Spring Semester 2003 Discussion Problem Set 7 Monday, March 10
1. For each of the signals fill in the table with values such that the sampling frequency will be
just high enough to accurately sample these signals (assume the P-clock is 8 MHz and that
only 1 channel is being sampled continuously):
Highest Signal SMP Lowest possible ATD Highest signal frequency Prescaler
Frequency KHz bits Clock frequency allowed at this setting bits
MHz
13.8 00 0.5 13.89 00111
Using ratios from the table,
41.7KHz x 0.667MHz / 2MHz = 13.9KHz
31.25KHz x 1.0MHz / 2MHz = 15.62KHz
55.5KHz x 0.5MHz / 2MHz = 13.75KHz,
Refining, using the clock period for 0.5MHz
1/ (18*2us) /2 = 13.89KHz highest frequency allowed in signal for accurate sampling
Looking closer there are 2 answers,
1 . = 1 .
18 clocks x 16 . 24 clocks x 12 .
8MHz 8MHz
2. Give the values of the bits in ATDCTL5 which will setup the following
a) single scan of the upper 4 channels 0001 0100
b) continuous scan of the lower 4 channels 0011 0000
c) continuous scan of the upper 4 channels 0011 0100
d) single scan of channel 2, using 4 conv. 0000 0010
e) single scan of channel 6, using 4 conv. 0000 0110
3. For each part of Problem 2 give the register(s) name(s) and location(s) where the result(s)
will be placed.
a) ADR0H = ch4, ADR1H = ch5, ADR2H = ch6, ADR3H = ch7
b) ADR0H = ch0, ADR1H = ch1, ADR2H = ch2, ADR3H = ch3
c) ADR0H = ch4, ADR1H = ch5, ADR2H = ch6, ADR3H = ch7
d) ADR0H = ch2, ADR1H = ch2, ADR2H = ch2, ADR3H = ch2
e) ADR0H = ch6, ADR1H = ch6, ADR2H = ch6, ADR3H = ch6
4. Write a program to set up an interrupt to occur when an 8-conversion sequence is completed

for input on channel 6. Assume the ATD has been turned on for more than 100us.
atdct2 equ $62
atdct5 equ $65
affc equ %01000000
ascie equ %00000010 ; enable interrupt
inict5 equ %01000110 ;8-conv, single ch, ch6
bset atdct2,affc
bset atdct2,ascie
ldaa #inict5
staa adtct5
5. Write a program to poll for completion of conversion of channel 3.
atdstat2 equ $67

loop: brclr atdstat2,$08,loop ; $08 = 0000 1000
Monday, March 24
1. For each part below assume that all maskable and non-maskable interrupts are enabled and
that the content of the HPRIO register is $F2. The ISR for an IRQ interrupt has the
following listing:
loc obj code ; enter the IRQ ISR

0820 8601 ldaa #BIT0
0822 5A21 staa KWIFD ; reset a flag
0824 0B rti ; return from the ISR
a) Where in memory is the vector for the IRQ interrupt and what should it be initialized to
for this ISR?
The vector is at $FFF2:FFF3 and should contain the address $0820.
b) Suppose that an IRQ interrupt occurs. If no other interrupts are pending when the
current instruction completes execution what information is pushed on the stack (you
don’t need to specify the order) and what bits, if any, are set or cleared in the CCR?
The 2 byte return address, Y, X, A, B, and CCR are put on the stack. The I bit in the
CCR is then set to 1.
c) As the IRQ interrupt service routine shown above is executing, a Real Time Interrupt is
generated. Describe what happens.
Since I=1 the Real Time Interrupt is ignored until the return to the main program.
d) As the IRQ interrupt service routine shown above is executing, an XIRQ interrupt is
Since XIRQ is a nonmaskable interrupt it is accepted, after the current instruction is

executed, the 2 byte return address, Y, X, A, B, and CCR are put on the stack, I and X
are set to 1, and control is transfered to the XIRQ ISR with starting address in
$FFF4:FFF5.
2. Suppose the ATD converter on the MC68HC812A4 is programmed to do a sequence of four

conversions of channels 4-7. Let the P-clock frequency be 8 MHz, the ATD-clock frequency be
2MHz, and assume the conversion time is 20 ATD clock periods.
a) What, if any, prescaling divisor is being used?
The prescaling divisor is 2 and the total divisor is 4.
b) What is the conversion time in microseconds?

Conversion time is (ATD clock period)(ATD clocks) = (0.5e-6)(20) = 10.0e-6 seconds or 10
microseconds.
c) What is the maximum signal frequency fmax on any input channel that can be converted
without aliasing errors ?
Note that conversion time is 10 microseconds for one channel. Since we need to sample
four channels the sample period for a channel is 4(10 microseconds) = 40
microseconds. The sample frequency is then fsamp = 1/(40e-6 seconds) = 25 kHz. Thus
fmax = fsamp/2 = 12.5 kHz.
d) If the full-scale input signal has a range of 0 to 4 volts what is the resolution (in
millivolts) of the conversion?
Resolution = 4/256 =1/64 volts or 1000/64 = 15.63 mV.
3. The ATD is setup to do continuously perform 8 conversions on channel 6.

a) What is the content of ATDCTL5? 0110 0110
b) Where will the result(s) will be placed? ADRxH = ch6 for x = 0 thru 7
4. Write a line of code to poll for completion of conversion of channel 2.

loop: brclr $67,$4,loop
5. Write one line of code to clear the flag associated with the result register for channel 2 and
the SCF flag.
ldaa $74 ; but the AFFC must be set = 1 to clear SCF also.
; if AFFC=0 then the SCF will be cleared automatically the next time ATDCTL5 is
written
Monday, March 31
1. A byte of data is located at RCVD_DATA in memory. The data represents a 7-bit ASCII
character with a parity bit in the MSB location. Assuming odd parity write a subroutine
PAR_CHK which will check the byte of data for correct parity. If parity is correct the
subroutine is to clear the C bit in the condition code register before it returns, if parity is
incorrect it will set the C bit.
Solution:
PAR_CHK: pshd
ldaa RCVD_DATA ; load data into A
ldab #$00 ; set B=0
LOOP: tsta ; is A=0?
beq CHECK ; if it is we are done counting
lsla ; otherwise get the next bit also shifts in a “o”
bcc LOOP ; is the bit 0?
incb ; it was 1!
bra LOOP
CHECK: clc ; set C=0
andb #$01 ; do we have an odd number in B?
bne DONE ; yes
sec ; no, C=1
DONE: puld
rts
2. SCI Serial ports

a) What registers do we normally initialize to use the SCI’s and what is intialized when
not using interrupts?
SCxBDH (2 bytes) – baud rate (use 16-bits by transferring from D register)
SCxCR1 – data length (mode), parity enable, parity type (and serial connections,
not covered in lecture)
SCxCR2 – transmit and receive enables
b) What flags are monitored?

SCIxSR1 – transmit data reg empty, transmit complete, receive data reg full, idle
c) What register is initialized to use interrupts?

SCxCR2
d) What causes the interrupts to be set?

Selected interrupts are enabled!!
Conditions that can set interrupts are,
transmit data register empty, TDRE
transmit complete, TC
receiver data register full, RDRF
idle set, IDLE
3. Write the missing code to use SC0 to transmit a character. Skip equates. Use binary
numbers for codes to set the control registers and check status register. Use register names
for registers that need to be read or written.
1 start, 8 data and 1 stop bit
odd parity
Character is in $903
B9600 EQU !52
bset ?????? ; TxRx enable

??
??
??
??
spin: brclr SC0SR1,??????,spin
ldaa ????
??
??
Solution:

bset SC0CR1,%00000011 ; parity on, odd parity
ldd #B9600
std SC0BDH
ldaa $903
staa SC0DRL
l
EE2361 - Introduction to Microcontrollers - Spring 2003
Name (printed) _____________________________
Signature: _____________________________
Student ID# _____________________________
1st Examination
CPU12 Reference Manual Required
Crib Notes
February 27, 2003
SOLUTIONS

• Circle or clearly label your final answers. Problems with conflicting answers will
receive no credit.
5 problems – 20 points each

1. Addressing modes
2. Conversions
3. Arithmetic
4. Register and memory contents
5. Coin program
1) For each of the instructions (not a sequence) fill in the table below (x=$1500).
Instruction Address Mode Effective Object Code # Cycles

Address
ldy $1907 Extended $1907 FD19 07 3
staa $4,x Constant indexed $1504 6A 04 2
staa $31 Direct $31 5A 31 2
staa $1,x+ Postincrement $1500 6A 30 2
2) Number conversion problems.
a) Convert the signed binary number, 11100101 to decimal. Give the decimal value contributed by
each bit; for example, 1*20 = 1.
11100101
00011010
+1
00011011
1*24 + 1*23 + 0*22 +1*21 + 1*20 = 16+8+2+1 = 27 → -27
b) Convert the following decimal number, -55 to binary. Show each stage of the conversion. The
binary number is a signed 8-bit number.
0← 1 ← 3 ← 6 ← 13 ← 27 ← 55 /2
↓ ↓ ↓ ↓ ↓ ↓
1 1 0 1 1 1
00110111 = 32+16+4+2+1= 55
11001000
+1
11001001
3) Perform the indicated 16-bit arithmetic operations on the signed-hex numbers and give the resulting
values of the condition code bits, NZVC.
a) 2DFE
+ 7B42
A940 1010
b) D3EC
- 2B0F
A8DD 1000
c) 38EB
- 793D
BFAE 1001
4) For the program below step through the program and fill out the table to give the contents of
registers and memory after each program step is executed. Fill in cells only as they change (do not
repeat the contents line-after-line).
prog: equ $800

data: equ $5000
rslts: equ $5004
A B X Y 5000 5001 5002 5003 5004 5005 5006
org data
fdb $C7E2 C7 E2
fcb $E4,$B6 E4 B6
org rslts
ds !2
org prog
lds #$1000
ldy $5002 E4B6
ldx data+1 E2E4
pshx
pshy
puld E4B6
staa rslts+1 E4
5) You have just won 9 coins (values in cents): !25,!10,!10,!25,!5,!5,!10,!25,!10 (use 2-bytes for each)
Write a program that will find the sum (16-bit) of the coin values and save the result in location
$930:931 and find the total number of 5-cent coins and store the number in a 1-byte in location
$940. Your program must include a loop to use in stepping through the coin values.
; Equates
; Data placed in memory
; Org program
; Initialize number of coins for coin counter
; Addition code
; Number of coins counter
; Loop to count coins
; Set up location for count
; Initialize count
; Initialize sum
; Value of 5 cents to compare
; Increment number of 5 cent coins
prog equ $800
data equ $900
datact equ !9
sum equ $930
number5 equ $940
value5 equ $942
org data
dw !25,!10,!10,!25,!5,!5,!10,!25,!10
org prog
ldd #!5
std value5
ldd #$0
staa number5
std sum
ldy #datact
ldx #data
loop nop
ldd $2,x+
cpd value5
bne continue
inc number5
continue addd sum
std sum
dey
bne loop
Scores
1. _______ (20 points)
2. _______ (20 points)
3. _______ (20 points)
4. _______ (20 points)
5. _______ (20 points)
Total ________ (100)
Evening 2361 HW 12 James Lamberg
05/01/03 #2485126
1. Determine the memory locations in the Fuzzy Robot program.

a) $6003
b) $603F
c) $6000
d) $6001
e) $6030
f) $603A
g) $6002
2. Fuzzy Robot Outputs
Fuzzy Inputs System

Output
Input Set Inputs VW W M S VS
1 Right $9A 0 0 $60 $A0 0
Left $6C 0 $40 $C0 0 0
Output $63
2 Right $9C 0 0 $40 $C0 0
Left $B9 0 0 0 $70 $90
Output $76
3 Right $63 0 $D0 $30 0 0
Left $43 $D0 $30 0 0 0
Output $74
3. Fuzzy Logic and Braking

a) Distance: Close, Middle, Far
Rate: Crawl, Trot, Gallop
b) Feathering, Light, Medium, Hard, Pedal_To_The_Floor
Rate\Distance Close Middle Far

Crawl Medium Light Feathering
Trot Hard Medium Light
Gallop Pedal_To_The_Floor Hard Medium
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/Encrypt.txt
;**********************
;
; Lab 3
; Crypto algorithm
; Jason Wachholz
; July 16,1998
;
;***********************
PROGRAM EQU $0800

INDEXES EQU $0AFE
KEY_TABLE EQU $0B00
STRING EQU $0A50
MASK EQU $20
org INDEXES
;**********************
; Variables Declared
Xindex ds 1 ;declare One Byte at $AFE for Xindex
Yindex ds 1 ;declare One Byte at $AFF for Yindex
org STRING
;**********************
; String initalization
plain_text db 'encryption'
cipher_text ds $20
decode_text ds $20
org PROGRAM
;***************
; INIT Variables
lds #$0AFD ;set stackpointer
;***************
; MAIN Program

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/Encrypt.txt (1 of 3) [06Nov07 22:48:22 ]

perm: psha ;put counter on the stack; permutate key_table 255 times
bne perm ;branch to perm 255 times, then encrypt the string
ldx #plain_text ;Load Index Register X; set X index register to location of plain_text
ldy #cipher_text ;Load Index Register Y; set Y index register to location to store cipher_text
encrypt: psha ;Push accum A (psha) onto the stack;
stab A,Y ;Store accum B (stab) in cipher_text memory
bne encrypt ;Branch not equal (bne); stops encrypt loop when counter is equal to MASK.
;
;
;
; YOUR DECRYPTION ROUTINE GOES HERE...
; The code above has been a routine that initialized the KEY_TABLE and encrypted the
; data located and plain_text and stored the encrypted result in cipher_text.
; Your code should decrypt the text located in the cipher_text memory area
; and store it in the decode_text memory area.
;
;
;
nop ;leave instruction for breakpoint
;
;
; subroutines follow
;
;
init_array: movw #$0000,INDEXES ;Move word (movw); clear Xindex, Yindex

ldaa #$00 ;Load accum A (ldaa); init counter variable
ldx #KEY_TABLE ;Load Idex Register X (ldx) init X = key_table

;for (a = 0; a < 256; a++) key_table[a] = a;

inca ;A++
bne init_loop ;8 bit auto mod 256, fall through when A = 0
get_key: ;get_key is a destructive routine of accumulators A:B

;assumes global definition of Xindex, Yindex, and INDEXES
ldd INDEXES ;load accum D (ldd); loads A with Xindex; B with Yindex
inca ;add 1 to Xindex (if overflow mods); x=(x+1)%256
addb A,X ;add key_table[x] to b (if overflow mods); y=(y+key_table[x])%256
;prepare to swap
;swap
aba ;accum A <- (A + B); (key_table[x] + key_table[y])%256

ldab A,X ;accum B <- index[accum A]; key_table[A]
clra ;clear accum A
nop ;breakpoint to stop program

end

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/EX4-7.txt
; ex4-7.asm
; Block memory copy program
;
; The EQU mnemonic is an assembler directive which defines

; a variable and assigns it a value.
; An example is; PROGRAM EQU $800
; During the assembly process everytime PROGRAM is used the
; compiler knows to use $800
; Space for all EQU directives
PROGRAM EQU $800

LISTOLD EQU $A00
LISTNEW EQU $B00
PTR1 EQU $900
PTR2 EQU $902
; The program
org PROGRAM ; Another assembler mnemonic it

; lets the compiler know to start
; assembling at address PROGRAM
LDX #$A00 ;Load Index Register X, Load pointer 1

STX $900 ;Store Index Register X, Store pointer 1
LDX #$B00 ;Load Index Register X, Load pointer 2
START LDX $900 ;Load Index Register X, Get pointer 1
LDAA 0,X ;Load accum A, Get data at X into A
INX ;Increment Index Reg. X, Update pointer 1
LDX $902 ;Load Index Register X, Get pointer 2
STAA 0,X ;Store accum A, Store date in new table
INX ;Increment X, Update pointer 2
BRA START ;Branch Unconditional, Loop back for next byte
nop ;no operation, typically used for end breakpoint

end ;Another assembler mnemonic letting
;the compiler know it is the end of
;the program
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/EX4-7.txt [06Nov07 22:48:23 ]

EXAM II
November 16, 2001
Fall Semester 2001 - Prof. Thomas Posbergh

(Closed book, closed notes, no calculators)
This exam consists of 5 problems. Each problem is worth 20 points. You should read
through the problems before you begin. You should clearly identify your answers to each
part of the problem and show how you arrived at your solution. Additional blank pages
can be found at the end of the exam.
Problem 1._______/20
2._______/20
3._______/20
4._______/20
5._______/20
Total Score ________/100

1. (20 points) Assume that an asynchronous serial communications channel uses 1 start bit, 8 data bits, 1 parity bit,
and 1 stop bit so there are a total of 11 bits per frame.
(a) If the bit time is 1/22000 seconds = 45.45 microseconds what is the baud rate in bits/second? Calculate the
frame time (in milliseconds) and the number of frames per second.
(b) If the system is configured for odd parity, determine the correct value of the parity bit for each of the
following 8-bit data words: 10010100, 10101010.
(c) Assuming that the serial communications interface SCI0 on the 68HC12 has been properly initialized. Data
must be written to which register to initiate data transmission? Give the name and address of this 8-bit
register.
2. (20 points) Consider the following sequence of instructions:
ldaa #$48
tfr a,y
ldaa #$F6
tfr a,d
emuls
(a) Assuming that this represents signed integer multiplication, give the decimal values of the two
operands and calculate the decimal value of the product.
(b) What are the contents (in hex) of Y and D just prior to the execution of the emuls instruction?
(c) What are the contents (in hex) of Y and D immediately after the execution of the emuls instruction?
(d) Assuming that the two numbers are fractions what is the 16-bit rounded approximation (in hex) to
the result?
3. (20 points) Consider the following C-code:
for (i=0; i<4, i++) {

result[i]=2*(i+1);
}
Implement this in assembly code. Assume that array result is a contiguous sequence of memory
locations, with 8-bit integer values for each element, beginning at address RESULT.
4. (20 points) Suppose the ATD converter on the MC68HC812A4 is programmed to do a sequence of four
conversions of channels 4-7. Let the P-clock frequency be 8 MHz, the ATD-clock frequency be 4 MHz, and
assume the conversion time is 20 ATD clock periods.
(a) What, if any, prescaling divisor is being used?
(b) What is the conversion time in microseconds?
(c) Ignoring aperture time effects, what is the maximum signal frequency fmax on any input channel that can be
converted without aliasing errors ?
(d) If the full-scale input signal has a range of 0 to 4 volts what is the resolution (in millivolts) of the
conversion? (you may leave your answer as a fraction.)
5. (20 points) For each part below assume that all maskable and non-maskable interrupts are enabled
and that the content of the HPRIO register is $F0. The ISR for an IRQ interrupt has the following
listing:
IRQ_ISR: ; enter the IRQ ISR

0820 8601 ldaa #BIT0
0822 5A21 staa KWIFD ; reset a flag
0824 0B rti ; return from the ISR
(a) Where in memory is the vector for the IRQ interrupt and what should it be initialized to for this
ISR?
(b) Suppose that an IRQ interrupt occurs. If no other interrupts are pending when the current
instruction completes execution what information is pushed on the stack (you don’t need to
specify the order) and what bits, if any, are set or cleared in the CCR?
(c) As the IRQ interrupt service routine shown above is executing, a Real Time Interrupt is
(d) As the IRQ interrupt service routine shown above is executing, an XIRQ interrupt is generated.
Describe what happens.
Summary of Selected Instructions
Opcode Operand Symbolic Operation X I Z V

C
aba A + B → A c c c c
adca A + (M) + C → A c c c c
adcb B + (M) + C → B c c c c
adda A + (M) → A c c c c
addb B + (M) → B c c c c
addd A:B + (M:M+1) → A:B c c c c

beq branch if Z=1 - - - -
bne branch if Z=0 - - - -
bmi branch if N=1 - - - -
bpl branch if N=0 - - - -
bvs branch if V=1 - - - -
bvc branch if V=0 - - - -
bita test bits in A, (A)•(M) c c 0 -
cmpa A - (M) c c c c
cmpb B - (M) c c c c
cpx X - (M:M+1) c c c c
dbne reg - 1 → reg, branch if not 0 - - - -
decb B - 1 → B c c c -
inca A + 1 → A c c c -
ldaa (M) → A c c 0 -
ldab (M) → B c c 0 -
ldd (M:M+1) → A:B c c 0 -

leax EA → X - - - -
ldx (M:M+1) → X c c 0 -
ldy (M:M+1) → Y c c 0 -
movb (M1) → (M2) c c 0 -
staa A → (M) c c 0 -
stab B → (M) c c 0 -
EE2361 Exam I page ___of ___
EE2361 - Introduction to Microcontrollers - Spring 2003
Name (printed) _____________________________
Signature: _____________________________
Student ID# _____________________________
2nd Examination, April 17 – 70 minutes

Instruction Reference Manual & Notes
SOLUTIONS

• Circle or clearly label your final answers. Problems with conflicting answers will receive no
credit.
4 problems - 25 points each

1. Timer
2. ATD
3. Serial Port
4. Interrupts
For the code writing problems, do the following:

a) Skip the equates.
b) Use register names (not hex locations) in the code.
c) Include ORG statements for Program and DS statements for Data.
d) Skip setting up the STACK.
e) Use binary numbers (not hex) in the code to perform functions such as set/clear control bits, clear
flags and check for flag setting; for example,
ldaa #%00010011
staa ATDCTL2
bset ATDCTL2, %11100101
f) Include a comment for EACH line of code. NO CREDIT will be given for code without
comments. This will improve your opportunity to get partial credit in case of errors.
1) Write a single program that will perform the following actions when a signal input on pin PT0 falls
from “1” to “0”.
• Initialize the timer including setting the prescaler to divide MCLK (8 MHz) by 8.
• Detect the falling edge on PT0.
• After 1.2ms generate a “1” on PT1.
• Then after 5ms generate a “0” on PT1
Channel 0
(input)
1.2 ms
5 ms
Channel 1
(output)
ORG $900
COUNT ds !2
ORG PROG
bset TMSK2,%00000011 ; divide MCLK by 8
bset TCTL4,%00000010 ; initialize IC0 to catch falling edge
bclr TCTL4,%00000001 ; initialize IC0 to catch falling edge
bclr TIOS,%00000001 ; configure TP0 for Input
bset TIOS,%00000010 ; configure TP1 for Output
bset TSCR,%10000000 ; enable the timer system
bset TFLG1,%00000001 ; clear IC0 flag
SPIN1 brclr TFLG1,%00000001,SPIN1 ; Wait for rising edge
ldd TC0 ; Get the count that was latched
addd #!1200 ; add 1.2ms to COUNT
std TC1 ; store COUNT+1.2ms
bset TCTL2,%00001100 ; Initialize IC1 to generate a “1”
SPIN2 brclr TFLG1,%00000010,SPIN2 ; wait for COUNT+1.2ms
ldd TC1 ; get COUNT+1.2ms
addd #!5000 ; add 5ms to COUNT
std TC1 ; store COUNT+1.2ms+5ms
bclr TCTL2,%00000100 ; Initialize IC1 to generate a “0”, OM1 =1
SPIN3 brclr TFLG1,%00000010,SPIN3 ; wait for COUNT+1.2ms+5ms
2) ATD questions
a) The resolution of an ATD converter must be at least 2 mv. The voltage levels range from 1.6v to
4v. What is the minimum number of bits needed in the ATD to convert this range of input
signal?
2400 mv => 1200 steps => 11 bits
b) Give the values of the bits in ATDCTL5 which will initialize the ATD to perform a continuous
scan of the lower 4 channels.
0011 0000
c) Give the register names where the conversion results produced by the ATD in Problem 2b will
be placed.
ADR0H
ADR1H
ADR2H
ADR3H
d) If the HC12 ATD is initialized to sample 4 channels, using a 0.5 MHz ATD clock and a 20 total
conversion periods. What is the maximum signal frequency on any of the channels that can be
sampled without distortion.
0.5 MHz clock => 2 usec period

Total conversion time = 20 x 2 usec = 40 usec
Sampling freq = 1 / 40 usec = 25 KHz
Signal freq 1 channel = 12.5 KHz
4 channels => 12.5 KHz / 4 = 3.125 KHz
e) What ATD register causes the conversion process to be started when information is stored in it?
ATDCTL5
3) The output of SC0 is connected to the input of SC1 and the output of SC1 has been connected to the
input of SC0. Write a program that will continuously send a character back and forth between
SC0 and SC1. The MCLK frequency is 8 MHz.
• Label the character transmitted and received by SC0 as CHAR0.
• Reserve memory for CHAR0 at location $900.
• Label the character transmitted and received by SC1 as CHAR1.
• Reserve memory for CHAR1 after CHAR0.
• Start with the character $E for the first transmission.
• Start the transmission process with $E stored into the appropriate register in SC0.
• Store the characters received by SC1 in CHAR1 and by SC0 in CHAR0.
• After storing, use the instruction rola to rotate the character after each reception at each
serial port before sending it back to the other port.
• Use polling to trigger transmit and receive.
• Initialize the serial ports to function with,
Even parity
8-bit data
Baud rate equal to 38400
org $900 ; location of data

CHAR0 ds !1 ; location for CHAR0
CHAR1 ds !1 ; location for CHAR1
org PROG ; start of program code
bset SC0CR1,%00000010 ; parity on
bclr SC0CR1,%00000001 ; even parity
bset SC1CR1,%00000010 ; parity on
bclr SC1CR1,%00000001 ; even parity
ldd #!13 ; BR divisor for 38400
std SC0BDH ; setup SC0 data rate
std SC1BDH ; setup SC1 data rate
ldaa #$E ; initial character to send
staa CHAR0 ; initialize the character to send
ldaa CHAR0 ; prepare to send the character
SPIN1 brclr SC0SR1,%10000000,SPIN1 ; wait for TDRE flag of SC0
staa SC0DRL ; transmit using SC0
SPIN2 brclr SC1SR1,%00100000,SPIN2 ; wait for RDRF flag in SC1
ldaa SC1DRL ; read character received by SC1
staa CHAR1 ; store the character received by SC1
rola ; rotate the character
SPIN3 brclr SC1SR1,%10000000,SPIN3 ; wait for TDRE flag of SC1
staa SC1DRL ; transmit using SC1
SPIN4 brclr SC0SR1,%00100000,SPIN4 ; wait for RDRF flag in SC0
ldaa SC0DRL ; read character received by SC0
staa CHAR0 ; store the character received by SC0
rola ; rotate the character
bra SPIN1 ; return to top of loop
4) An ISR is being developed for the Real Time Interrupt (see table below). The subroutine is,
ISRmisc: ldd #$2

addd #$2
a) Write a few lines of code which will store the ISR in memory at location $6000.
ORG $6000
ISRmisc: ldd #$2
addd #$2
b) Write a few lines of code to store the interrupt vector in memory.
ldd #$6000
std $FFF0
c) What would you do to raise this ISR to the highest level?
Store the Real Time Interrupt priority code in HPRIO
d) What information is pushed onto the stack when the interrupt occurs?
A, B, X, Y, PC, CC
e) Which of the interrupts in the table below are maskable?
IRQ pin
Real Time Interrupt
Interrupt Source Vector Address

SWI $FFF6:FFF7
XIRQ pin $FFF4:FFF5
IRQ pin $FFF2:FFF3
Real Time Interrupt $FFF0:FFF1
Scores
1. _______ (25 points)
2. _______ (25 points)
3. _______ (25 points)
4. _______ (25 points)
Total ________ (100)

FINAL EXAM
December 21, 2001
Fall Semester 2001 - Prof. Thomas Posbergh

(Closed book, closed notes, no calculators)
This exam consists of 6 problems worth 100 points. The problems vary as to degree of
difficulty, number of parts, and point value. You should read through the problems
before you begin. You should clearly identify your answers to each part of a problem and
show how you arrived at your solution. Additional blank pages can be found at the end
of the exam.
Problem 1._______/16
2._______/16
3._______/18
4._______/14
5._______/18
6._______/18
Total Score ________/100

1. (16 points) Assume the contents of 8 sequential memory locations beginning at $0A00 are $0A, $06,
$0A, $05, $0A, $02, $0A, and $01. Assume also that the content of the X index register is $0A00, the
content of the Y index register is $0A02, and the content of the D accumulator is $0402. Give the
contents of those same 8 memory locations and the contents of the X andY registers and the D
accumulator after the following code has executed:
dec [4,y]
inc [2,x]
ldaa 2,-y
ldab 3,x+
std 2,+y
2. (16 points) The following code is used to multiply an unsigned 8-bit fractional number NUM8 with
a 16-bit unsigned integer NUM16:
clra
ldy #NUM16
ldab #NUM8
emul
(a) If NUM8 is the hex fraction .8016 and NUM16 is hex integer B52116 what are the contents of Y
and D immediately after the emul instruction executes?
(b) What is a 16-bit rounded approximation (in hex) to the result in (a)?
(c ) Add additional instructions following the code above to compute the 16-bit rounded
approximation and leave the result in D. This code should work for all possible values of NUM8
and NUM16.
3. (18 points) There are 8 LED's connected to PORT A. The LED's are driven through inverters such
that (for n=0,1,…7) if a 0 is written to PAn (Port A, bit n) then LED number n will light, if a 1 is
written the LED is dark. The schematic shown in the figure below is for output pin n,
Figure 3.1. Schematic for Port A, pin number n.
Write a program to light the LEDs in the following sequence 0, 01, 012 , 0123 , 01234, ...01234567
and then turn them off in reverse 01234567, 0123456, 012345, ...,01, 0 and all off.
4. (14 points) Recall that the timer system in the 68HC12 is based on a free-running 16-bit counter TCNT.
In addition, there are 8, 16-bit registers TC0-TC7, which are used for input capture and output compare.
Assume in the following the timer is enabled in a system with an 8-MHz M-clock. The timer is
prescaled by 8.
(a) What is the frequency in MHz at which the timer is incremented? How long does it take to cycle
through all possible values of TCNT?
(b) Where is the timer overflow flag located (give the bit and register), what event causes it to be set,
how is it cleared?
(c) Summarize in a sentence or two the basic operation of the output compare feature of the timer.
(d) Summarize in a sentence or two the basic operation of the input capture feature of the timer.
5. (18 points) For a fuzzy logic inference system the inputs are pressure and speed. Pressure can be
LOW or HIGH, speed can be SLOW, MEDIUM, or FAST. The single output can be UP or DOWN.
The rule matrix for this system is given as follows:
HIGH UP DOWN DOWN

LOW UP UP DOWN
SLOW MEDIUM FAST
Table 5.1. Rule Matrix for Problem 5
(a) How many bytes are needed in a 68HC12 knowledgebase for this set of input trapezoids, rules, and
output singletons?
(b) If after fuzzification the truth values of the input labels are HIGH = $20, LOW = $DF, SLOW =
$7F, MEDIUM = $80, and FAST = $00 use the rule matrix to determine the values of the output
labels UP and DOWN.
(c) For the output defuzzification UP is a singleton membership function at $A0 and DOWN is a
singleton membership function at $50. Compute the value of the "crisp" output. What 68HC12
instructions are used to compute it?
6. (12 points) The following subroutine SUM has been written to implement an accumulate
function. It will sum a sequence of 16-bit signed integers. The address of the first integer is
passed to the subroutine in the X register and the number of integers in the Y register.
SUM: ldd #$0000 ; clear D

LOOP:addd 2,x+ ; accumulate
dbne y,LOOP ; done?
DONE:rts
(a) For the sequence of 3 16-bit integers $F020, $2100, and $7003 what value would be returned
in accumulator D from this subroutine?
(b) Modify the subroutine to saturate with the maximum or mimimum values if the sum in D is
greater than the maximum value or less than the minimum value of possible signed integers
in D..
(c) For the sequence of 3 16-bit integers $F020, $2100, and $7003 what value would be
returned in accumulator D from this subroutine?
Summary of Selected Instructions
Opcode Symbolic Operation N Z V C
aba A + B → A c c c c
adca A + (M) + C → A c c c c
adcb B + (M) + C → B c c c c
adda A + (M) → A c c c c
addb B + (M) → B c c c c
addd A:B + (M:M+1) → A:B c c c c
beq branch if Z=1 - - - -
bne branch if Z=0 - - - -
bmi branch if N=1 - - - -
bpl branch if N=0 - - - -
bvs branch if V=1 - - - -
bvc branch if V=0 - - - -
bita test bits in A, (A)•(M) c c 0 -
brclr branch if (M)•(Mask) = 0 - - - -
clc clear carry - - - 0
cmpa A - (M) c c c c
cmpb B - (M) c c c c
cpx X - (M:M+1) c c c c
dbne reg - 1 → reg, branch if not 0 - - - -
decb B - 1 → B c c c -
ediv Y:D ÷ X → Y, Remainder → D c c c c
inca A + 1 → A c c c -
jsr jump to subroutine - - - -
ldaa (M) → A c c 0 -
ldab (M) → B c c 0 -
ldd (M:M+1) → A:B c c 0 -
leax EA → X - - - -
ldx (M:M+1) → X c c 0 -
ldy (M:M+1) → Y c c 0 -
lsla logical shift left A c c c c
lsld logical shift left D c c c c
lsra logical shift right A c c c c
lsrd logical shift right D c c c c
movb (M1) → (M2) c c 0 -
rola roll left A c c c c
rora roll right A c c c c
rts return from subroutine - - - -
rti return from interrupt c c c c
sec set carry - - - 0
staa A → (M) c c 0 -
stab B → (M) c c 0 -
std D → (M:M+1) c c 0 -
EE2361 Exam I page
___of ___
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; James Lamberg #2485126
; Evening 2361
; Homework #10
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<><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 1
; Using Input Capture on Channel 0
; the most recent value of the calculated pulse width will be in
pulse_width
; the most recent value of the calculated separation will be in the
variable memory location separation
; the most recent value of the calculated period will be in the variable
memory location period
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Register Definitions
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080

CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Sections
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000
; Declare Variables, there are 4 edges in each set of 2 pulses

first_edge ds 2 ; stores value of counter at first edge
old_first ds 2 ; stores counter value at previous first
edge
second_edge ds 2 ; stores value of counter at second edge
third_edge ds 2 ; stores value of counter at third edge
fourth edge ds 2 ; stores value of counter at fourth edge
pulse_width ds 2 ; stores calculated pulse width
separation ds 2 ; stores pulse separation
period ds 2 ; stores period
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Timer Counter Initialization for Input Capture
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
movb #$0,TIOS ; sets all channels for input capture

movb #$0,CFORC ; disables Timer Compare Force
movb #$0,OC7M ; sets TIMPORT pins as input
movb #$80,TSCR ; sets TEN bit (timer enable)
movb #$03,TCTL4 ; enables input capture on ANY EDGE on channel 0
movb #$0,TMSK1 ; disables interrupts
movb #$03,TMSK2 ; sets prescaler-->8, so we can measure with 1us
accuracy
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Main Code for Problem 1
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
wait_first: ; waiting for first edge

ldaa TFLG1 ; check the timer flag register 1 for input
anda #$01 ; clears all except (maybe) Channel 0 flag
beq wait_first ; keep waiting for first edge if C0F isn't
set
ldx TCNT ; loads present value of TCNT
ldy first_edge ; loads Y with counter value at previous
first edge
sty old_first ; moves Y to old_first
stx first_edge ; stores TCNT to first_edge
movw #$ff,TFLG1 ; writing 1 clears flags in this register
; calculate period
ldd first_edge
subd old_first ; subtracts first_edge - old_first
andcc #$01 ; clears all CCR bits except (maybe) carry
bit
beq store_period ; if carry bit is set, counter wrapped
around
; between detecting old_first and first
edges
; counter period is 1us and period is about
18ms,
; there is only approx 18000 counter clocks
between
; the two present and previous first_edge.
; therefore, the counter could only have
rolled over
; once (at most) between the two
first_edge's
ldd #$ff
subd old_first ; subtracts $FF - old_first
addd first_edge ; this is the period
store_period: std period ; stores calculated period
wait_second: ; waiting for second edge

beq wait_second ; keep waiting for second edge if C0F isn't
set
stx second_edge ; stores TCNT to second_edge
; calculate pulse width

ldd second_edge
subd first_edge ; subtracts time of second edge from time
of first edge
andcc #$01 ; clears all except (maybe) the C-bit in
the CCR
beq store_width ; if Carry bit is not set, skip to
store_width
; if carry bit is not set, counter wrapped
around
; between detecting the first and second
edges
ldd #$ff
subd first_edge ; calculates $FF-first_edge
addd second_edge ; this is the pulse width
store_width: std pulse_width ; stores calculated pulse width
wait_third: ; waiting for third edge

beq wait_third ; keep waiting for third edge if C0F isn't
set
stx third_edge ; stores TCNT to third_edge
; calculate separation
ldd third_edge
subd second_edge ; calculates time between second
and third edge --separation
andcc #$01 ; clears all except (maybe) C bit
of CCR
beq store_separation ; if carry bit is set, counter
wrapped around
; between detecting the second and
third edges
ldd #$ff
subd second_edge ; calculates $FF-second_edge
addd third_edge ; this is separation
store_separation: std separation ; stores calculated separation
wait_fourth: ; waiting for fourth edge

beq wait_fourth ; keep waiting for fourth edge if C0F isn't
set
stx fourth_edge ; stores TCNT to fourth_edge
bra wait_first
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 2
; Using Output Compare on Channel 0
; pulse width will be 100us, separation will be 500us
; period will me 18ms
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080

CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL2 equ $0089
TMSK1 equ $008C
TMSK2 equ $008D
TCNT equ $0085
TC0H equ $0090
TFLG1 equ $008E
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Timer Counter Initialization for Output Compare
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000
movb #$ff,TIOS ; set all channels for output compare

movb #$0,CFORC ; no force output compare
movb #$80,TSCR ; enable counter-timer
movb #$01,TCTL2 ; sets channel 0 to toggle on output
compare
movb #$0,TMSK1 ; disable interrupts
movb #$03,TMSK2 ; sets prescaler divisor to 8--
>counter=1MHz, period=1us
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
first: ; sets counter to cycle for 17.3ms and then

; generate first edge (first of four edges in each
sequence)
ldd TCNT ; loads current value of counter
addd #$4394 ; adds !17300 to D
std TC0H ; sets counter to do output compare after 17300
counter cycles
; since the period is 1us, this corresponds to
17.3ms
; which is the time between sets of pulses (period
= 18ms)
wait_1: ; waits for first edge
ldaa TFLG1 ; loads flag register
anda #$01 ; clears all bits except (maybe) C0F
beq wait_1 ; if C0F is not set, keep waiting
movb #$01,TFLG1 ; writing 1 clears the C0F bit
second: ; generates second edge
addd #!100 ; adds 100 to D
counter cycles(100us)
wait_2: ; waits for second edge
third: ; generates third edge
ldd TCNT ; loads current counter value
addd #!500 ; add 500 to D
cycles (500us)
wait_3: ; waits for third edge
fourth: ; generates fourth edge
cycles (100us)
wait_4: ; waits for fourth edge
bra first
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
<><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 3
; Input Capture on Channel 0 w/ Wave from Problem 1
; do same calculations as in problem 1
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080
CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
TCTL2 equ $0089
TC0H equ $0090
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Section
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $800
; initialize timer channel 0 for input capture with interrupts

movb #$0,TIOS ; set all channels for input capture
movb #$0,DFORC ; disables force timer counter
movb #$0,OC7M ; sets TIMPORT pin input
movb #$80,TSCR ; enable counter
movb #$03,TCTL4 ; sets channel 0 for input capture on any edge
movb #$01,TMSK1 ; enable interrupts on channel 0
movb #$03,TMSK2 ; set prescaler value to 8-->period=1us
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>

old_first ds 2 ; stores counter value at previous first
edge
which_edge ds 1 ; stores vale (1,2,3,4), indicating which
edge should arrive next
movb #$01,which_edge ; initialize which_edge to wait for 1st
edge
movw #$1000,$FFEE ; puts address of ISR in timer channel 0

place in IVT
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000 ; ISR

ISR_1: ldx TCNT ; load value of counter at time of interrupt
movb #$01,TFLG1 ; writing 1 clears the channel 0 flag
ldaa which_edge ; loads variable indicating which edge was detected
cmpa #$01
beq first ; if which_edge is 1, detected edge was first one
cmpa #$02
beq second ; if which_edge is 2, detected edge was second one
cmpa #$03
beq third ; if which_edge is 3, detected edge was third one
cmpa #$04
beq fourth ; if which_edge is 4, detected edge was fourth one
first: movb #$02,which_edge ; increment which_edge

ldd first_edge ; load previous value of first edge
std old_first ; move previous value to first edge
stx first_edge ; store new first edge in x
; now calculate the period
ldd first_edge ; load first edge
subd old_first ; subtract first_edge-old_first
andcc #$01 ; clears all CCR bits except (maybe) the
carry flag
beq store_period ; if carry bit is set, counter wrapped around
; between detecting old_first and first
edges
; counter period is 1us and period is about

18ms,
; there is only approx 18000 counter clocks
between
; therefore, the counter could only have
rolled over
; once (at most) between the two
first_edge's
ldd #$ff
subd old_first ; subtracts $FF-old_first

rti
second: movb #$03,which_edge ; increment which_edge

stx second_edge ; store new value of second edge
ldd second_edge
subd first_edge ; subtracts time of second edge from time
of first edge
andcc #$01 ; clears all except (maybe) the C-bit in
the CCR
beq store_width ; if Carry bit is not set, skip to
store_width
; if carry bit is not set, counter wrapped
around
; between detecting the first and second
edges
ldd #$ff

rti
third: movb #$04,which_edge ; increment which_edge

stx third_edge ; store new value of third edge
ldd third_edge
subd second_edge ; calculates time between second
and third edge --separation
andcc #$01 ; clears all except (maybe) C bit
of CCR
beq store_separation ; if carry bit is set, counter
wrapped around
; between detecting the second and
third edges
ldd #$ff

rti
fourth: movb #$01,which_edge ; reset which_edge to 1

stx fourth_edge ; stores new value of fourth edge
rti
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 4
; Output Compare on Channel 0, Same Wave as Problem 2
; output same wave as in problem 2, but use interrupts
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080
CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
TCTL2 equ $0089
TC0H equ $0090
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Section
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $800
which_edge ds 1 ; will store a value (1-4) indicating which

edge should be generated next
movb #$01,which_edge ; initialize which_edge to 1
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>

movb #$01,TCTL2 ; sets channel 0 to toggle on output
compare
movb #$01,TMSK1 ; enable channel 0 interrupts
movb #$03,TMSK2 ; sets prescaler divisor to 8--
>counter=1MHz, period=1us
movw #$1000,$FFEE ; puts address of ISR in timer channel 0

place in IVT
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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000
ISR_2: ldd TCNT
movb #$01,TFLG1
ldx which_edge ; loads variable indicating which edge to generate
cpx #$01
beq first ; if which_edge is 1, generate first edge
cpx #$02
beq second ; if which_edge is 2, generate second edge
cpx #$03
beq third ; if which_edge is 3, generate third edge
cpx #$04
beq fourth ; if which_edge is 4, generate fourth edge

addd #!17300 ; add 17300 to D
std TC0H ; store TCNT + 17300 in the compare
register
; waits 17.3ms before generating first edge
rti

std TC0H ; store TCNT + 100 in compare register
; waits 100us for pule width before
generating second edge
rti

; waits 500us for separation before
rti
fourth: movb #$01,which_edge ; increment which_edge

; waits 100us for pulse width before
rti
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/hw10.txt
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Evening 2361
; Homework #10
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 1
; Using Input Capture on Channel 0
; the most recent value of the calculated pulse width will be in pulse_width
; the most recent value of the calculated separation will be in the variable memory location separation
; the most recent value of the calculated period will be in the variable memory location period
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080

CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Sections
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000
; Declare Variables, there are 4 edges in each set of 2 pulses

old_first ds 2 ; stores counter value at previous first edge
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/hw10.txt (1 of 11) [06Nov07 22:48:27 ]

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;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
movb #$0,TIOS ; sets all channels for input capture

movb #$0,CFORC ; disables Timer Compare Force
movb #$80,TSCR ; sets TEN bit (timer enable)
movb #$03,TCTL4 ; enables input capture on ANY EDGE on channel 0
movb #$0,TMSK1 ; disables interrupts
movb #$03,TMSK2 ; sets prescaler-->8, so we can measure with 1us accuracy
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
wait_first: ; waiting for first edge

beq wait_first ; keep waiting for first edge if C0F isn't set
ldy first_edge ; loads Y with counter value at previous first edge
sty old_first ; moves Y to old_first
stx first_edge ; stores TCNT to first_edge
; calculate period
ldd first_edge
subd old_first ; subtracts first_edge - old_first
andcc #$01 ; clears all CCR bits except (maybe) carry bit
; between detecting old_first and first edges
; counter period is 1us and period is about 18ms,
; there is only approx 18000 counter clocks between
; therefore, the counter could only have rolled over
; once (at most) between the two first_edge's
ldd #$ff
subd old_first ; subtracts $FF - old_first
wait_second: ; waiting for second edge

beq wait_second ; keep waiting for second edge if C0F isn't set
stx second_edge ; stores TCNT to second_edge

ldd second_edge
subd first_edge ; subtracts time of second edge from time of first edge
andcc #$01 ; clears all except (maybe) the C-bit in the CCR
beq store_width ; if Carry bit is not set, skip to store_width
; if carry bit is not set, counter wrapped around
; between detecting the first and second edges
ldd #$ff
wait_third: ; waiting for third edge

beq wait_third ; keep waiting for third edge if C0F isn't set
stx third_edge ; stores TCNT to third_edge
ldd third_edge
subd second_edge ; calculates time between second and third edge --separation
andcc #$01 ; clears all except (maybe) C bit of CCR
beq store_separation ; if carry bit is set, counter wrapped around
; between detecting the second and third edges
ldd #$ff

wait_fourth: ; waiting for fourth edge

beq wait_fourth ; keep waiting for fourth edge if C0F isn't set
stx fourth_edge ; stores TCNT to fourth_edge
bra wait_first
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 2
; Using Output Compare on Channel 0
; pulse width will be 100us, separation will be 500us
; period will me 18ms
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080

CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL2 equ $0089
TMSK1 equ $008C
TMSK2 equ $008D
TCNT equ $0085
TC0H equ $0090
TFLG1 equ $008E
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000

movb #$01,TCTL2 ; sets channel 0 to toggle on output compare
movb #$0,TMSK1 ; disable interrupts
movb #$03,TMSK2 ; sets prescaler divisor to 8-->counter=1MHz, period=1us
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
first: ; sets counter to cycle for 17.3ms and then

; generate first edge (first of four edges in each sequence)
addd #$4394 ; adds !17300 to D
std TC0H ; sets counter to do output compare after 17300 counter cycles
; since the period is 1us, this corresponds to 17.3ms
; which is the time between sets of pulses (period = 18ms)
wait_1: ; waits for first edge
second: ; generates second edge
std TC0H ; sets counter to do output compare after 100 counter cycles(100us)
wait_2: ; waits for second edge
third: ; generates third edge
std TC0H ; sets counter to do output compare after 500 cycles (500us)
wait_3: ; waits for third edge

fourth: ; generates fourth edge
std TC0H ; sets counter to do output compare after 100 cycles (100us)
wait_4: ; waits for fourth edge
bra first
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 3
; Input Capture on Channel 0 w/ Wave from Problem 1
; do same calculations as in problem 1
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080
CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
TCTL2 equ $0089
TC0H equ $0090
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Section
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $800
; initialize timer channel 0 for input capture with interrupts

movb #$0,TIOS ; set all channels for input capture
movb #$0,DFORC ; disables force timer counter
movb #$0,OC7M ; sets TIMPORT pin input
movb #$80,TSCR ; enable counter
movb #$03,TCTL4 ; sets channel 0 for input capture on any edge
movb #$01,TMSK1 ; enable interrupts on channel 0
movb #$03,TMSK2 ; set prescaler value to 8-->period=1us
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>

old_first ds 2 ; stores counter value at previous first edge
which_edge ds 1 ; stores vale (1,2,3,4), indicating which edge should arrive next
movb #$01,which_edge ; initialize which_edge to wait for 1st edge
movw #$1000,$FFEE ; puts address of ISR in timer channel 0 place in IVT
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000 ; ISR

ISR_1: ldx TCNT ; load value of counter at time of interrupt
movb #$01,TFLG1 ; writing 1 clears the channel 0 flag
ldaa which_edge ; loads variable indicating which edge was detected
cmpa #$01
beq first ; if which_edge is 1, detected edge was first one
cmpa #$02
beq second ; if which_edge is 2, detected edge was second one
cmpa #$03
beq third ; if which_edge is 3, detected edge was third one
cmpa #$04
beq fourth ; if which_edge is 4, detected edge was fourth one

ldd first_edge ; load previous value of first edge
std old_first ; move previous value to first edge
stx first_edge ; store new first edge in x
; now calculate the period
ldd first_edge ; load first edge
subd old_first ; subtract first_edge-old_first
andcc #$01 ; clears all CCR bits except (maybe) the carry flag
; between detecting old_first and first edges
; counter period is 1us and period is about 18ms,

; there is only approx 18000 counter clocks between
; therefore, the counter could only have rolled over
; once (at most) between the two first_edge's
ldd #$ff
subd old_first ; subtracts $FF-old_first

rti

stx second_edge ; store new value of second edge
ldd second_edge
subd first_edge ; subtracts time of second edge from time of first edge
andcc #$01 ; clears all except (maybe) the C-bit in the CCR
beq store_width ; if Carry bit is not set, skip to store_width
; if carry bit is not set, counter wrapped around
; between detecting the first and second edges
ldd #$ff

rti

stx third_edge ; store new value of third edge

ldd third_edge
subd second_edge ; calculates time between second and third edge --separation
andcc #$01 ; clears all except (maybe) C bit of CCR
beq store_separation ; if carry bit is set, counter wrapped around
; between detecting the second and third edges
ldd #$ff

rti
fourth: movb #$01,which_edge ; reset which_edge to 1

stx fourth_edge ; stores new value of fourth edge
rti
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Problem 4
; Output Compare on Channel 0, Same Wave as Problem 2
; output same wave as in problem 2, but use interrupts
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
TIOS equ $0080
CFORC equ $0081
OC7M equ $0082
TSCR equ $0086
TCTL4 equ $008B
TMSK1 equ $008C
TMSK2 equ $008D
TFLG1 equ $008E
TCNT equ $0084
TCTL2 equ $0089
TC0H equ $0090
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Section
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $800
which_edge ds 1 ; will store a value (1-4) indicating which edge should be generated next
movb #$01,which_edge ; initialize which_edge to 1
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>

movb #$01,TCTL2 ; sets channel 0 to toggle on output compare
movb #$01,TMSK1 ; enable channel 0 interrupts
movb #$03,TMSK2 ; sets prescaler divisor to 8-->counter=1MHz, period=1us
movw #$1000,$FFEE ; puts address of ISR in timer channel 0 place in IVT
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org $1000
ISR_2: ldd TCNT
movb #$01,TFLG1
ldx which_edge ; loads variable indicating which edge to generate
cpx #$01
beq first ; if which_edge is 1, generate first edge
cpx #$02
beq second ; if which_edge is 2, generate second edge
cpx #$03
beq third ; if which_edge is 3, generate third edge
cpx #$04
beq fourth ; if which_edge is 4, generate fourth edge

addd #!17300 ; add 17300 to D
std TC0H ; store TCNT + 17300 in the compare register
; waits 17.3ms before generating first edge

rti

; waits 100us for pule width before generating second edge
rti

; waits 500us for separation before generating second edge
rti
fourth: movb #$01,which_edge ; increment which_edge

; waits 100us for pulse width before generating second edge
rti

EE 2361 Spring 2003
Homework Assignment 10
Due: Thursday, April 10
4 problems
Turn in typed pages for the programs you develop.

Include comments for each line. No credit will be given for code without comments.
1) Write a program to make measurements on a signal consisting of two pulses repeating roughly every
120 millisecond as shown below. Use the Input Capture Edge Bit mechanism of the HC12 and
polling. Do not use the pulse accumulator mechanism.
a) Width of the first pulse (roughly 100 us) to within 1 us accuracy.
b) Time between pulses (separation). Roughly 500 us. Measure to within 10 us.
c) Time from leading edge of the first pulse of a pair to the leading edge of the second pair
(period). Measure to within 1 millisecond.
separation
pulse width
period
2) Write a program to generate the waveform described in problem. Use the Output Compare
mechanism of the HC12 and polling. Do not use the pulse accumulator mechanism. Generate the
waveform edge times to the accuracy described in Problem 1.
3) Repeat Problem 1 using interrupts so that the HC12 can do other work while waiting between the
measurements.
4) Repeat Problem 2 using interrupts so that the HC12 can do other work while waiting to generate each
waveform edge.
EE 2361 Spring 2003
4 problems

1) Write a program to make measurements on a signal consisting of two pulses repeating roughly every
18 milliseconds as shown below. Use the Input Capture Edge Bit mechanism of the HC12 and
polling. Do not use the pulse accumulator mechanism.
a) Width of the first pulse (roughly 100 us) to within 1 us accuracy.
b) Time between pulses (separation). Roughly 500 us. Measure to within 10 us.
c) Time from leading edge of the first pulse of a pair to the leading edge of the second pair
(period). Measure to within 1 millisecond.
separation
pulse width
period
MAIN:
; Memory equates
PROG EQU $800
DATA EQU $900
STACK EQU $7FFF
; Timer equates
TCNT EQU $84
C1 EQU %00000010 ; Channel 1
EDG1B EQU %00001000 ;
EDG1A EQU %00000100 ;
OMC1 EQU %00001000
OLC1 EQU %00000100
PR2 EQU %00000100
PR1 EQU %00000010
PR0 EQU %00000001
TCTL2 EQU $89 ; control generating edges, lower 4 channels
TCTL4 EQU $8B ; control detecting edges, lower 4 channels
; ISR equates
ISR_EDGE_TIME EQU $6000 ; arbitrary location for ISR
ISR_GEN_PULSE EQU $7000 ; arbitrary location for ISR
; Reserve memory for data
ORG DATA
FIRSTRISE DS !2
SECONDRISE DS !2
THIRDRISE DS !2
FALL DS !2
PULSEWIDTH DS !2
SEPARATION DS !2
; Start main program
ORG PROG
lds #STACK
bclr TMSK1,PR2 ; set prescalar for divide by 8
bset TMSK1,PR1
bset TMSK1,PR0
; Get count of first rising edge detected
bclr TCTL4,EDG1B ; Initialize IC1 for rising edge
bset TCTL4,EDG1A
staa TFLG1
SPIN1 brclr TFLG1,C1,SPIN1 ; Wait for rising edge
std FIRSTRISE ; save it
; Get count of second rising edge detected
staa TFLG1
std SECONDRISE ; save it
; Get count of third rising edge detected
staa TFLG1
std THIRDRISE ; save it
; Get count of falling edge detected
bset TCTL1,EDG1B ; Initialize IC1 for falling edge
bclr TCTL1,EDG1A ;
ldaa #C1 ; Reset the IC1 Flag
staa TFLG1
SPIN4 brclr TFLG1,C1,SPIN4 ; Wait for falling edge
std FALL ; save it
; Determine if the first rising edge was for the first or second of the 2 pulses
ldd THIRDRISE
subd FIRSTRISE
std PERIOD ; period has been found
ldd THIRDRISE
subd FALL
std PULSEWIDTH
ldd THIRDRISE
subd SECONDRISE
std SECONDDIFF
ldd SECONDRISE
subd FIRSTRISE
std FIRSTDIFF
cmp SECONDDIFF
bhi REVERSED ;
; if it did not branch then FIRSTDIFF is time between leading edges of first two pulses
ldd FIRSTDIFF
subd WIDTH ; width has been found
std SEPARATION
bra CONTINUE ;
REVERSED ldd SECONDDIFF
subd WIDTH
std SEPARATION
CONTINE swi
2) Write a program to generate the waveform described in problem. Use the Output Compare
mechanism of the HC12 and polling. Do not use the pulse accumulator mechanism. Generate the
waveform edge times to the accuracy described in Problem 1.
MAIN:
; Memory equates
PROG EQU $800
DATA EQU $900
STACK EQU $7FFF
; Timer equates
TCNT EQU $84
C1 EQU %00000010 ; Channel 1
EDG1B EQU %00001000 ;
EDG1A EQU %00000100 ;
OMC1 EQU %00001000
OLC1 EQU %00000100
PR2 EQU %00000100
PR1 EQU %00000010
PR0 EQU %00000001
; ISR equates
; Pulse edge time equates
WIDTH1 EQU !100
WIDTH2 EQU !500
WIDTH3 EQU !17300
; PORTT equates
PORTT EQU $AE
DDRT EQU $AF
ORG PROG
lds #STACK
bset TMSK1,PR1
bset TMSK1,PR0
bset TIOS,C1 ; Reset TIOS bit-1 to enable output compare
; Output the first rising edge
bset DDRT,C1 ; set C1 for output
bset PORTT,C1 ; set C1 to “1”
ldd TCNT
std TC1
; Start of loop to generate 2 pulses
; Setup TCTL2 to generate a falling edge
LOOP bset TCTL2,OMC1 ; Initialize IC1 to generate a falling edge
bclr TCTL2,OLC1
; Setup to wait 100us
ldd TC1
addd WIDTH1 ; count for 100us
std TC1
staa TFLG1
SPIN1 brclr TFLG1,C1,SPIN1 ; After 100us falling edge will be generated
; Setup TCTL2 to generate second rising edge
bset TCTL2,OMC1 ; Initialize IC1 to generate a rising edge
bset TCTL2,OLC1
ldd TC1
std TC1
staa TFLG1
SPIN2 brclr TFLG1,C1F,SPIN2 ; After 500us rising edge will be generated
; Setup TCTL2 to generate second falling edge
bset TCTL2,OMC1 ; Initialize IC1 to generate a falling edge
bclr TCTL2,OLC1
ldd TC1
std TC1
staa TFLG1
SPIN3 brclr TFLG1,C1,SPIN1 ; After 100us falling edge will be generated
; Setup TCTL2 to generate a rising edge
bset TCTL2,OLC1
; Setup to wait 17.3ms
ldd TC1
addd WIDTH3 ; count for 17.3ms
std TC1
staa TFLG1
SPIN4 brclr TFLG1,C1F,SPIN2 ; After 17.3ms a rising edge will be generated
bra LOOP
3) Repeat Problem 1 using interrupts so that the HC12 can do other work while waiting between the
measurements.
MAIN:
; Memory equates
PROG EQU $800
DATA EQU $900
STACK EQU $7FFF
; Timer equates
TCNT EQU $84
C1 EQU %00000010 ; Channel 1
EDG1B EQU %00001000 ;
EDG1A EQU %00000100 ;
OMC1 EQU %00001000
OLC1 EQU %00000100
PR2 EQU %00000100
PR1 EQU %00000010
PR0 EQU %00000001
; ISR equates
ISR_CLEAR_FLAG EQU $7000 ; arbitrary location for ISR
; Reserve memory for data & variables
ORG DATA
FIRSTRISE DS !2
SECONDRISE DS !2
THIRDRISE DS !2
FALL DS !2
PULSEWIDTH DS !2
SEPARATION DS !2
INT_COUNT DS !1
ORG PROG
lds #STACK ; do not include this line if code is subroutine
bset TMSK1,PR1
bset TMSK1,PR0
ldd # ISR_EDGE_TIME ; get address of ISR
ldaa #$00
staa INT_COUNT ; initialize interrupt counter for ISR
; Prepare to get count of first rising edge detected
bclr TCTL4,EDG1B ; Initialize IC1 for rising edge
bset TCTL4,EDG1A
staa TFLG1
staa TMSK1 ; enable Channel 1 interrupts
; put in other program codes as wanted
;
;
;
; ISR for detecting edges and computing widths
ORG ISR_EDGE_TIME ; start of ISR
inc INT_COUNT
ldaa INT_COUNT
cmpa #$1
beq FIRSTEDGE
cmpa #$2
lbeq SECONDEDGE
cmpa #$3
lbeq THIRDEDGE
cmpa #$4
lbeq FOUTHEDGE
FIRSTEDGE ldd TC1 ; Get the count that was latched
std FIRSTRISE ; save it
staa TFLG1
rti
; Get count of second rising edge detected
SECONDEDGE ldd TC1 ; Get the count that was latched
std SECONDRISE ; save it
staa TFLG1
rti
; Get count of third rising edge detected
THIRDEDGE ldd TC1 ; Get the count that was latched
std THIRDRISE ; save it
ldaa #C1
staa TFLG1
; Prepare to get count of falling edge detected
bset TCTL1,EDG1B ; Initialize IC1 for falling edge
bclr TCTL1,EDG1A ;
ldaa #C1 ; Reset the IC1 Flag
staa TFLG1
rti
FOURTHEDGE ldd TC1 ; Get the count that was latched
std FALL ; save it
ldaa #$0
staa INT_COUNT ; clear the interrupt counter for future
; Determine if the first rising edge was for the first or second of the 2 pulses
ldd THIRDRISE
subd FIRSTRISE
std PERIOD ; period has been found
ldd THIRDRISE
subd FALL
std PULSEWIDTH
ldd THIRDRISE
subd SECONDRISE
std SECONDDIFF
ldd SECONDRISE
subd FIRSTRISE
std FIRSTDIFF
cmp SECONDDIFF
bhi REVERSED ;
; if it did not branch then FIRSTDIFF is time between leading edges of first two pulses
ldd FIRSTDIFF
subd WIDTH ; width has been found
std SEPARATION
bra CONTINUE ;
REVERSED ldd SECONDDIFF
subd WIDTH
std SEPARATION
ldd #$0 ; clear the interrupt counter
staa INT_COUNT
ldaa #C1
staa TMSK1 ; clear the interrupt enable
staa TFLG1 ; clear the flag
CONTINE rti
4) Repeat Problem 2 using interrupts so that the HC12 can do other work while waiting to generate each
waveform edge.
MAIN:
; Memory equates
PROG EQU $800
DATA EQU $900
STACK EQU $7FFF
; Timer equates
TCNT EQU $84
C1 EQU %00000010 ; Channel 1
EDG1B EQU %00001000 ;
EDG1A EQU %00000100 ;
OMC1 EQU %00001000
OLC1 EQU %00000100
PR2 EQU %00000100
PR1 EQU %00000010
PR0 EQU %00000001
; ISR equates
; Pulse edge time equates
WIDTH1 EQU !100
WIDTH2 EQU !500
WIDTH3 EQU !17300
; PORTT equates
PORTT EQU $AE
DDRT EQU $AF
; Reserve memory for data & variables
ORG DATA
INT_COUNT DS !1
ORG PROG
lds #STACK
bset TMSK1,PR1
bset TMSK1,PR0
bset TIOS,C1 ; Reset TIOS bit-1 to enable output compare
ldaa #$00
staa INT_COUNT ; initialize interrupt counter for ISR
staa TFLG1
; Output the first rising edge
bset DDRT,C1 ; set C1 for output
bset PORTT,C1 ; set C1 to “1”
ldd TCNT
std TC1
; Setup TCTL2 to generate a falling edge
bclr TCTL2,OLC1
ldd TC1
std TC1
staa TFLG1
; put in other program codes as wanted
;
;
;
; ISR for generating pulse edges
ORG ISR_GEN_PULSE ; start of ISR
inc INT_COUNT
ldaa INT_COUNT
cmpa #$1
lbeq SECONDRISING
cmpa #$2
lbeq SECONDFALLING
cmpa #$3
lbeq FIRSTRISING
cmpa #4
lbeq FIRSTFALLING
SECONDRISING
; Setup TCTL2 to generate second rising edge
bset TCTL2,OLC1
ldd TC1
std TC1
staa TFLG1
rti
SECONDFALLING
; Setup TCTL2 to generate second falling edge
bclr TCTL2,OLC1
ldd TC1
std TC1
staa TFLG1
rti
FIRSTRISING
; Setup TCTL2 to generate a rising edge
bset TCTL2,OLC1
; Setup to wait 17.3ms
ldd TC1
addd WIDTH3 ; count for 17.3ms
std TC1
staa TFLG1
rti
FIRSTFALLING
bclr TCTL2,OLC1
ldd TC1
std TC1
ldd #$0 ; clear the interrupt counter
staa INT_COUNT
staa TFLG1
rti
EE 2361 Spring 2003
$FF
$10 $30 $80 $B0 $FF
1. Inputs to a fuzzy controller whose membership function includes the one shown above
are $70, $22 and $A3. What are the corresponding truth values of the function?
2. Suppose we have the following two rules with the same consequent: (1) IF A and B,
then C and (2) IF D and E, then C. Furthermore the truth values assigned for
membership function C are 0.7 and 0.5 by rule (1) and rule (2) respectively. What is
the final truth value for C?
3. Suppose you have the following rules: If A and b, the C. Symbols A, B, and C
represent membership functions. If the truth value for A is 0.7 and the truth value B is
0.8 what is the truth value for C when the particular rule is processed?
4. If equally weighted 80 rules for the balancing root are to be implemented in the
68HC12, how many bytes are needed to specify the rules?
5. Find left and right slopes of the trapezoid which starts at $00, ends at $80 and the left
slope intersects the top ($FF) at $15 and the right slope intersects the top at $60.
6. In the figure below there are 5 membership sets shown. Describe the memberships of
each of the 5 sets using four numbers as needed for input to the HC12 (farthest left
point, farthest right point, left slope and right slope, p 371 of CPU12 Reference
Manual). The lines were meant to intersect the vertical lines which are spaced every
$10.
Left Sensor = $6C Right Sensor = $9A
Very Weak Weak Medium Strong Very Strong

255
224
192
128
64
32
$40 $50 $60 $70 $80 $90 $A0 $B0 $C0
7. In the figure the sensor input values are given as,

Left Sensor = $6C
Right Sensor = $9A
Compute the truth values for each sensor in each of the 5 sets and fill in the table
below.
Left Sensor Right Sensor
Very Weak
Weak
Medium
Strong
Very Strong
EE 2361 Spring 2003
$FF
$10 $30 $80 $B0 $FF
1. Inputs to a fuzzy controller whose membership function includes the one shown above
are $70, $22 and $A3. What are the corresponding truth values of the function?
a. $FF
b. $FF($22-$10)/($30-$10) = 255*18/32 = 143.4375 = $8F
c. $FF($B0-$A3)/($B0-$80) = 255*13/48 = 69.0625 =$45
2. Suppose we have the following two rules with the same consequent: (1) IF A and B,
then C and (2) IF D and E, then C. Furthermore the truth values assigned for
membership function C are 0.7 and 0.5 by rule (1) and rule (2) respectively. What is
the final truth value for C?
0.7 because it is the maximum
3. Suppose you have the following rules: If A and b, the C. Symbols A, B, and C
represent membership functions. If the truth value for A is 0.7 and the truth value B is
0.8 what is the truth value for C when the particular rule is processed?
0.7, because it is the minimum of the two truths
4. If equally weighted 80 rules for the balancing root are to be implemented in the
68HC12, how many bytes are needed to specify the rules?
5 bytes per rule = 400
5. Find left and right slopes of the trapezoid which starts at $00, ends at $80 and the left
slope intersects the top ($FF) at $15 and the right slope intersects the top at $60.
a. $FF/($15-$00) = 256/21 = 12.19 = $C
b. $FF/($80-$60) = 256/32 = 8 = $8
6. In the figure below there are 5 membership sets shown. Describe the memberships of
each of the 5 sets using four numbers as needed for input to the HC12 (farthest left
point, farthest right point, left slope and right slope, p 371 of CPU12 Reference
Manual). The lines were meant to intersect the vertical lines which are spaced every
$10.
VeryWeak $00 $50 $00 $10
Weak $40 $70 $10 $10
Medium $60 $A0 $10 $10
Strong $90 $C0 $10 $10
Very Strong $B0 $FF $10 $00

255
224
192
128
64
32
$40 $50 $60 $70 $80 $90 $A0 $B0 $C0
6. In the figure the sensor input values are given as,

Left Sensor = $6C
Right Sensor = $9A
Compute the truth values for each sensor in each of the 5 sets and fill in the table
below.
Left Sensor Right Sensor
Very Weak 0 0
Weak 64 0
Medium 192 96
Strong 0 160
Very Strong 0 0
EE 2361 Spring 2003
Due: Thursday, May 1
The first two problems of the homework are based on the Fuzzy Robot application provided by Pack and
Barrett in the P&E files C:\Program Files\P&E\PrenticeHall\Examples\ch4 and called application.asm
(see links on Notes page of class web site.
1. Determine the memory locations for the following:

a) Starting address for Input Membership functions (4 bytes each)
b) Starting address for Rules
c) Location of Right Sensor Value
d) Location of Left Sensor Value
e) Starting address for Fuzzy Inputs (computed by MEM instruction)
f) Starting address for Fuzzy Outputs (computed by REV instruction)
g) Location of System Output
2. Run the program and determine the values produced by the following:
Fuzzy Inputs System

Output
INPUT System Inputs (Crisp Sensor VW W M S VS
SET Values)
1 Right Sensor $9A na
Left Sensor $6C na
System Output na na na na na
2 Right Sensor $9C na

Left Sensor $B9 na
3 Right Sensor $63 na

Left Sensor $43 na
3. Consider the following situation: Your car is closing on the car ahead. Your radar sensor is
measuring the distance (DISTANCE) between cars and your car’s microcomputer is calculating the
rate of change in distance (RATE). You want to program the automatic braking system to respond
properly to these inputs (BRAKE PRESSURE = system output).
a) Create 3 input membership names for each of the two System Inputs (just names of sets, not
values)
b) Create a set of System Output names (singletons) which describe the amount of brake pressure
which should be applied.
c) Create a set of Rules (in a table) which relate the Fuzzy Inputs and System Outputs.
EE 2361 Spring 2003
The first two problems of the homework are based on the Fuzzy Robot application provided by Pack and
Barrett in the P&E files C:\Program Files\P&E\PrenticeHall\Examples\ch4 and called application.asm
(see links on Notes page of class web site.
1. Determine the memory locations for the following:

a) Starting address for Input Membership functions (4 bytes each)
b) Starting address for Rules
c) Location of Right Sensor Value 6000
d) Location of Left Sensor Value 6001
e) Starting address for Fuzzy Inputs (computed by MEM instruction) 6030
f) Starting address for Fuzzy Outputs (computed by REV instruction)
g) Location of System Output 6002
2. Run the program and determine the values produced by the following:
You may have reversed the Fuzzy Inputs ( see second table) due to the columns being
given in the wrong order. Full credit will be given for that oversight.
Fuzzy Inputs System
Output
INPUT System Inputs (Crisp Sensor VW W M S VS
SET Values)
1 Right Sensor $9A 00 A0 60 A0 00 na
Left Sensor $6C 00 C0 40 00 00 na
System Output na na na na na $63
2 Right Sensor $9C 00 00 40 C0 00 na

Left Sensor $B9 00 00 00 70 90 na
System Output na na na na na 76
3 Right Sensor $63 00 00 D0 30 00 na

Left Sensor $43 D0 30 00 00 00 na
This table’s column order matches the order in memory following runs of the simulator.
Fuzzy Inputs System
Output
INPUT System Inputs (Crisp Sensor VS S M W VW
SET Values)
1 Right Sensor $9A 00 A0 60 00 00 na
Left Sensor $6C 00 00 40 C0 00 na
System Output na na na na na $63
2 Right Sensor $9C 00 C0 40 00 00 na

Left Sensor $B9 90 70 00 00 00 na
3 Right Sensor $63 00 30 D0 00 00 na
Left Sensor $43 00 00 00 30 D0 na
3. Consider the following situation: Your car is closing on the car ahead. Your radar sensor is
measuring the distance (DISTANCE) between cars and your car’s microcomputer is calculating the
rate of change in distance (RATE). You want to program the automatic braking system to respond
properly to these inputs (BRAKE PRESSURE = system output).
a)Create 3 input membership names for each of the two System Inputs (just names of sets, not
values)
CLOSE, MEDIUM, DISTANT
RAPID DECREASE, DECREASING, CONSTANT
b) Create a set of System Output names (singletons) which describe the amount of brake pressure
which should be applied.
HARD, MILD, NONE
c) Create a set of Rules (in a table) which relate the Fuzzy Inputs and System Outputs.
DISTANCE\RATE RAPID DECREASING CONSTANT

CLOSE HARD HARD MILD
MEDIUM HARD MILD MILD
DISTANT MILD NONE NONE
EE 2361 Spring 2003
1) Prepare to make a memory timing analysis by filling in the propagation delay times
in the table below using the data sheets provided on the web (link on Memory timing
line):
tPH, tPL or tPD for CL = 50pf VCC = 4.5 volts

250C -550C to1250C
74HC00 NAND
74HC04 NOT
74HC08 AND
74HC138 DECODER
Address change max
Output enable max
Chip enable max
Pulse width min
Chip select min
2) A memory design like the one given in the Timing Note has been constructed using
the chips given above. Fill in the memory timing for the two temperature conditions
in the tables below:

250C -550C to1250C
READ Time when output data of memory chip becomes
from memory valid due to Address change
chip Time when output data of memory chip becomes
valid due to Output Enable
Time when output data of memory chip becomes
valid due to Chip Select
nanoseconds
250C -550C to1250C
WRITE Time left over (margin) between pulse width
to memory chp needed to write data to the memory chip and the
falling edge of the ECLK.
Note: this ignores the extra margin available due
to propagation delays.
Time left over (margin) between the chip select
time needed and the falling edge of the ECLK.
Note: this ignores the extra margin available due
to propagation delays.
EE 2361 Spring 2003
Solutions
1) Prepare to make a memory timing analysis by filling in the propagation delay times in the table below
using the data sheets provided on the web (link on Memory timing line):
tPH, tPL or tPD for CL = 50pfVCC = 4.5 volts

250C -550C to1250C
74HC00 NAND 18 27
74HC04 NOT 17 26
74HC08 AND 20 25
74HC138 DECODER 30 45
Address change max 25
Output enable max 15
Chip enable max 25
Pulse width min 15
Chip select min 20
2) A memory design like the one given in the Timing Note has been constructed using the chips given
above. Fill in the memory timing for the two temperature conditions in the tables below:

250C -550C to1250C
READ Time when output data of memory chip becomes 25 25
from valid due to Address change
memory Margin available for Address change 125 125
chip –30tDSR –30tDSR
–25add –25add
= 70 = 70
Time when output data of memory chip becomes +18nand +27nand
valid due to Output Enable +25oe +25oe
= 43 = 52
Margin available for Output Enable 125 125
– 30tDSR –30tDSR
–43 -52
= 52 = 43
Time when output data of memory chip becomes 30decoder 45decoder
valid due to Chip Select +20and +25and
+25tace +25tace
= 75 = 95
Margin available for Chip Select 125 125
–30 tDSR –30 tDSR
– 75 –95
= 20 =0
nanoseconds
250C -550C to1250C
WRITE Time left over (margin) between pulse 125 125
to memory width needed to write data to the memory –(25not-20rwch)
chp chip and the falling edge of the ECLK. –18nand -27nand
Note: this ignores the extra margin –15tPWE –15tPWE
available due to propagation delays. = 92 = 78
Time left over (margin) between the chip 125 125
select time needed and the falling edge of –30decoder –45decoder
the ECLK. –20and –25and
Note: this ignores the extra margin –20tSCE –20tSCE
available due to propagation delays. = 55 = 35
EE 2361 Spring 2003
Due: Thursday, January 30th
8 problems
No credit will be given for answers given without work showing how the answers were
developed.
1. Convert the following unsigned binary numbers to decimal numbers.

a) 11001101
b) 011011010101
2. Convert the following signed binary numbers to decimal numbers.

a) 11101011
b) 1101
3. Convert the following decimal numbers into 16-bit two’s complement binary
numbers.
a) 237
b) -647
c) -61
4. Convert each of the following unsigned hex numbers to decimal numbers.

a) $E496
b) $B11F
c) $A1
5. Form the two’s complement of the signed hex numbers (do not convert to binary).
a) B4
b) ED27
c) 2D6E
6. Sign-extend the signed hex numbers to 16-bit hex numbers.

a) E3
b) 2DD
c) D4E
7. Perform the binary arithmetic operations on these signed binary numbers and indicate
if overflow occurs.
a) 01110101
+ 11001101
b) 10110011
- 11011010
c) 01011010
+ 01110101
8. Perform the indicated 16-bit arithmetic operations on the signed-hex numbers and
indicate if overflow occurs.
a) 2DFE
+ 7B42
b) D3EC
- 2B0F
c) 38EB
- 793D
d) 9D00
+ A100
e) DE0F
+ A4E2
EE 2361 Spring 2003
Due: Thursday, February 6th
8 problems
1. For the program below step through the program using the simulator and fill out the table to give the
contents of registers and memory after each program step is executed. Fill in cells only as they
change (do not repeat the contents line-after-line).
PC A B X Y 900 901 902 903 904 905
prog: equ $800
org prog
ldx #$0900
ldy #$0907
ldaa #!254
staa $4,x
ldaa #$5
staa $905
ldab #$89
staa -4,y
staa $1000,x
LEAS to verify your answer for the indexed instructions.
Instruction Address Mode Effective Address LEAS result
ldx #$0900
ldy #$0907
ldaa #!254
staa $4,x
ldaa #$5
staa $905
ldab #$89
staa -4,y
staa $1000,x
Tables from the CPU12 Reference Manual, A-2 for timing and A-3 for postbye.
ldx #$0900
ldy #$0907
ldaa #!254
staa $4,x
ldaa #$5
staa $905
ldab #$89
staa -4,y
staa $1000,x
4. Suppose the contents of accumulator D are $72EC. Give the contents of accumulator D and the values
of the N, Z, V, and C bits of the CCR after each of the following instructions are executed (this is not
a sequence of instructions):
a) suba #$EF
b) adda #$CD
c) negb
d) addd #$A435
e) tstb
5. Suppose the contents of memory starting at address $900 are as follows: $C1, $78, $21, $5C, $67,
$89, $00, $FF. Give the contents of A, B, NZVC and memory locations $900 to $90B after each step
of the code sequence has executed (assume the contents of A and B are both $00 at the start):
prog equ $800

data equ $900
org prog
ldx #$900
ldaa !1,x
ldab $2,x
sba
std $0,x
ldd $904
sba
staa $90A
stab $90B
org data
DB $C1,$78,$21,5C,67,89,00,FF
A B NZVC 900 901 902 903 904 905 906 907 908 909 90A 90B
ldx #$900
ldaa !1,x
ldab $2,x
sba
std $0,x
ldd $904
sba
staa $90A
stab $90B
6. Assume that the contents of memory starting at address $1000 are as follows; $86, $40, $CF, $0C,
$00, $D6, $64, $5A, $65, $B6. The following program is then executed. Give the contents of those
same memory locations ($1000 to $1009 inclusive) and the contents of register X and accumulator D
at the time the stop instruction begins execution.
PROGRAM: EQU $0900

DATA: EQU $1009
ORG PROGRAM
ldx #DATA
ldd #DATA
LOOP: ldaa DATA_WORD
aba
decb
staa 1,x-
bne LOOP
stop
DATA_WORD: DW $00FF
7. Give the addressing mode and the effective address for each of the following instructions. Assume
that index register X contains $1234, index register Y contains $0A32, and accumulator D contains
$FF02.
a. ldaa -7, y
b. ldab 1, -x
c. staa a, x
d. stab 2, y+
e. ldab d, x
8. Correct the following instructions as needed.
staa $6D,x-
stab $ 45
stab $y,x
ldx !$0034
stab $0B00
ldy $09N
stab $ FF
ldx !$00FA
stab $0B00
ldy $090X
staa $2E,+x
stab $y,x
EE 2361 Spring 2003
1. For the program below step through the program using the simulator and fill out the table to give the
contents of registers and memory after each program step is executed. Fill in cells only as they
change (do not repeat the contents line-after-line).
PC A B X Y 900 901 902 903 904 905

prog: equ $800
org prog
ldx #$0900 900 c1 78 21
ldy #$0907 907
ldaa #!254 FE
staa $4,x FE
ldaa #$5 05
staa $905 905
ldab #$89 89
staa -4,y 89
staa $1000,x
; $05 → $1900
LEAS to verify your answer for the indexed instructions.
Instruction Address Mode Effective Address LEAS result

ldx #$0900 immediate na
ldy #$0907 immediate na
ldaa #!254 immediate na
staa $4,x constant indexed x + 7 = 907
ldaa #$5 immediate na
staa $905 extended 905
ldab #$89 immediate na
staa -4,y constant indexed y –4 = 903
staa $1000,x constant indexed x + $1000 = 1900
Tables from the CPU12 Reference Manual, A-2 for timing and A-3 for postbye.
ldx #$0900 CE 09 00 2 250
ldy #$0907 CD 09 07 2 250
ldaa #!254 86 FE 1 125
staa $4,x 6A 04 2 250
ldaa #$5 86 05 1 125
staa $905 7A 09 05 3 375
ldab #$89 C6 89 1 125
staa -4,y 6A 5C 2 250
staa $1000,x 6A E2 10 00 3 375
staa –4,y 6A rr0nnnn rr=01 for y register, nnnn is complement of 00100 = 11100
01011100 = 5C
4. Suppose the contents of accumulator D are $72EC. Give the contents of accumulator D and the values
of the N, Z, V, and C bits of the CCR after each of the following instructions are executed (this is not
a sequence of instructions):
a) suba #$EF
b) adda #$CD
c) negb
d) addd #$A435
e) tstb
A B NZVC
72 EC
suba #$EF 83 EC 1011
adda #$CD 3F EC 0001
negb 3F 14 0001
addd #$A435 17 21 0001
tstb 72 EC 1000
5. Suppose the contents of memory starting at address $900 are as follows: $C1, $78, $21, $5C, $67,
$89, $00, $FF. Give the contents of A, B, NZVC and memory locations $900 to $90B after each step
of the code sequence has executed (assume the contents of A and B are both $00 at the start):
prog equ $800
data equ $900
org prog
ldx #$900
ldaa !1,x
ldab $2,x
sba
std $0,x
ldd $904
sba
staa $90A
stab $90B
org data
DB $C1,$78,$21,5C,67,89,00,FF
A B NZVC 900 901 902 903 904 905 906 907 908 909 90A 90B
ldx #$900 0000 C1 78 21 5C 67 89 00 FF
ldaa !1,x 78 0000
ldab $2,x 21 0000
sba 57 0000
std $0,x 0000 57 21
ldd $904 67 89 0000
sba DE 89 1011
staa $90A 1001 DE
stab $90B DE 89 1001 57 21 21 5C 67 89 00 FF DE 89
6. Assume that the contents of memory starting at address $1000 are as follows; $86, $40, $CF, $0C,
$00, $D6, $64, $5A, $65, $B6. The following program is then executed. Give the contents of those
same memory locations ($1000 to $1009 inclusive) and the contents of register X and accumulator D
at the time the stop instruction begins execution.
PROGRAM: EQU $0900

DATA: EQU $1009
ORG PROGRAM
ldx #DATA
ldd #DATA
LOOP: ldd DATA_WORD
aba
decb
staa 1,x-
bne LOOP
stop
DATA_WORD: DW $00FF
The contents of memory at the time the stop instruction begins execution starting at $1000 are: $00, $01,
$02, $03, $04, $05, $06, $07. The contents of the index register X is $0FFF and the content of the double
accumulator D=A:B=$0000.
7. Give the addressing mode and the effective address for each of the following instructions. Assume
that index register X contains $1234, index register Y contains $0A32, and accumulator D contains
$FF02.
a. ldaa -7, y
b. ldab 1, -x
c. staa a, x
d. stab 2, y+
e. ldab d, x
The effective address and addressing mode are as follows:

a. EA = (Y) - $0007 = $0A2B (indexed, constant 5-bit offset)
b. EA = (X) - $0001 = $1233 (indexed, pre decrement)
c. EA = (X) + (A) = $1333 (indexed, accumulator offset)
d. EA = (Y) = $0A32 (indexed, post increment
e. EA = (X) + (D) = $1136 (indexed, accumulator offset)
8. Correct the following instructions as needed.
staa $6D,x-
stab $ 45
stab $y,x
ldx !$0034
stab $0B00
ldy $09N
stab $ FF
ldx !$00FA
stab $0B00
ldy $090X
staa $2E,+x
stab $y,x
Correct the following instructions as needed.
staa $6,x- ; $6D,x-

stab $45 ; $ 45
stab $1,x ; $y,x
ldx #$34 ; !$0034
stab $0B00 ; OK as is
ldy $0900 ; $09N
stab $FF ; $ FF
ldx #$FA ; !$00FA
stab $0B00 ; OK as is
ldy $0900 ; $090X
staa $2,+x ; $2E,+x
stab $1,x ; $y,x
EE 2361 Fall 2003
8 problems
Turn in type-written pages for the programs you develop for these problems.
1) A program for computing Average Temperature is referred to on the class Notes page.
a) Modify the program to find the average for the following 7 days of temperatures
(74,78,83,91,87,85,93) using indexed postincrement addressing. Did you change the
address of AVGC? Remove code used for the other forms of addressing.
b) Why was the D register used for arithmetic rather than the A or B register.
2) Develop a program to sort the temperature data in Problem 1. It should put the highest
temperature into memory location $1000, the next highest into $1001, etc. The program should
include the capability to stop when all of the data has been sorted. Put the data in memory
starting in location $900 and ORG the program at $800. Use the X and Y index registers to help
address the data and the new memory locations.
3) A program for moving bytes in memory, Memory Copy, is referred to on the class Notes page.
Modify the program to move 3 16-bit words. The data definition should now be,
DW $8791,$0251,$6444.
4) Compare the following sets of two numbers and determine which of the instructions below will
result in a Branch (Y or N). Indicate in the left column if the instruction is signed or unsigned.
A Branch program is referred to on the class Notes page which you could modify and use to
check your work. Just to be clear on the order (CONST2 – DATA2) or,
ldaa CONST2
cmpa DATA2
Number Signed - s CONST2 2C B3 D4

Unsigned -us DATA2 C5 6D C3
1 bge
2 ble
3 bgt
4 blt
5 beq
6 bne
7 bhs
8 bls
9 bhi
10 blo
11 bmi
12 bpl
13 brn
14 bvs
15 bvc
5) Fill in the table with the register contents after executing each of the instructions in the program
sequence below. The initial register contents are; A=$05, B=$28, X=$900, and Y=$1000. The
memory reference needed by some of the instructions should be $1050 at which the following
bytes should be located $65,$E1. For the last 2 instructions in the sequence assume that the
carry bit is set (SEC) prior to executing the instruction.
A B D X Y
05 28 0528 0900 1000
ABA
ABX
ABY
ADDA $1050
ADDB $1050
ADDD $1050
ADCA $1050
ADCB $1050
6) Write a program to check your answers for Problem 5. Provide the listing and show that your
program works by giving the value of all 8 condition bits after executing the last instruction.
7) Suppose the registers contain the following: X=$09BD, Y=$1020, D=$3C8D and SP=$8000.
Fill in the register and memory contents as the following program sequence is executed.
A B X Y SP 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000
3C 8D 09BD 1020
pshd
pshx
pshy
pulb
pula
puld
8) Write a program which will take the difference between each number in two lists of 10 numbers,
sum the differences and compare that sum with the differences of the two sums of the original
numbers!! In other words, perform the following operation on the decimal numbers in the two
lists below:
Number List 1 List 2 Differences
1 85 45
2 21 33
3 73 88
4 64 99
5 78 22
6 98 11
7 34 77
8 56 42
9 13 65
10 55 89
Sum = ? Sum = ? Sum of diff = ?
Program should show that Sum1 – Sum2 equals the Sum of the differences.
; hw3p4s03
;
PROG: EQU $800
CONST1: EQU $2C
DATA1: EQU $C5
CONST2: EQU $B3
DATA2: EQU $6D
CONST3: EQU $D4
DATA3: EQU $C3
ORG PROG
; 1st tests, 2C - C5
lds #$1000
clc ; p1
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbge BRANCH1 ;Y
pulx ; if no BRANCH reset SP
clc ; p2
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lble BRANCH1 ;N
clc ; p3
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbgt BRANCH1 ;Y
clc ; p4
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lblt BRANCH1 ;N
clc ; p5
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbeq BRANCH1 ;N
clc ; p6
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbne BRANCH1 ;Y
clc ; p7
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbhs BRANCH1 ;N
clc ; p8
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbls BRANCH1 ;Y
clc ; p9
clv
ldaa #CONST1
cmpa #DATA1
leax $8,PC
pshx
lbhi BRANCH1 ;N
clc ; p10
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
blo BRANCH1 ;Y
clc ; p11
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bmi BRANCH1 ;N
pulx
clc ; p12
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bpl BRANCH1 ;Y
pulx
clc ; p13
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
brn BRANCH1 ;N
pulx
clc ; p14
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bvs BRANCH1 ;N
pulx
clc ; p15
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bvc BRANCH1 ;Y
pulx
clc ; p16
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bge BRANCH1 ;Y
pulx
clc ; p17
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bgt BRANCH1 ;Y
pulx
clc ; p18
clv
ldaa #CONST1
cmpa #DATA1
leax $6,PC
pshx
bhi BRANCH1 ;N
pulx
nop
bra NEXT2
BRANCH1: nop
rts
; B3 - 6D
NEXT2:
clc ; p1
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbge BRANCH2 ;N
clc ; p2
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lble BRANCH2 ;Y
clc ; p3
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbgt BRANCH2 ;N
clc ; p4
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lblt BRANCH2 ;Y
clc ; p5
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbeq BRANCH2 ;N
clc ; p6
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbne BRANCH2 ;Y
clc ; p7
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbhs BRANCH2 ;Y
clc ; p8
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbls BRANCH2 ;N
clc ; p9
clv
ldaa #CONST2
cmpa #DATA2
leax $8,PC
pshx
lbhi BRANCH2 ;Y
clc ; p10
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
blo BRANCH2 ;N
clc ; p11
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bmi BRANCH2 ;N
pulx
clc ; p12
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bpl BRANCH2 ;Y
pulx
clc ; p13
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
brn BRANCH2 ;N
pulx
clc ; p14
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bvs BRANCH2 ;Y
pulx
clc ; p15
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bvc BRANCH2 ;N
pulx
clc ; p16
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bge BRANCH2 ;N
pulx
clc ; p17
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bgt BRANCH2 ;N
pulx
clc ; p18
clv
ldaa #CONST2
cmpa #DATA2
leax $6,PC
pshx
bhi BRANCH2 ;Y
pulx
nop
bra NEXT3
BRANCH2: nop
rts
; B3 - 6D
NEXT3:
clc ; p1
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbge BRANCH3 ;Y
clc ; p2
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lble BRANCH3 ;N
clc ; p3
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbgt BRANCH3 ;Y
clc ; p4
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lblt BRANCH3 ;N
clc ; p5
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbeq BRANCH3 ;N
clc ; p6
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbne BRANCH3 ;Y
clc ; p7
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbhs BRANCH3 ;Y
clc ; p8
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbls BRANCH3 ;N
clc ; p9
clv
ldaa #CONST3
cmpa #DATA3
leax $8,PC
pshx
lbhi BRANCH3 ;Y
clc ; p10
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
blo BRANCH3 ;N
clc ; p11
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bmi BRANCH3 ;N
pulx
clc ; p12
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bpl BRANCH3 ;Y
pulx
clc ; p13
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
brn BRANCH3 ;N
pulx
clc ; p14
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bvs BRANCH3 ;N
pulx
clc ; p15
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bvc BRANCH3 ;Y
pulx
clc ; p16
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bge BRANCH3 ;Y
pulx
clc ; p17
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bgt BRANCH3 ;Y
pulx
clc ; p18
clv
ldaa #CONST3
cmpa #DATA3
leax $6,PC
pshx
bhi BRANCH3 ;Y
pulx
nop
swi
BRANCH3: nop
rts
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/hw3p7s03.txt
; hw3p7s03
; sort temperature data
; put highest temp in $1000
PROG: EQU $800
DATA: EQU $900
DEST: EQU $1000
HTEMP: EQU $18F6
HTEMPLOC: EQU $18F8 ; location of highest temp in a scan of the data
DAYCT: EQU $18FA
DAYTOT: EQU $18FB
SCANS: EQU $18FC
SCANCT: EQU $18FE
DAYS: EQU !7 ; number of days temp recorded minus 1
; x is DATA list counter
; y is Destination list counter
; DATA list is scanned for highest temp
; When found, that temp is moved to Destination
; and that zero is put in place of the temp in DATA
org PROG
ldab #$0 ; start SCANCT at zero
stab SCANCT ;
loop1: nop ; start of top of DATA list to get biggest temp
ldaa #DAYS
deca
staa DAYCT
staa DAYTOT
ldx #DATA
ldd !0,x ; get temp from top of list
std HTEMP ; value of highest temp for this scan of data
stx HTEMPLOC ; location of highest temp for this scan of data
loop2: ldd HTEMP
cpd !2,+x
bgt keep ; if new temp is not higher move to next temp
ldd $0,x ; new temp is higher, so put it in HTEMP
std HTEMP
stx HTEMPLOC ; get the new higher temp
keep: nop
dec DAYCT
ldaa DAYCT
bgt loop2 ; branch if not all temps have been tested in this scan
;
; all data tested this scan. store the biggest temp in Dest
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/hw3p7s03.txt (1 of 2) [06Nov07 22:48:37 ]

ldx #DEST
ldaa SCANCT
ldab #$2
mul
movw HTEMP,b,x
ldd #$0
ldx HTEMPLOC
std $0,x
inc SCANCT
ldaa SCANCT
cmpa #DAYS
blt loop1
swi
org DATA
DW !74,!78,!83,!91,!87,!85,!93

EE 2361 Fall 2003
Turn in type-written pages for programs you develop for these problems.
1) A program for computing Average Temperature is referred to on the class Notes page.
a) Modify the program to find the average for the following 7 days of temperatures
(74,78,83,91,87,85,93) using indexed postincrement addressing. Did you change the address of
AVGC? Remove code used for the other forms of addressing.
b) Why was the D register used for arithmetic rather than the A or B register.
DATA: EQU $900
AVGC: EQU $910 ; calculated average temperature this week
AVGD: EQU !69 ; average temperature for time of year
DELT: EQU $906 ; temp diff, this week minus avg year
DAYS: EQU !7 ; number of days temp recorded
org PROG
ldd #$0
ldx #DAYS
ldy #DATA
loop: nop
addd $2,y+
dbne x,loop
ldx #DAYS
idiv
stx AVGC
org DATA
DW !74,!78,!83,!91,!87,!85,!93
Average temp = $54 = !84
D was used because the sum exceeded 1 byte.
2) Develop a program to sort the temperature data in Problem 1. It should put the highest temperature
into memory location $1000, the next highest into $1001, etc. The program should include the
capability to stop when all of the data has been sorted. Put the data in memory starting in location
$900 and ORG the program at $800. Use the X and Y index registers to help address the data and
the new memory locations.
Solution will be provided next week when this problem is due to be handed in.
3) A program for moving bytes in memory, Memory Copy, is referred to on the class Notes page.
Modify the program to move 3 16-bit words. The data definition should now be, DW
$8791,$0251,$6444.
memcpy: equ $800
words: equ !3 ; Number of words to copy: Must be at least 1
source: equ $900 ; X, Source address
dest: equ $A00 ; Y, Destination Address
; Trashes D, X, Y
org source
DW $8791,$0251,$6444
org memcpy
ldx #source
ldy #dest
ldd #words
loop: nop
movw $2,x+,$2,y+
dbne D,loop
nop
4) Compare the following sets of two numbers and determine which of the instructions below will
result in a Branch (Y or N). Indicate in the left column if the instruction is signed or unsigned. A
Branch program is referred to on the class Notes page which you could modify and use to check
your work. Just to be clear on the order (CONST2 – DATA2) or,
ldaa CONST2
cmpa DATA2
Number Signed - s CONST2 2C B3 D4

Unsigned -us DATA2 C5 6D C3
1 S bge Y N Y
2 S ble N Y N
3 S bgt Y N Y
4 S blt N Y N
5 S beq N N N
6 S bne Y Y Y
7 U bhs N Y Y
8 U bls Y N N
9 U bhi N Y Y
10 U blo Y N N
11 S bmi N N N
12 S bpl Y Y Y
13 - brn N N N
14 S bvs N Y N
15 - bvc Y N Y
See class Notes web page for program, Hw3p3f03
5) Fill in the table with the register contents after executing each of the instructions in the program
sequence below. The initial register contents are; A=$05, B=$28, X=$900, and Y=$1000. The
memory reference needed by some of the instructions should be $1050 at which the following
bytes should be located $65,$E1. For the last 2 instructions in the sequence assume that the carry
bit is set (SEC) prior to executing the instruction.
A B D X Y
05 28 0528 0900 1000
ABA 2D 28 2D28 0900 1000
ABX 2D 28 2D28 0928 1000
ABY 2D 28 2D28 0928 1028
ADDA $1050 92 28 9228 0928 1028
ADDB $1050 92 8D 928D 0928 1028
ADDD $1050 F8 6E F86E 0928 1028
ADCA $1050 5E 6E 5E6E 0928 1028
ADCB $1050 5E D4 5ED4 0928 1028
6) Write a program to check your answers for Problem 5. Provide the listing and show that your
program works by giving the value of all 8 condition bits after executing the last instruction.
SHXIN.V.
; hw3p4s03
prog equ 800
org prog
ldd #$65E1
std $1050
ldd #$0528
ldx #$900
ldy #$1000
ABA
ABX
ABY
ADDA $1050
ADDB $1050
ADDD $1050
SEC
ADCA $1050
SEC
ADCB $1050
nop
7) Suppose the registers contain the following: X=$09BD, Y=$1020, D=$3C8D and SP=$8000. Fill
in the register and memory contents as the following program sequence is executed.
A B X Y 7ffa SP 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000
3C 8D 09BD 1020
pshd 7ffe 3C 8D
pshx 7ffc 09 BD
pshy 7ffa 10 20
pulb 10 7ffb
pula 20 7ffc
puld 09 BD 7ffe
8) Write a program which will take the difference between each number in two lists of 10 numbers,
sum the differences and compare that sum with the differences of the two sums of the original
numbers!! In other words, perform the following operation on the decimal numbers in the two lists
below:
Number List 1 List 2 Differences
1 85 45
2 21 33
3 73 88
4 64 99
5 78 22
6 98 11
7 34 77
8 56 42
9 13 65
10 55 89
Sum = $241 Sum = $23B Sum of diff = $6
Program shows that Sum1 – Sum2 equals the Sum of the differences.
; hw3p8s03
; sums and differences
prog equ $800
sums equ $900
data equ $910
ndata equ !10
org sums
sum1 ds !2
sum2 ds !2
sumd ds !2
org data
data1 dw !85,!21,!73,!64,!78,!98,!34,!56,!13,!55
data2 dw !45,!33,!88,!99,!22,!11,!77,!42,!65,!89
org prog
lds #ndata
ldd #$0
std sum1
std sum2
std sumd
ldx #data1
ldy #data2
loop ldd 0,x
subd 0,y
addd sumd
std sumd
ldd sum1
addd 2,x+
std sum1
ldd sum2
addd 2,y+
std sum2
dbne sp,loop
ldd sum1
subd sum2
cpd sumd
bne bad
nop
bad swi
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/HW4P1.txt
;****************************************
; Homework #4
; Problem #1
; Merge and Sort
; James Lamberg
; Feb. 17th, 2003
;****************************************
program equ $0800

list1 equ $0900
list2 equ $1000
low equ $1100
high equ $1200
merged equ $1300
nlist1 equ !8
nlist2 equ !6
nmerged equ !14
;****************************************
; define lists one and two
;****************************************
org list1
db $E5,$43,$98,$BE,$72,$11,$00,$81
org list2
db $23,$91,$61,$36,$AA,$E5
;****************************************
; begin main program
;****************************************
org program
;****************************************
; move list1 to merged with loop
;****************************************
ldaa #nlist1
ldx #list1
ldy #merged
looplist1: ; moves accum x to accum y
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/HW4P1.txt (1 of 3) [06Nov07 22:48:38 ]

movb 1,x+,1,y+
deca
bne looplist1 ; loop until end of list
;****************************************
; move list2 to merged with loop
;****************************************
ldaa #nlist2
ldx #list2
ldy #merged
looplist2: ; moves accum x to accum y nlist2 times

movb 1,x+,1,y+
deca
bne looplist2 ; loop until end of list
;****************************************
; sort merged list from bottom up
;****************************************
ldx #nmerged
loopsort:
cpy 1,-y ; compare to find largest byte
dex
bge swapbytes ; if current value is larger, swap
bne loopsort
swapbytes: ; swaps current value with compared value

ldab 0,y ; bottom number, smaller
ldaa 1,-y ; top number, larger
exg a,b
staa high
stab low
ldy high
iny
ldy low
dey ; move it up to a value
dey ; move it up to next
bra loopsort
nop

end

; hw4p1s03
; merge and sort 2 lists 8-bit arithmetic
PROG: EQU $800
DATA: EQU $900
DEST: EQU $1000
VARS: EQU $1800
SCANS: EQU !13 ; total number of values minus 1
VALUES: EQU !14
org DATA
LIST1 DB $E5,$43,$98,$BE,$72,$11,$00,$81
LIST2 DB $23,$91,$61,$36,$AA,$E5
org VARS
HDATA: DS !2 ; value of highest number from 2 lists
HDATALOC: DS !2 ; location of highest value in a scan of the data
DATACT: DS !1 ; current number of data item being compared
SCANCT: DS !1 ; number of values placed in Destination
DATATOT: DS !1 ; total number of values of both lists

; list1 and list2 are scanned for highest value
; When found, that data is moved to Destination
; and that zero is put in place of the value in DATA
org PROG
stab SCANCT ;
loop1: nop ; start of top of DATA list to get biggest value
ldaa #VALUES
deca
staa DATACT
staa DATATOT
ldx #DATA ; location of data list
ldaa !0,x ; get temp from top of list
staa HDATA ; value of highest temp for this scan of data
stx HDATALOC ; location of highest temp for this scan of data
loop2: ldaa HDATA
cmpa !1,+x
bgt keep ; if new data is not higher move to next temp
ldaa $0,x ; new data is higher, so put it in HTEMP
staa HDATA
stx HDATALOC ; get the new higher temp

keep: nop
dec DATACT
ldaa DATACT
bgt loop2 ; branch if not all values have been tested in this scan
; all data tested this scan. store the biggest value in Dest
ldx #DEST
ldab SCANCT
movb HDATA,b,x
ldaa #$81
ldx HDATALOC
staa $0,x
inc SCANCT
ldaa SCANCT
cmpa #VALUES
blt loop1
swi

; hw4p2s03
prog equ $800
data equ $900
bincts equ $940
scorect equ $950
nscores equ !26
bin1 equ !20
bin2 equ !40
bin3 equ !60
bin4 equ !80
bin5 equ !100
org data
scores1 DW !76,!89,!23,!45,!12,!70,!90,!56,!87,!28,!69
scores2 DW !21,!47,!98,!11,!54,!89,!23,!72,!79,!35,!34
scores3 DW !89,!44,!88,!55
org bincts
bin1ct ds !2
bin2ct ds !2
bin3ct ds !2
bin4ct ds !2
bin5ct ds !2
org prog
ldaa #nscores
std scorect
ldd #$0
std bin1ct ; initialize the bin counts
std bin2ct
std bin3ct
std bin4ct
std bin5ct
ldx #data ; starting address of scores
loop ldd 2,x+ ; get score
cpd #bin1 ; compare with 20
bgt next2
inc bin1ct
bra checkct
next2 nop
cpd #bin2
bgt next3
inc bin2ct
bra checkct

next3 nop
cpd #bin3
bgt next4
inc bin3ct
bra checkct
next4 nop
cpd #bin4
bgt next5
inc bin4ct
bra checkct
next5 inc bin5ct
checkct ldaa scorect ; have all scores been counted?
deca
staa scorect
bne loop
nop

; hw4p3s03
; W = 0.9*V + 7
; V: 345 271 684 35 921 237 833 912 348 1049
prog equ $800 ; start of program

data equ $900
rslts equ $1000
vars equ $1100
ndata equ !10
ndata2 equ !20 ; 2 times number of values,words
offset equ !7
org vars
scale ds !2
datact ds !1
org data
dw !345,!271,!684,!35,!921,!237,!833,!912,!348,!1049
org prog
ldd #$9
ldx #$10
fdiv
stx scale
ldaa #$0
staa datact
loop: ldaa datact
ldx #data
ldy a,x
ldd scale
emul
tfr y,d
addd #offset
tfr d,y
ldaa datact
ldx #rslts
std a,x
; stored adjusted data value
; check for end of data
ldaa datact
inca
inca
staa datact
suba #ndata2
bne loop

nop

; hw4ps03
; 59*U + 235/V = W
prog equ $800

temp equ $900
org temp
ds !2
org prog
nop ; U=4 V=21
ldd #!235
ldx #!21
idiv
ldaa #!59
ldab #!4
mul
stab temp
tfr x,d
addb temp
nop ; result is $f7 = 247
ldd #!235
ldx #!21
idiv
ldd #!59
ldy #!4
emul
std temp
tfr x,d
addd temp
ldd #!235 ; U=451 V=3
ldx #!3
idiv
ldd #!59
ldy #!451
emul
std temp
tfr x,d
addd temp ; result is !26687 = $683f
nop


; ship problem hw4p7s03

; Ship A is traveling at 95 miles per hour.
; Radar detects ship B ahead traveling at 35 miles per hour and 800 miles ahead.
; The speed of ship A can be reduced by $5 miles per hour each
; time your program loop is executed. Each time the loop is executed, 2 hours pass.
; From the time the radar detects ship B 2 hours pass.
; Write a program will reduce the speed of ship A to be less than or equal to ship B
; and will determine the distance between ships when this is achieved.
prog equ $800

ts equ !2 ; 2 hours for each loop
variables equ $900
org variables
spdastart dw !95 ; speed of ship A at start
spdb dw !35 ; speed of ship B
spda ds !2 ; speed of ship A
spdiff ds !2 ; difference in speed between A and B
sepstart dw !800 ; 800 miles initial separation
sep ds !2 ; distance between ships
org prog
ldd sepstart ; initialize variables
std sep
ldd spdastart
std spda
; start loop
loop ldd spdb
subd spda
std spdiff
ldd sep
addd spdiff
addd spdiff
std sep
ldd spda
subd #!5
std spda
cpd spdb
bne loop
nop

; final separation equals $14 or 20 miles

EE 2361 Fall 2003
8 problems
1) Develop a program to merge two lists of signed-hex numbers in a single list ordered
from largest to smallest starting at $900. The lists differ in length.
Include comments with the instructions.
Provide a paragraph description of how the program works.
List1 E5 43 98 BE 72 11 00 81
List2 23 91 61 36 AA E5 none none
2) Develop a program to build a histogram of student test scores. The program counts
the number of scores in each of 5 16-bit bins starting at $900.
Provide comments with the code.
Scores: 76 89 23 45 12 70 90 56 87 28 69 21 47 98 11 54 89 23 72 79 35 34 89 44 88 55
Bins: 0 to 20, 21 to 40, 41 to 60, 61 to 80, 81 to 100
3) Develop a program to correct instrument readings using the following equation:

W = 0.9*V + 7 where V is the instrument reading and W is the corrected value.
Use a divide instruction to implement the value 9/10 and throw away the
fractional part of multiplication result.
Run the program on the following decimal data and give the hex outputs.
V: 345 271 684 35 921 237 833 912 348 1049
4) Develop a program that performs the arithmetic operation, 59*U + 235/V = W

Give the hex results for the decimal inputs and compare using a calculator.
List the register contents (A,B,X,Y,SP) as each instruction is executed.
U V W Calculator
8-bit operations 4 21
5) Conversion & condition problems
a) Convert the signed binary number, 101010101 to decimal.
b) Convert the following decimal number, -692378 to hex.

6) Give the addressing mode and the effective address for each of the following
instructions. Assume that index register X contains $A43E, index register Y contains
$BE45, and accumulator D contains $67E2.
stx !6,+y
stx !266,y
sty A,x
sty $1045
stx $23
7) Ship A is traveling at 95 miles per hour. Radar detects ship B ahead traveling at 35
miles per hour and 800 miles ahead. The speed of ship A can be reduced by $5 miles
per hour each time your program loop is executed. Each time the loop is executed, 2
hours pass. From the time the radar detects ship B 2 hours pass. Write a program
that will reduce the speed of ship A to be less than or equal to ship B and will
determine the distance between ships when this is achieved.
8) Complete Problem #2 from last week’s homework.

EE 2361 Fall 2003
1) Develop a program to merge two lists of signed-hex numbers in a single list ordered
from largest to smallest starting at $900. The lists differ in length.
Include comments with the instructions.
List1 E5 43 98 BE 72 11 00 81
List2 23 91 61 36 AA E5 none none
; hw4p1s03
; merge and sort 2 lists 8-bit arithmetic
PROG: EQU $800
DATA: EQU $900
DEST: EQU $1000
VARS: EQU $1800
SCANS: EQU !13 ; total number of values minus 1
VALUES: EQU !14
org DATA
LIST1 DB $E5,$43,$98,$BE,$72,$11,$00,$81
LIST2 DB $23,$91,$61,$36,$AA,$E5
org VARS
HDATA: DS !2 ; value of highest number from 2 lists
HDATALOC: DS !2 ; location of highest value in a scan of the data
DATACT: DS !1 ; current number of data item being compared
SCANCT: DS !1 ; number of values placed in Destination
DATATOT: DS !1 ; total number of values of both lists

; list1 and list2 are scanned for highest value
; When found, that data is moved to Destination
; and that zero is put in place of the value in DATA
org PROG
stab SCANCT ;
loop1: nop ; start of top of DATA list to get biggest value
ldaa #VALUES
deca
staa DATACT
staa DATATOT
ldx #DATA ; location of data list
ldaa !0,x ; get temp from top of list
staa HDATA ; value of highest temp for this scan of data
stx HDATALOC ; location of highest temp for this scan of data
loop2: ldaa HDATA
cmpa !1,+x
bgt keep ; if new data is not higher move to next temp
ldaa $0,x ; new data is higher, so put it in HTEMP
staa HDATA
stx HDATALOC ; get the new higher temp
keep: nop
dec DATACT
ldaa DATACT
bgt loop2 ; branch if not all values have been tested in this scan
; all data tested this scan. store the biggest value in Dest
ldx #DEST
ldab SCANCT
movb HDATA,b,x
ldaa #$81
ldx HDATALOC
staa $0,x
inc SCANCT
ldaa SCANCT
cmpa #VALUES
blt loop1
swi
2) Develop a program to build a histogram of student test scores. The program counts
the number of scores in each of 5 16-bit bins starting at $900.
Scores: 76 89 23 45 12 70 90 56 87 28 69 21 47 98 11 54 89 23 72 79 35 34 89 44 88 55
Bins: 0 to 20, 21 to 40, 41 to 60, 61 to 80, 81 to 100
prog equ $800

data equ $900
bincts equ $940
scorect equ $950
nscores equ !26
bin1 equ !20
bin2 equ !40
bin3 equ !60
bin4 equ !80
bin5 equ !100
org data
scores1 DW !76,!89,!23,!45,!12,!70,!90,!56,!87,!28,!69
scores2 DW !21,!47,!98,!11,!54,!89,!23,!72,!79,!35,!34
scores3 DW !89,!44,!88,!55
org bincts
bin1ct ds !2
bin2ct ds !2
bin3ct ds !2
bin4ct ds !2
bin5ct ds !2
org prog
ldaa #nscores
std scorect
ldd #$0
std bin1ct ; initialize the bin counts
std bin2ct
std bin3ct
std bin4ct
std bin5ct
ldx #data ; starting address of scores
loop ldd 2,x+ ; get score
cpd #bin1 ; compare with 20
bgt next2
inc bin1ct
bra checkct
next2 nop
cpd #bin2
bgt next3
inc bin2ct
bra checkct
next3 nop
cpd #bin3
bgt next4
inc bin3ct
bra checkct
next4 nop
cpd #bin4
bgt next5
inc bin4ct
bra checkct
next5 inc bin5ct
checkct ldaa scorect ; have all scores been counted?
deca
staa scorect
bne loop
nop
3) Develop a program to correct instrument readings using the following equation:
W = 0.9*V + 7 where V is the instrument reading and W is the corrected value.
Use a divide instruction to implement the value 9/10 and throw away the
fractional part of multiplication result.
Run the program on the following decimal data and give the hex outputs.
V: 345 271 684 35 921 237 833 912 348 1049
prog equ $800 ; start of program

data equ $900
rslts equ $1000
vars equ $1100
ndata equ !10
ndata2 equ !20 ; 2 times number of values,words
offset equ !7
org vars
scale ds !2
datact ds !1
org data
dw !345,!271,!684,!35,!921,!237,!833,!912,!348,!1049
org prog
ldd #$9
ldx #$10
fdiv
stx scale
ldaa #$0
staa datact
loop: ldaa datact
ldx #data
ldy a,x
ldd scale
emul
tfr y,d
addd #offset
tfr d,y
ldaa datact
ldx #rslts
std a,x
; stored adjusted data value
; check for end of data
ldaa datact
inca
inca
staa datact
suba #ndata2
bne loop
nop
4) Develop a program that performs the arithmetic operation, 59*U + 235/V = W

Give the hex results for the decimal inputs and compare using a calculator.
List the register contents (A,B,X,Y,SP) as each instruction is executed.
U V W Calculator
prog equ $800
temp equ $900
org temp
ds !2
org prog
nop ; U=4 V=21
ldd #!235
ldx #!21
idiv
ldaa #!59
ldab #!4
mul
stab temp
tfr x,d
addb temp
ldd #!235
ldx #!21
idiv
ldd #!59
ldy #!4
emul
std temp
tfr x,d
addd temp
ldd #!235 ; U=451 V=3
ldx #!3
idiv
ldd #!59
ldy #!451
emul
std temp
tfr x,d
addd temp ; result is !26687 = $683f
nop
5) Conversion & condition problems
a) Convert the signed binary number, 101010101 to decimal.

101010101
010101010
+1
010101011
1*27 + 0*26 + 1*25 + 0*24 + 1*23 + 0*22 +1*21 + 1*20 = 128+32+8+2+1 = 171 → -171
b) Convert the following decimal number, -692378 to hex.

0 ← 10 ← 169 ← 2704 ← 43273 ← 692378 / 16
↓ ↓ ↓ ↓ ↓
A 9 0 9 A
6) Give the addressing mode and the effective address for each of the following
instructions. Assume that index register X contains $A43E, index register Y contains
$BE45, and accumulator D contains $67E2.
stx !6,+y indexed preincrement, $BE4A

stx !266,y indexed constant, $6F4F
sty A,x indexed accumulator, $A448
sty $1045 extended, $1045
stx $23 direct, $23
7) Ship A is traveling at 95 miles per hour. Radar detects ship B ahead traveling at 35
miles per hour and 800 miles ahead. The speed of ship A can be reduced by $5 miles
per hour each time your program loop is executed. Each time the loop is executed, 2
hours pass. From the time the radar detects ship B 2 hours pass. Write a program
will reduce the speed of ship A to be less than or equal to ship B and will determine
the distance between ships when this is achieved.
prog equ $800

ts equ !2 ; 2 hours for each loop
variables equ $900
org variables
spdastart dw !95 ; speed of ship A at start
spdb dw !35 ; speed of ship B
spda ds !2 ; speed of ship A
spdiff ds !2 ; difference in speed between A and B
sepstart dw !800 ; 800 miles initial separation
sep ds !2 ; distance between ships
org prog
ldd sepstart ; initialize variables
std sep
ldd spdastart
std spda
; start loop
loop ldd spdb
subd spda
std spdiff
ldd sep
addd spdiff
addd spdiff
std sep
ldd spda
subd #!5
std spda
cpd spdb
bne loop
nop
; final separation equals $14 or 20 miles
8) Complete Problem #2 from last week’s homework.

; hw3p7s03
; sort temperature data
PROG: EQU $800
DATA: EQU $900
DEST: EQU $1000
HTEMP: EQU $18F6
HTEMPLOC: EQU $18F8 ; location of highest temp in a scan of the data
DAYCT: EQU $18FA
DAYTOT: EQU $18FB
SCANS: EQU $18FC
SCANCT: EQU $18FE
DAYS: EQU !7 ; number of days temp recorded minus 1
; DATA list is scanned for highest temp
; When found, that temp is moved to Destination
; and that zero is put in place of the temp in DATA
org PROG
stab SCANCT ;
loop1: nop ; start of top of DATA list to get biggest temp
ldaa #DAYS
deca
staa DAYCT
staa DAYTOT
ldx #DATA
ldd !0,x ; get temp from top of list
std HTEMP ; value of highest temp for this scan of data
stx HTEMPLOC ; location of highest temp for this scan of data
loop2: ldd HTEMP
cpd !2,+x
bgt keep ; if new temp is not higher move to next temp
ldd $0,x ; new temp is higher, so put it in HTEMP
std HTEMP
stx HTEMPLOC ; get the new higher temp
keep: nop
dec DAYCT
ldaa DAYCT
bgt loop2 ; branch if not all temps have been tested in this scan
;
; all data tested this scan. store the biggest temp in Dest
ldx #DEST
ldaa SCANCT
ldab #$2
mul
movw HTEMP,b,x
ldd #$0
ldx HTEMPLOC
std $0,x
inc SCANCT
ldaa SCANCT
cmpa #DAYS
blt loop1
swi
org DATA
DW !74,!78,!83,!91,!87,!85,!93
EE 2361 Fall 2003
8 problems
Write all of the code requested in problems 1 thru 6 as a single program. At the start of the program write
groups of Equate statements for constants and registers so that you can use labels in the code instead of
numbers (except Problem 4 – use a number in the code).
1. Set the COPCTL register to each of the following conditions:

a) Set the COPCTL to enable the clock monitor & timer rate = 1.049s (8mHz).
b) Set the COPCTL to disable the clock monitor, disable resets & timer rate = 0.262144s (8mHz).
2. Interrupt mask bit:

a) Set interrupt mask bit I to prevent interrupts.
b) Clear interrupt mask bit.
3. Set the Interrupt Control Register INTCR to generate an interrupt when IRQ at low level, enable
external interrupts and enable a 4096 clock delay before resuming processing when coming out of
STOP.
4. Select Key Wakeup H as highest priority.
5. Set inputs and outputs of Data Direction Register, DDRJ, to the following:
IN_BITS: EQU %00001111 ; Bits 3-0
O_BITS: EQU %11110000 ; Bits 7-4
6. Set the Key Wakeups using Port J

Choose IN_BITS Bits 3-0
Choose bit 3 and 2 for falling edge interrupts
Choose bits 1 and 0 for rising edge interrupts
Initialize data direction register
Select pull-ups for bits 3-0
Enable pull-ups
Set polarity bits 3-2 falling, bits 1-0 rising
Clear the flags register of any pending interrupt
Enable the interrupts
Unmask the I bit
7. What is the starting address for the interrupt vector table? What is the starting address for the RAM-
based interrupt vector table?
8. You are developing a Timer Channel 1 ISR for a new application.

a) If you are using a clean HC12 (not the EVB) in what memory location will you place the address
vector for you ISR?
b) If you are using the EVB in what memory location will you place the address vector for your
ISR?
c) When an interrupt occurs how does the 68HC12 determine if it should use the D-BUG12 ISR or
the user-defined ISR?
EE 2361 Fall 2003
Write all of the code requested in problems 1 thru 6 as a single program. At the start of the program write
groups of Equate statements for constants and registers so that you can use labels in the code instead of
numbers (except Problem 4 – use a number in the code).
1. Set the COPCTL and load the contents of COPCTL into A (clear COPCTL and clear A at the start of
each:
a) Set the COPCTL to enable the clock monitor & timer rate = 1.049s (8mHz).
b) Set the COPCTL to disable the clock monitor, disable resets & timer rate = 0.262144s (8mHz).
2. Interrupt mask bit:

a) Set interrupt mask bit I to prevent interrupts.
b) Clear interrupt mask bit.
3. Set the Interrupt Control Register INTCR to generate an interrupt when IRQ at low level, enable
external interrupts and enable a 4096 clock delay before resuming processing when coming out of
STOP.
4. Write a code sequence to Select Key Wakeup H as highest priority.
5. Write a code sequence to set inputs and outputs of Data Direction Register, DDRJ, to the following:
IN_BITS: EQU %00001111 ; Bits 3-0
O_BITS: EQU %11110000 ; Bits 7-4
6. Write a code sequence to set up the Key Wakeups using Port J

Choose IN_BITS Bits 3-0
Choose bit 3 and 2 for falling edge interrupts
Choose bits 1 and 0 for rising edge interrupts
Initialize data direction register
Select pull-ups for bits 3-0
Enable pull-ups
Set polarity bits 3-2 falling, bits 1-0 rising
Clear the flags register of any pending interupt
Enable the interrupts
Unmask the I bit
; hw5f02
; Interrupt code
;
; Computer Operating Properly Control Register equates
COPCTL: EQU $16
COPRST: EQU $17
CME: EQU %10000000 ; Clock Monitor Enable
FCME: EQU %01000000 ; Force Clock Monitor Enable
FCM: EQU %00100000 ; Force Clock Monitor Reset
FCOP: EQU %00010000 ; Force COP Watchdog Reset
DISR: EQU %00001000 ; Disable resets from COP Watchdog and Clock Monitor
; Interrupt Bit equates
SETI: EQU %00010000 ; sets interrupt mask bit I, prevents interrupts
CLEARI: EQU %11101111 ; clears interrupt mask bit
; Interrupt Control Register equates
INTCR: EQU $1E ; location of INTCR
IRQEN: EQU %01000000 ; External IRQ (and key Wakeup D signals are enabled
DLY: EQU %00100000 ; Enable a 4096 clock delay before resuming processing
; when coming out of STOP
; High Priority Interrup equates
HPRIO: EQU $1F ; HPRIO is at $1F
; Key Wakeups using Port J equates
KWIEJ: EQU $2A ; Key Wakeup Interrupt Enable Register
KWIFJ: EQU $2B ; Flags register
KPOLJ: EQU $2C ; Key Wakeup Port J polarity Register
PUPSJ EQU $2D ; Pull-up select
PULEJ EQU $2E ; Enable pull-ups
PORTJ: EQU $28 ; Data register
DDRJ: EQU $29 ; Data direction register
IN_BITS: EQU %00001111 ; Bits 3-0
O_BITS: EQU %11110000 ; Bits 7-4
FALLING: EQU %00001100 ; Choose bit 3 and 2 for falling edge interrupts
RISING: EQU %00000011 ; Choose bits 1 and 0 for rising edge interrupts
; Constant equates
WDTR1: EQU %00000111 ; COP Watchdog Timer Rate = 1.049s
WDTR2 EQU %00000101 ; COP Watchdog Timer Rate = 0.262144s
; Memory Map equates
CODE: EQU $0800
DATA: EQU $0900
STACK: EQU $0a00
;
; problem 1
; set the COPCTL to enable the clock monitor & timer rate = 1.049s (8mHz)
org CODE
lds #STACK
clr COPCTL
clra
bset COPCTL,CME|WDTR1
ldaa COPCTL
nop
; set the COPCTL to disable the clock monitor, disable resets & timer rate = 0.262144s (8mHz)
clr COPCTL
clra
bset COPCTL,DISR|WDTR2
ldaa COPCTL
nop
; problem 2 - set and clear the interrupt mask bit
orcc #SETI ; sets interrupt mask bit I, prevents interrupts
andcc #CLEARI ; clears interrupt mask bit
; problem 3
; Set the Interrupt Control Register to generate an interrupt when at low level,
; enable external interrupts and enable a 4096 clock delay before resuming processing
; when coming out of STOP.
clc
clra
bset INTCR,IRQEN|DLY ; enables IRQs, enables 4096 clock after coming
; out of STOP
ldaa INTCR
; problem 4
; Code sequence to Select Key Wakeup J as highest priority
ldaa #$D0 ; from Interrupt Vector Map, p215, KWIEH HPRIO value
staa HPRIO
; problem 5
; Initialize Data Direction Register, DDRJ
bset DDRJ,O_BITS
bclr DDRJ,IN_BITS
; problem 6
; Code sequence to set up the Key Wakeups using Port J
; Initialize data direction register
bset DDRJ,O_BITS
bclr DDRJ,IN_BITS
;Select pull-ups for bits 3-0
bset PUPSJ,IN_BITS
; Enable pull-ups
bset PULEJ,IN_BITS
; Set polarity bits 3-2 falling, bits 1-0 rising
bclr KPOLJ,FALLING
bset KPOLJ,RISING
; Clear the flags register of any pending interupt
ldaa #IN_BITS
staa KWIFJ
; Now it is safe to enable the interrupts
bset KWIEJ,IN_BITS
; Unmask I bit
cli
7. What is the starting address for the interrupt vector table? What is the starting address for the RAM-
based interrupt vector table?
$FFCE
$0B0E
8. You are developing a Timer Channel 1 ISR for a new application.

a) If you are using a clean HC12 (not the EVB) in what memory location will you place the starting
address for you ISR?
b) If you are using the EVB in what memory location will you place the starting address for your
ISR?
c) When an interrupt occurs how does the 68HC12 determine if it should use the D-BUG12 ISR or
the user-defined ISR?
PROG: EQU $800

org PROG
ldd #$6000 ; location of user-ISR
; $6000 was selected by user
pshd
ldd #!22 ; relative location of IRQ
ldx $FE1A ; contains address of SetVect D-Bug12 monitor routine
jsr 0,x ; jump to monitor routine
nop ; return from monitor routine
b) $6000
c) address = $B2C
d) d) H12 looks in RAM-base interrupt vector table for a starting address. If empty H12 uses the
D-BUG 12 routine.
EE 2361 Spring 2003
Due: Thursday, March 6th
8 problems
Turn in typed pages for the programs you develop for these problems.
1) An analog signal has a spectrum (frequency content) that varies from 400 Hz to
5.9 KHz. It is to be sampled at a rate of 10,000 samples pr second. Is the sampling
rate adequate to allow reconstruction of the signal?
2) The 68HC12 ATD converter system converts each analog sample to an eight-bit,
unsigned binary value. What is the resolution of the converter? Assume the
reference voltages for the 68HC12 designated as VRH and VRL and 4 volts and 1
volts, respectively.
3) If the 68HC12 is improved such that each analog conversion yields an unsigned,
10-bit binary value, what is the resolution of the converter?
4) A 2 KHz sine wave is to be sampled using an ATD conversion system. What

should sampling frequency be?
5) In the previous question, how many bits of binary data are generated per second
assuming an eight-bit converter?
6) What is the dynamic range of the ATD system aboard the 68HC12? Explain.
7) What is aliasing? Describe two methods to avoid aliasing.
8) Write a program to power-up the ATD and provide a delay of 120 microseconds
before setting the registers.
EE 2361 Spring 2003
Due: Thursday, March 13
6 problems
1. For each of the signals fill in the table with values such that the sampling frequency
will be just high enough to accurately sample these signals (assume the P-clock is 8
MHz and that only 1 channel is being sampled continuously):
MHz
8.4
10.38
36.6
a) continuous scan of the upper 4 channels
b) single scan of the lower 4 channels
c) single scan of the upper 4 channels
d) single scan of all 8 channels
e) continuous scan of all 8 channels
f) single scan of channel 5, 4 conversions
g) continuous scan of channel 3, 4 conversions
3. For each part of Problem 2 give the register(s) name(s) and location(s) where the
result(s) will be placed.
4. Write a program to set up an interrupt to occur when a four-conversion sequence is

completed.
6. Write a program to clear the flag associated with the result register for channel 2 and
the SCF flag.
EE 2361 Spring 2003
Due: Thursday, March 13
6 problems
1. For each of the signals fill in the table with values such that the sampling frequency
will be just high enough to accurately sample these signals (assume the P-clock is 8
MHz and that only 1 channel is being sampled continuously):
MHz
8.4 11 0.571 8.92 00110
10.38 11 0.667 10.41 00101
36.6 00 1.33 36.9 00010
a) continuous scan of the upper 4 channels 0011 0100
b) single scan of the lower 4 channels 0001 0000
c) single scan of the upper 4 channels 0001 0100
d) single scan of all 8 channels 0101 0000
e) continuous scan of all 8 channels 0111 0000
f) single scan of channel 5 0000 0101
g) continuous scan of channel 3 0010 0011
3. For each part of Problem 2 give the register(s) name(s) and location(s) where the
result(s) will be placed.
4. Write a program to set up an interrupt when a four conversion sequence is

completed.
adtctl5 equ $65
ena_1 equ $10
adtctl2 equ $62
ena_2 equ $82
ldaa #ena_1
staa adtctl5
ldaa #ena_2
staa adtctl2

atdstat2 equ $67
loop: brclr atdstat,#$40,loop
6. Write a program to clear the flag associated with the result register for channel 2 and
the SCF flag.
atdctl2 equ $62
adr2h equ $74
set _bits equ $c0 ;to set affc and adpu bits
bset atdctl2,set_bits
ldaa adr2h ; read result register (clear SCF chn flags)
EE 2361 Spring 2003
1 problem
Turn in typed pages for the program you develop.

Check the web site regularly for revisions including code verification requirements.
;*******************************************************
; Description:
; This program is used to monitor two IR sensor values on ATD inputs PAD2 & PAD3
; using the 68HC12EVB. New samples are to be taken every 1 second.
;
; Perform the following operations for each scan of the IR inputs (store results in words
; starting in location $4000:
; 1) Simulate loading the inputs into the PAD2 and PAD3.
; 2) Update current sensor values in SENX and SENY locations.
; 2) Determine the rate of change in sensor values and update current rates in RATEX and RATEY locations.
; The rate equals the difference between the current sensor input value and the last value.
; 3) Based on the above data update a prediction as to how many seconds will elapse before each sensor
; will reach max value !255 (simulates hitting a wall). Sensor values are positive numbers 0 to 255.
; Store these in TIMEX and TIMEY.
; 4) Develop a weighted prediction for #3 using 0.8 of last rate and 0.2 of new rate and store the
; weighted rates in WRATEX and WRATEY.
; 5) Use the weighted rates to compute the number of seconds before each sensor will reach max value and
; store there in WTIMEX and WTIMEY.
Assume the initial values are,
DATAX 41
RATEX 1
WRATEX 1
DATAY 169
RATEY 1
WRATEY 1
;*******************************************************
; Testing procedure:
; Simulate the ATD converter results for 8 scans.
; Each scan cycle load the result registers with 2 values from the following sensor
; result values starting in location $4020.
; DATAX db !42,!45,!65,!90,!150,!200,!210,!215
; DATAY db !170,!174,!178,!195,!205,!211,!220,!237
; After testing and verifying your algorithm convert each of the lines of test code to a
; comment by putting ";" in front of the code.
;*******************************************************
; Code development:
; Document the code with comments. Be generous with use of words.
; Write all the program first without regard to testing.
; First write code to process one sensor and debug the code, then copy the code for the second sensor
; Fill in the testing code and put the word TEST in the comment line along with a note on what is happening.
; Then, take the test code blocks and put them in in subroutines.
; For testing put comments in front of code that will not execute without hardware; i.e., the simulator
; will not automatically load the result registers so the result registers will be empty.
; Don't forget the code needed to create a one second delay
;*******************************************************
;* Symbol Definitions *
;*******************************************************
;*******************************************************
;* Data Section
;*******************************************************
;*******************************************************
;* Main Program
;*******************************************************
Format for results (in addition to code). Repeat for DATAY
--------Calculator Results---------------- ------------------------------------------Microcontroller Results-----------------------------------
value rate time WRATE WTIME Rate timex wrate wtimex
dec hex dec hex dec hex dec hex dec
42
45
65
90
150
200
210
215
EE 2361 Spring 2003
1 problem

Check the web site regularly for revisions including code verification requirements.
; hw8p1s03
;*******************************************************
; Description:
; This program is used to monitor two IR sensor values on ATD inputs PAD2 & PAD3 using the
; 68HC12EVB. New samples are taken every 1 second.
;
; Perform the following operations for each scan of the IR inputs (store results in words
; starting in location $4000:
; 1) Simulate loading the inputs into the PAD
; 2) Update current sensor values in SENX and SENY locations.
; 2) Determine the rate of change in sensor values and update current rates in RATEX and RATEY locations.
; The rate equals the difference between the current sensor input value and the last value.
; 3) Based on the above data update a prediction as to how many seconds will elapse before each sensor
; will reach max value !255 (simulates hitting a wall). Sensor values are positive numbers 0 to 255.
; Store these in TIMEX and TIMEY.
; 4) Develop a weighted prediction for #3 using 0.8 of last rate and 0.2 of new rate and store the
; weighted rates in WRATEX and WRATEY.
; 5) Use the weighted rates to compute the number of seconds before each sensor will reach max value and
; store there in WTIMEX and WTIMEY.
Assume the initial values are,
DATAX 41
RATEX 1
WRATEX 1
DATAY 169
RATEY 1
WRATEY 1
;*******************************************************
; Testing procedure:
; Simulate the ATD converter results for 8 scans.
; Each scan cycle load the result registers with 2 values from the following sensor
; result values starting in location $4020.
; DATAX db !42,!45,!48,!52,!56,!60,!64,!70
; DATAY db !170,!174,!178,!195,!205,!211,!220,!237
; After testing and verifying your algorithm convert each of the lines of test code to a
; comment by putting ";" in front of the code.
;*******************************************************
; Code development:
; Document the code with comments. Be generous with use of words.
; Write all the program first without regard to testing.
; First write code to process one sensor and debug the code, then copy the code for the second sensor
; Fill in the testing code and put the word TEST in the comment line along with a note on what is happening.
; Then, take the test code blocks and put them in in subroutines.
; For testing put comments in front of code that will not execute without hardware; i.e., the simulator
; will not automatically load the result registers so the result registers will be empty.
; Don't forget the code needed to create a one second delay
;*******************************************************
;* Symbol Definitions *
;*******************************************************
REGBAS EQU $0000h ; base addresses
ATDCTL2 EQU $62 ; AD control register with ADPU bit
ATDCTL5 EQU $65 ; AD mode control register
ATDSTAT EQU $66 ; sequence complete flag register
ADR2H EQU $74 ; sensor X value
ADR3H EQU $76 ; sensor Y value
ADPU EQU %10000000 ; mask for ATD
MADCTL EQU %00010000 ; mask to choose multiple lower four channels converting once
STACK EQU $7FFF
SMALL EQU !50 ; weight for new RATE
LARGE EQU !150 ; weight for old RATE
NORM EQU !200 ; normalize value
;*******************************************************
;* Data Section
;*******************************************************
ORG $4000
SENX DS $02 ; sensor X
SENY DS $02 ; sensor Y
RATEX DS $02 ; rate of change in sensor X value
RATEY DS $02 ; rate of change in sensor Y value
TIMEX DS $02 ; predicted time to max X value
TIMEY DS $02 ; predicted time to max Y value
WRATEX DS $02 ; weighted rate of change in sensor X value
WRATEY DS $02 ; weighted rate of change in sensor Y value
WTIMEX DS $02 ; weighted time to max X value
WTIMEY DS $02 ; weighted time to max Y value
DCOUNT DS $02 ; pointer count for addressing data
TEMPWRATE DS $02 ; weighted new rate (X or Y)
ORG $4020
DATAX DB !42,!45,!65,!90,!150,!200,!210,!215
DATAY DB !170,!174,!178,!195,!205,!211,!220,!237
NDATA DW !8 ; number of pairs of sensor test values
;*******************************************************
;* Main Program
;*******************************************************
ORG $4100
LDS #STACK ; setup stack pointer
LDD #$1 ; setup minimum starting weights
STD WRATEX ; initialize WRATEX
STD WRATEY ; initialize WRATEY
LDX #$00
LDY #$00
MOVB DATAX,SENX+1 ; TEST, initialize SENX for testing algo
MOVB #$00,SENX ;
MOVB DATAY,SENY+1 ; TEST, initialize SENY for testing algo
MOVB #$00,SENY ;
LDAA #ADPU ; turn on ATD converter
STAA ATDCTL2
LDY #$C8 ; stabilize the ATD converter by delaying 100 usec
STALL DEY
; BNE STALL ;
;
; start sampling the sensors
LOOP1 LDAB #MADCTL ; start the AD converter
STAB ATDCTL5
; LOOP2 LDAB ATDSTAT ; wait until all sensor values are gathered
; BPL LOOP2
nop ; TEST, insert loading ADR2H with DATAX value
LDD #$00 ; TEST, initialize count of sensors values
STD DCOUNT ; TEST, count number of sensor values processed
LOOP3 NOP ; TEST
LDX DCOUNT ; TEST, prepare to fetch sensor values
LDAB DATAX,X ; TEST
STAB ADR2H ; TEST, store test sensor values into ADR2H
LDAB DATAY,X ; TEST
STAB ADR3H ; TEST, store test sensor values into ADR3H
INX ; TEST, increment count of senor values procressed
STX DCOUNT ; TEST
;
; start processing the X sensor value
; update the RATEX
LDAB ADR2H ; read new sensor X value into lower byte of D
LDAA #$00 ; clear the upper byte of D to form 16-bit positive value
SUBD SENX ; subtract last sensor X value to form new RATEX
BNE CONT ; check for zero rate
LDD #$01 ; if rate is zero force to be equal to a minumum, 1
CONT STD RATEX ; new RATEX stored
LDAB ADR2H ; store the new sensor value SENX
LDAA #$00 ;
STD SENX ; new sensor value is now in SENX
; update the TIMEX
; compute difference between current sensor value and max value
LDD #$00FF ; max sensor value
SUBD SENX ;
LDX RATEX ; current rate of closure (sensor value rate of change - delta value/sec)
IDIVS ;
STX TIMEX ; time to hit the wall
; update the weighted rate and time to hit the wall
LDD RATEX ;
LDY #SMALL ; weight the new rate, multiply new RATEX by 2
EMUL
STD TEMPWRATE ; store weighted new RATEX (lower 16 bits)
LDD WRATEX ; load old WRATEX
LDY #LARGE ; weight the old rate, multiply old WRATEX by 8
EMUL
ADDD TEMPWRATE ; add wighted new RATEX
; divide by 10
LDX #NORM
IDIVS ;
STX WRATEX ; updated WRATEX is stored
; use WRATEX to compute WTIMEX, time to hit the wall
LDD #$00FF ;
SUBD SENX ;
IDIVS ;
STX WTIMEX ;
;
; start processing the Y sensor
LDD DCOUNT ; TEST

CPD NDATA ; TEST, have all data been processed
BMI LOOP3 ; TEST
; delay 1 second
BRA LOOP1
;*******************************************************
;* Test Subroutines
;*******************************************************
------------Calculator Results---------------------- -------------------------------------------------Microcontroller Results------------------------------------------
value rate time WRATE WTIME Rate timex wrate wtimex
dec hex dec hex dec hex dec hex dec
41 1 1.0 1 1
42 1 213.0 1.0 213.0 d5 213 d5 213 1 1 d5 213
45 3 70.0 1.0 210.0 3 3 46 70 1 1 d2 210
65 20 9.0 5.0 38.0 14 20 9 9 5 5 26 38
90 25 6.0 10.0 16.0 19 25 6 6 a 10 10 16
150 60 1.0 22.0 4.0 3c 60 1 1 16 22 4 4
200 50 1.0 29.0 1.0 32 50 1 1 1d 29 1 1
210 10 4.0 24.0 1.0 a 10 4 4 18 24 1 1
215 5 8.0 19.0 2.0 5 5 8 8 13 19 2 2
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Evening 2361
; Homework #9
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Symbol Definitions
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
PROG: EQU $800
DATA_T: EQU $900 ;transmit data memory
DATA_R: EQU $920 ;receive data memory
DATA: EQU $940
SC0BDL: equ $C1 ;SCI 0 Baud Rate Register Low

SC0CR1: equ $C2 ;SCI 0 Control Register 1
SC0CR2: equ $C3 ;SCI 0 Control Register 2
SC0SR1: equ $C4 ;SCI 0 Status Register 1
SC0DRL: equ $C7 ;SCI 0 Data Register Low
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Data Section
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org DATA_T
DB 'Times to remember!'
org DATA
recv_data ds 2
tx_data ds 2
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Main
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Homework Question #1
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
org PROG
movb #!13,SC0BDL ;38400bps baud rate

movb #$03,SC0CR1 ;8 data bits, odd parity

movb #$08,SC0CR2 ;enable the transmitter
ldx #DATA_T ;point to the data

next: ldaa 1,x+ ;load the byte and point to the next byte
trans: brclr SC0SR1,$80,trans ;wait for TDRE
staa SC0DRL ;transmit the next byte
cmpa #'!' ;check for end of message
bne next ;if not do next character in message
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Homework Question #2
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
movb #!13,SC0BDL ;38400bps

movb #$04,SC0CR2 ;enable the receiver
ldx #DATA_R ;point to the data

recv: brclr SC0SR1,$20,recv ;wait for RDRF
ldaa SC0DRL ;get the new byte
staa 1,x+ ;save the byte and point to the next byte
bne next ;if not do next character in message
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
; Homework Question #3 and #4
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
sei ;disable interrupts

movb #!13,SC0BDL ;38400bps
movb #%10101100,SC0CR2 ;enable the transmitter and receiver and ints
ldx #DATA_T ;setup th pointer to the data
stx tx_data
ldx #DATA_R ;setup th pointer to the data
stx recv_data
cli ;enable interrupts
loop: bra loop ;do something else while we wait for an int
sci_isr:
brclr SC0SR1,$20,trans1 ;check for RDRF

ldaa SC0DRL ;get the new byte

ldx recv_data ;point to the data
staa 1,x+ ;save the byte and point to the next byte
stx recv_data ;save the pointer
trans1: brclr SC0SR1,$80,end ;check for TDRE

ldx tx_data ;point to the data
ldaa 1,x+ ;load the byte and point to the next byte
stx tx_data ;save the pointer
staa SC0DRL ;transmit the next byte
bne end ;if not do next character in message
movb #%00101100,SC0CR2 ;disable tx ints
end: rti
org $FFD6 ;SCI0 vector

DW sci_isr

EE 2361 Spring 2003
4 problems

1) Write a program to send the message listed below with,

Odd parity
Baud rate equal to 38.4 KHz with MCLK=8MHz
8-bit data (7 character & 1 parity)
Message (put it starting at $900)

Times to remember!
Include code to stop sending when your program detects the “!”.
2) Write a program to receive the message sent in Problem 1.

Store the received characters starting at $920.
Include code to stop receiving when your program detects the “!”.
3) Modify the code written for sending the message in Problem 1 so as to use interrupts. Write an ISR
program to process each character. Assume that you have clean HC12 (no built-in ISRs).
4) Modify the code written for receiving the message in Problem 1 so as to use interrupts. Write an ISR
program to process each character. Assume that you have clean HC12 (no built-in ISRs).
EE 2361 Spring 2003
4 problems

1) Write a program to send the message listed below with,

Odd parity
Baud rate equal to 38.4 KHz with MCLK=8MHz
8-bit data (7 character & 1 parity)
Message (put it starting at $900)

Times to remember!
Include code to stop sending when your program detects the “!”.
PROG: equ $800
B38400 equ !13
SC0CR1 equ $C2
SC0CR2 equ $C3
SC0DRL equ $C7
org $900
DATA: db $54,$69,$6D,$65,$73,$20,$74,$6F,$20,$72,$65,$6D,$65,$6D,$62,$65,$72,$21
org PROG
ldd #B38400
std SC0BDH
ldx #DATA ; initialize pointer to bytes in message
SPIN: brclr SC0SR1,%10000000,SPIN ; wait for TDRE flag
ldaa 1,x+ ; increment pointer to bytes in message
staa SC0DRL ; load character to be transmitted
cmpa #$21 ; check for ! character, signals end of message
beq DONE ; last character has been sent
bra SPIN ; continue to send rest of message
DONE: swi
2) Write a program to receive the message sent in Problem 1.

Store the received characters starting at $920.
Include code to stop receiving when your program detects the “!”.
PROG: equ $800

B38400 equ !13
SC0CR1 equ $C2
SC0CR2 equ $C3
SC0DRL equ $C7
org $920
DATA: ds !18
org PROG
ldd #B38400
std SC0BDH
ldx #DATA
SPIN: brclr SC0SR1,%00100000,SPIN
ldaa SC0DRL
staa 1,x+
staa SC0DRL
cmpa #$21 ; !character
beq DONE
bra SPIN
DONE: swi
3) Modify the code written for sending the message in Problem 1 so as to use interrupts. Write an ISR
to process each character. Assume that you have clean HC12 (no built-in ISRs).
PROG: equ $800

B38400 equ !13
SC0CR1 equ $C2
SC0CR2 equ $C3
SC0DRL equ $C7
org $900
DATA: db $54,$69,$6D,$65,$73,$20,$74,$6F,$20,$72,$65,$6D,$65,$6D,$62,$65,$72,$21
;
; setup ISR
org $FFD6 ; SC0 vector location
TX_INT: dw $6000 ; location of ISR for transmitting
; ISR code
org $6000 ; start of ISR
ldx TEMP ; pointer to next character to transmit
ldaa 1,x+
stx TEMP
staa SC0DRL
cmpa #$21 ; ! character
beq CONTINUE
bclr SC0CR2,%10000000 ; disable interrupt on TDRE
CONTINE: cli
rti
org $1000 ; place for TEMP
TEMP: ds !2
;
;
; main program
org PROG
; initialize SC0
bset SC0CR2,%10000000 ; enable interrupt on TDRE
ldd #B38400
std SC0BDH
; initialize pointer to next character to process
ldaa #DATA
staa TEMP
; other programs follow this comment line
;
4) Modify the code written for receiving the message in Problem 1 so as to use interrupts. Write an ISR
to process each character. Assume that you have clean HC12 (no built-in ISRs).
PROG: equ $800

B38400 equ !13
SC0CR1 equ $C2
SC0CR2 equ $C3
SC0DRL equ $C7
org $920
DATA: ds !18
;
; setup ISR
org $FFD6 ; SC0 vector location
TX_INT: dw $6000 ; location of ISR for receiving
; ISR code
org $6000 ; start of ISR
ldaa SC0DRL
ldx TEMP ; pointer to next character to transmit
staa 1,x+
stx TEMP
staa SC0DRL
cmpa #$21 ; ! character
cter) beq CONTINUE
bclr SC0CR2,%00100000 ; disable interrupt on RDRF
CONTINE: cli
rti
org $1000 ; place for TEMP
TEMP: ds !2
;
;
;
; main program
org PROG
ldd #B38400
std SC0BDH
; initialize pointer to next character to process
ldaa #DATA
staa TEMP
; other programs follow this comment line
;
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/initialize.txt
; Name: James Lamberg & Abbey Sullivan

; Date: 6th Feb., 2003
; University of Minnesota
; EE 2361 Introduction to Microcontrollers
; initialize.asm
; Description : Initializes 256 byte array of memory
; Defining Constants
PROGRAM EQU $800 ;Single chip RAM $0800 - $0BFF
DATA EQU $A00 ;space to initialize to zero
SIZE EQU $FF ;size of array to clear
org PROGRAM ;assembler directive of where to start compiling
ldaa #$00 ;clear accum A

ldab #$00 ;clear accum B, B will act as an offset value
ldx #DATA ;load Index Register X with address DATA
Next: staa B,X ;store accum A at address defined by the operation (X)+(B)
addb #$01 ;add 1 to accum B, added to get memory address
adda #$01 ;add 1 to accum A, value to be stored
cmpb #SIZE ;compare accum B with the value of the variable SIZE
;this instruction sets the ZNVC bits of the CCR. (Ch. 4-6) of your text.
;the mathematical equation is (B)-(M), where (B) is the
;contents of accum B.
bne Next ;Branch if not equal. if Z bit != 1 branch to next
;if Z bit = 1 the result of the cmpb is equal to zero.
staa B,X ;does last byte at 256
nop ;use for a breakpoint
end
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/initialize.txt [06Nov07 22:48:48 ]

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/LAB5.txt
;*******************************************************************
; Lab #5
; LED Settings
; James Lamberg & Abbey Sullivan
; Feb. 27th, 2003
;*******************************************************************
prog equ $800

porta equ $0000
ddra equ $0002
org prog ; start main program
lds #$0AFD
ldaa #$FF
staa ddra ; store 1s in DDRA
ldaa #$FD
staa porta ; store 1s and a 0 in PORTA
sec
again ldx #$0007
loop rol porta ; next led

ldy #$000A ; wait time
jsr wait ; delay
dex
loop1 bne loop
bra back
wait dey ; delay loop

bne wait
rts
back ldx #$0007

loop2 ror porta ; led before
ldy #$000A ; wait time
jsr wait ; delay
dex
bne loop2
bra done
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/LAB5.txt (1 of 2) [06Nov07 22:48:48 ]

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/LAB5.txt
done jmp again
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/LAB5.txt (2 of 2) [06Nov07 22:48:48 ]

1
TIMING
8K x 16 SRAM memory at $2000

8
2
3 to 8 1
A10
Decoder 8
1K x 8 1K x 8
A11
A12 addr addr
notOE notOE
A13*ECLK G1 2 notWE notWE
A14 notG2A 1 notCS notCS
A15 notG2B
22ns
R/notW notOE = R/notW*ECLK
notWE = !ECLK *!(R/notW)

ECLK
15ns 15ns
2
TIMING (READ) ECLK=250ns
ECLK
Address (input to memory

chip, direct from HC12)
memory chip address access time, tADDR, (time when memory chip output data
becomes valid after input address change) must be less than 125–30 = 95 ns.
This assumes chip select and output enable are already set .
R/notW tRWV 20
memory chip output enable access time, tOE , (time when

NAND 15 ns memory chip output data becomes valid after notOE input to
notOE = !(ECLK*(R/notW)
chip changed) must be less than 125–30–15 = 80 ns.
37 = tdcoder 22 (if needed) + tAND 15 ns (A13*ECLK)

notCS = !(ECLK*A13)
tDSR 30 ns
Data
memory chip select access time, tCS, must be less than

which is 125-30-37 = 58ns (output data becomes stable
following chip select input to memory chip going low). Data from memory chip
must be stable before this time
3
TIMING (WRITE) ECLK = 250ns
ECLK
Address
tRWV 20 required
R/notW
NOT 15
tRWH 20
!R/notW
tDSW 30 ns
Data tDHW 20 ns
NAND 15
pulse width, tWP, to write the memory chip must be less
notWE = !(ECLK*!R/notW) than 125–15 = 110ns
37 = tdcoder 22 (if needed) + tAND 15
notCS = !(ECLK*A13) memory chip select time, tCSW , must be less than 125-37 = 88
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/PROG6.txt
DDRA equ $0002

PORTA equ $0000
org $800
ldaa #$FF
staa DDRA
ldaa #$00
staa PORTA
begin: ldab #$1A ; B counts from 26 to 0

inca
staa PORTA
loop: dbne B,loop ; 3 clock
bra begin
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/PROG6.txt [06Nov07 22:48:50 ]

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/receiving%20unit%20prog.txt
; lab 9
; program for receiving unit
; Port A definitions
DDRA equ $0002
PORTA equ $0000
; SC0 definitions
SC0BDH equ $00C0
SC0BDL equ $00C1
SC0CR1 equ $00C2
SC0CR2 equ $00C3
SC0SR1 equ $00C4
SC0DRL equ $00C7
; encryption definitions
INDEXES EQU $900
KEY_TABLE EQU $1000
MASK EQU $20 ; number of bytes encoding before sending
synch byte
org INDEXES
Xindex ds 1 ;declare One Byte
Yindex ds 1 ;declare One Byte
org $800
; set baud rate to 256000

movb #$02,SC0BDL
movb #$00,SC0BDH
; init SCI0 ctl registers

movb #%00000100,SC0CR1 ; disable everything, enable idle bit after
stop bit
movb #%00001100,SC0CR2 ; enable receive and transmit, disable
interrupts
; setup port A
movb #$ff,DDRA ; set porta as output
movb #$00,PORTA ; initialize porta to zero
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/receiving%20unit%20prog.txt (1 of 5) [06Nov07 22:48:51 ]

; now we will init the key table and wait for it to be done to go on
foo: lds #$0AFD ;set stackpointer
jsr init_array ;Jump to subroutine (jsr) init_array for
key_table init
perm: psha ;put counter on the stack; permutate
key_table 255 times
bne perm ;branch to perm 255 times
; now wait to receive sequence 1, 2, 3, 4

synch_test: ldab #$0
wait_init: incb
cmpb #$5 ; if 1, 2, 3, 4 have been received, go to
next step
beq send9
ldaa SC0SR1
anda #$20 ; clears all except (maybe) RDRF flag
beq wait_init
subb SC0DRL
beq wait_init ; if value received is expected value, wait
for next
bra synch_test ; if value wasn't expected value, start over
; send ACK byte -- $09

send9: movb #$09,SC0DRL
wait0: ; wait for $09 to be sent
ldaa SC0SR1
anda #$80 ; clears all except (maybe) TDRE flag
beq wait0
; now we are ready to go!
ldx #0
loop: ldaa SC0SR1
anda #$20 ; clears all except RDRF flag
beq loop ; continue polling until RDRF is set
ldab SC0DRL

cmpb #$50
lbeq synch
inx
cpx #MASK
lbeq foo
; now we decrypt the data

decrypt: psha ;Push accum A (psha) onto the stack;
jsr get_key ;Jump to subroutine get_key; new key
is now in accum B
pula ;Pull accum A (pula) get accum A off
stack
eorb A,X ;exclusive or accum B (eorb); This
instruction is kind of complex
;it is an accumulator index offset
instruction. X+A is the address
;of the byte to eor with accum B,
the result is stored in accum B
; sends decrypted data to port A

stab PORTA
lbra loop
synch: ; if previous byte was $50, wait to see if next byte is $60
ldaa SC0SR1
anda #$20 ; clears all except RDRF flag
beq synch
ldab SC0DRL
cmpb #$60
lbne loop
; if bytes received were $50 and $60, respectively, we send the ACK
byte ($50)
movb #$50,SC0DRL
wait_ACK: ; wait for $50 to finish being sent
ldaa SC0SR1
anda #$80 ; clears all except T flag
beq wait_ACK
ldx #0
lbra loop

init_array: movw #$0000,INDEXES ;Move word (movw); clear Xindex,

Yindex
ldaa #$00 ;Load accum A (ldaa); init counter
variable
ldx #KEY_TABLE ;Load Idex Register X (ldx) init X =
key_table
;for (a = 0; a < 256; a++)
key_table[a] = a;
inca ;A++
bne init_loop ;8 bit auto mod 256, fall through
when A = 0
get_key: ;get_key is a destructive routine of

accumulators A:B
;assumes global definition of
Xindex, Yindex, and INDEXES
ldd INDEXES ;load accum D (ldd); loads A with
Xindex; B with Yindex
inca ;add 1 to Xindex (if overflow mods);
x=(x+1)%256
addb A,X ;add key_table[x] to b (if overflow
mods); y=(y+key_table[x])%256
;prepare to swap
;swap

aba ;accum A <- (A + B); (key_table[x] +

key_table[y])%256
ldab A,X ;accum B <- index[accum A];
key_table[A]
clra ;clear accum A

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/sending%20unit%20prog.txt
; lab 9
; program for sending unit
; SCI0 defenitions
SC0BDH equ $00C0
SC0BDL equ $00C1
SC0CR1 equ $00C2
SC0CR2 equ $00C3
SC0SR1 equ $00C4
SC0DRL equ $00C7
; encryption defenitions
INDEXES EQU $900
KEY_TABLE EQU $1000
MASK EQU $20 ; number of bytes encoding before sending
synch byte
org INDEXES
Xindex ds 1 ;declare One Byte
Yindex ds 1 ;declare One Byte
; ATD defenitions
ATDCTL2 equ $0062
ATDCTL3 equ $0063
ATDCTL4 equ $0064
ATDCTL5 equ $0065
ATDSTAT1 equ $0066
ADR0 equ $0070
org $800
; set baud rate to 256000

movb #$02,SC0BDL
movb #$00,SC0BDH
; init SCI0 ctl registers
movb #%00000000,SC0CR1 ; disable everything, disable idle bit after
stop bit
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/sending%20unit%20prog.txt (1 of 6) [06Nov07 22:48:51 ]

movb #%00001100,SC0CR2 ; enable transmitter AND receiver, disable

interrupts
; set up ATD and wait for ready

movb #$80,ATDCTL2
ldaa #$C8
delay: dbne a,delay
movb #$00,ATDCTL3
movb #$00,ATDCTL4
; now we will init the key table and wait for it to be done to go on
foo: lds #$0AFD ;set stackpointer
jsr init_array ;Jump to subroutine (jsr) init_array for
key_table init
perm: psha ;put counter on the stack; permutate
key_table 255 times
bne perm ;branch to perm 255 times, then encrypt
the string
; now we will send the sequence $01,$02,$03,$04 serially (unencoded) to the

receiving unit
; then we will wait to receive $09 back from the receiving unit to confirm
that it's ready
ldab #$0
synch_test:
wait0: ; wait for previous bit to be sent
ldaa SC0SR1
beq wait0
incb
ldab SC0DRL ; sends B
cmpb #$04
bne synch_test

ldx #$0
wait_4_9: ; wait for $9 to be received from the receiving unit
ldaa SC0SR1
anda #$20 ; clears all except (maybe) RDRF flag
beq wait_4_9
inx
cpx #$10
beq synch_test ; if 9 wasn't received after $10 cycles, go
back
ldaa SC0DRL ; loads a with whatever was received and clears RDRF
flag
cmpa #$9
bne wait_4_9 ; if byte received WAS NOT 9, keep waiting
; now we are ready to go!
; main program
ldx #0
loop:
movb #$00,ATDCTL5 ; starts a new conversion
wait1: ; wait for conversion complete

ldaa ATDSTAT1
anda #$80 ; clears all except (maybe) SCF flag
beq wait1
ldab ADR0 ; load conversion result
; now encrypt the byte

;*********************************
encrypt: psha ;Push accum A (psha) onto the stack
jsr get_key ;Jump to subroutine get_key; new key

is now in accum B
pula ;Pull accum A (pula) get accum A off
stack
eorb ADR0 ;exclusive or accum B (eorb)
; B now contains the encrypted bit
wait2: ; wait for previous encrypted byte to be sent

ldaa SC0SR1
beq wait2
stab SC0DRL ; sends conversion result via SCI0
inx
cpx MASK
beq send_synch
bra loop
send_synch: ; sends $50 and $60 and waits for a $50 back from the other
unit
wait_more: ;wait for previous byte to finish sending
ldab SC0SR1
andb #$80 ; clears all except (maybe) TDRE flag
beq wait_more
movb #$50,SC0DRL ; sends $50
wait_more2: ; wait for $50 to finish sending and then clear SC0SR1
ldab SC0SR1
andb #$80
beq wait_more2
movb #$60,SC0DRL ; sends $60

wait_more3: ; wait for $60 to finish sending and clear T flag

ldab SC0SR1
andb #$80
beq wait_more3
; now wait for $50 to be received from other unit---ACK byte

ldy #$0
wait_4_50: iny
cpy #$10
beq foo
ldaa SC0SR1
anda #$20
beq wait_4_50
ldaa SC0DRL
cmpa #$50
bne send_synch
ldx #$0
bra loop
init_array: movw #$0000,INDEXES ;Move word (movw); clear Xindex,

Yindex
ldaa #$00 ;Load accum A (ldaa); init counter
variable
ldx #KEY_TABLE ;Load Idex Register X (ldx) init X =
key_table
;for (a = 0; a < 256; a++)
key_table[a] = a;
inca ;A++
bne init_loop ;8 bit auto mod 256, fall through
when A = 0
get_key: ;get_key is a destructive routine of

accumulators A:B

;assumes global definition of

Xindex, Yindex, and INDEXES
ldd INDEXES ;load accum D (ldd); loads A with
Xindex; B with Yindex
inca ;add 1 to Xindex (if overflow mods);
x=(x+1)%256
addb A,X ;add key_table[x] to b (if overflow
mods); y=(y+key_table[x])%256
;prepare to swap
;swap
aba ;accum A <- (A + B); (key_table[x] +

key_table[y])%256
ldab A,X ;accum B <- index[accum A];
key_table[A]
clra ;clear accum A

file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/ZERO.txt
; Name: James Lamberg & Abbey Sullivan

; Date: 6th Feb., 2003
; University of Minnesota
; EE 2361 Introduction to Microcontrollers
; zero.asm
; Description : Does Stuff
; Defining Constants
PROGRAM EQU $800 ;Single chip RAM $0800 - $0BFF
DATA EQU $A00 ;space to initialize to zero
SIZE EQU $0F ;size of array to clear
org PROGRAM ;assembler directive of where to start compiling
ldaa #$55 ;clear accum A (changed to #$55)

ldab #$00 ;clear accum B, B will act as an offset value
ldx #DATA ;load Index Register X with address DATA
Next: staa B,X ;store accum A at address defined by the operation (X)+(B)
addb #$01 ;add 1 to accum B
cmpb #SIZE ;compare accum B with the value of the variable SIZE
;this instruction sets the ZNVC bits of the CCR. (Ch. 4-6) of your text.
;the mathematical equation is (B)-(M), where (B) is the
;contents of accum B.
bne Next ;Branch if not equal. if Z bit != 1 branch to next
;if Z bit = 1 the result of the cmpb is equal to zero.
nop ;use for a breakpoint
end
file:///Users/admin/Documents/Academic/UMN-Year-PDF/EE-2361/ZERO.txt [06Nov07 22:48:52 ]

1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Fuzzy Logic Controller for A Mobile Robot
; Description: This program takes in two Infrared sensor values and computes a direction control
; signal to avoid wall collisions. The two sensor values are read from memory locations $6000 and
; $6001 and the control output value is written to memory location $6002.
;
Output functions
Left medium
Right
Left small
Left
Sensor Sensor Zero
Right small
Right medium
1.0 LM LS ZR RS RM
$40 $60 $80 $A0 $C0

2
Input Membership Function Definitions


255
224
192
128
64
32
$00 $10 $20 $40 $50 $60 $70 $80 $90 $A0 $B0 $C0 $D0 $E0 $F0
Sensor Value
Left/Right VS ST MD WE VW
VS ZR 5 RS 10 RS 15 RM 20 RM 25
ST LS 4 ZR 9 RS 14 RM 19 RM 24
MD LS 3 LS 8 ZR 13 RS 18 RS 23
WE LM 2 LM 7 LS 12 ZR 17 RS 22
VW LM 1 LM 6 LS 11 LS 16 ZR 21
3
Rule Right Sensor Left Sensor Min Current Output New Output
1 LM VS 0 VW 0 0 LM 0 0
2 LM VS 0 WE 64 0 LM 0 0
3 LS VS 0 MD 192 0 LS 0 0
4 LS VS 0 ST 0 0 LS 0 0
5 ZR VS 0 VS 0 0 ZR 0 0
6 LM ST 160 VW 0 0 LM 0 0
7 LM ST 160 WE 64 64 LM 0 64
8 LS ST 160 MD 192 160 LS 0 160
9 ZR ST 160 ST 0 0 ZR 0 0
10 RS ST 160 VS 0 0 RS 0 0
11 LS MD 96 VW 0 0 LS 160 160
12 LS MD 96 WE 64 64 LS 160 160
13 ZR MD 96 MD 192 96 ZR 0 96
14 RS MD 96 ST 0 0 RS 0 0
15 RS MD 96 VS 0 0 RS 0 0
16 LS WE 0 VW 0 0 LS 160 160
17 ZR WE 0 WE 64 0 ZR 96 96
18 RS WE 0 MD 192 0 RS 0 0
19 RM WE 0 ST 0 0 RM 0 0
20 RM WE 0 VS 0 0 RM 0 0
21 ZR VW 0 VW 0 0 ZR 96 96
22 RS VW 0 WE 64 0 RS 0 0
23 RS VW 0 MD 192 0 RS 0 0
24 RM VW 0 ST 0 0 RM 0 0
25 RM VW 0 VS 0 0 RM 0 0
4
Output Values
LM 64
LS 160
ZR 96
Output membership function

LM $40 = 64
LS $60 = 96
ZR $80 = 128
Weighted average = 64x64 + 160x96 + 96x128

64+160+96
= 99.2
Ran program and got $69 = 105

5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Fuzzy Logic Controller for A Mobile Robot
; Description: This program takes in two Infrared
; sensor values and computes a direction control
; signal to avoid wall collisions. The two sensor
; values are read from memory locations $6000 and
; $6001 and the control output value is written
; to memory location $6002.
;
; Authors: Daniel Pack and Steve Barrett Date: 8-21-2000
; comments added by Allen, 4-23-1003
;
; $6000 – load 2 sensor values in memory
; Right Sensor $9A
; Left Sensor $6C
;
; $6003 location of Defuzzification result
; Running MEM look at Fuzzification results being enter starting at $6030
; See Output values change starting at $603A
; Final result is $63 = !99
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; offsets to use in addressing Fuzzy Inputs (which are computed by MEM
instruction)
O_R_VS EQU $00 ; Offset values for input and output mem fns
O_R_ST EQU $01 ; Right Sensor Strong
O_R_ME EQU $02 ; Right Sensor Medium
6
O_R_WE EQU $03 ; Right Sensor Weak

O_R_VW EQU $04 ; Right Sensor Very Weak
O_L_VS EQU $05 ; Left Sensor Very Strong
O_L_ST EQU $06 ; Left Sensor Strong
O_L_ME EQU $07 ; Left Sensor Medium
O_L_WE EQU $08 ; Left Sensor Weak
O_L_VW EQU $09 ; Left Sensor Very Weak
; offsets to use in addressing Fuzzy Outputs (which are computed by
REV instruction)
O_ML EQU $0A ; Medium Left
O_SL EQU $0B ; Small Left
O_ZR EQU $0C ; Zero
O_SR EQU $0D ; Small Right
O_MR EQU $0E ; Medium Right
; markers
MARKER EQU $FE ; rule separator
ENDR EQU $FF ; end of rule marker
; inputs, result, variables
ORG $6000
RSENSOR RMB $01 ; Crisp value for Right Sensor
LSENSOR RMB $01 ; Crisp value for Left Sensor
CONTROLS RMB $01 ; for input/output variables
; Fuzzy Input Membership Function Definitions for Right Sensor
R_Very_Strong FCB $B0,$FF,$10,$00
R_Strong FCB $90,$C0,$10,$10
7
R_Medium FCB $60,$A0,$10,$10

R_Weak FCB $40,$70,$10,$10
R_Very_Weak FCB $00,$50,$00,$10
; Fuzzy Input Membership Function Definitions for Left Sensor (same as
for Right Sensor)
L_Very_Strong FCB $B0,$FF,$10,$00
L_Strong FCB $90,$C0,$10,$10
L_Medium FCB $60,$A0,$10,$10
L_Weak FCB $40,$70,$10,$10
L_Very_Weak FCB $00,$50,$00,$10
; Fuzzy Output Membership Function Definitions (singletons) - 5
possible robot turns
Medium_Left FCB $40
Small_Left FCB $60
Zero FCB $80
Small_Right FCB $A0
Medium_Right FCB $C0
; Locations for fuzzy membership values for Right Sensor (truths)
; computed by MEM instruction given crisp input value
R_VS RMB $01
R_ST RMB $01
R_ME RMB $01
R_WE RMB $01
R_VW RMB $01
; Locations for fuzzy membership values for Left Sensor (truths)
8
; computed by MEM instruction given crisp input value

L_VS RMB $01
L_ST RMB $01
L_ME RMB $01
L_WE RMB $01
L_VW RMB $01
; Output Fuzzy Logic Membership Values (Fuzzy Outputs) - must be
initialized to zero
; final values are computed by REV instruction
ML FCB $00
SL FCB $00
ZR FCB $00
SR FCB $00
MR FCB $00
; Rule Definitions
Rule_Start FCB O_R_VS,O_L_VS,MARKER,O_ZR,MARKER
FCB O_R_VS,O_L_ST,MARKER,O_SL,MARKER
FCB O_R_VS,O_L_ME,MARKER,O_SL,MARKER
FCB O_R_VS,O_L_WE,MARKER,O_ML,MARKER
FCB O_R_VS,O_L_VW,MARKER,O_ML,MARKER
FCB O_R_ST,O_L_VS,MARKER,O_SR,MARKER
FCB O_R_ST,O_L_ST,MARKER,O_ZR,MARKER
FCB O_R_ST,O_L_ME,MARKER,O_SL,MARKER
FCB O_R_ST,O_L_WE,MARKER,O_ML,MARKER
FCB O_R_ST,O_L_VW,MARKER,O_ML,MARKER
9
FCB O_R_ME,O_L_VS,MARKER,O_SR,MARKER
FCB O_R_ME,O_L_ST,MARKER,O_SR,MARKER
FCB O_R_ME,O_L_ME,MARKER,O_ZR,MARKER
FCB O_R_ME,O_L_WE,MARKER,O_SL,MARKER
FCB O_R_ME,O_L_VW,MARKER,O_SL,MARKER
FCB O_R_WE,O_L_VS,MARKER,O_MR,MARKER
FCB O_R_WE,O_L_ST,MARKER,O_MR,MARKER
FCB O_R_WE,O_L_ME,MARKER,O_SR,MARKER
FCB O_R_WE,O_L_WE,MARKER,O_ZR,MARKER
FCB O_R_WE,O_L_VW,MARKER,O_SL,MARKER
FCB O_R_VW,O_L_VS,MARKER,O_MR,MARKER
FCB O_R_VW,O_L_ST,MARKER,O_MR,MARKER
FCB O_R_VW,O_L_ME,MARKER,O_SR,MARKER
FCB O_R_VW,O_L_WE,MARKER,O_SR,MARKER
FCB O_R_VW,O_L_WE,MARKER,O_ZR,ENDR
; Main Program
ORG $4000
; Fuzzification
LDX #R_Very_Strong ; Start of Input Membership function
definitions - 4 bytes each
LDY #R_VS ; Start of Fuzzy Mem values called Fuzzy
Inputs or truths
; which are to be computed by MEM
instruction
; Process the Right Sensor
10
LDAA RSENSOR ; Right Sensor Value (crisp value)

LDAB #5 ; Number of iterations = the number of
Right Sensor membership functions
; for the Right Senson
Loopr MEM ; Assign mem values; each iteration MEM
reads the 4 byte membership defn
; and computes the Fuzzy Input which
will be used in the Rule evaluation by REV
DBNE B,Loopr ; Do all five iterations (5 membership
functions for Right Sensor)
; Process the Left Sensor
LDAA LSENSOR ; Left Sensor Value (crisp value)
LDAB #5 ; Number of iterations = the number of
Left Sensor membership functions
Loopl MEM ; Assign mem value; each iteration MEM
reads the 4 byte membership defn
; and computes the Fuzzy Input which
will be used in the Rule evaluation by REV
DBNE B,Loopl ; Do all five iterations (5 membership
functions for Left Sensor)
; Process the rules
LDY #R_VS ; Start of Fuzzy Inputs
LDX #Rule_Start ; Start of Rules
LDAA #$FF ; Initialize a minimum value for use by
REV and clear the V bit
11
REV ; Evaluate rules

; For each rule the two Fuzzy Inputs are
compared with $FF
; and the minimum value (consequent) is
picked for the next step.
; Then all the consequents are compared
for each Fuzzy Output
; and the maximums are selected for each
Fuzzy Output
; The V bit is used by REV to keep track
of when it is
; processing antecedents, V = 0
; processing consequents, V = 1
; Defuzzification Process
LDX #Medium_Left ; Start of output mem func
LDY #ML ; Start of mem values
LDAB #$05 ; Five elements sum
WAV ; Computing a crisp value
EDIV ; Divides numerator by sum of the Fuzzy
Outputs
TFR Y,D ; Store answer to D
STAB CONTROLS ; Save the answer
SWI
END

Fuzzy

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EE2361 Spring 2002 - Extension

Memory location $820 contains the bit pattern %10101100.

d) If represents a signed number, what number (in decimal,

be the contents of and the CCR after the instruction?

program: ;this subroutine is supposed to count the number

a) This program, as written, will not work. I've made an

Problem 2: 0,sp contains the saved value of , not .

the bit counter at 0,sp, but that's where is stored!

The corrected subroutine should have zeroed instead of x,

we could zero before pushing it on the stack and left the

Here's the final, tested, version of the program:

bitctr: ;this subroutine is supposed to count the number

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EE2361 Spring 2002 - Extension

$18 $09 $1e $09 $00

is executed. Describe the contents of the CCR after this instruction.

(Assume that the label ``foo'' refers to an instruction at address $840.)

The X bit cannot be set.

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EE2361 Spring 2003 - Extension

soln: contains . This means that it represents a

negative number (since it's signed.) To find that number, find

complement, , or 32 + 14, or 46. The answer is -46.

b) Considered as representing an unsigned number, what number does

d) Suppose that ``adda $800'' is executed. What will the contents

of and the CCR be after the instruction?

add $12 to $D2. The result: = $E4 (no carry, no overflow.)

be the contents of and the CCR after the instruction?

The answer: = $DA59 (so = $59), CCR = %00001000.

org $200 ___________________

Problem 4: Memory contents and procesor registers are as shown:

;this subroutine counts all occurrences of the value

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Name (printed) _____________________________

Student ID# _____________________________

b) Convert the signed binary number 11011010 to a decimal number.

$B5 => $4A + 1 = $4B

$88CD + $F781 = $804E

$8333 - $7FF6 = $033D

EA = $0003+(Y) = $1994, (indexed)

PROG: EQU $800

loop: ldaa !48

a) What binary code must be loaded into ATDCTL5 ?

b) What binary code must be loaded into ATDCTL4 ?

c) What register will contain the result for Channel 6?

spin: brclr ATDSTAT, %10000000,spin

(256 – 1)steps * resolution = (5 – 0)

a) What binary value must be loaded into register SC0CR2?

bset SC0CR2,%00001100 ; TxRx enable

b) What binary value must be loaded into register SC0CR1?

%00010011 ; mode, parity, odd

spin: brclr SC9SR1,%00100000,spin

SC0BDH or SC0BDH and SC0BDL

spin: brclr SC0SR1,%10000000,spin

spin1: brclr TFLG1,%00100000,spin1

Rule Right Sensor Left Sensor Truth Rule Current Final

37 = tdcoder 22 (if needed) + tAND 15 ns

tADDR access available

120 + 121 + 124 + 126 = 1 + 2 + 16 + 64 = 83 → -83

3160 + 5161 = 3 + 80 = 83 → -83

2163 + 10162 +1161 + 4160 + = 8192 + 2560 + 16 + 4 = 10772 → -10772

2162 +6161 + 6*160 = 512