BEHAVIORAL DESCRIPTION

HALF ADDER
module half_add(I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2; /* Since O1 and O2 are outputs and they are written inside “always,”
they should be declared as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1 & I2; // statement 2./*The above two statements are signal-
assignment statements with 10 simulation screen units delay*/ /*Other behavioral
(sequential) statements can be added here*/
end
endmodule

4 BIT BINARY TO GRAY CONVERTER

module b2g(b, g);

input [3:0] b;
output [3:0] g;
reg [3:0] g;
always @(b)
begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

IF Statement
IF is a sequential statement that appears inside always or initial in Verilog. It has
several formats, some of which are as follows:

Verilog IF-Else Formats

if (Expression)
begin
statement 1; /* if only one statement, begin and end can be omitted */
statement 2;
statement 3;
.......
end
else
begin
statement a; /* if only one statement, begin and end can be omitted */
statement b;
statement c;
.......
end

Verilog
if (clk == 1’b1) // 1’b1 means 1-bit binary number of value 1.
temp = s1;
else
temp = s2;

if clk is high (1), the value of s1 is assigned to the variable temp. Otherwise, s2 is
assigned to the variable temp.

EXECUTION OF IF AS ELSE-IF
if (Expression1)
 begin
statement1;
statement 2; .....
end
else if (expression2)
begin
statementi;
statementii; .....
end
else
begin
statement a;
statement b; ....
end

IMPLEMENTING ELSE-IF
if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;

BEHAVIORAL DESCRIPTION OF A LATCH USING VARIABLE AND

SIGNAL ASSIGNMENTS
Behavioral Description of a D-Latch
module D_latch (d, E, Q, Qb);
input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E)
begin
if (E == 1)
begin
Q = d;
Qb = ~ Q;
end
end
endmodule

BEHAVIORAL DESCRIPTION OF A 2x1 MULTIPLEXER WITH TRI-

STATE OUTPUT
module mux2x1(A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y;
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 1)
Y = 1’bz;
else
begin
if (SEL)
Y = B;
else
Y = A;
end
end
endmodule
HDL Description of a 2x1 Multiplexer Using Else-IF
module MUXBH(A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y; /*since Y is an output and appears inside always, Y has to be declared as
reg(register) */
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 0 & SEL == 1)
begin
Y = B;
end
else if (Gbar == 0 & SEL == 0)
Y = A;
else
Y = 1’bz; //Y is assigned to high impedance
end
endmodule

2 bit comparator

module comp(a,b, agrb,alsb,aeqb);

input [1:0] a,b;
output agrb,alsb,aeqb;
reg aeqb,agrb,alsb;
always @(a, b)
begin
aeqb=0;
agrb=0;
alsb=0;
if(a==b)
aeqb=1;
else if (a>b)
agrb=1;
else
alsb=1;
end
 endmodule

The case Statement

The case statement is a sequential control statement. It has the following format:

Verilog Case Format

case (control-expression)
test value1: begin statements1; end
test value2: begin statements2; end
test value3: begin statements3; end
default: begin default statements end
endcase

Example
case sel
2’b00: temp = I1;
2’b01: temp = I2;
2’b10: temp = I3;
default: temp = I4;
endcase

If sel = 00, then temp = I1, if sel = 01, then temp = I2, if sel = 10, then temp = I3,
if sel = 11 (others or default), then temp = I4. All four test values have the same
priority; it means that if sel = 10, for example, then the third (VHDL) statement
(temp:= I3) is executed directly without checking the first and second expressions
(00 and 01).

FULL ADDER
 module fulladd(cin,a,b,sum,cout);
input cin,a,b;
output sum,cout;
reg sum,cout;
always@(cin,a,b)
begin
case ({cin,a,b})
3'b000:{cout,sum}=2'b00;
3'b001:{cout,sum}=2'b01;
3'b010:{cout,sum}=2'b01;
3'b011:{cout,sum}=2'b10;
3'b100:{cout,sum}=2'b01;
3'b101:{cout,sum}=2'b10;
3'b110:{cout,sum}=2'b10;
3'b111:{cout,sum}=2'b11;
endcase
end
endmodule

8 to 1 multiplexer
module mux8(sel, I, y);
input [2:0] sel;
input [7:0] I;
output y;
reg y;
always @(sel ,I)
begin
case(sel)
3'b000:y=I[0];
3'b001:y=I[1];
3'b010:y=I[2];
3'b011:y=I[3];
3'b100:y=I[4];
3'b101:y=I[5];
3'b110:y=I[6];
3'b111:y=I[7];
default : y=1'b0;
endcase
end
endmodule

1 to 4 de multiplexer
module demux (sel, I, y);
input [1:0] sel;
input I;
output[3:0] y;
reg [3:0] y;
always@(I,sel)
begin
y=4'b0000;
case (sel)
2'b00:y[0]=I;
2'b01:y[1]=I;
2'b10:y[2]=I;
2'b11:y[3]=I;
default:y=4'b0000;
endcase
end
endmodule

BEHAVIORAL DESCRIPTION OF A POSITIVE EDGE-TRIGGERED JK

FLIP-FLOP USING THE CASE STATEMENT
module JK_FF (JK, clk, q, qb);
input [1:0] JK;
input clk;
output q, qb;
reg q, qb;
always @ (posedge clk)
begin
case (JK)
2’d0: q = q;
2’d1: q = 0;
2’d2: q = 1;
2’d3: q =~ q;
endcase
qb =~ q;
end
endmodule
2:4 Decoder

module dec(en, ab, y);

input en;
input [1:0] ab;
output [3:0] y;
reg [3:0] y;
always@(en or ab)
begin
if(en)
y=4'b0000;
else
case(ab)
2'b00:y=4'b0001;
2'b01:y=4'b0010;
2'b10:y=4'b0100;
2'b11:y=4'b1000;
default:y=4'b0000;
endcase
end
endmodule
8:3 Encoder With Priority

module enc8_3(I, z, y);

input [7:0] I;
output z;
output [2:0] y;
reg [2:0]y;
reg z;
always@(I)
begin
if(I==8'b00000000)
begin
y=3'b000;
z=1'b0;
end
else
case(I)
8'b00000001 :y=3'b000;
8'b0000001x :y=3'b001;
8'b000001xx :y=4'b010;
8'b00001xxx :y=4'b011;
8'b0001xxxx :y=4'b100;
8'b001xxxxx :y=4'b101;
8'b01xxxxxx :y=4'b110;
8'b1xxxxxxx :y=4'b111;
default: begin end
Endcase
End
Endmodule
8:3 Encoder Without Priority

module enc8_3(en, I, y);

input en;
input [7:0] I;
output [2:0] y;
reg [2:0]y;
always @(en or I)
Begin
if(en==1)
y=3'b000;
Else
case(I)
8'b00000001:y=3'b000;
8'b00000010:y=3'b001;
8'b00000100:y=3'b010;
8'b00001000:y=3'b011;
8'b00010000:y=3'b100;
8'b00100000:y=3'b101;
8'b01000000:y=3'b110;
8'b10000000:y=3'b111;
default:y=3'b000;
Endcase
End
Endmodule

For-Loop
for <lower index value> <upper index value> <step>
statements1; statement2; statement3; ….
end loop

Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1)
begin
result = result + 2**i;
end
end
statement1; statement2; ....

While-Loop
The general format of the While-Loop is:
while (condition)
Statement1; Statement2; …………
end

while (i < x)
begin
i = i + 1;
z = i*z;
end

Verilog repeat
In Verilog, the sequential statement repeat causes the execution of statements
between its begin and end to be repeated a fixed number of times; no condition is
allowed in repeat.

Verilog Repeat
repeat (32)
begin
#100 i = i + 1;
end

Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common use for
forever is to generate clocks in code-oriented test benches. The following code
describes a clock with a period of 20 screen time units:
initial
begin
clk = 1’b0;
forever #20 clk = ~clk;
end