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High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW CPU FEATURES
DR8051CPU is a high performance, area ● 100% software compatible with industry
optimized soft core of a single-chip 8-bit em- standard 8051
bedded controller dedicated for operation with
● RISC architecture enables to execute in-
fast (typically on-chip) and slow (off-chip)
structions 6.7 times faster compared to
memories. The core has been designed with a
standard 8051
special concern about low power consump-
tion. Additionally an advanced power man- ● 12 times faster multiplication
agement unit makes DR8051CPU core perfect ● 9.6 times faster division
for portable equipment where low power
consumption is mandatory. ● Up to 256 bytes of internal (on-chip) Data
DR8051CPU soft core is 100% binary- Memory
compatible with the industry standard 8051 8- ● Up to 64K bytes of Program Memory
bit microcontroller. There are two configura-
tions of DR8051CPU: Harward where external ● Up to 16M bytes of external (off-chip) Data
data and program buses are separated, and Memory
von Neumann with common program and ex- ● User programmable Program Memory Wait
ternal data bus. DR8051CPU has RISC archi- States solution for wide range of memories
tecture 6.7 times faster compared to standard speed
architecture and executes 65-200 million in-
structions per second. This performance can ● User programmable External Data Memory
also be exploited to great advantage in low Wait States solution for wide range of
power applications where the core can be memories speed
clocked up to seven times more slowly than ● De-multiplexed Address/Data bus to allow
the original implementation for no performance easy connection to memory
penalty.
DR8051CPU is delivered with fully auto- ● Interface for additional Special Function
mated testbench and complete set of tests Registers
allowing easy package validation at each stage ● Fully synthesizable, static synchronous de-
of SoC design flow. sign with positive edge clocking and no in-
ternal tri-states
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are trademarks of their respective owners. http://www.dcd.pl
xramdatai(7:0)
xramdatao(7:0)
xramdataz External
Memory
Interrupt int0
xramaddr(23:0) Controller int1
Interface
xramrd
xramwr
ramdatai(7:0)
ramdatao(7:0) Internal Data Power stop
ramaddr(7:0) Memory Management pmm
ramoe Interface Unit
ramwe
sfrdatai(7:0)
sfrdatao(7:0) docddatai
User SFR DoCD™ docddatao
sfraddr(7:0) Interface Debug Unit
sfroe docdclk
sfrwe
Power Management
Architecture speed
Compare/Capture
Interrupt sources
Stack space size
additional SFRs
Timer/Counters
Interrupt levels
Floating Point
Data Pointers
Coprocessor
Coprocessor
Design
Interface for
Fixed Point
Wait States
Watchdog
Controller
Controller
I\O Ports
States
space
space
UART
grade
Unit
SPI
DR8051CPU 6.7 64k 256 256 16M 2 2 1 - - - - - - - - - - -
DR8051 6.7 64k 256 256 16M 5 2 1 2 1 4 - - - - - - - -
DR8051XP 6.7 64k 256 256 16M 15 2 2 3 2 4
DR8051 family of High Performance Microcontroller Cores
The main features of each DR80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
Program Memory space
Power Management
Architecture speed
Compare/Capture
Interrupt sources
Stack space size
additional SFRs
Timer/Counters
Interrupt levels
Master I C Bus
Floating Point
Data Pointers
Coprocessor
Coprocessor
Design
Interface for
Fixed Point
Wait States
Watchdog
Controller
Controller
I\O Ports
2
States
space
space
UART
grade
Unit
SPI
DR80390CPU 6.7 16M 256 256 16M 2 2 1 - - - - - - - - - - -
DR80390 6.7 16M 256 256 16M 5 2 1 2 1 4 - - - - - - - -
DR80390XP 6.7 16M 256 256 16M 15 2 2 3 2 4
DR80390 family of High Performance Microcontroller Cores