Stlc4560 Datasheet F

STLC4560
Single chip 802.11b/g WLAN radio
Features
■ Extremely small footprint
■ Ultra low power consumption
■ Fully compliant with the IEEE 802.11b and LFBGA240 (8.5x8x1.4mm)
802.11g WLAN standards
■ Support for 54, 48, 36, 24, 18, 12, 9, and
6 Mbit/s OFDM, 11 and 5.5 Mbit/s CCK and Description
legacy 2 and 1 Mbit/s data rates
The STLC4560 is a single chip 802.11b/g WLAN
■ Single chip 802.11b/g WLAN solution with fully radio for embedded, low-power and very small
integrated: form factor mobile applications. The product
– zero IF (ZIF) transceiver conforms to the IEEE 802.11b and 802.11g
– voltage controlled oscillator (VCO) protocols operating in the 2.45 GHz ISM
– high-speed A/D and D/A converters frequency band supporting OFDM data rates of
54, 48, 36, 24, 18, 12, 9, and 6 Mbit/s as well as
– OFDM and CCK baseband processor
CCK data rates of 11 and 5.5 Mbit/s and legacy
– ARM9 media access controller (MAC) data rates of 2 and 1 Mbit/s.
– SPI serial host interface
The STLC4560 is a fully integrated wireless radio
– passive components integration
including a ZIF transceiver, RF Synthesizer/VCO,
– PA bias control high-speed data converters, an OFDM/CCK
– flexible integrated power management unit digital baseband processor, an ARM9-based
– glueless FEM interface MAC and a complete power management unit
■ Intelligent power control, including 802.11 with integrated PA bias control. In addition some
power save mode passive components are integrated further
reducing the overall reference design cost and
■ Fully integrated Bluetooth coexistence size. An external FEM completes a highly
integrated chip set solution.
Applications Host control is provided by a flexible SPI serial
■ Cellular phones interface. The SPI interface supports a maximum
clock rate of 48 MHz. For maximum flexibility, the
■ Personal digital assistants (PDA) STLC4560 accepts system reference clock
■ Portable computers frequencies of 19.2, 26, 38.4 and 40 MHz. A
■ Hand-held data transfer devices reference design evaluation platform of hardware
and software is provided to system integrators to
■ Cameras rapidly enable wireless connectivity to mobile
■ Computer peripherals platforms.
■ Cable replacement
November 2007 8030121 rev F- ST Confidential 1/44

www.st.com 44
Contents STLC4560
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Reference clock general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Reference clock noise and jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Serial host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Host pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 SPI mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 AHB (AMBA high performance bus) masters . . . . . . . . . . . . . . . . . . . . . . 25
4.4 Host registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5 Host writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Host multi-word writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.7 Host reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.8 Host multi-word reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.9 ARM AHB slave access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10 Recommended bootup sequence for SPI hosts . . . . . . . . . . . . . . . . . . . . 31
5 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ARM INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 ARM INTERRUPT ACKNOWLEDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 ARM INTERRUPT ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4 HOST INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 HOST INTERRUPT ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6 HOST INTERRUPT ACKNOWLEDGE . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.7 GENERAL PURPOSE 1 and 2 COMMUNICATION . . . . . . . . . . . . . . . . . 35
5.8 DEVICE CONTROL/STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STLC4560 Contents
5.9 DMA DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.10 DMA WRITE CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.11 DMA WRITE LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.12 DMA WRITE BASE ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.13 DMA READ CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.14 DMA READ LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.15 DMA READ BASE ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1 Mechanical data and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2 Marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8030121 rev F- ST Confidentiall 3/44

Block diagram and pin description STLC4560
1 Block diagram and pin description
Figure 1. Block diagram
STLC4560
Power management unit (PMU)

Host
SPI I/F
RF ZIF section: CPU
RF VCO
FEM: Rx down converters
PA, switches, Tx up converters
FEM I/F baseband filters Baseband MAC
Balun,
passives processor
OFDM/CCK ARM9
modulation WEP Bluetooth
High speed CXS I/F
data converters device
Switch control

STLC4560 Block diagram and pin description
1.1 Pin connection

Figure 2. Pin out (top view) H
R P N M L K J H G F E D C B A
RSRV_ VBAT PMU_ LNA_ LB_LNA LB_LNA LNA_ TX_ LB_ TX_ TX_ VDDA_ RSRV_ RSRV_
NC V2X GND SHIELD _IN+ _IN- SHIELD GND TX_OUT GND VDD PLL SW3 NC NC
1 1
VBAT VBAT LNA_ LNA_ LNA_ LNA_ TX_ TX_ TX_ TX_ RSRV_
V2XOUT V2X V2X SHIELD SHIELD SHIELD SHIELD GND GND GND VDD SW1 SW4 SW2 NC
2 2
FB_ RX_ LNA_ LNA_ LNA_ TX_ TX_ TX_ SYN_ RSRV_ PMU_ PMU_
V2XOUT V2XOUT V2X VDD SHIELD SHIELD SHIELD GND GND GND GND NC SDA SCL VDIG
3 3
FB_ POR_ DGND_ DGND_ DGND_ RSRV_ PMU_ STAND V4_OUT
V2OUT V2OUT V2 V4O AGND AGND RF RF RF GPIO_0 NC DGND VI2C BY1 SEL
4 4
VDD_ RSRV_ DGND_ DGND_ DGND_ RSRV_ RSRV_ RSRV_ POWER STAND PMU_
VBATV2 VBATV2 VBAT QLO AGND NC RF RF RF NC NC NC _UP BY2 RSET
5 5
VDD_ RSRV_ RSRV_ DGND_ DGND_ DGND_ RSRV_ RSRV_ RSRV_ RSRV_ POR_ PMU_
VCO V1OUT V4OUT VBATV4 NC NC RF RF RF NC NC NC NC V4I CREF
6 6
RSRV_ POR_ RSRV_ DGND_ DGND_ DGND_ RSRV_ RSRV_ RSRV_ RSRV_ RSRV_
NC V1OUT VBATV1 V2O GP1_2 NC RF RF RF NC NC NC NC GND GP2_2
7 7
VDD_ LF_ RSRV_ DGND_ DGND_ DGND_ RSRV_ RSRV_
V1OUT V1OUT CORE XTAL_IN AGND NC RF RF RF MODE3 VDDA VDDD DGND NC NC
8 8
RSRV_ DGND I_ DGND DGND_ DGND_ DGND_ VDDD_ DGND_
NC GP1_4 HIO VDDA TEST+ CORE RF RF RF MODE2 AGND DAC CORE EESDA EESCL
9 9
I_ Q_ DGND_ DGND_ DGND_ VDD_ RSRV_ DGND_
GP2_8 AGND LB_VPA FREQ TEST- TEST+ RF RF RF CORE MODE1 NC CORE SCL SDA
10 10
VDD_ UART_ Q_ RSRV_ DGND_ DGND_ DGND_ DGND_ DGND_ DGND_
SPI_CLK SPI_DIN CORE SOUT TEST- NC RF RF RF MODE0 RF RF RF TRSTN TDI
11 11
UART_ RSRV_ RSRV_ DGND_ RSRV_ RSRV_ RSRV_ VDDD_
SIN SPI_CSX VIO PA_DET0 NC NC RF NC NC NC ADC MODE4 DGND TMS TDO
12 12
RF_ DGND_ RSRV_ RSRV_ DGND_ RSRV_ RSRV_ RSRV_ RSRV_ VDD_ REF_
ACTIVE STATUS CORE DAT2 NC NC RF NC NC NC NC OSC_EN CORE TCK CLK
13 13
TX_ SPI_ RSRV_ VDD_ RSRV_ RSRV_ RSRV_ RSRV_ VDD_ POR VDD_
GP2_9 CONF GP1_15 DOUT NC DGND CORE NC NC NC NC CORE V2I CORE DGND
14 14
RSRV_ HOST_ VDD_ DGND_ RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ SER_ RSRV_
RC IRQ GP2_10 CORE CORE VDDD NC NC NC NC NC VDDD GP2_13 MODE NC
15 15
RSRV_ RSRV_ DGND_ DGND_ VDDD_ DGND_ DGND_ RSRV_ RSRV_
NC NC GP1_13 CORE VIO HIO ADC RF VDDD DGND CORE GP2_11 GP2_12 NC NC
16 16
R P N M L K J H G F E D C B A

1.2 Pin description

Table 1. Pin description
Pin name Pin # Type Function
RF front end interface pins
LB_LNA_IN- K1 RF input
100Ω RF differential RX inputs.
LB_LNA_IN+ L1 RF input
Low noise amplifier (LNA) input shield pins.
(Analog GND).
J1, J2, J3, K2,
All LNA_SHIELD pins must be connected
LNA_SHIELD K3, L2, L3, RF shield
M1, M2 together via a solid ground plane for optimal
performance. Refer to the evaluation platform
layout for the recommended layout scheme.
LB_TX_OUT G1 RF output 50 Ω RF transmit (Tx) single ended output.
Digital output Antenna switch control outputs. I/O voltage
SW1 D2
(ANTSEL-) level determined by VDIG. See Table 2 on
page 13.
Digital output
SW2 B2 Output word determined by TX/RX mode. See
(ANTSEL+)
Table 3 on page 13.
Digital output Note: The SWx numbering of pins D2, B2, C1
SW3 C1
(TRSW+) and C2 may not match with earlier revisions of
the schematics. The reference numbering is
defined here. To avoid ambiguity, only refer to
SW4 C2 Digital output (TRSW-) the pin number and type when reading
schematics.
PA_DET0 M12 Analog input PA detector.
Host interface and clock pins
Host interrupt request. Typically asserted to

HOST_IRQ P15 1.86 V digital output
request a SPI data transfer (VIO domain).
Power up enable from host. Internal pull-down.
When POWER_UP is LOW, the PMU is
1.86 V digital input disabled and I/Os are not supplied. All Inputs
POWER_UP C5
(pull-down) should than be kept low or special precaution
should be taken to avoid current leakage and
bus loading (1.).
Oscillator enable output. Initially driven high on
OSC_EN D13 1.86V digital output powerup, after which it is under the control of
firmware.
Reference clock input (19.2, 26.0, 38.4 or 40.0
REF_CLK A13 Clock input MHz). Internally coupled through a 1000 pF
ceramic capacitor.

Table 1. Pin description (continued)

MODE strapping pins are used to initialize the

PLL for the following REF_CLK frequencies.
Connect appropriate pin to the ground plane
with a 10 kΩ pulldown resistor for a logic 0 input
or to a 10 kΩ pull-up 1.86 V VDDD power plane
for a logic 1.
43210: Bit position
D12 (MSB),
MODE[4:0] F8, F9, E10, 1.86 V digital input 00000 = 19.2 MHz
F11(LSB) 11100 = 26.0 MHz
10000 = 38.4 MHz
10100 = 40.0 MHz
All other MODE pin combinations are reserved.
Use of pullup and pulldown resistors not
mandatory, can strap pins direct to VDDD or
ground plane.
ARM sleep clock input (32.768 kHz typical) from
LF_XTAL_IN M8 1.86 V digital input
host.
Serial host mode (VIO domain). Logic high
SER_MODE B15 1.86 V digital input
selects SPI mode.
DAT2 M13 1.86 V digital I/O Reserved. Keep floating for proper operation.
1.86 V digital input
SPI_CLK R11 SPI clock from host (VIO domain).
(pull-down)
SPI chip select from host (VIO domain). Active
SPI_CSX P12 1.86 V digital input
low.
SPI data input for 4-wire modes. In 3-wire
SPI_DIN P11 1.86 V digital I/O modes, this is the data input/output signal (VIO
domain).
SPI data output for 4-wire modes only (VIO
SPI_DOUT M14 1.86 V digital output domain). Requires an external 10 kΩ pull-up
resistor.
MAC GPIO pin typically implementing a
1.86 V digital I/O
FREQ M10 Bluetooth coexistence input function. (VIO
(input)
domain).
1.86 V digital I/O
RF_ACTIVE R13 Bluetooth coexistence input function. (VIO
(input)
domain).
1.86 V digital I/O
STATUS P13 Bluetooth coexistence input function. (VIO
(input)
domain).
1.86 V digital I/O
TX_CONF P14 Bluetooth coexistence output function. (VIO
(output)
domain).


Power supply pins
Battery supply input for regulator V1 of the

VBATV1 N7 Supply input (3.6 V)
PMU.
VBATV2 P5, R5 Supply input (3.6 V)
PMU.
Battery supply input for regulator V2X of the
VBATV2X N2, P1, P2 Supply input (3.6 V)
PMU.
VBATV4 M6 Supply input (3.6 V)
PMU.
VBAT N5 Supply input (3.6 V) Battery supply input for the PMU.
Supply pin for SWx (x={1, 2, 3, 4} digital output
VDIG A3 Supply input (3.6 V)
drivers.
Digital 1.86V I/O power supply input pin
VI2C C4 Digital supply input
dedicated to the PMU I2C bus interface.
P6, P7, P8,
V1OUT Regulator output Linear regulator 1.86 V output (V1).
R8
V2OUT P4, R4 Regulator output Linear regulator 1.86 V output (V2).
V2XOUT P3, R2, R3 Regulator output Linear regulator 1.2 V output (V2X).
Linear regulator output selectable for 2.8 V or
V4OUT N6 Regulator output 3.15 V (V4). Output voltage controlled by
V4_OUTSEL pin A4.
Control input for selection of V4OUT regulator
V4_OUTSEL A4 1.86 V digital input
output voltage. Logic 0 => 2.81 V, 1 => 3.11 V.
Sense line for V2 regulator. Connect to V2OUT
FB_V2 N4 Regulator sense
pins P4, R4 with a short trace.
Sense line for V2X regulator. Connect to
FB_V2X N3 Regulator sense
V2XOUT pins P3, R2, R3 with a short trace.
Reference capacitor for internal power
PMU_CREF A6 Analog reference management unit (PMU). Connect a 1uF
capacitor to a solid board ground plane.
Reference resistor for the internal power
PMU_RSET A5 Analog reference management unit (PMU). Connect a 1MΩ
resistor to a solid board ground plane.
VDDA E8, M9 Analog supply input RFIC analog 1.86V supply input pins.
RX_VDD M3 Analog supply input RX power supply (1.86V).
VDDA_PLL D1 Analog supply input Synthesizer power supply (1.86V).
TX_VDD E1, E2 Analog supply input TX power supply (1.86V).
Analog 1.86 V supply input for RF quadrature
local oscillator (QLO). Decouple to a solid
VDD_QLO M5 Analog supply input ground plane using a ceramic capacitor located
as close as possible to the pin. Refer to
evaluation platform schematics.


Analog 1.86 V supply input for the RF voltage

controlled oscillator (VCO). Typically connected
to V1OUT pins P6, P7, P8, R8. Decouple to a
VDD_VCO R6 Analog supply input
solid ground plane using a ceramic capacitor
located as close as possible to the pin. Refer to
evaluation platform schematics.
Digital 1.86 V I/O power supply input pins.
Decouple to a solid ground plane using ceramic
VDDD_ADC E12, J16 Digital supply input capacitors located as close a possible to the
appropriate pins. Refer to evaluation platform
schematics.
Digital 1.86 V I/O power supply input pins.
Decouple to a solid ground plane using ceramic
VDDD_DAC D9 Digital supply input capacitors located as close a possible to the
appropriate pins. Refer to evaluation platform
schematics.
D8, D15, G16,
VDDD Digital supply input Digital 1.86 V I/O power supply input pins.
K15
B14, C13,
Digital 1.2 V core supply.
D14, F10,
VDD_CORE Digital supply input Internally decoupled to DGND_CORE via three
J14, M15, N8,
N11 1000 pF ceramic capacitors.
Host digital I/O supply input for SPI and

VIO L16, N12 Supply input (1.86 V) Bluetooth interfaces. Internally decoupled to
DGNDHIO via a 0.1µF ceramic capacitor.
All AGND pins must be connected together
through a solid ground plane for optimal
E9, K4, L4,
AGND Analog ground performance. Refer to the evaluation platform
L5, L8, P10
layout for the proper AGND and DGND
grounding scheme.
Synthesizer analog ground.
All AGND pins must be connected together
SYN_GND E3 Analog ground through a solid ground plane for optimal
layout for the proper AGND and DGND
grounding scheme.
All TX_GND pins must be connected together
F1, F2, F3,
through a solid ground plane for optimal
TX_GND G2, G3, H1, Analog ground
H2, H3
layout for the proper grounding scheme.
Host digital I/O ground for SPI and Bluetooth
interfaces.
All DGND pins must be connected together
DGNDHIO K16, N9 Digital ground through a common solid ground plane for
optimal performance. Refer to the evaluation
platform layout for the proper AGND and DGND
grounding scheme.
PMU_GND N1 Ground Ground of the PMU.


PMU_DGND D4 Ground Ground of the PMU level shifter.

Digital ground of the ADCs.
C11, D11, All DGND pins must be connected together
E11, G4-11, through a common solid ground plane for
DGND_RF Digital ground
H4-11, H16, optimal performance. Refer to the evaluation
J4-13 platform layout for the proper AGND and DGND
grounding scheme.
Digital ground of the Baseband and MAC.
K9, N13, E16,
DGND_CORE L15, M16, C9, Digital ground through a common solid ground plane for
C10 optimal performance. Refer to the evaluation
grounding scheme.
Digital I/Os ground.
A14, C8, C12, through a common solid ground plane for
DGND Digital ground
F16, K14 optimal performance. Refer to the evaluation
grounding scheme.
Miscellaneous pins
Firmware controlled 3 V digital GPIO. Float for

GPIO_0 F4 3 V GPIO
proper operation.
Firmware controlled 1.86 V digital GPIO. Float
GP1_2 L7 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP1-2.
GP1_4 P9 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP1-4.
GP1_13 N16 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP1-13.
GP1-15.
GP2_2 A7 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-2.
GP2_8 R10 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-8.
GP2_9 R14 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-9.
GP2-10.



GP2_11 D16 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-11.
GP2_12 C16 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-12.
GP2_13 C15 1.86 V GPIO for proper operation. Assigned to ARM MAC
GP2-13.
I_TEST- L10
I_TEST+ L9 Reserved analog test pins. Float for proper
Reserved
Q_TEST- L11 operation.
Q_TEST+ K10
SCL B10 Miscellaneous (O/P) I2C clock from digital baseband.(1)(1)
Miscellaneous
SDA A10
(Master) I2C data/address from digital baseband. (1)
PMU_SCL B3 Miscellaneous (I/P) PMU programming I2C clock.(1)

PMU_SDA C3 Miscellaneous (Slave) PMU programming I2C data/address.(1)
Optional serial clock line (SCL) for external
1.86 V GPIO 1.86 V serial flash device. This I/O has an
EESCL A9
(pull-down)
internal pull-down resistor.(1)
Optional serial data line (SDA) for external 1.86
EESDA B9 1.86 V GPIO
V serial flash device.(1)
Reserved pin. Connect to ground plane for
RSRV_GND B7 Reserved
proper operation.
A1, A2, A8,
A15, A16, B1,
B8, B16, C6,
C7, D3, D5,
D6, D7, D10,
E4, E5, E6,
E7, E13, E14,
E15, F5, F6, Reserved pins. Float for proper operation.
F7, F12, F13,
D3 and D5 can also be left connected to 2.8V
F14, F15,
RSRV_NC Reserved as was case in STLC4550.
G12, G13,
G14, G15, Inside STLC4560 package, balls D3, D5 E4 not
H12, H13, connected to any dice.
H14, H15,
J15, K5, K6,
K7, K8, K11,
K12, K13, L6,
L12, L13, L14,
P16, R1, R7,
R9, R15, R16


JTAG clock. Internal pull-up active in normal

TCK B13 JTAG
operation mode. Leave floating when not in use.
JTAG data input. Internal pull-up active in
TDI A11 JTAG normal operation mode. Leave floating when
not in use.
JTAG data output. Internal pull-up active in
TDO A12 JTAG normal operation mode. Leave floating when
not in use.
JTAG test mode select. Internal pull-up active in
TMS B12 JTAG normal operation mode. Leave floating when
not in use.
JTAG reset. Connect to POR_V2O. JTAG
TRSTN B11 JTAG
interface is 1.86 V.
UART_SIN R12 Miscellaneous UART serial input.
UART_SOUT M11 Miscellaneous UART serial output.
Active low V2 power-on reset output. Connect
POR_V2O M7 1.86 V digital output
to POR_V2I.
Baseband reset input - active low. Connect to
POR_V2I C14 1.86 V digital input
POR_V2O.
Active low V4 power-on reset output. Connect
POR_V4O M4 1.86 V digital output to POR_V4I. Ball M4 shorted to Ball M7 inside
STLC4560 package.
RF reset input - active low. Connect to
POR_V4I B6 1.86 V digital input
POR_V4O.
LB_VPA N10 3.0 V digital output Low band PA enable.
1.86 V digital input Stand-by modes:
STANDBY1 B4
(pull-down) 00 - default (float) - PMU regulators on,
01 - V1, V2, V4 in low power mode; V2X @
1.2 V,
1.86 V digital input
STANDBY2 B5 10 - V1, V2, V4 in low power mode; V2X @
(pull-down)
1.2 V (0.8 V in low power),
11 - unused.
1. Refer to the evaluation platform schematics for additional information.

Table 2. I/O voltage level as determined by VDIG

Description Min Typ Max Unit Comment
Vol SWx
0 0.3 x VDIG V Max source current 3 mA
(x={1, 2, 3, 4})
Voh SWx
0.7 x VDIG VDIG V Max sink current 3 mA
(x={1, 2, 3, 4})
Note: See Table 5 for VDIG operating conditions.
Table 3. SWx (x={1, 2, 3, 4}) output depending on the TX/RX state

SW1 [D2] SW2 [B2] SW3 [C1] SW4 [C2]
State (input)
(ANTSEL-) (ANTSEL+) (TRSW+) (TRSW-)
WLAN TX Low High Low High

WLAN RX Low Low High Low
Bluetooth High Low Low High

Electrical specifications STLC4560
2 Electrical specifications
The STLC4560 has an ESD classification as follows:
Table 4. ESD & latch-up classification

Balls HBM ESD CDM ESD latch-up
all +1.8kV / -1.8kV + 500V / -400V 200mA
Electrical specifications of the STLC4560 are provided in Table 5.

Caution: Stresses above those listed in the “Absolute maximum ratings” may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not
advised.
2.1 Electrical characteristics

Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Absolute maximum ratings
PMU VBATT (Vcc) -0.3 - 7.0 V

Vcc +
Voltage on any other pin -0.3 - V
Within shared voltage rails 0.3
Vcc to Vcc -0.3 - +0.3 V
Any GND to GND -0.3 - +0.3 V
Operating conditions and input power specifications
Operating temperature range -30 85 oC
Power management unit VBATT supply

Input supply voltage 3.0 3.6 5.5 V
input
Average continuous Continuous transmitting @ 54 Mbit/s,
400 mA
VBATT TX current VBATT = 3.6 V
supply Average continuous Receiving valid packets @ 54 Mbit/s,
400 mA
RX current VBATT = 3.6 V
Average standby
VBATT = 3.6 V 10 µA
mode current
VDIG Input supply voltage SWx (x={1, 2, 3, 4}) supply input 1.7 VBATT V

STLC4560 Electrical specifications
Table 5. Electrical characteristics (continued)

For measurement methods and suggestions, please refer to the ST Power Consumption Application Note.
Power management unit VBATT supply

Input supply voltage 3.0 3.6 5.5 V
input
Standby current 25 oC, POWER_UP = 0V. The resulting 10 µA

current is mainly leakage
25 oC, POWERUP = 1.86 V. The radio is

Sleep mode current operating on the sleep clock at 32.768 120 µA
kHz. Sleep mode is a subset of PSM.
Power save mode 25 oC, 100 ms Beacon period, 75 byte

VBATT Beacons @ 1 Mbit/s, short preamble, 610 µA
current
Power DTIM = 6
consumption
Receive or Idle 25 oC, the radio is always on, receiving 195 mA
current beacons, no TX
o
PSM Receive current 25 C, PSM, receiving packets at 76 mA
1.9Mbit/s at the application layer
Transmit current 25 oC, the radio is always on, transmitting 199 mA

1.9Mbit/s at the application layer
PSM Transmit 25 oC, PSM, transmitting 1.9Mbit/s at the 49 mA

currentr application layer
VIO input supply determines host CMOS
logic levels for: SPI_CSX, SPI_CLK,
Input supply voltage SPI_DIN, SPI_DOUT, HOST_IRQ, 1.62 1.86 1.98 V
VIO supply LF_XTAL_IN, FREQ, RF_ACTIVE,
STATUS, TX_CONF
Input supply current VIO = 1.86 V 0.5 6 mA
Internal power management unit specifications
PMU_CREF PMU reference capacitor -30% 1 +30% uF

PMU_RSET PMU reference resistor -1% 1 +1% MΩ
Active mode 1.817 1.86 1.901
Output voltage V
Low power mode 1.819 1.86 1.907
V1OUT
Active mode 50
linear Peak output current mA
regulator Low power mode 5
External output load
Typical ESR = 0.1 Ω -35% 1 +35% uF
capacitor
Active mode 1.819 1.86 1.904
Output voltage V
Low power mode 1.8 1.86 1.920
V2OUT
Active mode 300
Low power mode 5
regulator
Typical ESR = 0.1 Ω -35% 2.2 +35% uF
capacitor


Active mode 1.249 1.29 1.334

Output voltage V
Low power mode 1.24 1.29 1.34
V2XOUT
Active mode 280
regulator Low power mode 20
Typical ESR = 0.1 Ω -35% 2.2 +35% uF
capacitor
Active mode:
V4_OUTSEL=0 2.82 2.904 2.988
V4_OUTSEL=1 3.12 3.214 3.307
Output voltage V
Low power mode:
V4OUT
linear V4_OUTSEL=0 2.82 2.904 2.988
regulator V4_OUTSEL=1 3.12 3.214 3.307
Active mode 30
Peak output current mA
Low power mode 5
Typical ESR = 0.1 Ω -35% 1 +35% uF
capacitor
Receiver specifications
RX RF frequency Typical WLAN RF front end components

2300 2500 MHz
range selected.
RX LO frequency
4600 5000 MHz
range
RF input VSWR Differential, 100 Ω reference 2:1
RX LO phaser jitter 50 kHz to 10 MHz, RMS LO/2 1.25 Deg
At LO/2 frequency. RF front end properly
-70 dBm
LO to LNA input matched and isolated
feed-through At LO frequency. RF front end properly
-50 dBm
matched and isolated
Maximum RX input b/g band only. RF front end properly
-23 -10 dBm
level matched
Adjacent channel CCK CH6 35 37

rejection OFDM 54 Mbits Ch6 -1 11
TX to RX input During transmit mode, affecting TX
+5 dBm
leakage distortion
DSB NF 5 7 dB
High gain RX mode, -90dBm input, b and
IP3 input -17 -16 dBm
g band only, front end losses not included
IP2 input +13 dBm


DSB NF 29.8 dB
Low gain RX mode, -20dBm input, b and
IP3 input +9 dBm
g band only, front end losses not included
IP2 input +33 dBm
RF Hi/Lo gain b/g band only. RF front end properly
-38 dBm
switching point matched.
6 Mbit/s OFDM, 10% PER -93 -85 dBm
9 Mbit/s OFDM, 10% PER -91 dBm
Receive sensitivity, b 36 Mbit/s OFDM, 10% PER -81 dBm
and g band, front end
losses not included 48 Mbit/s OFDM, 10% PER -76 dBm
54 Mbit/s OFDM, 10% PER -74 -68 dBm
1 Mbit/s BPSK, 8% PER -96.8 -89 dBm
2 Mbit/s QPSK, 8% PER -94.5 dBm
5.5 Mbit/s CCK, 8% PER -93.5 dBm
11 Mbit/s CCK, 8% PER -90.5 -82 dBm
6 Mbit/s, 10% PER 820 ns
Multipath delay
spread 36 Mbit/s, 10% PER 210 ns
48 Mbit/s,10% PER 160 ns
1 Mbit/s BPSK and 2 Mbit/s QPSK, 8%
250 ns
PER
5.5 and 11 Mbit/s CCK, 8% PER 100 ns
Transmitter specifications
TX RF frequency
2300 2500 MHz
range
TX LO frequency
4600 5000 MHz
range
Note: Over AGC range, b and g bands
RF output VSWR 3:1
only
TX LO phase jitter 50 kHz to 10 MHz, RMS, LO/2 1.25 Deg


TX AGC control
40 dB
dynamic range
TX AGC control step
Monotonic 2 dBm
size
At 0 control attenuation. RF front end
CCK output power 5 8 dBm
properly matched
CCK output power 3 dBm
Case 1: Set TX AGC to obtain this Pout.
OFDM output power -6 dBm
dBm/
-135
Carrier offsets 0 to 10 MHz Hz
Output noise floor
Carrier offsets >20 MHz dBm/
-138
Hz
CCK output power -7 dBm
Case 2: Set TX AGC to obtain this Pout
dBm/
-137.5
Hz
Output noise floor Carrier offsets 0 to 10 MHz
-140.5
Hz
dBm/
-140
Hz
-143
Hz
dBm/
-142.5
Hz
-145.5
Hz
dBm/
-145
Hz
Output noise floor Carrier offsets 0 to 10 MHz carrier
offsets >20 MHz dBm/
-148
Hz


External power amplifier detector ADC specifications
Full scale input

At input of ADC 0 1.0 V
voltage
Maximum input
VDDA V
voltage
At PA_DET0 input -- 16 tap resistive
Input resistance divider tap node 30 Ω
Input capacitance 0.5 pF
Table 6. Host interface specifications

Parameter Test condition / comment Min. Typ. Max. Units
Digital interface specifications
VIH PMU power up control. Active high. 0.8 - VBATT V

POWER_UP
VIL 0 - 0.3 V
input
Pull-down - 500 - kΩ
0.7*VI VIO +
VIH - V
Host CMOS O 0.3
VIO supply domain
inputs 0.3*VI
VIL 0 - V
O
VIO -
VOH IOH = 0.2 mA, VIO supply domain - VIO V
0.2
Host CMOS
outputs VOL IOL = 6 mA, VIO supply domain 0 - 0.6 V
Input current VIO supply domain -1.0 - +1.0 µA
OSC_EN VOH IOH <= 2 mA 1.4 - - V

output VOL IOL <= 2 mA - - 0.4 V
Input level 450 - 1.86 V mVpp
AC coupled
Accuracy - - 25 ppm
REF_CLK 1.143 kΩ
Input impedance Power-on mode
input 2.165 pF
Capacitive and
resistive elements in 1.033 kΩ
series Power-off mode
0.667 pF
Frequency - 32.768 - kHz
SLEEP_CLK
Accuracy VIO supply domain - - 150 ppm
input
Duty cycle 30 - 70 %

Table 6. Host interface specifications

Parameter Test condition / comment Min. Typ. Max. Units
SPI timing specification (See Figure 3)
20.8 ns
TCMIN SPI_CLK period
1/48 MHz-1
SPI_CLK
TCH SPI_CLK high time 10.4 ns
TCL SPI_CLK low time 10.4 ns
TCSSU SPI_CSX setup time to first clock edge 10.4 ns
SPI_CSX
TCSH SPI_CSX hold time from last clock edge 10.4 ns
SPI_DIN setup time to receive edge of
TDISU 3 ns
SPI_CLK
SPI_DIN
SPI_DIN hold time to receive edge of
TDIH 0.5 ns
SPI_CLK
SPI_DOUT delay from transmit edge of
TDOD 0 9 ns
SPI_CLK
SPI_DOUT delay before HI-Z state from
SPI_DOUT TDOZH 0 ns
rising edge of SPI_CSX
SPI_DOUT delay before driven from HI-
TDOZD 10 ns
Z state on falling edge of SPI_CSX
Figure 3. SPI timing specifications

STLC4560 Reference clock
3 Reference clock
3.1 Reference clock general

Table 7. Reference clock general
Parameter Test condition Min. Typ. Max. Units
o
Operating temperature -30 25 85 C
Frequency 19.2, 26, 38.4, 40 supported 19 40 MHz
Temperature stability -25 25 ppm
Vdd -5% 1.86 5% V
O/P Vpp 0.45 1.86 V
802.11a/b/g slew rate (dual band 30% to 70% of the AC coupled output
300 500 mV/ns
radio) or around the common mode voltage
30% to 70% of the AC coupled output
802.11b/g (single band radio) 100 mV/ns
or around the common mode voltage
High 0.7Vdd V
Venable
Low 0.3Vdd V
3.2 Reference clock noise and jitter

Table 8. Oscillator frequency <= 20 MHz
Oscillator frequency 19.2 20 MHz

Jitter Integration from 65 kHz to 10 MHz 21.2 mo rms
@ 1 kHz -124
@ 10 kHz -133
Phase noise dBc/Hz
@ 100 kHz -140
@ 1 MHz -142
Table 9. Oscillator frequency > 20 MHz

Oscillator frequency 21 40 MHz

Jitter Integration from 65 kHz to 10 MHz 42.4 mo rms
@ 1 kHz -118
@ 10 kHz -127
Phase noise dBc/Hz
@ 100 kHz -134
@ 1 MHz -136

Serial host interface STLC4560
4 Serial host interface
4.1 Host pins

The serial host interface consists of five pins.
● SPI_CLK: serial host clock input, 0 – 48 MHz.
● SPI_DIN: serial host data input, sampled on active edge of SPI_CLK.
● SPI_DOUT: serial host data output, driven when asserted low and floating when de-
asserted. SPI_DOUT is driven on inactive edge of SPI_CLK.
● SPI_CSX: serial host chip select, active low chip select.
● HOST_IRQ, serial host interrupt, active high interrupt to host.
The serial host interface has twelve modes of operation controlled by four variables. The
default 4-wire mode may be changed by a SPI host write to the device status/control
register. If the host requires a different SPI mode for normal operation, the host may need to
toggle the necessary SPI pins using GPIO-style interfacing to perform a 4-wire write
sequence to change the mode.
The default 4-wire single word write is show below in Figure 4.
Figure 4. 4-WIRE mode single word write
The default 4-wire single word read is shown below in Figure 5.
Figure 5. 4-WIRE mode single word read

STLC4560 Serial host interface
4.2 SPI mode selection

As shown in Table 10, the twelve modes of operation are controlled by four variables in the
device status/control register.
Table 10. Serial host modes of operation

Invert clock Phase shift 3-wire-mode 3-wire-ADR DATAWAIT Name
0 0 0 X 4-WIRE
1 0 0 X 4-WIREINV
0 1 0 X 4-WSHFT
1 1 0 X 4-WIREINVSHFT
0 0 1 0 3-WIRE
1 0 1 0 3-WIREINV
0 1 1 0 3-WIRESHFT
1 1 1 0 3-WIREINVSHFT
0 0 1 1 3-WIREWAIT1
1 0 1 1 3-WIREINVWAIT1
0 1 1 1 3-WIRESHFTWAIT1
1 1 1 1 3-WIREINVSHFTWAIT1
When invert clock = 0, SPI_CLK receive edge is the rising edge and SPI_CLK transmit edge
is the falling edge. The SPI_CLK polarity can be reversed by a host write to the device
status/control register to change the invert clock = 1. In this case, the SPI_CLK transmit
edge becomes the rising edge and SPI_CLK receive edge becomes the falling edge.
Figure 6. Single word read 4-WIREINVMODE
Figure 7. Single word read 4-WIRESHFTMODE

Figure 8. Single word read 4-WIREINVSHFTMODE
Figure 9. 3-wire
Figure 10. 3-WIREINV
Figure 11. 3-WIRESHFT
Figure 12. 3-WIREINVSHFT

Figure 13. 3-WIREWAIT1
Figure 14. 3-WIREINVWAIT1
Figure 15. 3-WIRESHIFTWAIT1
Figure 16. 3-WIREINVSHIFTWAIT1
4.3 AHB (AMBA high performance bus) masters

The DMA engines are contained within the serial host interface. The DMA engines access
data on the device via a pair of AHB masters. AHB1 is connected to the standard AHB bus
which is shared with the CPU and DMA controller AHB masters.
The serial host has a second AHB master connected to the AHB Ram directly via a AHB2.
The serial host AHB2 master and the AHB RAM AHB2 slave are the only master and slave
on the AHB2 bus. This guarantees sufficient bandwidth for the serial host interface.
When the AHB master is accessing APB (AMBA peripheral bus) registers, the
APBACCESS bit in the DMA WRITE CONTROL register must be set to force the master to
use word
(32-bit) transfers so that the APB registers are not set to an indeterminate state by a pair of
half-word (16-bit) transfers.

DMA read data is prefetched when the DMA READ BASE ADDRESS is written and the
DMA WRITE ENABLE bit is asserted. The host must not read the DMA DATA register
before the prefetch completes. There must be 20 ABCLOCK cycles between the end of the
data phase when DMA READ BASE ADDRESS is written and the end of address phase
which selects the DMA READ register (t1 in Figure 17).
Figure 17. AHB bus timing
20 ABCLOCK cycles
The read data is registered on the 15th SPI_CLK of the DMA DATA register address phase.
SPI_CSX high time must be 20ABCLOCKS - 15SPI_CLKs. If ABCLOCK period is 100 ns
(10 MHz) and the SPI_CLK period is 40 ns then the time between writing DMA READ BASE
address register and reading the DMA DATA register is (20 * 100) - (15 * 40) = 1.4µs. If the
ABCLOCK period is 25 ns (40 MHz) then SPI_CSX high time is < 0 for read data to be valid.
In this case, only the minimum high time for SPI_CSX must be observed.
4.4 Host registers

The host can access the registers listed in Table 11.
Table 11. Register summary

Sleep
Domain A14-A8 Access Description Notes
access
X00 0000
SPI_CLK RW RW ARM interrupt Note 1, Note 2
X00 0010
X00 0100 ARM interrupt
ARM R --
X00 0110 enable
X00 1000
ARM R -- Host interrupt Note 1
X00 1010
X00 1100 Host interrupt
SPI_CLK RW RW
X00 1110 enable
X01 0000 Host interrupt
SPI_CLK W --
X01 0010 acknowledge
X01 0100 GP1
Shared RW --
X01 0110 communication
X01 1000 GP2
Shared RW --
X01 1010 communication
X01 1100
-- -- -- Reserved
X01 1110

Table 11. Register summary (continued)

Sleep
Domain A14-A8 Access Description Notes
access
X10 0000
-- -- -- Reserved
X10 0010
X10 0100 Device
Host RW RW Note 1, Note 2
X10 0110 control/ status
Host X10 1000 RW -- DMA DATA
DMA write
Shared X10 1100 RW --
control
DMA write
length
X11 0000
Shared RW -- DMA write base
X11 0010
DMA read
control
DMA read
length
X11 1000
Shared RW -- DMA read base
X11 1010
Note: 1 Readable during sleep mode without generating sleep interrupt. All registers are
readable during sleep mode. Reading registers not marked as readable during
sleep set the ARMASLEEP bit in the host and ARM INTERRUPT registers.
2 Writable during Sleep Mode. All registers are writable during Sleep mode. Writing
registers not marked as writable during sleep mode requires several 32 kHz clock
cycles to complete the write access and set the ARMASLEEP bit in the host and
ARM INTERRUPT.
The host accesses each register as a 16-bit register.
Registers which are physically 32-bits have two addresses in the host address space. The
even address (A9 == 0) is the low 16-bits and the odd address (A9 == 1) is the high 16-bits.
A15 is the read bit. A15 is set for reads and cleared for writes. For example, to write ARM
INTERRUPT[31:16], address bits [15:0] are set to 0x0200. Address bits 15:0 are set to
0x8200 to read ARM INTERRUPT[31:16]. A[7:0] and A[14] are ‘don't care’ bits that can be
set to any value by the host. It is required that a full 16-bit address be sent. The data phase
does not begin until the 16-bit address phase has completed.

4.5 Host writes

The host writes to a 16-bit register by sending a 16-bit address phase with A15 set to zero.
The address phase is followed by a 16-bit data phase. D15 is the first bit of data phase and
D0 is the last bit of the data phase. D[15:0] are written to the selected register on the active
edge of SPI_CLK when D0 is present on SPI_DIN.
When the register is in the ARM or shared clock domain, the write process begins on the
active edge of SPI_CLK and when D0 is present on SPI_DIN. The write completes after the
data is synchronized into the ABCLOCK domain. This process takes 3 ABCLOCK cycles.
ABCLOCKs are 30µs each in sleep mode. The host must ensure a 90µs delay between
writes to non-sleep accessible registers when the device is in sleep mode.
If less than 16 bits are written during the data phase, the data is not written to the addressed
register. The SPI_CLK may stop at any time. The current phase (address or data) is not
interrupted by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until
SPI_CLK resumes or SPI_CSX is de-asserted.
4.6 Host multi-word writes

The host may write to multiple consecutive 16-bit registers by keeping SPI_CSX asserted
and continuing to toggle SPI_CLK after the initial 16-bit data phase has completed.
The register address is incremented by 0x0200 at the end of each data phase for all register
addresses except the DMA DATA register.
Figure 18. Serial host multi-word write
0x2C00 0x2E00
DMA Write Length
Consecutive writes to the DMA DATA register are written without address increment.
Figure 19. Serial host multi-word write DMA DATA

4.7 Host reads

The host reads from a 16-bit register by sending a 16-bit address phase with A15 set to 1.
The address phase is followed by a 16-bit data phase. D15 is the first bit of data phase and
D0 is the last. Data is available on SPI_DOUT.
Any register may be accessed during sleep mode, however, the usual synchronization
mechanism for ARM or shared clock domain registers is bypassed in sleep mode. Read
data is unpredictable if the ARM writes to the ARM or shared clock domain register during a
sleep mode read by the host.
The SPI_CLK may stop at any time. The current phase (address or data) is not interrupted
by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until SPI_CLK
resumes or SPI_CSX is de-asserted. If less than 16-bits are read by the host during a data
phase from any register except the DMA DATA register there is no effect on the internal
state of the registers. If less than 16-bits are read by the host during a data phase from the
DMA DATA register the contents of subsequent DMA read accesses are unpredictable until
the DMA is disabled and restarted.
4.8 Host multi-word reads

The host may read from multiple consecutive 16-bit registers by keeping SPI_CSX asserted
and continuing to toggle SPI_CLK after the initial 16-bit data phase has completed.
The register address is incremented by 0x0200 at the end of each data phase for all register
address except the DMA DATA register.
Figure 20. Serial host multi-word read
Consecutive reads from the DMA DATA register are read from the DMA DATA register with
no address increment.

Figure 21. Serial host multi-word read DMA data
4.9 ARM AHB slave access

The ARM accesses the registers of the serial host via the AHB slave interface. Table 12 lists
the registers that are implemented. ‘Host only’ registers are listed for convenience only.
Table 12. ARM register

ARM Register
Offset Access Description Reference
0x00 R ARM INTERRUPT [31:0] ARMINT

0x04 W ARM INTERRUPT ACKNOWLEDGE [31:0] ARMINTACK
0x08 RW ARM INTERRUPT ENABLE [31:0] ARMINTEN
0x10 RW HOST INTERRUPT [31:0] HOSTINT
0x18 R HOST INTERRUPT ENABLE [31:0] HOSTINTEN
- - HOST INTERRUPT ACKNOWLEDGE [31:0] --
0X20 RW GP1 COMMUNICATION [31:0] GP1COM
0x24 RW GP2 COMMUNICATION [31:0] GP2COM
- - DEVICE CONTROL/STATUS [31:0] --
- - DMA DATA --
0x40 RW DMA WRITE CONTROL DMAWRITECONTROL
0x44 RW DMA WRITE LENGTH DMAWRITELENGTH
0x48 RW DMA WRITE BASE DMAWRITEBASE
0x50 RW DMA READ CONTROL DMAREADCONTROL
0x54 RW DMA READ LENGTH DMAREADLENGTH
0x58 RW DMA READ BASE DMAREADBASE

4.10 Recommended bootup sequence for SPI hosts

This sequence can be run with the maximum SPI clock frequency (that is, 48 MHz).
1. Power up.
2. Wait 240 ms.
3. Halt processor (EHostDeviceCntrl2 = KSetHostOverride | KSetHostCPUEn=0).
4. Wait 1 µs.
5. Enable DMA TX (EHostDmaTxCntrl, KDmaTxCntrlEnable).
6. Write DMA TX length (EHostDmaTxLength).
7. Write DMA TX base (EHostDmaTxBase1).
8. Wait 1 µs.
9. Write firmware image (EHostDmaData).
10. RAM reset (EHostDeviceCntrl2 = KSetHostOverride | KSetHostReset | KSetRamBoot).
11. Wait 40 ms.
12. RAM boot (EHostDeviceCntrl2 = KSetHostOverride | KSetRamBoot),
13. Enable host interrupts (EHostIntEnable1 = KIrqReady | KIrqWrReady | KHwUpdate |
KSwUpdate).
14. Wait for the READY interrupt (100 ms timeout).
15. Acknowledge the READY interrupt.
16. Issue the SLEEP interrupt.

Register descriptions STLC4560
5 Register descriptions
5.1 ARM INTERRUPT

The HOSTMSG bits of this register are written by the host and generate interrupts to the
ARM processor when the corresponding bit is set in the ARM INTERRUPT ENABLE
register. Writing a logic 1 causes the corresponding interrupt bit to be set. All other bits are
unaffected; previously set bits remain set. This register can be read/written while the device
is in sleep mode (that is, running off the low frequency oscillator) and not generate an
ARM_ASLEEP interrupt.
Note: Both the ARM and HOST INTERRUPT register have the bit ARM_ASLEEP. Although only
the host generates this bit it is used as an interrupt source to both. When the host receives
this interrupt, it is polls the DEVICE CONTROL/STATUS register until the SLEEPMODE
status bit is de-asserted by the ARM before continuing.
The format of the register is defined in Table 13.
r
Table 13. ARM INTERRUPT register

Bit position Name Description
Indicates that an access to hardware registers or

[31] ARM_ASLEEP device memory (by Host) was attempted while the
device was in sleep-mode.
[30] DMA WR DONE Last write occurred.
[29] DMA RD DONE Last read occurred.
[28] DMA RD READY DMA RD FIFO ready to be read.
[27:16] Reserved Undefined.
General purpose host message interrupts. May be
[15:0] HOSTMSG written by the host to cause an interrupt to the ARM
processor.

STLC4560 Register descriptions
5.2 ARM INTERRUPT ACKNOWLEDGE

This register is written by the ARM processor and clears bits in the ARM INTERRUPT
register. Writing a logic 1 in any bit position cause the corresponding interrupt bit to be
cleared. All other bits are unaffected.
Note: The host does not have access to this register.
Table 14. ARM INTERRUPT ACKNOWLEDGE register


[31] ARM_ASLEEP device memory (by the host) was attempted while
the device was in sleep-mode.
General purpose host message interrupts. May
[15:0] HOSTMSG be written by the host to cause an interrupt to the
ARM processor.
5.3 ARM INTERRUPT ENABLE

The ARM processor writes this register, and enables interrupts from the ARM INTERRUPT
register. An interrupt is generated when corresponding bits in both the ARM INTERRUPT
register and the ARM INTERRUPT ENABLE register are both logic 1.
Table 15. ARM INTERRUPT ENABLE register

Bit Position Name Description

General purpose host message interrupts. Written
[15:0] HOSTMSG
by the ARM to enable interrupt on selected bit(s)

5.4 HOST INTERRUPT

The bits of this register reflect the HOST INTERRUPT register with the masking by the
HOST INTERRUPT ENABLE register. This register can be written or read while the device
is in sleep mode (that is, running off the low frequency oscillator) and not generate an
ARM_ASLEEP interrupt.
Table 16. HOST INTERRUPT register

Indicates that an access to hardware registers or device

[31] ARM_ASLEEP memory (by the host) was attempted while the device was
in sleep-mode.
Level interrupt bit asserted when high frequency oscillator
is enabled and selected as the clock source for the MAC.
[27] NOTSLEEP 1 = MAC clocked by high FREQ OSC.
0 = MAC clocked by low FREQ OSC (for example,
32.768 kHz)
General purpose host message interrupts. Written by ARM
[15:0] ARMMSG
to cause an interrupt to the host.
5.5 HOST INTERRUPT ENABLE

The host writes this 32-bit register to enable interrupts from the HOST INTERRUPT register.
A host interrupt is generated if the corresponding bit in both the HOST INTERRUPT register
and the HOST INTERRUPT ENABLE register are both active.
Table 17. HOST INTERRUPT ENABLE register


Level interrupt bit asserted when high frequency
oscillator is enabled and selected as the clock
source for the MAC.
[27] NOTSLEEP
1 = MAC clocked by high frequency osc.
0 = MAC clocked by low frequency osc (that is,
32.768 kHz)

Table 17. HOST INTERRUPT ENABLE register (continued)


General purpose ARM message interrupts. Written
[15:0] ARMMSG
by ARM to cause an interrupt to the host.
5.6 HOST INTERRUPT ACKNOWLEDGE

This 32-bit register is written by the host, and clears interrupts in the HOST INTERRUPT
register. Writing a logic 1 in any bit position cause the corresponding interrupt bit to be
cleared. All other bits are unaffected.
Table 18. HOST INTERRUPT acknowledge register


General purpose ARM message interrupts. Written
[15:0] ARMMSG
by ARM to cause an interrupt to the host.
5.7 GENERAL PURPOSE 1 and 2 COMMUNICATION

These 32-bit general-purpose registers can be written to or read by either the host or the
ARM processor.
5.8 DEVICE CONTROL/STATUS

The DEVICE CONTROL/STATUS register is used by the host to configure the device by
writing to bits [31:27]. The status of the device is visible to the host by reading bits [22:6].
Table 19. DEVICE CONTROL/STATUS

Bit
Name Description
number
When set, tells processor to use boot options set by bits 30

[31] SETHOSTOVERRIDE
and 29 and override boot strapping options after reset.
When bit 31 is set, this bit forces CPU to remain idle when
[30] SETSTARTHALTED
reset is de-asserted (read/write).
When bit 31 is set, processor boots from RAM. Over-rides
[29] SETRAMBOOT
TMSEL strapping options (read/write).

Table 19. DEVICE CONTROL/STATUS (continued)

Bit
Name Description
number
When set, produces an active high(1) reset level to the ARM

[28] SETHOSTRESET
(read/write). Must be cleared to de-assert(0) reset.
Enables processor after STARTHALTED has been asserted
[27] SETHOSTCPUEN
(read/write).
[26:23] RESERVED Undefined
Indicates that the processor clock was stopped after the
[22] STARTHALTED
previous reset (read only).
[21] RESTARTASSERTED Indicates that OSC restart is asserted (read only).
[20] Reserved Undefined
Soft reset flag. A logic 1 indicates that the previous reset
[19] SOFTRES was generated by a write to the PMU system control
register bit 0.
RTC reset flag. A logic 1 indicates that the previous reset
[18] RTCRES
was generated by the real time clock.
Hard reset flag. A logic 1 indicates that the previous reset
[17] HARDRES
was generated by asserting the RESET_N pin.
Host reset flag. A logic 1 indicates that the previous reset
[16] HOSTRES was generated by the host asserting the HOSTRESET bit in
this register.
SLEEPMODE flag. A logic 1 indicates that the device is in
[15] SLEEPMODE sleep mode, that is, running off the low frequency oscillator
(read only).
The clock divisor setting on the PMU clock control register
[14:6] CLOCKDIVISOR
(read only).
[5] Reserved Undefined.
When asserted, SERHOST mode is updated by bits [3:0].
[4] USESERHOSTOVER RIDE 1: update SERHOST mode based on bits [3:0].
0: no change to SERHOST mode.
Number of wait states between the address and data phase
in 3_WIRE mode.
0: zero wait states between address and data phase.
HOST_3_
[3] 1: one wait state between address and data phase.
WIREADRDATAWAIT
Read value is currently selected 3_ WIREADRDATAWAIT.
May be different to the last written value when
USESERHOSTOVERRIDE is deasserted.
Select 3-WIRE mode using SPI_DIN for serial data input
and output.
0: use 4-wire mode, SPI_DIN input only and SPI_DOUT
output only.
[2] HOST_3_WIREMODE
1: use 3-wire mode, SPI_DIN for input and output.
Read value is currently selected 3_ WIREMODE.
May be different to the last written value when

Table 19. DEVICE CONTROL/STATUS (continued)

Bit
Name Description
number
Shift SPI_DIN and SPI_DOUT by 1 clock phase.

0: no phase shift.
1: phase shift SPI_DIN and SPI_DOUT by 1 clock phase.
[1] HOST_PHASESHIFT
Read value is currently selected PHASESHIFT. May be
different to the last written value when
Select active edge of SPI_CLK.
0: rising edge of SPI_CLK is active edge.
[0] HOST_INVERTCLOCK 1: falling edge of SPI_CLK is active edge.
Read value is currently selected INVERTCLOCK. May be
different from the last written value when
5.9 DMA DATA

The DATA register allows the host to read data directly from RAM or to write data directly
into RAM. The read address is post incremented by 0x0200 after each read.
The read length is decremented by 0x0200 after each read.
Data is prefetched into the DMA DATA register when the DMA READ ADDRESS is written
(if the DMA WRITE ENABLE bit is set). The write address is post incremented by 0x0200
after each write. The write length is decremented by 0x0200 after each write.
It is possible to mix reads and writes to the DMA DATA register if the both DMA read and
write channels are enabled.
Table 20. DMA DATA register

[15:0] DATA Data.

5.10 DMA WRITE CONTROL

The DMA WRITE CONTROL register allows either the ARM or the host to enable the DMA
write channel. Both the ARM and host are also able to control when the 32-bit APB access
is utilized. Only the ARM can modify the HOSTALLOWED bit. When the HOSTALLOWED
bit is de-asserted the host is not allowed to write the DMA WRITE CONTROL, LENGTH or
BASE registers.
Only bits [15:0] are accessible by the host.
Table 21. DMA WRITE CONTROL register

[31:8] Reserved Undefined

When bit is set, the host is allowed to write to DMA
WRITE CONTROL, LENGTH and BASE registers.
HOSTALLOWED bit is only writable by the ARM.
HOSTALLOWED default value is '1'.
[7] HOSTALLOWED
0: host is not permitted to write to CONTROL,
LENGTH and BASE registers.
1: host is permitted to write CONTROL, LENGTH
and BASE registers.
Bit must be asserted when DMA is used to write APB
registers.
[3] APBACCESS
0: access to APB register is not permitted.
1: access to APB register is permitted.
0: DMA WRITE disabled.
[0] ENABLE
1: DMA WRITE enabled.
5.11 DMA WRITE LENGTH

This 16-bit register is programmed with the maximum byte count of the next DMA write
transfer. Only the low-order 16 bits are used. The value programmed can be any number of
bytes from 1 to 65535.
Table 22. DMA WRITE LENGTH register


[15:0] DATA LENGTH Maximum byte count.

5.12 DMA WRITE BASE ADDRESS

The DMA WRITE BASE ADDRESS is written to point to the first location for the DMA DATA
register write in the devices AHB space. The address will be incremented after every host
access to the DATA register. There is no restriction on the base address. Byte, half-word,
word and quadword addresses are supported.
Table 23. DMA WRITE BASE ADDRESS register

[31:0] DMA WRITE BASE Address for first DMA write.
5.13 DMA READ CONTROL

The DMA READ CONTROL register allows the ARM or host to enable the DMA read
channel. Only the ARM can modify the HOSTALLOWED bit. When the HOSTALLOWED bit
is de-asserted the host is not allowed to write the DMA READ CONTROL, LENGTH or
BASE registers.
Only bits 15:0 are accessible by the host.
Table 24. DMA READ CONTROL register


When bit is set, the host is allowed to write to DMA
READ CONTROL, LENGTH and BASE registers.
HOSTALLOWED bit is only writable by the ARM.
HOSTALLOWED default value is 1.
[7] HOST ALLOWED
0: host is not permitted to write CONTROL, LENGTH
and BASE registers.
1: host is permitted to write CONTROL, LENGTH
and BASE registers.
0: DMA READ disabled.
[0] ENABLE
1: DMA READ enabled.
5.14 DMA READ LENGTH

This 16-bit register is programmed with the maximum byte count of the next DMA read
transfer. Only the low-order 16 bits are used. The value programmed can be any number of
bytes from 1 to 65535. A value of ‘0’ disables the byte count logic, causing any transfers to
continue until terminated by clearing the ENABLE bit.
Table 25. DMA READ LENGTH register


[15:0] DATA LENGTH Maximum byte count.

5.15 DMA READ BASE ADDRESS

The DMA READ BASE ADDRESS is written to point to the first location for the DMA DATA
register read in the devices AHB space. The address is incremented after every host access
to the data register. There is no restriction on the BASE ADDRESS. Byte, half-word, word
and quadword addresses are supported.
Table 26. DMA read base address register

[31:0] DMA READ BASE Address for first DMA write.

STLC4560 Package information
6 Package information
6.1 Mechanical data and dimensions

Figure 22. LFBGA240 mechanical data and package dimensions
mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.4 0.055
A1 0.15 0.006
A2 1.065 0.042
A3 0.28 0.011
A4 0.8 0.031
b 0.25 0.3 0.35 0.010 0.012 0.014
D 8.35 8.5 8.65 0.329 0.335 0.341
D1 7.5 0.295
E 7.85 8 8.15 0.309 0.315 0.321
E1 7 0.276
e 0.5 0.020 Body: 8.5 x 8 x 1.4mm
F 0.5 0.020
ddd 0.08 0.003

LFBGA240
eee 0.15 0.006
Low Profile Ball Grid Array
fff 0.05 0.002
7870466 A

Ordering information STLC4560
6.2 Marking information

The marking information of the component is stored in the BSA document, which is stored
within the PRIS system. This document is owned by the CPA division (central packaging)
and shared with planning, engineering and plants.
Table 27. BGA content and marking information

Marking CD00 CD04 TG24 Laminate BOM source
STLC4560-1 V.1 V.1 V.1 V.1 V.1

STLC4560-2 For internal qualification only.
STLC4560-3 V.1 V.1 V.1.1(1) V.1 V.1
1. The TG24 silicon remains unchanged. The programming of the embedded flash is modified. The delay
between the startup of V2X on one side and V1 and V2 on the other side is set to 0ms.
7 Ordering information
Table 28. Order code

Operating
Part number Package Packing
temperature range
STLC4560TRAY -30°C to 85°C LFBGA240- (8.5x8x1.4mm) Tray

STLC4560 -30°C to 85°C LFBGA240- (8.5x8x1.4mm) Tape and reel

STLC4560 Revision history
8 Revision history
Table 29. Document revision history

Date Revision Changes
19-Nov-2007 F Add the reference STLC4560-2 in Table 27

18-Oct-2007 E Power consumption figures adjusted in Table 5
Multiple changes to Features, Description, Table 1 related to the
supression of SDIO support.
Description of POWER_UP modified in Table 1.
11-Jul-2007 D Addition of reference clock input impedance in Table 6.
Addition of Table 27.
The power consumption figures on p15 are preliminary.
Moved the ordering information to Chapter 7: Ordering information
All pins in VIO domain listed in Table 1.
28-Feb-2007 C
A8 & B8 balls moved from RSRV_GND to RSRV_NC in Table 1.
Updates to Table 1: Pin description on page 6, added Table 2 on
page 13 and Table 3 on page 13.
In Chapter 2.1: Electrical characteristics: Added Table 4: ESD &
latch-up classification on page 14. Updated Table 5: Electrical
characteristics on page 14, Table 6: Host interface specifications on
29-Jan-2007 B page 19.
In Chapter 3: Reference clock: Updated Table 7: Reference clock
general on page 21.
In Chapter 4: Serial host interface: Added Section 4.10:
Recommended bootup sequence for SPI hosts on page 31.
Additional section: Section 6.2: Marking information on page 42
20-Nov-2006 A Initial version.

STLC4560
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STLC4560

Single chip 802.11b/g WLAN radio

November 2007 8030121 rev F- ST Confidential 1/44

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Serial host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/44 8030121 rev F- ST Confidential

5.9 DMA DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8030121 rev F- ST Confidentiall 3/44

1 Block diagram and pin description

Figure 1. Block diagram

Power management unit (PMU)

4/44 8030121 rev F- ST Confidential

1.1 Pin connection

8030121 rev F- ST Confidentiall 5/44

1.2 Pin description

RF front end interface pins

PA_DET0 M12 Analog input PA detector.

Host interface and clock pins

Host interrupt request. Typically asserted to

6/44 8030121 rev F- ST Confidential

Table 1. Pin description (continued)

MODE strapping pins are used to initialize the

8030121 rev F- ST Confidentiall 7/44

Table 1. Pin description (continued)

Power supply pins

Battery supply input for regulator V1 of the

8/44 8030121 rev F- ST Confidential

Table 1. Pin description (continued)

Analog 1.86 V supply input for the RF voltage

Host digital I/O supply input for SPI and

8030121 rev F- ST Confidentiall 9/44

Table 1. Pin description (continued)

PMU_DGND D4 Ground Ground of the PMU level shifter.

Firmware controlled 3 V digital GPIO. Float for

10/44 8030121 rev F- ST Confidential

Table 1. Pin description (continued)

Firmware controlled 1.86 V digital GPIO. Float

PMU_SCL B3 Miscellaneous (I/P) PMU programming I2C clock.(1)

8030121 rev F- ST Confidentiall 11/44

Table 1. Pin description (continued)

JTAG clock. Internal pull-up active in normal

12/44 8030121 rev F- ST Confidential

Table 2. I/O voltage level as determined by VDIG

Note: See Table 5 for VDIG operating conditions.

Table 3. SWx (x={1, 2, 3, 4}) output depending on the TX/RX state

WLAN TX Low High Low High

8030121 rev F- ST Confidentiall 13/44

The STLC4560 has an ESD classification as follows:

Table 4. ESD & latch-up classification

all +1.8kV / -1.8kV + 500V / -400V 200mA

Electrical specifications of the STLC4560 are provided in Table 5.

2.1 Electrical characteristics

Absolute maximum ratings

PMU VBATT (Vcc) -0.3 - 7.0 V

Operating conditions and input power specifications

Operating temperature range -30 85 oC

Power management unit VBATT supply

14/44 8030121 rev F- ST Confidential

Table 5. Electrical characteristics (continued)

Power management unit VBATT supply

Standby current 25 oC, POWER_UP = 0V. The resulting 10 µA

25 oC, POWERUP = 1.86 V. The radio is