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z/Architecture
Principles of Operation
SA22-7832-08
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z/Architecture
Principles of Operation
SA22-7832-08
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v
Nullification . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Control Register 2 . . . . . . . . . . . . . . . . . . . .5-50
Termination . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Control Register 5 . . . . . . . . . . . . . . . . . . . .5-50
Interruptible Instructions. . . . . . . . . . . . . . . . . 5-20 Control Register 8 . . . . . . . . . . . . . . . . . . . .5-51
Point of Interruption . . . . . . . . . . . . . . . . . . 5-20 Access Registers. . . . . . . . . . . . . . . . . . . . . . .5-51
Unit of Operation . . . . . . . . . . . . . . . . . . . . 5-20 Access-Register-Translation Tables . . . . . . . .5-52
Execution of Interruptible Instructions . . . . 5-21 Dispatchable-Unit Control Table and
Condition-Code Alternative to Access-List Designations . . . . . . . . . . . . .5-52
Interruptibility . . . . . . . . . . . . . . . . . . . . . . 5-22 Access-List Entries . . . . . . . . . . . . . . . . . . .5-53
Exceptions to Nullification and Suppression . 5-23 ASN-Second-Table Entries . . . . . . . . . . . . .5-54
Storage Change and Restoration for DAT- Access-Register-Translation Process . . . . . . .5-55
Associated Access Exceptions . . . . . . . . 5-23 Selecting the Access-List-Entry Token . . . .5-58
Modification of DAT-Table Entries . . . . . . . 5-24 Obtaining the Primary or Secondary
Trial Execution for Editing Instructions and Address-Space-Control Element . . . . . . . .5-58
Translate Instruction. . . . . . . . . . . . . . . . . 5-24 Checking the First Byte of the ALET . . . . . .5-58
Authorization Mechanisms . . . . . . . . . . . . . . . . . 5-24 Obtaining the Effective Access-List
Mode Requirements . . . . . . . . . . . . . . . . . . 5-24 Designation . . . . . . . . . . . . . . . . . . . . . . . .5-58
Extraction-Authority Control . . . . . . . . . . . . 5-25 Access-List Lookup . . . . . . . . . . . . . . . . . . .5-58
PSW-Key Mask . . . . . . . . . . . . . . . . . . . . . 5-25 Locating the ASN-Second-Table Entry . . . .5-59
Secondary-Space Control . . . . . . . . . . . . . 5-25 Authorizing the Use of the Access-List
Subsystem-Linkage Control . . . . . . . . . . . . 5-26 Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-59
ASN-Translation Control . . . . . . . . . . . . . . 5-26 Checking for Access-List-Controlled
Authorization Index . . . . . . . . . . . . . . . . . . 5-26 Protection . . . . . . . . . . . . . . . . . . . . . . . . .5-60
Instructions and Controls Related to ASN- Obtaining the Address-Space-Control Element
and-LX Reuse . . . . . . . . . . . . . . . . . . . . . 5-27 from the ASN-Second-Table Entry . . . . . .5-60
PC-Number Translation . . . . . . . . . . . . . . . . . . . 5-30 Recognition of Exceptions during Access-
PC-Number Translation Control. . . . . . . . . . . 5-31 Register Translation . . . . . . . . . . . . . . . . .5-60
Control Register 0 . . . . . . . . . . . . . . . . . . . 5-31 ART-Lookaside Buffer . . . . . . . . . . . . . . . . . . .5-60
Control Register 5 . . . . . . . . . . . . . . . . . . . 5-32 ALB Structure . . . . . . . . . . . . . . . . . . . . . . .5-60
PC-Number Translation Tables . . . . . . . . . . . 5-32 Formation of ALB Entries . . . . . . . . . . . . . .5-60
Linkage-Table Entries . . . . . . . . . . . . . . . . 5-33 Use of ALB Entries . . . . . . . . . . . . . . . . . . .5-61
Linkage-First-Table Entries . . . . . . . . . . . . 5-33 Modification of ART Tables . . . . . . . . . . . . .5-61
Linkage-Second-Table Entries . . . . . . . . . . 5-33 Subspace Groups . . . . . . . . . . . . . . . . . . . . . . . .5-62
Entry-Table Entries. . . . . . . . . . . . . . . . . . . 5-34 Subspace-Group Tables . . . . . . . . . . . . . . . . .5-62
Table Summary . . . . . . . . . . . . . . . . . . . . . 5-35 Subspace-Group Dispatchable-Unit Control
PC-Number-Translation Process . . . . . . . . . . 5-35 Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-62
Obtaining the Linkage-Table or Linkage- Subspace-Group ASN-Second-Table
First-Table Designation . . . . . . . . . . . . . . 5-39 Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-64
Linkage-Table Lookup . . . . . . . . . . . . . . . . 5-39 Subspace-Replacement Operations . . . . . . . .5-65
Linkage-First-Table Lookup . . . . . . . . . . . . 5-39 Linkage-Stack Introduction . . . . . . . . . . . . . . . . .5-66
Linkage-Second-Table Lookup . . . . . . . . . 5-40 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-66
Linkage-Second-Table-Entry-Sequence- Linkage-Stack Functions . . . . . . . . . . . . . . . . .5-67
Number Comparison . . . . . . . . . . . . . . . . 5-40 Transferring Program Control . . . . . . . . . . .5-67
Entry-Table Lookup . . . . . . . . . . . . . . . . . . 5-40 Branching Using the Linkage Stack. . . . . . .5-69
Recognition of Exceptions during PC- Adding and Retrieving Information . . . . . . .5-70
Number Translation . . . . . . . . . . . . . . . . . 5-41 Testing Authorization. . . . . . . . . . . . . . . . . .5-70
Home Address Space . . . . . . . . . . . . . . . . . . . . 5-41 Program-Problem Analysis . . . . . . . . . . . . .5-71
Access-Register Introduction . . . . . . . . . . . . . . . 5-42 Linkage-Stack Entry-Table Entries . . . . . . . . . . .5-71
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Linkage-Stack Operations . . . . . . . . . . . . . . . . . .5-72
Access-Register Functions . . . . . . . . . . . . . . 5-43 Linkage-Stack-Operations Control . . . . . . . . .5-74
Access-Register-Specified Address Control Register 0 . . . . . . . . . . . . . . . . . . . .5-74
Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 Control Register 15 . . . . . . . . . . . . . . . . . . .5-74
Access-Register Instructions . . . . . . . . . . . 5-49 Linkage Stack . . . . . . . . . . . . . . . . . . . . . . . . .5-74
Access-Register Translation . . . . . . . . . . . . . . . 5-50 Entry Descriptors . . . . . . . . . . . . . . . . . . . . .5-75
Access-Register-Translation Control . . . . . . . 5-50 Header Entries. . . . . . . . . . . . . . . . . . . . . . .5-76
vii
Page-Translation Exception . . . . . . . . . . . . 6-27 ADD LOGICAL WITH SIGNED IMMEDIATE
PC-Translation-Specification Exception . . . 6-28 HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
PER Event . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
Primary-Authority Exception. . . . . . . . . . . . 6-28 AND IMMEDIATE . . . . . . . . . . . . . . . . . . . . . .7-32
Privileged-Operation Exception . . . . . . . . . 6-29 BRANCH AND LINK . . . . . . . . . . . . . . . . . . . .7-33
Protection Exception . . . . . . . . . . . . . . . . . 6-30 BRANCH AND SAVE . . . . . . . . . . . . . . . . . . .7-34
Region-First-Translation Exception . . . . . . 6-30 BRANCH AND SAVE AND SET MODE . . . . .7-35
Region-Second-Translation Exception. . . . 6-31 BRANCH AND SET MODE . . . . . . . . . . . . . . .7-36
Region-Third-Translation Exception. . . . . . 6-31 BRANCH ON CONDITION . . . . . . . . . . . . . . .7-36
Secondary-Authority Exception . . . . . . . . . 6-32 BRANCH ON COUNT . . . . . . . . . . . . . . . . . . .7-37
Segment-Translation Exception . . . . . . . . . 6-32 BRANCH ON INDEX HIGH . . . . . . . . . . . . . . .7-38
Space-Switch Event . . . . . . . . . . . . . . . . . . 6-32 BRANCH ON INDEX LOW OR EQUAL . . . . .7-38
Special-Operation Exception . . . . . . . . . . . 6-33 BRANCH RELATIVE AND SAVE . . . . . . . . . .7-39
Specification Exception . . . . . . . . . . . . . . . 6-35 BRANCH RELATIVE AND SAVE LONG. . . . .7-39
Stack-Empty Exception . . . . . . . . . . . . . . . 6-38 BRANCH RELATIVE ON CONDITION . . . . . .7-40
Stack-Full Exception. . . . . . . . . . . . . . . . . . 6-38 BRANCH RELATIVE ON CONDITION LONG 7-40
Stack-Operation Exception. . . . . . . . . . . . . 6-39 BRANCH RELATIVE ON COUNT. . . . . . . . . .7-41
Stack-Specification Exception . . . . . . . . . . 6-39 BRANCH RELATIVE ON COUNT HIGH. . . . .7-41
Stack-Type Exception . . . . . . . . . . . . . . . . 6-39 BRANCH RELATIVE ON INDEX HIGH. . . . . .7-41
Trace-Table Exception . . . . . . . . . . . . . . . . 6-39 BRANCH RELATIVE ON INDEX LOW OR
Translation-Specification Exception . . . . . . 6-40 EQUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-41
Collective Program-Interruption Names . . . . . 6-40 CHECKSUM . . . . . . . . . . . . . . . . . . . . . . . . . .7-43
Recognition of Access Exceptions . . . . . . . . . 6-40 CIPHER MESSAGE . . . . . . . . . . . . . . . . . . . .7-46
Multiple Program-Interruption Conditions. . . . 6-44 CIPHER MESSAGE WITH CHAINING . . . . . .7-46
Access Exceptions . . . . . . . . . . . . . . . . . . . 6-46 KM-Query (KM Function Code 0) . . . . . . . .7-50
ASN-Translation Exceptions . . . . . . . . . . . 6-49 KM-DEA (KM Function Code 1) . . . . . . . . .7-51
Subspace-Replacement Exceptions . . . . . 6-49 KM-Encrypted-DEA (KM Function Code 9) .7-51
Trace Exceptions . . . . . . . . . . . . . . . . . . . . 6-49 KM-TDEA-128 (KM Function Code 2) . . . . .7-51
Restart Interruption . . . . . . . . . . . . . . . . . . . . . . 6-49 KM-Encrypted-TDEA-128 (KM Function
Supervisor-Call Interruption . . . . . . . . . . . . . . . . 6-50 Code 10) . . . . . . . . . . . . . . . . . . . . . . . . . .7-51
Priority of Interruptions . . . . . . . . . . . . . . . . . . . . 6-50 KM-TDEA-192 (KM Function Code 3) . . . . .7-53
KM-Encrypted-TDEA-192 (KM Function
Chapter 7, General Instructions. . . . . .7-1 Code 11) . . . . . . . . . . . . . . . . . . . . . . . . . .7-53
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 KM-AES-128 (KM Function Code 18) . . . . .7-54
Binary-Integer Representation . . . . . . . . . . . . . . . 7-5 KM-Encrypted-AES-128 (KM Function
Binary Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Code 26) . . . . . . . . . . . . . . . . . . . . . . . . . .7-54
Signed Binary Arithmetic . . . . . . . . . . . . . . . . . 7-6 KM-AES-192 (KM Function Code 19) . . . . .7-55
Addition and Subtraction . . . . . . . . . . . . . . . 7-6 KM-Encrypted-AES-192 (KM Function
Fixed-Point Overflow . . . . . . . . . . . . . . . . . . 7-7 Code 27) . . . . . . . . . . . . . . . . . . . . . . . . . .7-55
Unsigned Binary Arithmetic . . . . . . . . . . . . . . . 7-7 KM-AES-256 (KM Function Code 20) . . . . .7-56
Signed and Logical Comparison . . . . . . . . . . . . . 7-8 KM-Encrypted-AES-256 (KM Function
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Code 28) . . . . . . . . . . . . . . . . . . . . . . . . . .7-56
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 KM-XTS-AES-128 (KM Function Code 50) .7-57
ADD IMMEDIATE. . . . . . . . . . . . . . . . . . . . . . 7-25 KM-XTS-Encrypted-AES-128 (KM Function
ADD HALFWORD . . . . . . . . . . . . . . . . . . . . . 7-27 Code 58) . . . . . . . . . . . . . . . . . . . . . . . . . .7-57
ADD HALFWORD IMMEDIATE . . . . . . . . . . . 7-27 KM-XTS-AES-256 (KM Function Code 52) .7-59
ADD HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 KM-XTS-Encrypted-AES-256 (KM Function
ADD IMMEDIATE HIGH. . . . . . . . . . . . . . . . . 7-28 Code 60) . . . . . . . . . . . . . . . . . . . . . . . . . .7-59
ADD LOGICAL . . . . . . . . . . . . . . . . . . . . . . . . 7-28 KMC-Query (KMC Function Code 0). . . . . .7-60
ADD LOGICAL IMMEDIATE . . . . . . . . . . . . . 7-28 KMC-DEA (KMC Function Code 1) . . . . . . .7-61
ADD LOGICAL HIGH . . . . . . . . . . . . . . . . . . . 7-29 KMC-Encrypted-DEA (KMC Function
ADD LOGICAL WITH CARRY . . . . . . . . . . . . 7-29 Code 9) . . . . . . . . . . . . . . . . . . . . . . . . . . .7-61
ADD LOGICAL WITH SIGNED IMMEDIATE . 7-30 KMC-TDEA-128 (KMC Function Code 2) . .7-62
ix
COMPARE LOGICAL LONG . . . . . . . . . . . . 7-135 EXECUTE . . . . . . . . . . . . . . . . . . . . . . . . . . .7-207
COMPARE LOGICAL LONG EXTENDED. . 7-138 EXECUTE RELATIVE LONG . . . . . . . . . . . .7-207
COMPARE LOGICAL LONG UNICODE . . . 7-140 EXTRACT ACCESS . . . . . . . . . . . . . . . . . . .7-208
COMPARE LOGICAL STRING . . . . . . . . . . 7-143 EXTRACT CACHE ATTRIBUTE . . . . . . . . . .7-208
COMPARE UNTIL SUBSTRING EQUAL . . 7-144 EXTRACT CPU TIME . . . . . . . . . . . . . . . . . .7-210
COMPRESSION CALL . . . . . . . . . . . . . . . . 7-147 EXTRACT PSW . . . . . . . . . . . . . . . . . . . . . .7-210
COMPUTE INTERMEDIATE MESSAGE FIND LEFTMOST ONE . . . . . . . . . . . . . . . . .7-211
DIGEST . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159 INSERT CHARACTER . . . . . . . . . . . . . . . . .7-211
COMPUTE LAST MESSAGE DIGEST . . . . 7-159 INSERT CHARACTERS UNDER MASK. . . .7-212
KIMD-Query (KIMD Function Code 0) . . . 7-162 INSERT IMMEDIATE . . . . . . . . . . . . . . . . . .7-212
KIMD-SHA-1 (KIMD Function Code 1). . . 7-162 INSERT PROGRAM MASK. . . . . . . . . . . . . .7-213
KIMD-SHA-256 (KIMD Function Code 2). 7-163 LOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-213
KIMD-SHA-512 (KIMD Function Code 3). 7-163 LOAD IMMEDIATE . . . . . . . . . . . . . . . . . . . .7-213
KIMD-GHASH (Function Code 65). . . . . . 7-164 LOAD RELATIVE LONG . . . . . . . . . . . . . . . .7-214
KLMD-Query (KLMD Function Code 0) . . 7-164 LOAD ACCESS MULTIPLE . . . . . . . . . . . . .7-214
KLMD-SHA-1 (KLMD Function Code 1). . 7-165 LOAD ADDRESS . . . . . . . . . . . . . . . . . . . . .7-215
KLMD-SHA-256 (KLMD Function Code 2) 7-166 LOAD ADDRESS EXTENDED . . . . . . . . . . .7-215
KLMD-SHA-512 (KLMD Function Code 3) 7-168 LOAD ADDRESS RELATIVE LONG. . . . . . .7-216
COMPUTE MESSAGE AUTHENTICATION LOAD AND ADD . . . . . . . . . . . . . . . . . . . . . .7-217
CODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-171 LOAD AND ADD LOGICAL . . . . . . . . . . . . . .7-217
KMAC-Query (Function Code 0) . . . . . . . 7-175 LOAD AND AND . . . . . . . . . . . . . . . . . . . . . .7-218
KMAC-DEA (Function Code 1). . . . . . . . . 7-175 LOAD AND EXCLUSIVE OR. . . . . . . . . . . . .7-218
KMAC-Encrypted-DEA (Function Code 9) 7-175 LOAD AND OR . . . . . . . . . . . . . . . . . . . . . . .7-219
KMAC-TDEA-128 (Function Code 2) . . . . 7-176 LOAD AND TEST . . . . . . . . . . . . . . . . . . . . .7-219
KMAC-Encrypted-TDEA-128 (Function LOAD BYTE . . . . . . . . . . . . . . . . . . . . . . . . .7-220
Code 10) . . . . . . . . . . . . . . . . . . . . . . . . 7-176 LOAD BYTE HIGH . . . . . . . . . . . . . . . . . . . .7-221
KMAC-TDEA-192 (Function Code 3) . . . . 7-177 LOAD COMPLEMENT . . . . . . . . . . . . . . . . .7-221
KMAC-Encrypted-TDEA-192 (Function LOAD HALFWORD . . . . . . . . . . . . . . . . . . . .7-221
Code 11) . . . . . . . . . . . . . . . . . . . . . . . . 7-177 LOAD HALFWORD IMMEDIATE . . . . . . . . .7-222
KMAC-AES-128 (Function Code 18) . . . . 7-178 LOAD HALFWORD RELATIVE LONG . . . . .7-222
KMAC-Encrypted-AES-128 (Function LOAD HALFWORD HIGH . . . . . . . . . . . . . . .7-222
Code 26) . . . . . . . . . . . . . . . . . . . . . . . . 7-178 LOAD HIGH. . . . . . . . . . . . . . . . . . . . . . . . . .7-223
KMAC-AES-192 (Function Code 19) . . . . 7-179 LOAD LOGICAL . . . . . . . . . . . . . . . . . . . . . .7-223
KMAC-Encrypted-AES-192 (Function LOAD LOGICAL RELATIVE LONG. . . . . . . .7-223
Code 27) . . . . . . . . . . . . . . . . . . . . . . . . 7-179 LOAD LOGICAL CHARACTER. . . . . . . . . . .7-223
KMAC-AES-256 (Function Code 20) . . . . 7-179 LOAD LOGICAL CHARACTER HIGH. . . . . .7-224
KMAC-Encrypted-AES-256 (Function LOAD LOGICAL HALFWORD. . . . . . . . . . . .7-224
Code 28) . . . . . . . . . . . . . . . . . . . . . . . . 7-179 LOAD LOGICAL HALFWORD RELATIVE
CONVERT TO BINARY . . . . . . . . . . . . . . . . 7-181 LONG . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-224
CONVERT TO DECIMAL. . . . . . . . . . . . . . . 7-182 LOAD LOGICAL HALFWORD HIGH. . . . . . .7-225
CONVERT UTF-16 TO UTF-32 . . . . . . . . . . 7-183 LOAD LOGICAL IMMEDIATE . . . . . . . . . . . .7-225
CONVERT UTF-16 TO UTF-8 . . . . . . . . . . . 7-186 LOAD LOGICAL THIRTY ONE BITS . . . . . .7-226
CONVERT UNICODE TO UTF-8. . . . . . . . . 7-186 LOAD MULTIPLE . . . . . . . . . . . . . . . . . . . . .7-226
CONVERT UTF-32 TO UTF-16 . . . . . . . . . . 7-189 LOAD MULTIPLE DISJOINT. . . . . . . . . . . . .7-227
CONVERT UTF-32 TO UTF-8 . . . . . . . . . . . 7-192 LOAD MULTIPLE HIGH . . . . . . . . . . . . . . . .7-227
CONVERT UTF-8 TO UTF-16 . . . . . . . . . . . 7-195 LOAD NEGATIVE . . . . . . . . . . . . . . . . . . . . .7-227
CONVERT UTF-8 TO UNICODE. . . . . . . . . 7-195 LOAD ON CONDITION . . . . . . . . . . . . . . . . .7-228
CONVERT UTF-8 TO UTF-32 . . . . . . . . . . . 7-199 LOAD PAIR DISJOINT . . . . . . . . . . . . . . . . .7-229
COPY ACCESS . . . . . . . . . . . . . . . . . . . . . . 7-203 LOAD PAIR FROM QUADWORD . . . . . . . . .7-230
DIVIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-203 LOAD POSITIVE . . . . . . . . . . . . . . . . . . . . . .7-230
DIVIDE LOGICAL. . . . . . . . . . . . . . . . . . . . . 7-204 LOAD REVERSED . . . . . . . . . . . . . . . . . . . .7-230
DIVIDE SINGLE . . . . . . . . . . . . . . . . . . . . . . 7-204 MONITOR CALL . . . . . . . . . . . . . . . . . . . . . .7-231
EXCLUSIVE OR. . . . . . . . . . . . . . . . . . . . . . 7-205 Monitor-Event Program Interruption . . . . .7-232
EXCLUSIVE OR IMMEDIATE . . . . . . . . . . . 7-206 Monitor-Event Counting Operation . . . . . .7-232
xi
STORE MULTIPLE HIGH . . . . . . . . . . . . . . 7-309 EDIT AND MARK . . . . . . . . . . . . . . . . . . . . . .8-10
STORE ON CONDITION . . . . . . . . . . . . . . . 7-309 MULTIPLY DECIMAL . . . . . . . . . . . . . . . . . . .8-11
STORE PAIR TO QUADWORD. . . . . . . . . . 7-310 SHIFT AND ROUND DECIMAL . . . . . . . . . . .8-12
STORE REVERSED . . . . . . . . . . . . . . . . . . 7-310 SUBTRACT DECIMAL . . . . . . . . . . . . . . . . . .8-13
SUBTRACT . . . . . . . . . . . . . . . . . . . . . . . . . 7-311 TEST DECIMAL . . . . . . . . . . . . . . . . . . . . . . .8-13
SUBTRACT HALFWORD . . . . . . . . . . . . . . 7-312 ZERO AND ADD . . . . . . . . . . . . . . . . . . . . . . .8-13
SUBTRACT HIGH . . . . . . . . . . . . . . . . . . . . 7-312
SUBTRACT LOGICAL . . . . . . . . . . . . . . . . . 7-313 Chapter 9, Floating-Point Overview and
SUBTRACT LOGICAL IMMEDIATE . . . . . . 7-313
Support Instructions . . . . . . . . . . . . . 9-1
SUBTRACT LOGICAL HIGH . . . . . . . . . . . . 7-314
Sign Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
SUBTRACT LOGICAL WITH BORROW . . . 7-314
Finite Floating-Point Numbers . . . . . . . . . . . .9-2
SUPERVISOR CALL . . . . . . . . . . . . . . . . . . 7-315
Infinities . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
TEST ADDRESSING MODE . . . . . . . . . . . . 7-315
Not-A-Number (NaN). . . . . . . . . . . . . . . . . . . . .9-2
TEST AND SET . . . . . . . . . . . . . . . . . . . . . . 7-316
Signaling and Quiet NaNs . . . . . . . . . . . . . . .9-2
TEST UNDER MASK (TEST UNDER MASK
Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
HIGH, TEST UNDER MASK LOW) . . . . . . 7-316
Propagation of NaNs . . . . . . . . . . . . . . . . . . .9-3
TRANSLATE . . . . . . . . . . . . . . . . . . . . . . . . 7-317
Default QNaN . . . . . . . . . . . . . . . . . . . . . . . .9-3
TRANSLATE AND TEST . . . . . . . . . . . . . . . 7-318
Hexadecimal-Floating-Point (HFP) . . . . . . . . . .9-3
TRANSLATE AND TEST EXTENDED. . . . . 7-319
Binary Floating-Point (BFP). . . . . . . . . . . . . . . .9-4
TRANSLATE AND TEST REVERSE
Decimal Floating-Point (DFP) . . . . . . . . . . . . . .9-4
EXTENDED . . . . . . . . . . . . . . . . . . . . . . . . 7-319
Canonical DFP Data . . . . . . . . . . . . . . . . . . .9-4
TRANSLATE AND TEST REVERSE . . . . . . 7-323
Comparison of Floating-Point Number
TRANSLATE EXTENDED . . . . . . . . . . . . . . 7-324
Representations . . . . . . . . . . . . . . . . . . . . . . .9-4
TRANSLATE ONE TO ONE . . . . . . . . . . . . 7-327
Floating-Point Number Ranges . . . . . . . . . . .9-4
TRANSLATE ONE TO TWO . . . . . . . . . . . . 7-327
Equivalent Floating-Point Number
TRANSLATE TWO TO ONE . . . . . . . . . . . . 7-327
Representations . . . . . . . . . . . . . . . . . . . . .9-5
TRANSLATE TWO TO TWO . . . . . . . . . . . . 7-327
Effective Width. . . . . . . . . . . . . . . . . . . . . . . .9-7
UNPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-331
Floating-Point Data in Storage . . . . . . . . . . . . .9-8
UNPACK ASCII . . . . . . . . . . . . . . . . . . . . . . 7-332
Registers And Controls . . . . . . . . . . . . . . . . . . . . .9-8
UNPACK UNICODE. . . . . . . . . . . . . . . . . . . 7-333
Floating-Point Registers . . . . . . . . . . . . . . . . . .9-8
UPDATE TREE . . . . . . . . . . . . . . . . . . . . . . 7-334
Additional Floating-Point (AFP) Registers . . .9-9
Protection of Cryptographic Key . . . . . . . . . . . 7-339
Valid Floating-Point-Register Designations . .9-9
Protection of DES Keys . . . . . . . . . . . . . . . . 7-340
Floating-Point-Control (FPC) Register. . . . . . . .9-9
Protection of AES Keys . . . . . . . . . . . . . . . . 7-341
IEEE Masks and Flags . . . . . . . . . . . . . . . .9-10
FPC DXC Byte. . . . . . . . . . . . . . . . . . . . . . .9-10
Chapter 8, Decimal Instructions . . . . .8-1 Operations on the FPC Register . . . . . . . . .9-10
Decimal-Number Formats . . . . . . . . . . . . . . . . . . 8-1 AFP-Register-Control Bit . . . . . . . . . . . . . . . . .9-11
Zoned Format . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 IEEE Computational Operations . . . . . . . . . . . . .9-11
Packed-Decimal Formats. . . . . . . . . . . . . . . . . 8-1 Intermediate Values . . . . . . . . . . . . . . . . . . . .9-11
Signed-Packed-Decimal Format . . . . . . . . . 8-1 Precise Intermediate Value . . . . . . . . . . . . .9-12
Unsigned-Packed-Decimal Format . . . . . . . 8-2 Precision-Rounded Value . . . . . . . . . . . . . .9-12
Decimal Codes. . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Denormalized Value . . . . . . . . . . . . . . . . . .9-12
Decimal Operations . . . . . . . . . . . . . . . . . . . . . . . 8-3 Functionally-Rounded Value . . . . . . . . . . . .9-12
Decimal-Arithmetic Instructions . . . . . . . . . . . . 8-3 Rounded Intermediate Value. . . . . . . . . . . .9-12
Editing Instructions. . . . . . . . . . . . . . . . . . . . . . 8-4 Scaled Value . . . . . . . . . . . . . . . . . . . . . . . .9-12
Execution of Decimal Instructions . . . . . . . . . . 8-4 Scale Factor (Ψ) . . . . . . . . . . . . . . . . . . . . .9-12
Other Instructions for Decimal Operands. . . . . 8-4 Unsigned Scaling Exponent (α). . . . . . . . . .9-12
Decimal-Operand Data Exception . . . . . . . . . . 8-4 Signed Scaling Exponent (Ω) . . . . . . . . . . .9-12
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 IEEE Rounding . . . . . . . . . . . . . . . . . . . . . . . .9-13
ADD DECIMAL. . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Permissible Set . . . . . . . . . . . . . . . . . . . . . .9-13
COMPARE DECIMAL . . . . . . . . . . . . . . . . . . . 8-6 Selection of Candidates. . . . . . . . . . . . . . . .9-13
DIVIDE DECIMAL . . . . . . . . . . . . . . . . . . . . . . 8-7 Ties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
EDIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
xiii
PCKMO-Encrypt-AES-192-Key (Function Chapter 11, Machine-Check
Code 19) . . . . . . . . . . . . . . . . . . . . . . . . 10-69 Handling . . . . . . . . . . . . . . . . . . . . . . 11-1
PCKMO-Encrypt-AES-256-Key (Function Machine-Check Detection . . . . . . . . . . . . . . . . . .11-2
Code 20) . . . . . . . . . . . . . . . . . . . . . . . . 10-69 Correction of Machine Malfunctions . . . . . . . . . .11-2
PERFORM FRAME MANAGEMENT Error Checking and Correction . . . . . . . . . . . .11-2
FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . 10-70 CPU Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
PERFORM TIMING FACILITY FUNCTION . 10-73 Effects of CPU Retry . . . . . . . . . . . . . . . . . .11-3
PERFORM TOPOLOGY FUNCTION . . . . . 10-80 Checkpoint Synchronization . . . . . . . . . . . .11-3
Operation of Function Codes 0 and 1 . . . 10-81 Handling of Machine Checks during
Operation of Function Code 2: . . . . . . . . . 10-81 Checkpoint Synchronization . . . . . . . . . . .11-3
PROGRAM CALL. . . . . . . . . . . . . . . . . . . . . 10-81 Checkpoint-Synchronization Operations . . .11-3
PROGRAM RETURN. . . . . . . . . . . . . . . . . . 10-94 Checkpoint-Synchronization Action. . . . . . .11-4
PROGRAM TRANSFER . . . . . . . . . . . . . . . 10-98 Channel-Subsystem Recovery . . . . . . . . . . . .11-4
PROGRAM TRANSFER WITH INSTANCE. 10-98 Unit Deletion . . . . . . . . . . . . . . . . . . . . . . . . . .11-4
PURGE ALB. . . . . . . . . . . . . . . . . . . . . . . . 10-107 Handling of Machine Checks. . . . . . . . . . . . . . . .11-4
PURGE TLB. . . . . . . . . . . . . . . . . . . . . . . . 10-107 Validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-5
RESET REFERENCE BIT EXTENDED. . . 10-107 Invalid CBC in Storage . . . . . . . . . . . . . . . . . .11-6
RESET REFERENCE BITS MULTIPLE . . 10-108 Programmed Validation of Storage . . . . . . .11-7
RESUME PROGRAM . . . . . . . . . . . . . . . . 10-108 Invalid CBC in Storage Keys . . . . . . . . . . . . . .11-7
SET ADDRESS SPACE CONTROL . . . . . 10-110 Invalid CBC in Registers . . . . . . . . . . . . . . . . .11-8
SET ADDRESS SPACE CONTROL FAST 10-111 Check-Stop State . . . . . . . . . . . . . . . . . . . . . . . .11-9
SET CLOCK. . . . . . . . . . . . . . . . . . . . . . . . 10-112 System Check Stop . . . . . . . . . . . . . . . . . .11-10
SET CLOCK COMPARATOR . . . . . . . . . . 10-113 Machine-Check Interruption . . . . . . . . . . . . . . .11-10
SET CLOCK PROGRAMMABLE FIELD . . 10-113 Exigent Conditions . . . . . . . . . . . . . . . . . . . .11-10
SET CPU TIMER . . . . . . . . . . . . . . . . . . . . 10-114 Repressible Conditions . . . . . . . . . . . . . . . . .11-10
SET PREFIX . . . . . . . . . . . . . . . . . . . . . . . 10-114 Interruption Action . . . . . . . . . . . . . . . . . . . . .11-11
SET PSW KEY FROM ADDRESS. . . . . . . 10-115 Point of Interruption . . . . . . . . . . . . . . . . . . . .11-13
SET SECONDARY ASN . . . . . . . . . . . . . . 10-115 Machine-Check-Interruption Code . . . . . . . . . .11-13
SET SECONDARY ASN WITH INSTANCE 10-115 Subclass . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14
SET STORAGE KEY EXTENDED. . . . . . . 10-121 System Damage . . . . . . . . . . . . . . . . . . . .11-14
Setting Storage Keys in Multiple 4K-Byte Instruction-Processing Damage . . . . . . . .11-14
Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . 10-123 System Recovery . . . . . . . . . . . . . . . . . . .11-14
SET SYSTEM MASK . . . . . . . . . . . . . . . . . 10-124 Timing-Facility Damage. . . . . . . . . . . . . . .11-15
SIGNAL PROCESSOR . . . . . . . . . . . . . . . 10-124 External Damage. . . . . . . . . . . . . . . . . . . .11-15
STORE CLOCK COMPARATOR. . . . . . . . 10-126 Degradation . . . . . . . . . . . . . . . . . . . . . . . .11-15
STORE CONTROL . . . . . . . . . . . . . . . . . . 10-126 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16
STORE CPU ADDRESS . . . . . . . . . . . . . . 10-126 Channel Report Pending . . . . . . . . . . . . . .11-16
STORE CPU ID . . . . . . . . . . . . . . . . . . . . . 10-127 Service-Processor Damage. . . . . . . . . . . .11-16
STORE CPU TIMER . . . . . . . . . . . . . . . . . 10-128 Channel-Subsystem Damage . . . . . . . . . .11-16
STORE FACILITY LIST . . . . . . . . . . . . . . . 10-128 Subclass Modifiers . . . . . . . . . . . . . . . . . . . .11-16
STORE PREFIX. . . . . . . . . . . . . . . . . . . . . 10-128 Backed Up . . . . . . . . . . . . . . . . . . . . . . . . .11-16
STORE REAL ADDRESS . . . . . . . . . . . . . 10-129 Delayed Access Exception . . . . . . . . . . . .11-16
STORE SYSTEM INFORMATION. . . . . . . 10-130 Ancillary Report . . . . . . . . . . . . . . . . . . . . .11-17
CPU Topology Overview . . . . . . . . . . . . 10-145 Synchronous Machine-Check-Interruption
CPU Slack . . . . . . . . . . . . . . . . . . . . . . . 10-147 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .11-17
STORE THEN AND SYSTEM MASK . . . . 10-149 Processing Backup . . . . . . . . . . . . . . . . . .11-17
STORE THEN OR SYSTEM MASK. . . . . . 10-149 Processing Damage . . . . . . . . . . . . . . . . .11-17
STORE USING REAL ADDRESS . . . . . . . 10-150 Storage Errors . . . . . . . . . . . . . . . . . . . . . . . .11-18
TEST ACCESS . . . . . . . . . . . . . . . . . . . . . 10-150 Storage Error Uncorrected . . . . . . . . . . . .11-18
TEST BLOCK. . . . . . . . . . . . . . . . . . . . . . . 10-152 Storage Error Corrected . . . . . . . . . . . . . .11-18
TEST PROTECTION . . . . . . . . . . . . . . . . . 10-155 Storage-Key Error Uncorrected . . . . . . . . .11-18
TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-157 Storage Degradation . . . . . . . . . . . . . . . . .11-18
TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-159 Indirect Storage Error . . . . . . . . . . . . . . . .11-19
xv
Condition Code . . . . . . . . . . . . . . . . . . . . . . . 14-2 Command-Mode ORB . . . . . . . . . . . . . . . .15-25
Program Exceptions. . . . . . . . . . . . . . . . . . . . 14-2 Transport-Mode ORB . . . . . . . . . . . . . . . .15-30
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 Channel-Command Word . . . . . . . . . . . . . . .15-31
CANCEL SUBCHANNEL . . . . . . . . . . . . . . . . 14-4 Transport Control Word . . . . . . . . . . . . . . . . .15-33
CLEAR SUBCHANNEL . . . . . . . . . . . . . . . . . 14-5 Transport-Command-Control Block. . . . . . . .15-36
HALT SUBCHANNEL . . . . . . . . . . . . . . . . . . 14-6 Transport-Command-Area Header . . . . . .15-36
MODIFY SUBCHANNEL . . . . . . . . . . . . . . . . 14-8 Transport-Command Area. . . . . . . . . . . . .15-37
RESET CHANNEL PATH . . . . . . . . . . . . . . . 14-9 Device-Command Word . . . . . . . . . . . . . .15-37
RESUME SUBCHANNEL . . . . . . . . . . . . . . 14-10 Transport-Command-Area Trailer . . . . . . .15-38
SET ADDRESS LIMIT . . . . . . . . . . . . . . . . . 14-12 Transfer-CBC-Offset Block DCW . . . . . . .15-40
SET CHANNEL MONITOR . . . . . . . . . . . . . 14-13 CBC-Offset Block . . . . . . . . . . . . . . . . . . .15-40
START SUBCHANNEL . . . . . . . . . . . . . . . . 14-15 Interrogate TCCB . . . . . . . . . . . . . . . . . . .15-41
STORE CHANNEL PATH STATUS. . . . . . . 14-17 Interrogate DCW . . . . . . . . . . . . . . . . . . . .15-41
STORE CHANNEL REPORT WORD . . . . . 14-17 Interrogate Data. . . . . . . . . . . . . . . . . . . . .15-41
STORE SUBCHANNEL . . . . . . . . . . . . . . . . 14-18 Transport Status Block . . . . . . . . . . . . . . . . .15-43
TEST PENDING INTERRUPTION. . . . . . . . 14-19 Transport-Status Header (TSH) . . . . . . . .15-43
TEST SUBCHANNEL . . . . . . . . . . . . . . . . . 14-20 I/O-Status TSA . . . . . . . . . . . . . . . . . . . . .15-44
Device-Detected-Program-Check TSA . . .15-45
Chapter 15, Basic I/O Functions . . . .15-1 Interrogate TSA . . . . . . . . . . . . . . . . . . . . .15-50
Control of Basic I/O Functions . . . . . . . . . . . . . . 15-1 Command Code . . . . . . . . . . . . . . . . . . . . . .15-52
Subchannel-Information Block . . . . . . . . . . . . 15-2 Designation of Storage Area . . . . . . . . . . . . .15-52
Path-Management-Control Word . . . . . . . . 15-2 CCW Channel Program Chaining . . . . . . . . .15-55
Subchannel-Status Word . . . . . . . . . . . . . . 15-9 Data Chaining . . . . . . . . . . . . . . . . . . . . . .15-56
Model-Dependent Area/Measurement Command Chaining. . . . . . . . . . . . . . . . . .15-58
Block Address . . . . . . . . . . . . . . . . . . . . . 15-9 TCW Channel Program Chaining . . . . . . . . .15-58
Summary of Modifiable Fields . . . . . . . . . 15-10 Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-59
Channel-Path Allegiance . . . . . . . . . . . . . . . . . 15-12 Program-Controlled Interruption . . . . . . . . . .15-59
Working Allegiance . . . . . . . . . . . . . . . . . . . 15-12 Indirect-Storage Designator (ISD) . . . . . . .15-61
Working Allegiance for Subchannels CCW Indirect Data Addressing . . . . . . . . . . .15-61
Operating in Command Mode . . . . . . . . 15-12 Modified CCW Indirect Data Addressing . . .15-63
Working Allegiance for Subchannels Transport Indirect Data Addressing. . . . . . . .15-65
Operating in Transport Mode . . . . . . . . . 15-12 Suspension of CCW Channel-Program
Active Allegiance . . . . . . . . . . . . . . . . . . . . . 15-13 Execution. . . . . . . . . . . . . . . . . . . . . . . . . . .15-68
Dedicated Allegiance . . . . . . . . . . . . . . . . . . 15-13 Commands and Flags for CCWs. . . . . . . . . .15-70
Channel-Path Availability . . . . . . . . . . . . . . . 15-13 Branching in CCW Channel Programs . . . . .15-71
Control-Unit Type . . . . . . . . . . . . . . . . . . . . . 15-14 Transfer in Channel . . . . . . . . . . . . . . . . .15-72
Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 Command Retry . . . . . . . . . . . . . . . . . . . . . .15-72
Clear-Function Path Management . . . . . . . . 15-14 Concluding I/O Operations before Initiation . . .15-72
Clear-Function Subchannel Modification . . . 15-15 Concluding I/O Operations during Initiation. . . .15-73
Clear-Function Signaling and Completion . . 15-15 Immediate Conclusion of Command-Mode I/O
Halt Function . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . .15-73
Halt-Function Path Management . . . . . . . . . 15-16 Concluding I/O Operations During Data
Halt-Function Signaling and Completion . . . 15-17 Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-74
Start Function and Resume Function . . . . . . . 15-20 Channel-Path-Reset Function . . . . . . . . . . . . . .15-75
Start-Function and Resume-Function Path Channel-Path-Reset-Function Signaling . . . .15-76
Management . . . . . . . . . . . . . . . . . . . . . . . 15-20 Channel-Path-Reset-Function-Completion
Interrogate Function . . . . . . . . . . . . . . . . . . . . . 15-22 Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . .15-76
Interrogate-Function Path Management . . . 15-22
Interrogate TCCB Transportation and Chapter 16, I/O Interruptions . . . . . . 16-1
Completion . . . . . . . . . . . . . . . . . . . . . . . 15-22 Interruption Conditions . . . . . . . . . . . . . . . . . . . .16-2
Execution of I/O Operations . . . . . . . . . . . . . . . 15-23 Intermediate Interruption Condition . . . . . . . . .16-4
Blocking of Data . . . . . . . . . . . . . . . . . . . . . . 15-24 Primary Interruption Condition. . . . . . . . . . . . .16-4
Operation-Request Block . . . . . . . . . . . . . . . 15-24 Secondary Interruption Condition . . . . . . . . . .16-5
xvii
Channel-Path Reset . . . . . . . . . . . . . . . . . 17-12 SUBTRACT NORMALIZED. . . . . . . . . . . . . .18-24
I/O-System Reset . . . . . . . . . . . . . . . . . . . 17-13 SUBTRACT UNNORMALIZED . . . . . . . . . . .18-24
Externally Initiated Functions . . . . . . . . . . . . . . 17-16
Initial Program Loading . . . . . . . . . . . . . . . . 17-16 Chapter 19, Binary-Floating-Point
CCW-type IPL . . . . . . . . . . . . . . . . . . . . . 17-17
Instructions . . . . . . . . . . . . . . . . . . . 19-1
List-Directed IPL. . . . . . . . . . . . . . . . . . . . 17-19
Binary-Floating-Point Facility. . . . . . . . . . . . . . . .19-1
Reconfiguration of the I/O System . . . . . . . . 17-22
Floating-Point-Control (FPC) Register . . . . . .19-2
Status Verification . . . . . . . . . . . . . . . . . . . . . . 17-22
BFP Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . .19-2
Address-Limit Checking . . . . . . . . . . . . . . . . . . 17-22
BFP Data Formats. . . . . . . . . . . . . . . . . . . . . .19-2
Configuration Alert . . . . . . . . . . . . . . . . . . . . . . 17-23
BFP Short Format . . . . . . . . . . . . . . . . . . . .19-2
Incorrect-Length-Indication Suppression . . . . . 17-23
BFP Long Format . . . . . . . . . . . . . . . . . . . .19-2
Concurrent Sense . . . . . . . . . . . . . . . . . . . . . . 17-24
BFP Extended Format . . . . . . . . . . . . . . . .19-2
Channel-Subsystem Recovery . . . . . . . . . . . . 17-24
Biased Exponent . . . . . . . . . . . . . . . . . . . . .19-2
Channel Report . . . . . . . . . . . . . . . . . . . . . . 17-25
Significand . . . . . . . . . . . . . . . . . . . . . . . . . .19-3
Channel-Report Word . . . . . . . . . . . . . . . . . 17-26
Values of Nonzero Numbers . . . . . . . . . . . .19-3
Restore-Subchannel Facility . . . . . . . . . . . . 17-28
Classes of BFP Data . . . . . . . . . . . . . . . . . . . .19-4
Extended-Subchannel-Logout Facility . . . . . 17-28
Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-4
Channel-Subsystem-I/O-Priority Facility . . . . . 17-29
Subnormal Numbers . . . . . . . . . . . . . . . . . .19-4
Number of Channel-Subsystem-Priority
Normal Numbers . . . . . . . . . . . . . . . . . . . . .19-4
Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29
Infinities . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-4
Multiple-Subchannel-Set Facility . . . . . . . . . . . 17-29
Signaling and Quiet NaNs . . . . . . . . . . . . .19-4
BFP-Format Conversion . . . . . . . . . . . . . . . . .19-5
Chapter 18, Hexadecimal-Floating- BFP Rounding . . . . . . . . . . . . . . . . . . . . . . . . .19-5
Point Instructions . . . . . . . . . . . . . . .18-1 BFP Comparison . . . . . . . . . . . . . . . . . . . . . . .19-5
HFP Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-5
HFP Number Representation. . . . . . . . . . . . . 18-1 IEEE Exceptions . . . . . . . . . . . . . . . . . . . . . . .19-7
Normalization . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Result Figures . . . . . . . . . . . . . . . . . . . . . . . . . . .19-7
HFP Data Formats . . . . . . . . . . . . . . . . . . . . . 18-2 Data-Exception Codes (DXC) and
HFP Short Format . . . . . . . . . . . . . . . . . . . 18-4 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . .19-7
HFP Long Format . . . . . . . . . . . . . . . . . . . 18-4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-8
HFP Extended Format . . . . . . . . . . . . . . . . 18-4 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-11
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . .19-16
ADD NORMALIZED . . . . . . . . . . . . . . . . . . . . 18-8 COMPARE AND SIGNAL . . . . . . . . . . . . . . .19-17
ADD UNNORMALIZED . . . . . . . . . . . . . . . . . 18-9 CONVERT FROM FIXED . . . . . . . . . . . . . . .19-18
COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 CONVERT FROM LOGICAL. . . . . . . . . . . . .19-20
CONVERT FROM FIXED . . . . . . . . . . . . . . 18-10 CONVERT TO FIXED . . . . . . . . . . . . . . . . . .19-21
CONVERT TO FIXED . . . . . . . . . . . . . . . . . 18-11 CONVERT TO LOGICAL . . . . . . . . . . . . . . .19-23
DIVIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 DIVIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-25
HALVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 DIVIDE TO INTEGER . . . . . . . . . . . . . . . . . .19-27
LOAD AND TEST. . . . . . . . . . . . . . . . . . . . . 18-13 LOAD AND TEST . . . . . . . . . . . . . . . . . . . . .19-30
LOAD COMPLEMENT . . . . . . . . . . . . . . . . . 18-14 LOAD COMPLEMENT . . . . . . . . . . . . . . . . .19-30
LOAD FP INTEGER. . . . . . . . . . . . . . . . . . . 18-14 LOAD FP INTEGER . . . . . . . . . . . . . . . . . . .19-31
LOAD LENGTHENED . . . . . . . . . . . . . . . . . 18-15 LOAD LENGTHENED . . . . . . . . . . . . . . . . . .19-32
LOAD NEGATIVE . . . . . . . . . . . . . . . . . . . . 18-15 LOAD NEGATIVE . . . . . . . . . . . . . . . . . . . . .19-33
LOAD POSITIVE . . . . . . . . . . . . . . . . . . . . . 18-16 LOAD POSITIVE . . . . . . . . . . . . . . . . . . . . . .19-33
LOAD ROUNDED . . . . . . . . . . . . . . . . . . . . 18-16 LOAD ROUNDED . . . . . . . . . . . . . . . . . . . . .19-34
MULTIPLY . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 MULTIPLY . . . . . . . . . . . . . . . . . . . . . . . . . . .19-35
MULTIPLY AND ADD . . . . . . . . . . . . . . . . . 18-18 MULTIPLY AND ADD . . . . . . . . . . . . . . . . . .19-37
MULTIPLY AND SUBTRACT. . . . . . . . . . . . 18-19 MULTIPLY AND SUBTRACT . . . . . . . . . . . .19-37
MULTIPLY AND ADD UNNORMALIZED. . . 18-20 SQUARE ROOT . . . . . . . . . . . . . . . . . . . . . .19-38
MULTIPLY UNNORMALIZED . . . . . . . . . . . 18-21 SUBTRACT . . . . . . . . . . . . . . . . . . . . . . . . . .19-39
SQUARE ROOT. . . . . . . . . . . . . . . . . . . . . . 18-23 TEST DATA CLASS . . . . . . . . . . . . . . . . . . .19-39
xix
BXLE Example 1 . . . . . . . . . . . . . . . . . . . . A-14 UNPACK (UNPK) . . . . . . . . . . . . . . . . . . . . . A-35
BXLE Example 2 . . . . . . . . . . . . . . . . . . . . A-14 UPDATE TREE (UPT). . . . . . . . . . . . . . . . . . A-36
COMPARE AND FORM CODEWORD (CFC) A-14 Decimal Instructions . . . . . . . . . . . . . . . . . . . . . A-36
COMPARE HALFWORD (CH). . . . . . . . . . . . A-14 ADD DECIMAL (AP) . . . . . . . . . . . . . . . . . . . A-36
COMPARE LOGICAL (CL, CLC, CLI, CLR) . A-15 COMPARE DECIMAL (CP) . . . . . . . . . . . . . . A-36
CLC Example . . . . . . . . . . . . . . . . . . . . . . . A-15 DIVIDE DECIMAL (DP) . . . . . . . . . . . . . . . . . A-37
CLI Example. . . . . . . . . . . . . . . . . . . . . . . . A-15 EDIT (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . A-37
CLR Example . . . . . . . . . . . . . . . . . . . . . . . A-15 EDIT AND MARK (EDMK). . . . . . . . . . . . . . . A-38
COMPARE LOGICAL CHARACTERS UNDER MULTIPLY DECIMAL (MP) . . . . . . . . . . . . . . A-39
MASK (CLM) . . . . . . . . . . . . . . . . . . . . . . . . A-16 SHIFT AND ROUND DECIMAL (SRP) . . . . . A-39
COMPARE LOGICAL LONG (CLCL). . . . . . . A-16 Decimal Left Shift . . . . . . . . . . . . . . . . . . . A-39
COMPARE LOGICAL STRING (CLST) . . . . . A-18 Decimal Right Shift . . . . . . . . . . . . . . . . . . A-39
CONVERT TO BINARY (CVB) . . . . . . . . . . . A-18 Decimal Right Shift and Round . . . . . . . . . A-40
CONVERT TO DECIMAL (CVD) . . . . . . . . . . A-19 Multiplying by a Variable Power of 10 . . . . A-40
DIVIDE (D, DR) . . . . . . . . . . . . . . . . . . . . . . . A-19 ZERO AND ADD (ZAP) . . . . . . . . . . . . . . . . . A-41
EXCLUSIVE OR (X, XC, XI, XR) . . . . . . . . . . A-20 Hexadecimal-Floating-Point Instructions. . . . . . A-41
XC Example . . . . . . . . . . . . . . . . . . . . . . . . A-20 ADD NORMALIZED (AD, ADR, AE, AER,
XI Example . . . . . . . . . . . . . . . . . . . . . . . . . A-21 AXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-41
EXECUTE (EX) . . . . . . . . . . . . . . . . . . . . . . . A-21 ADD UNNORMALIZED (AU, AUR, AW,
FIND LEFTMOST ONE (FLOGR) . . . . . . . . . A-22 AWR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-42
INSERT CHARACTERS UNDER MASK COMPARE (CD, CDR, CE, CER) . . . . . . . . . A-42
(ICM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23 DIVIDE (DD, DDR, DE, DER) . . . . . . . . . . . . A-42
LOAD (L, LR) . . . . . . . . . . . . . . . . . . . . . . . . . A-23 HALVE (HDR, HER) . . . . . . . . . . . . . . . . . . . A-43
LOAD ADDRESS (LA) . . . . . . . . . . . . . . . . . . A-23 MULTIPLY (MD, MDR, MDE, MDER, MXD,
LOAD HALFWORD (LH) . . . . . . . . . . . . . . . . A-24 MXDR, MXR). . . . . . . . . . . . . . . . . . . . . . . . A-43
MOVE (MVC, MVI). . . . . . . . . . . . . . . . . . . . . A-24 Hexadecimal-Floating-Point-Number
MVC Example . . . . . . . . . . . . . . . . . . . . . . A-24 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . A-44
MVI Example . . . . . . . . . . . . . . . . . . . . . . . A-25 Fixed Point to Hexadecimal Floating Point A-44
MOVE INVERSE (MVCIN). . . . . . . . . . . . . . . A-25 Hexadecimal Floating Point to Fixed Point A-44
MOVE LONG (MVCL) . . . . . . . . . . . . . . . . . . A-26 Multiprogramming and Multiprocessing
MOVE NUMERICS (MVN) . . . . . . . . . . . . . . . A-26 Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-45
MOVE STRING (MVST). . . . . . . . . . . . . . . . . A-27 Example of a Program Failure Using OR
MOVE WITH OFFSET (MVO) . . . . . . . . . . . . A-27 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . A-45
MOVE ZONES (MVZ) . . . . . . . . . . . . . . . . . . A-28 Conditional Swapping Instructions (CS, CDS) A-46
MULTIPLY (M, MR) . . . . . . . . . . . . . . . . . . . . A-28 Setting a Single Bit . . . . . . . . . . . . . . . . . . A-46
MULTIPLY HALFWORD (MH) . . . . . . . . . . . . A-29 Updating Counters. . . . . . . . . . . . . . . . . . . A-47
OR (O, OC, OI, OR) . . . . . . . . . . . . . . . . . . . . A-29 Bypassing Post and Wait . . . . . . . . . . . . . . . A-47
OI Example . . . . . . . . . . . . . . . . . . . . . . . . A-29 Lock/Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . A-47
PACK (PACK) . . . . . . . . . . . . . . . . . . . . . . . . A-29 Lock/Unlock with LIFO Queuing for
ROTATE THEN EXCLUSIVE OR SELECTED Contentions . . . . . . . . . . . . . . . . . . . . . . . A-48
BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30 Lock/Unlock with FIFO Queuing for
ROTATE THEN INSERT SELECTED BITS. . A-30 Contentions . . . . . . . . . . . . . . . . . . . . . . . A-49
ROTATE THEN OR SELECTED BITS . . . . . A-30 Free-Pool Manipulation . . . . . . . . . . . . . . . . . A-50
SEARCH STRING (SRST). . . . . . . . . . . . . . . A-31 PERFORM LOCKED OPERATION (PLO) . . A-51
SRST Example 1 . . . . . . . . . . . . . . . . . . . . A-31 Sorting Instructions . . . . . . . . . . . . . . . . . . . . . . A-53
SRST Example 2 . . . . . . . . . . . . . . . . . . . . A-31 Tree Format. . . . . . . . . . . . . . . . . . . . . . . . . . A-53
SHIFT LEFT DOUBLE (SLDA) . . . . . . . . . . . A-31 Example of Use of Sort Instructions . . . . . . . A-54
SHIFT LEFT SINGLE (SLA). . . . . . . . . . . . . . A-32
STORE CHARACTERS UNDER MASK Appendix B, Lists of Instructions . . . B-1
(STCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-32 Instructions Arranged by Name . . . . . . . . . . . . . B-4
STORE MULTIPLE (STM) . . . . . . . . . . . . . . . A-32 Instructions Arranged by Mnemonic . . . . . . . . . B-23
TEST UNDER MASK (TM) . . . . . . . . . . . . . . A-33 Instructions Arranged by Operation Code . . . . B-41
TRANSLATE (TR) . . . . . . . . . . . . . . . . . . . . . A-33
TRANSLATE AND TEST (TRT). . . . . . . . . . . A-34
xxi
xxii z/Architecture Principles of Operation
Notices
®
References in this publication to IBM products, pro-
grams or services do not imply that IBM intends to Trademarks
make these available in all countries in which IBM
operates. Any reference to an IBM product, program,
or service is not intended to state or imply that only The following terms are trademarks of the Interna-
IBM's product, program, or service may be used. Any tional Business Machines Corporation in the United
functionally equivalent product, program, or service States, other countries, or both:
that does not infringe any of IBM's intellectual prop-
erty rights may be used instead of the IBM product, AIX/ESA
program, or service. Evaluation and verification of BookMaster
operation in conjunction with other products, except CICS
those expressly designated by IBM, is the user's DB2
responsibility. Enterprise Systems Architecture/370
Enterprise Systems Architecture/390
IBM may have patents or pending patent applications Enterprise Systems Connection Architecture
covering subject matter in this document. The fur- ESA/370
nishing of this document does not give you any ESA/390
license to these patents. You can send license inquir- ESCON
ies, in writing, to the IBM Director of Licensing, IBM FICON
Corporation, North Castle Drive, Armonk, NY, IBM
10504-1785 USA. IBMLink
MVS/ESA
OS/390
Processor Resource/Systems Manager
PR/SM
Sysplex Timer
System/370
VM/ESA
z/Architecture
z/OS
This publication provides, for reference purposes, a should refer to the index, which indicates the location
detailed z/Architecture™ description. of the key description.
The publication applies only to systems operating as The information presented in this publication is
defined by z/Architecture. For systems operating in grouped in 20 chapters and several appendixes:
accordance with the Enterprise Systems Architec-
ture/390® (ESA/390™) definition, the IBM ESA/390 Chapter 1, Introduction, highlights the major facilities
Principles of Operation, SA22-7201, should be con- of z/Architecture.
sulted.
Chapter 2, Organization, describes the major group-
The publication describes each function at the level ings within the system — main storage, expanded
of detail needed to prepare an assembler-language storage, the central processing unit (CPU), the exter-
program that relies on that function. It does not, how- nal time reference (ETR), and input/output — with
ever, describe the notation and conventions that must some attention given to the composition and charac-
be employed in preparing such a program, for which teristics of those groupings.
the user must instead refer to the appropriate assem-
bler-language publication. Chapter 3, Storage, explains the information formats,
the addressing of storage, and the facilities for stor-
The information in this publication is provided princi- age protection. It also deals with dynamic address
pally for use by assembler-language programmers, translation (DAT), which, coupled with special pro-
although anyone concerned with the functional gramming support, makes the use of a virtual stor-
details of z/Architecture will find it useful. age possible.
This publication is written as a reference and should Chapter 4, Control, describes the facilities for the
not be considered an introduction or a textbook. It switching of system status, for special externally initi-
assumes the user has a basic knowledge of data- ated operations, for debugging, and for timing. It
processing systems. deals specifically with CPU states, control modes,
the program-status word (PSW), control registers,
All facilities discussed in this publication are not nec- tracing, program-event recording, timing facilities,
essarily available on every model. Furthermore, in resets, store status, and initial program loading.
some instances the definitions have been structured
to allow for some degree of extendibility, and there- Chapter 5, Program Execution, explains the role of
fore certain capabilities may be described or implied instructions in program execution, looks in detail at
that are not offered on any model. Examples of such instruction formats, and describes briefly the use of
capabilities are the use of a 16-bit field in the sub- the program-status word (PSW), of branching, and of
system-identification word to identify the subchannel interruptions. It contains the principal description of
number, the size of the CPU address, and the num- the advanced address-space facilities that were intro-
ber of CPUs sharing main storage. The allowance for duced in ESA/370™. It also details the aspects of
this type of extendibility should not be construed as program execution on one CPU as observed by other
implying any intention by IBM to provide such capa- CPUs and by channel programs.
bilities. For information about the characteristics and
availability of facilities on a specific model, see the Chapter 6, Interruptions, details the mechanism that
functional characteristics publication for that model. permits the CPU to change its state as a result of
conditions external to the system, within the system,
Largely because this publication is arranged for refer- or within the CPU itself. Six classes of interruptions
ence, certain words and phrases appear, of neces- are identified and described: machine-check inter-
sity, earlier in the publication than the principal ruptions, program interruptions, supervisor-call inter-
discussions explaining them. The reader who ruptions, external interruptions, input/output
encounters a problem because of this arrangement interruptions, and restart interruptions.
Chapter 9, Floating-Point Overview and Support Chapter 20, Decimal-Floating-Point Instructions, con-
Instructions, includes an introduction to the floating- tains detailed descriptions of the decimal-floating-
point operations, detailed descriptions of those point (DFP) data formats and the DFP instructions.
instructions common to binary-floating-point, deci-
mal-floating-point, and hexadecimal-floating-point The Appendixes include:
operations, and summaries of all floating-point
instructions. • Information about number representation
• Instruction-use examples
Chapter 10, Control Instructions, contains detailed • Lists of the instructions arranged in several
descriptions of all of the semiprivileged and privi- sequences
leged instructions except for the I/O instructions. • A summary of the condition-code settings
• A table of the powers of 2
Chapter 11, Machine-Check Handling, describes the • Tabular information helpful in dealing with hexa-
mechanisms for detecting, correcting, and reporting decimal numbers
machine malfunctions. • A table of EBCDIC and other codes.
Chapter 16, I/O Interruptions, covers I/O interruptions P (peta) 1,125,899,906,842,624 = 250
and interruption conditions.
E (exa) 1,152,921,504,606,846,976 = 260
Chapter 17, I/O Support Functions, describes such
functions as channel-subsystem usage monitoring, The following are some examples of the use of K, M,
resets, initial-program loading, reconfiguration, and G, T, and E:
channel-subsystem recovery.
2,048 is expressed as 2K.
All numbers in this publication are in decimal unless The FICON I/O interface is described in the ANSI®
they are explicitly noted as being in binary or hexa- standards document Fibre Channel - Single-Byte
decimal (hex). Command Code Sets-2 (FC-SB-2).
In this publication, unless otherwise specified, the The set-program-parameter and CPU-measurement
value given for a byte is the value obtained by consid- facilities are described in the publication The Set-
ering the bits of the byte to represent a binary code. Program-Parameter and CPU-Measurement Facili-
Thus, when a byte is said to contain a zero, the value ties, SA23-2260.
00000000 binary, or 00 hex, is meant, and not the
value for an EBCDIC character “0,” which would be
F0 hex.
Summary of Changes in Ninth
Edition
Other Publications
The parallel-I/O interface is described in the publica- The ninth edition of this publication differs from the
tion IBM System/360 and System/370 I/O Interface previous edition principally by containing the defini-
Channel to Control Unit Original Equipment Manu- tions of the following facilities:
facturers’ Information, GA22-6974.
• CMPSC-enhancement facility
The parallel-I/O channel-to-channel adapter is • Distinct-operands facility
described in the publication IBM Enterprise Systems • Enhanced-monitor facility
Architecture/390 Channel-to-Channel Adapter for the • Fast-BCR-serialization facility
xxvii
• Floating-point extension facility – Changes introduced by the message-secu-
• High-word facility rity assist extensions 3 and 4 are added.
• Interlocked-access facility
• IPTE-range facility – Changes introduced by the nonquiescing-
• Load/store-on-condition facility key-setting facility are added, including the
• Message-security-assist extension 3 description of quiescing.
• Message-security-assist extension 4 – Changes introduced by the interlocked-
• Nonquiescing key-setting facility access facility are added, including the
• Population-count facility description of an interlocked-fetch reference
• The Reset-reference-bits-multiple facility and specific-operand serialization.
– Clarification is added to the description of the – Clarification is made as to the content of the
translation-exception identification. chapter.
– A significant editorial change has been made – Changes introduced by the message-secu-
to the description of the instruction formats. rity-assist extension 4 are added.
Instruction formats having variations in
assembler syntax or field content are desig- – Changes introduced by the population-count
nated by an alphabetic suffix which is also facility are added.
reflected in the instruction descriptions in – Changes introduced by the instruction-for-
chapters 7-10, 14, and 18-20. mat clarifications are added.
– Changes introduced by the enhanced-moni- – Clarifications are made to the description of
tor facility are added. COMPARE AND SWAP AND STORE.
– Clarification is made to the description of – Changes introduced by the CMPSC-
suppression. enhancement facility are added.
– Changes are made to the STORE SYSTEM • In Chapter 7, “General Instructions,” the clock
INFORMATION instruction with regards to setting for the leap second on January 1, 2009 is
topology information returned. added to the description of STORE CLOCK
EXTENDED.
• In Chapter 14, “Basic I/O Functions,” the CBC-
offset block is added for the fibre-channel-exten- • In Chapter 13, “I/O Overview,” changes intro-
sions facility. duced by the fibre-channel-extensions facility are
added to various sections.
xxix
• In Chapter 14, “I/O Instructions,” changes intro- – Changes introduced by the move-with-
duced by the fibre-channel-extensions facility are optional-specifications facility are added to
added to various sections. the section “Protection.”
• In Chapter 17, “I/O Support Functions,” changes – Changes introduced by the general-instruc-
introduced by the fibre-channel-extensions facil- tions-extension facility are added to various
ity are added to various sections. sections.
– Programming notes are added to the • The definition of SYSIB 15.1.2 in support
description of the UTF conversion instruc- of the configuration-topology facility.
tions (CU12, CU14, CU21, CU24, CU41, and
CU42) indicating that the instructions sup- • In Chapter 11, “Machine-Check Handling:”
port big-endian encoding only. – Changes introduced by the enhanced-DAT
– Changes introduced by the execute-exten- facility are added to various sections.
sions facility are added to various sections, – Changes introduced by the execute-exten-
including the description of the EXECUTE sions facility are added to various sections.
RELATIVE LONG instruction.
• In Chapter 13, “I/O Overview,” changes intro-
– Changes introduced by the general-instruc- duces by the multiple-subchannel set facility are
tions-extension facility are added to various described.
sections, including the descriptions of the
facility’s 72 new instructions. • In Chapter 14, “I/O Instructions,” changes intro-
duces by the multiple-subchannel set facility are
– The description of the MOVE LONG UNI- described.
CODE instruction is amended such that an
odd length specification is permitted. • In Chapter 17, “I/O Support Functions,” changes
introduces by the multiple-subchannel set facility
– Changes introduced by the parsing- are described.
enhancement facility are added to various
xxxi
The seventh edition also contains numerous minor – In the section “Instruction Formats”, the RRR
corrections and clarifications. and SSF formats are added.
xxxiii
• In Chapter 3, “Storage”: – Changes introduced by the DAT-enhance-
ment facility 2 are added to various sections.
– In the “Information Formats” section, the
length of a storage-operand field that is – Changes introduced by the store-clock-fast
implied by the instruction now includes a facility are added to various sections.
16-byte operand.
– Changes introduced by the modified-CCW-
– Changes introduced by the modified-CCW- indirect-data-addressing facility are added to
indirect-data-addressing facility are added to the section “Channel-Program Serialization.”
various sections.
• In Chapter 6, “Interruptions”:
– Changes introduced by the DAT-enhance-
ment facility 2 are added to various sections. – Changes introduced by the PER-3 facility are
added to the various sections.
– Changes introduced by the PER-3 facility are
added to the section “Assigned Storage – Changes introduced by the server-time pro-
Locations.” tocol (STP) facility are added to various sec-
tions.
– Changes introduced by the store-facility-list-
extended facility are added to section – Changes introduced by the TOD-clock-steer-
“Assigned Storage Locations.” ing facility are added to various sections.
– Changes introduced by the server-time pro- – A note is added to the “Instructions” section
tocol (STP) facility are added to various sec- indicating that, for certain new or modified
tions. instructions, an operand may be optional.
– The location in which the PSW that is pre- – A description of the STORE FACILITY LIST
served as a result of switching from the EXTENDED instruction is added.
z/Architecture to the ESA/390 architectural – Changes introduced by the TOD-clock-steer-
mode is formally named the Captured ing facility are added to the STORE CLOCK,
z/Architecture PSW register. STORE CLOCK FAST, and STORE CLOCK
– The description of all facility-indication bits EXTENDED instructions.
has been moved to a new section at the end – Descriptions of new functions introduced by
of the chapter. the message-security-assist extension 1 are
• In Chapter 5, “Program Execution”: added to the CIPHER MESSAGE, CIPHER
MESSAGE WITH CHAINING, COMPUTE
– The instructions of the message-security INTERMEDIATE MESSAGE DIGEST, and
assist are added to the section “Condition COMPUTE LAST MESSAGE DIGEST
Code Alternative to Interruptibility.” instructions.
• In Chapter 11, “Machine-Check Handling”: • Changes are introduced to the section “List-
Directed IPL” to support storing of the sub-
– Changes introduced by the store-clock-fast system-identification word (SID) for the IPL-
facility are added to the section “CPU Retry.” device during list-directed IPL, if a subchan-
– Changes introduced by the modified-CCW- nel is associated with the IPL-device.
indirect-data-addressing facility are added to • In Chapter 18, “Hexadecimal-Floating-Point
the section “Invalid CBC in Storage”. Instructions”, descriptions of the twelve instruc-
– Changes introduced by the TOD-clock-steer- tions introduced by the HFP-unnormalized-
ing facility are added to the section “Timing- extensions facility are added.
Facility Damage.” • In Appendix I, character representations of
– Changes introduced by the server-time-pro- EBCDIC code pages 81C, 94C, 500, and 1047,
tocol facility are added to the section “Exter- IBM-PC, and BookMaster symbols are removed.
nal-Damage Code.” Only the commonly used EBCDIC code page
037 and ISO-8 characters are shown.
• In Chapter 13, “I/O Overview”, changes intro-
duced by the modified-CCW-indirect-data-
xxxv
– Serialization requirements for instructions
Summary of Changes in Fourth that implicitly store into the trace table or link-
age stack are relaxed.
Edition
• In Chapter 6, “Interruptions”:
The fourth edition of this publication differs from the – Changes introduced by the ASN-and-LX-
previous edition principally by containing the defini- reuse facility include the new LFX transla-
tions of the extended-translation facility 3 and the tion, LSX translation, LSTE sequence, and
ASN-and-LX-reuse facility. The fourth edition con- ASTE instance exceptions.
tains minor clarifications and corrections and also the
following significant changes relative to the previous – An additional condition for TRAP is added to
edition: the list of instructions that can cause a spe-
cial-operation exception to be recognized.
• In Chapter 3, “Storage”:
– SEARCH STRING UNICODE, a part of the
– Changes introduced by the ASN-and-LX- extended-translation facility 3, is added to
reuse facility are added, including changes the list of instructions that can cause a speci-
to the “Address Spaces” and “ASN Transla- fication exception to be recognized.
tion” sections.
• In Chapter 7, “General Instructions”:
– A programming note is added to the
– Six new instructions provided by the
“Dynamic Address Translation” section,
extended-translation facility 3 are added. The
describing implications in using common
instructions CONVERT UNICODE TO UTF-8
segments.
(CUUTF) and CONVERT UTF-8 TO UNI-
– The ATMID and AI fields are corrected in the CODE (CUTFU) are renamed to CONVERT
“Assigned Storage Locations” figure. UTF-16 TO UTF-8 (CU21) and CONVERT
UTF-8 TO UTF-16 (CU12), respectively. The
• In Chapter 4, “Control”: old mnemonics continue to be recognized.
– Changes introduced by the ASN-and-LX- – The instruction-format illustrations for
reuse facility are added, including changes STAMY and STMY are corrected.
to the “Trace” section.
• In Chapter 10, “Control Instructions”:
– The list-directed IPL function is added to the
“Initial Program Load” section. – Changes introduced by the ASN-and-LX-
reuse facility include the following:
– In the “Trace” section, serialization require-
ments for instructions that implicitly store into – Four new instructions provided by the
the trace table or linkage stack are relaxed. facility are added.
xxxvii
(All instructions that were of format RSE are – Five instructions provided by the message-
now referred to as being of format RSY.) security assist are added.
– The fetch of the address-space-control ele- – The COMPARE AND SWAP AND PURGE
ment from the ASN-second-table entry dur- (CSPG) and INVALIDATE DAT TABLE
ing access-register translation is doubleword ENTRY instructions provided by the DAT-
concurrent as observed by other CPUs. enhancement facility are added. CSPG oper-
ates on a doubleword operand in storage.
– The change bit is not necessarily set to one
currently with the related storage reference, – The definition of LOAD ADDRESS SPACE
as observed by other CPUs; it may be set to PARAMETERS is clarified.
one before or after the reference, within cer- – The LOAD REAL ADDRESS (LRAY) instruc-
tain limits. See “Storage-Key Accesses” on tion provided by the long-displacement facil-
page 5-91 for a detailed description of when ity is added.
the change bit is set.
– All previously existing format-RSE instruc-
– The five instructions of the message-security tions are changed to be of format RSY by
assist are added to the list of instructions use of a previously unused byte in the
having multiple-access references. instructions. These changes are not marked
• In Chapter 6, “Interruptions,” the list of conditions by a bar in the margin.
causing a specification exception to be recog- – The description of the bits set by STORE
nized is extended to include those caused by the FACILITY LIST is clarified, and new bits are
message-security assist instructions. assigned.
• In Chapter 7, “General Instructions”: • In Chapter 14, “I/O Instructions”:
– Thirty-nine instructions provided by the long- – The definition of MODIFY SUBCHANNEL is
displacement facility are added. With the modified.
exception of the new LOAD BYTE instruc-
tion, the instructions added by the long-dis- – The definition of SET CHANNEL MONITOR
placement facility have names and functions is modified.
that are the same as existing instructions
(but the mnemonics and opcodes are new). • In Chapter 15, “Basic I/O Functions,” the follow-
The new instructions are of formats RSY, ing changes are made to the subchannel-infor-
RXY, and SIY and have a 20-bit signed dis- mation-block (SCHIB):
placement instead of a 12-bit unsigned dis- – Bit 29 of word 6 of the path-management-
placement. control word (PMCW) is defined as the mea-
– All previously existing format-RSE and for- surement-block-format control.
mat-RXE instructions are changed to be of – Bit 30 of word 6 of the PMCW is defined as
formats RSY and RXY, respectively, by use the extended-measurement-word-mode
of a previously unused byte in the instruc- enablement bit.
tions. These changes are not marked by a
bar in the margin. – The definition of words 10-11 (words 0-1 of
the model-dependent area) are changed to
• In Chapter 16, “I/O Interruptions”, the interrup- – The definition of real locations 200-203,
tion-response block (IRB) is extended to include stored in by STORE FACILITY LIST, is cor-
the extended-measurement word. rected to state that bit 16 indicates the
extended-translation facility 2.
• In Chapter 17, “I/O Support Functions”:
• In Chapter 4, “Control,” a description of unas-
– The requirement that the measurement block signed fields in the PSW is corrected to state that
be updated when secondary status is bit 4 is unassigned and bit 31 is assigned.
accepted is clarified.
• In Chapter 5, “Program Execution,” the RSL for-
– The extended-measurement-block facility is mat and an RIL format with an M1 field are
added. added.
– The extended-measurement-word facility is • In Chapter 7, “General Instructions”:
added.
– The definition of BRANCH AND SET MODE
• In Chapter 18, “Hexadecimal-Floating-Point is corrected to state that bit 63 of the R1 gen-
Instructions,” the MULTIPLY AND ADD (four eral register remains unchanged in the 24-bit
instructions) and MULTIPLY AND SUBTRACT or 31-bit addressing mode; the bit is not set
(four instructions) instructions provided by the to zero.
HFP-multiply-add/subtract facility are added.
– The definitions of PACK ASCII, PACK UNI-
The above changes may affect other chapters CODE, UNPACK ASCII, and UNPACK UNI-
besides the ones listed. All technical changes to the CODE are clarified.
text or to an illustration are indicated by a vertical line
to the left of the change. – It is clarified that the following instructions
perform multiple-access references to their
storage operands:
xxxix
– STORE SYSTEM INFORMATION – It is clarified that address-limit checking
applies to data locations and not to locations
Chapters 13-17 contain many clarifying changes, all containing a CCW or IDAW.
indicated by a vertical line in the margin, in addition
to the significant changes listed below. • In Chapter 16, “I/O Interruptions,” the form of the
address stored in the failing-storage-address
• In Chapter 13, “I/O Overview,” statements about field is described in terms of the format-2-IDAW
the suspend flag in a CCW are clarified to control instead of an addressing mode.
describe the flag being specified as a one and • In Chapter 17, “I/O Support Functions”:
being valid because of a one value of the sus-
pend control in the associated ORB. – The introduction to the channel-subsystem
monitoring facilities is clarified.
• In Chapter 14, “I/O Instructions,” the results of
MODIFY SUBCHANNEL when the device-num- – References to the measurement block by the
ber-valid bit at the designated subchannel is zero measurement-block-update facility are sin-
are corrected. gle-access references and appear to be
word concurrent as observed by CPUs. They
• In Chapter 15, “Basic I/O Functions”: do not appear to be block concurrent.
– It is clarified that unlimited prefetching of – The description of the channel-subsystem-
data and IDAWs associated with the current I/O-priority facility is corrected by including
and prefetched CCWs is allowed indepen- mention of control-unit priority for fibre-chan-
dent of the value of the prefetch control in the nel-attached control units.
associated ORB.
– A specified control-unit-priority number is The above changes may affect other chapters
ignored if the channel-subsystem-I/O-prior- besides the ones listed.
ity facility is not operational due to an opera-
tor action.
This publication provides, for reference purposes, a of any particular implementation. Several dissimilar
detailed description of z/Architecture.™ machine implementations may conform to a single
architecture. When the execution of a set of pro-
The architecture of a system defines its attributes as grams on different machine implementations pro-
seen by the programmer, that is, the conceptual duces the results that are defined by a single
structure and functional behavior of the machine, as architecture, the implementations are considered to
distinct from the organization of the data flow, the log- be compatible for those programs.
ical design, the physical design, and the performance
The extract-CPU-time facility may be available on a • The ability to directly or indirectly designate any
model implementing z/Architecture. The facility adds or all of the TCCB, the input data storage area,
the general instruction EXTRACT CPU TIME. This and the output data storage area. When a stor-
instruction provides an efficient means by which a age area is designated directly, the TCW speci-
problem-state program can determine the amount of fies the location of a single, contiguous block of
storage. When a storage area is designated indi-
• ADD IMMEDIATE
FPR-GR-Transfer Facility • COMPARE HALFWORD
• COMPARE HALFWORD IMMEDIATE
The FPR-GR-transfer facility includes two instruc- • COMPARE LOGICAL IMMEDIATE
tions: LOAD FPR FROM GR and LOAD GR FROM • LOAD ADDRESS EXTENDED
FPR. These instructions provide the means to move • LOAD AND TEST
a 64-bit (long) floating-point datum between a float- • MOVE
ing-point register and a general register. (April, 2007) • MULTIPLY
• MULTIPLY HALFWORD
General-Instructions-Extension (February, 2008)
Facility
The general-instructions-extension facility may be
HFP Multiply-and-Add/Subtract
available on a model implementing z/Architecture. Facility
The facility provides the following new instructions:
The HFP-multiply-and-add/subtract facility provides
• ADD LOGICAL WITH SIGNED IMMEDIATE instructions for improved processing of hexadecimal
• COMPARE AND BRANCH floating-point numbers. The MULTIPLY AND ADD (or
• COMPARE AND BRANCH RELATIVE SUBTRACT) instruction is intended to be used in
• COMPARE AND TRAP place of MULTIPLY followed by ADD (or SUBTRACT)
• COMPARE HALFWORD RELATIVE LONG NORMALIZED. (June, 2003)
• COMPARE IMMEDIATE AND BRANCH
• COMPARE IMMEDIATE AND BRANCH
RELATIVE HFP-Unnormalized-Extensions
• COMPARE IMMEDIATE AND TRAP Facility
• COMPARE LOGICAL AND BRANCH
• COMPARE LOGICAL AND BRANCH RELATIVE The HFP-unnormalized-extension facility may be
• COMPARE LOGICAL AND TRAP available on a model implementing z/Architecture.
• COMPARE LOGICAL IMMEDIATE AND The facility provides instructions for improved pro-
BRANCH cessing of unnormalized hexadecimal floating-point
• COMPARE LOGICAL IMMEDIATE AND numbers. It extends the capabilities of the HFP-multi-
BRANCH RELATIVE ply-and-add/subtract facility, by providing the follow-
• COMPARE LOGICAL IMMEDIATE AND TRAP ing instructions that operate on unnormalized
• COMPARE LOGICAL RELATIVE LONG operands:
• COMPARE RELATIVE LONG
• EXTRACT CACHE ATTRIBUTE MULTIPLY UNNORMALIZED
• LOAD HALFWORD RELATIVE LONG MULTIPLY AND ADD UNNORMALIZED
• LOAD LOGICAL HALFWORD RELATIVE LONG
• LOAD LOGICAL RELATIVE LONG (September, 2005)
• LOAD RELATIVE LONG
• MULTIPLY SINGLE IMMEDIATE
• PREFETCH DATA High-Word Facility
• PREFETCH DATA RELATIVE LONG
• ROTATE THEN AND SELECTED BITS The high-word facility may be available on a model
• ROTATE THEN EXCLUSIVE OR SELECTED implementing z/Architecture. For selected 32-bit
BITS instructions, the high-word facility effectively provides
• ROTATE THEN INSERT SELECTED BITS sixteen additional 32-bit registers by utilizing bits 0-
• ROTATE THEN OR SELECTED BITS 31 of the sixteen 64-bit general registers. The facility
• STORE HALFWORD RELATIVE LONG provides the following instructions.
• STORE RELATIVE LONG
Message-Security-Assist Message-Security-Assist
Extension 1 Extension 3
The message-security-assist extension 1 may be
The message-security-assist extension 3 provides a
available on models implementing the message-
means to protect user cryptographic keys by encrypt-
security assist. The extension provides the following
ing them under machine-generated wrapping keys.
functions:
When this extension is installed, two wrapping keys
are provided for each configuration: one for protect-
MSA SHA-256 Facility: This facility consists of two
ing user DEA keys and another for protecting user
functions, one for generating an intermediate mes-
AES keys. The wrapping keys reside in the machine
sage digest and another for generating a final mes-
so that, with an appropriate setting of controls, no
sage digest.
clear value of user cryptographic keys is observed
any where in the system by any program.
1. These key lengths reflect the cryptographic strength. In subsequent chapters, they are referred to as 64-bit, 128-bit, or 192-bit,
respectively, to include the DEA-key-parity bits.
• A 192-Bit DEA Wrapping-Key Register: The reg- These functions provide a means for importing
ister contents are used to protect user DEA keys. clear cryptographic keys.
• Query
• The following functions under the COMPUTE
• DEA
MESSAGE AUTHENTICATION CODE instruc-
• TDEA 128
tion:
• TDEA 192
• Encrypted DEA • Encrypted DEA
• Encrypted TDEA 128 • Encrypted TDEA 128
• Encrypted TDEA 192 • Encrypted TDEA 192
• AES 128
These functions use an encrypted cryptographic • AES 192
key. • AES 256
• Encrypted AES 128
• Encrypted AES 192
• The following functions under the CIPHER MES- When modified CCW indirect data addressing is
SAGE instruction: used, the CCW data address is not used to directly
• XTS AES 128 address data. Instead, the address points to a contig-
• XTS AES 256 uous list of up to 256 quadwords called the modified-
indirect-data-address list (MIDAL). Each quadword in
• XTS Encrypted AES 128
the MIDAL is called a modified-indirect-data-address
• XTS Encrypted AES 256
word (MIDAW) that describes a block of storage to be
• The following function under the COMPUTE transferred and contains flags, a byte count, and a
INTERMEDIATE MESSAGE DIGEST instruction: 64-bit address designating a data area in absolute
storage. When modified CCW indirect data address-
• GHASH ing is used, transfer of control from one MIDAW to
the next is made when the count of bytes specified by
• The following functions under the COMPUTE
the MIDAW count field has been transferred and the
MESSAGE AUTHENTICATION CODE instruc-
total count of bytes transferred does not yet equal the
tion:
count specified by the CCW. This is dissimilar to indi-
• AES 128 rect data addressing where the transfer of control
• AES 192 from one IDAW to the next is made when a program-
• AES 256 specified 2K or 4K boundary is reached and the total
• Encrypted AES 128 count of bytes transferred does not yet equal the
• Encrypted AES 192 count specified in the CCW.
• Encrypted AES 256
In addition to the MIDAW, the ORB modified-CCW-
indirect-data-addressing-control bit and the CCW
The store-clock-fast facility may be available on a The CPU-related facilities that were new in ESA/390
model implementing z/Architecture. The facility pro- are summarized below. ESA/390 was announced in
vides a means by which an eight-byte time-of-day September, 1990. Any extension added subse-
clock value may be stored without any artificial delay quently has the date of its announcement in paren-
to ensure uniqueness. When the facility is installed, theses at the end of its summary.
the TOD-clock bits stored by TRACE (TRACE and
TRACG) are subject to additional control by a bit in The following extensions are described in detail in
control register 0. The facility provides the STORE SA22-7201 and in this publication:
CLOCK FAST instruction. (September, 2005)
The CPU-related facilities that were new in 370-XA • Path management, whereby the channel sub-
are as follows: system determines which paths are available for
selection, chooses a path, and manages any
• Bimodal addressing provides two modes of oper- busy conditions encountered while attempting to
ation: a 24-bit addressing mode for the execution initiate I/O processing with the associated
of old programs and a 31-bit addressing mode. devices.
• 31-bit logical addressing extends the virtual • Dynamic reconnection, which permits any I/O
address space from the 16M bytes addressable device using this capability to reconnect to any
with 24-bit addresses to 2G bytes available channel path to which it has access in
(2,147,483,648 bytes). order to continue execution of a chain of com-
mands.
• 31-bit real and absolute addressing provides
addressability for up to 2G bytes of main storage. • Programmable interruption subclasses, which
permit the programmed assignment of I/O-inter-
• The 370-XA protection facilities include key-con- ruption requests from individual I/O devices to
trolled protection on only 4K-byte blocks, page any one of eight maskable interruption queues.
protection, and, as in System/370, low-address
protection for addresses below 512. Fetch-pro- • An additional CCW format for the direct use of
tection override eliminates fetch protection for 31-bit addresses in channel programs. The new
locations 0-2047. CCW format, called format 1, is provided in addi-
tion to the System/370 CCW format, now called
• The tracing facility assists in the determination of format 0.
system problems by providing an ongoing record
in storage of significant events. • Address-limit checking, which provides an addi-
tional storage-protection facility to prevent data
• The COMPARE AND FORM CODEWORD and access to storage locations above or below a
UPDATE TREE instructions facilitate sorting specified absolute address.
applications.
• Monitoring facilities, which can be invoked by the
• The interpretive-execution facility allows creation program to cause the channel subsystem to
of virtual machines that may operate according measure and accumulate key I/O-resource
to several architectures and whose performance usage parameters.
is enhanced because many virtual-machine
functions are directly interpreted by the machine • Status-verification facility, which reports inappro-
rather than simulated by the program. This facil- priate combinations of device-status bits pre-
ity is described in the publication IBM 370-XA sented by a device.
Interpretive Execution, SA22-7095.
• A set of 13 I/O instructions, with associated con-
• The service-call-logical-processor (SCLP) facil- trol blocks, which are provided for the control of
ity provides a means of communicating between the channel subsystem.
the control program and the service processor
Expanded storage may also be available in the sys- Serial Channel Paths Parallel Channel Paths
tem, a cryptographic unit may be included in a CPU, …
Each configuration is isolated in that the main and Each 4K-byte block of expanded storage is
expanded storage in one configuration is not directly addressed by means of a 32-bit unsigned binary inte-
addressable by the CPUs and the channel sub- ger called an expanded-storage block number.
system of another configuration. It is, however, pos-
sible for one configuration to communicate with
another by means of shared I/O devices or a chan-
nel-to-channel adapter. At any one time, the storage,
CPU
CPUs, subchannels, and channel paths connected
together in a system are referred to as being in the The central processing unit (CPU) is the controlling
configuration. Each CPU, subchannel, channel path, center of the system. It contains the sequencing and
main-storage location, and expanded-storage loca- processing facilities for instruction execution, inter-
tion can be in only one configuration at a time. ruption action, timing functions, initial program load-
ing, and other machine-related functions.
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Note: The arrows indicate that the two registers may be coupled as a double-register pair, designated by specifying the
lower-numbered register in the R field. For example, the floating-point register pair 13 and 15 is designated by 1101
binary in the R field.
Figure 2-2. Control, Access, General, and Floating-Point Registers
This chapter discusses the representation of informa- tion, and reference and change recording. The
tion in main storage, as well as addressing, protec- aspects of addressing which are covered include the
Fetching and storing of data by a CPU are not Each byte location in storage is identified by a unique
affected by any concurrent channel-subsystem activ- nonnegative integer, which is the address of that byte
ity or by a concurrent reference to the same storage location or, simply, the byte address. Adjacent byte
location by another CPU. When concurrent requests locations have consecutive addresses, starting with 0
to a main-storage location occur, access normally is on the left and proceeding in a left-to-right sequence.
granted in a sequence determined by the system. If a Addresses are unsigned binary integers and are 24,
reference changes the contents of the location, any 31, or 64 bits. Addresses are described in “Address
subsequent storage fetches obtain the new contents. Size and Wraparound” on page 3-5.
When the length of a storage-operand field is implied Instructions must be on two-byte integral boundaries,
by the operation code of an instruction, the field is and CCWs, IDAWs, MIDAWs, and the storage oper-
said to have a fixed length, which can be one, two, ands of certain instructions must be on other integral
four, eight, or sixteen bytes. Larger fields may be boundaries. The storage operands of most instruc-
implied for some instructions. tions do not have boundary-alignment requirements.
When the length of a storage-operand field is not Programming Note: For fixed-field-length opera-
implied but is stated explicitly, the field is said to have tions with field lengths that are a power of 2, signifi-
a variable length. Variable-length operands can vary cant performance degradation is possible when
in length by increments of one byte. storage operands are not positioned at addresses
that are integral multiples of the operand length. To
improve performance, frequently used storage oper-
ands should be aligned on integral boundaries.
The channel subsystem and all CPUs in the configu- At any instant there is one real-address to absolute-
ration refer to a shared main-storage location by address mapping for each CPU in the configuration.
using the same absolute address. Available main When a real address is used by a CPU to access
24-bit Address
0 40 63
31-bit Address
0 33 63
64-bit Address
0 63
The bits of an address that is 31 bits regardless of When bit 31 is zero and bit 32 is one, the CPU is in
the addressing mode are numbered 1-31, and, when the 31-bit addressing mode, and 31-bit operand and
a 24-bit or 31-bit address is contained in a four-byte instruction effective addresses are specified. When
field in storage, the bits are numbered 8-31 or 1-31, bits 31 and 32 are both one, the CPU is in the 64-bit
respectively: addressing mode, and 64-bit operand and instruction
effective addresses are specified (see “Address Gen-
24-bit Address eration” on page 5-8).
0 8 31
The sizes of the real or absolute addresses used or
31-bit Address
yielded by the ASN-translation, ASN-authorization,
0 1 31
PC-number-translation, and access-register-transla-
tion processes are always 31 bits regardless of the
A 24-bit or 31-bit virtual address is expanded to 64 current addressing mode. Similarly, the sizes of the
bits by appending 40 or 33 zeros, respectively, on the real or absolute addresses used or yielded by the
left before it is translated by means of the DAT pro- DAT, stacking, unstacking, and tracing processes are
cess, and a 24-bit or 31-bit real address is similarly always 64 bits.
expanded to 64 bits before it is transformed by prefix-
ing. A 24-bit or 31-bit absolute address is expanded The size of the data address in a CCW is under con-
to 64 bits before main storage is accessed. Thus, the trol of the CCW-format-control bit in the operation-
24-bit address always designates a location in the request block (ORB) designated by a START SUB-
first 16M-byte block of the 16E-byte storage address- CHANNEL instruction. The CCWs with 24-bit and
able by a 64-bit address, and the 31-bit address 31-bit addresses are called format-0 and format-1
always designates a location in the first 2G-byte CCWs, respectively. Format-0 and format-1 CCWs
block. are described in “Basic I/O Functions” on page 15-1.
Similarly, the size of the data address in an IDAW is
Unless specifically stated to the contrary, the follow- under control of the IDAW-format-control bit in the
ing definition applies in this publication: whenever the ORB. The IDAWs with 31-bit and 64-bit addresses
machine generates and provides to the program a are called format-1 and format-2 IDAWs, respectively.
24-bit or 31-bit address, the address is made avail- MIDAWs contain 64-bit data addresses. IDAWs and
able (placed in storage or loaded into a general regis- MIDAWs are described in Chapter 15, “Basic I/O
ter) by being imbedded in a 32-bit field, with the Functions.”
leftmost eight bits or one bit in the field, respectively,
set to zeros. When the address is loaded into a gen-
Address Wraparound
eral register, bits 0-31 of the register remain
The CPU performs address generation when it forms
unchanged.
an operand or instruction address or when it gener-
ates the address of a table entry from the appropriate
The size of effective addresses is controlled by bits
table origin and index. It also performs address gen-
31 and 32 of the PSW, the extended-addressing-
eration when it increments an address to access suc-
mode bit and the basic-addressing-mode bit, respec-
cessive bytes of a field. Similarly, the channel
tively. When bits 31 and 32 are both zero, the CPU is
subsystem performs address generation when it
in the 24-bit addressing mode, and 24-bit operand
increments an address (1) to fetch a CCW, (2) to
and instruction effective addresses are specified.
fetch an IDAW, (3) to fetch a MIDAW, (4) to transfer
Handling when
Address Address Would
Address Generation for Type Wrap
Instructions and operands when EAM and BAM are zero L,I,R,V W24
1
Successive bytes of instructions and operands when EAM and BAM are zero I,L,V W24
Instructions and operands when EAM is zero and BAM is one L,I,R,V W31
Successive bytes of instructions and operands when EAM is zero and BAM is one I,L,V1 W31
Instructions and operands when EAM and BAM are one L,I,R,V W64
1
Successive bytes of instructions and operands when EAM and BAM are one I,L,V W64
DAT-table entries when used for implicit translation or for LPTEA, LRA, LRAG, or STRAG A or R2 X64
Explanation:
1
Real addresses do not apply in this case since the instructions which designate operands by means of real
24 31 64
addresses cannot designate operands that cross boundary 2 , 2 , 2 .
2
It is unpredictable whether the address is absolute or real.
A Absolute address.
BAM Basic-addressing-mode bit in the PSW.
EAM Extended-addressing-mode bit in the PSW.
I Instruction address.
L Logical address.
24
P24 An I/O program-check condition is recognized when the address exceeds 2 - 1 or is decremented below zero.
31
P31 An I/O program-check condition is recognized when the address exceeds 2 - 1 or is decremented below zero.
64
P64 An I/O program-check condition is recognized when the address exceeds 2 - 1 or is decremented below zero.
R Real address.
V Virtual address.
24
W24 Wrap to location 0 after location 2 - 1 and vice versa.
W31 Wrap to location 0 after location 231 - 1 and vice versa.
64
W64 Wrap to location 0 after location 2 - 1 and vice versa.
31
X31 When the address exceeds 2 - 1, it is unpredictable whether the address wraps to location 0 after location
231 - 1 or whether an addressing exception is recognized.
64
X64 When the address exceeds 2 - 1, it is unpredictable whether the address wraps to location 0 after location
64
2 - 1 or whether an addressing exception is recognized.
Change Bit (C): The change bit, bit 6, is set to one – When the ACCF-validity control is one, bit
each time information is stored at a location in the positions 48-52 of the segment-table entry
corresponding storage block. contain the access-control bits and the fetch-
protection bit for the segment. When deter-
Storage keys are not part of addressable storage. mining accessibility to a storage operand, it
The entire storage key may be set by SET STOR- is unpredictable whether bits 48-52 of the
AGE KEY EXTENDED and inspected by INSERT STE or bits 0-4 of the individual storage keys
STORAGE KEY EXTENDED. RESET REFERENCE for the 4K-byte blocks composing the seg-
BIT EXTENDED provides a means of inspecting the ment are examined. See “Translation Pro-
reference and change bits and of setting the refer- cess” on page 3-45 for further details.
ence bit to zero. RESET REFERENCE BITS MULTI-
PLE provides a means of inspecting the reference – Bit 55 of the segment-table entry is the
bits of 64 contiguous 4 K-byte blocks and setting the change-recording override (CO) for the seg-
reference bits to zero. Bits 0-4 of the storage key are ment. When the CO bit in the segment-table
inspected by the INSERT VIRTUAL STORAGE KEY entry is one, it is unpredictable whether the
instruction. The contents of the storage key are change bit is set for any store operations to
unpredictable during and after the execution of the the segment.
usability test of the TEST BLOCK instruction. When
the conditional SSKE facility is installed, SET STOR- Programming Notes:
AGE KEY EXTENDED may be used to set all or por-
tions of a storage key based on program-specified 1. When enhanced DAT applies, and both the
criteria. When the enhanced-DAT facility is installed, ACCF-validity control and the STE-format control
the SET STORAGE KEY EXTENDED or PERFORM (bits 47 and 53 of the segment-table entry,
FRAME MANAGEMENT FUNCTION instructions respectively) are one, bits 48-52 of the STE con-
may be used to set all or portions of one or more tain access-control and fetch protection bits
storage keys based on program-specified criteria. which may be used in lieu of the corresponding
bits in the storage keys. In this case, the program
When enhanced DAT applies,1 and the invalid bit of is responsible for ensuring that the access-con-
the segment-table entry used in the translation is trol and fetch-protection bits in the STE are iden-
zero, the following additional conditions are in effect: tical to the corresponding bits in each of the 256
storage keys for the segment. See “Modification
• When the STE-format control (FC, bit 53 of the of Translation Tables” on page 3-55 for restric-
segment-table entry used during a translation) is tions on modifying the STE or the storage keys
zero, bit 55 of the page-table entry used during when the STE-format control is one.
translation is the change-recording override (CO) 2. When enhanced DAT applies and the STE format
for the page. When the CO bit in the page-table control is zero, the change-recording override in
the PTE controls whether change recording for
1. See “Enhanced-DAT Terminology:” on page 3-37 for an explanation of the term “enhanced-DAT applies.”
2. Prior to the enhanced-DAT facility, the DAT-protection function was known as the page-protection facility.
3. The suppression-on-protection function originated as the ESA/390 suppression-on-protection facility. Suppression for page pro-
tection (now called DAT protection) was new as part of that facility.
When enhanced DAT applies, and the format- When the enhanced suppression-on-protection func-
control (FC) bit in the segment-table entry is one, tion is installed, there are the following additional
a similar technique may be used to map a single constraints on what may occur during a protection
segment frame of absolute storage. exception. These constraints take precedence over
any constraints defined in the original suppression-
2. Bit 61 being one in real locations 168-175 when on-protection function.
DAT was on indicates that the address that
caused a protection exception is virtual. This
Reference recording provides information for use in • The STE-format control in the segment-table
selecting pages for replacement. Reference record- entry used by DAT is zero, and the change-
ing uses the reference bit, bit 5 of the storage key.
• The STE-format control in the segment-table When enhanced DAT applies, and the virtual address
entry used by DAT is one, and the change- is translated by means of DAT-table entries, a
recording override (CO) in the segment-table change-recording override (CO) is provided in bit 55
entry used by DAT is zero. of both the segment-table entry and the page-table
entry.
The change bit is not set to one for an attempt to
store if the access is prohibited. In particular: When the STE-format control (FC), bit 53 of the seg-
ment-table entry is zero, the change-recording over-
1. For the CPU, a store access is prohibited when- ride in the page-table entry applies. When the
ever an access exception exists for that access, change-recording override in the PTE is zero, change
or whenever an exception exists which is of recording occurs for store operations to the 4K-byte
higher priority than the priority of an access block. When the change-recording override is one, it
exception for that access. is unpredictable whether change recording occurs for
store operations to the 4K-byte block.
2. For the channel subsystem, a store access is
prohibited whenever a key-controlled-protection When the STE-format control is one, the change-
violation exists for that access. recording override in the STE applies. When the
change-recording override in the STE is zero, change
Change recording is always active and takes place recording occurs for store operations to any of the
for all store accesses to storage, including those segment’s 256 4K-byte blocks. When the change-
made by any CPU (except when suppressed by the recording override in the STE is one, it is unpredict-
change-recording override, as described below), any able whether change recording occurs to any of the
operator facility, or the channel subsystem. It takes segment’s 256 4K-byte blocks.
place for implicit references made by the machine,
such as those which are part of interruptions. The change-recording override does not apply to real
or absolute addresses, or to a virtual address that is
Change recording does not take place for the oper- translated by means of a real-space designation.
ands of the following instructions since they directly
modify a storage key without modifying a storage Programming Notes:
location:
1. As stated in the section “Change Recording”,
• RESET REFERENCE BIT EXTENDED above, a fundamental use of the change bit is
• RESET REFERENCE BITS MULTIPLE determining if the contents of a storage block
• SET STORAGE KEY EXTENDED (change bit needs to be migrated to auxiliary storage prior to
may be set to a specified value) replacing the block. If the program does not need
to migrate certain blocks of storage, for example,
Change bits which have been changed from zeros to blocks that are long-term “fixed” (also known as
ones are not necessarily restored to zeros on CPU “pinned”), the program may not need to rely on
retry (see “CPU Retry” on page 11-2). See “Excep- the change bit for those blocks. In this case,
tions to Nullification and Suppression” on page 5-23 either or both of the following techniques may
for a description of the handling of the change bit in improve CPU performance:
certain unusual situations.
• Setting the change-recording override to one
When the condition specified by the M3 field of a to indicate that change recording is not
STORE ON CONDITION instruction is not met, it is required for the blocks
model dependent whether the change bit is set for • Presetting the change bit to one in the stor-
the storage location designated by the second oper- age key
and.
2. See “Modification of Translation Tables” on
page 3-55 for restrictions on modifying the
change-recording override in the STE or PTE.
Prefixing causes real addresses in the range 0-8191 3. Bits 0-50 of the address, if not all zeros and not
to correspond one-for-one to the block of 8K-byte equal to bits 0-50 of the prefix, remain
absolute addresses (the prefix area) identified by the unchanged.
value in bit positions 0-50 of the prefix register for the
CPU, and the block of real addresses identified by Only the address presented to storage is translated
that value in the prefix register to correspond one-for- by prefixing. The contents of the source of the
one to absolute addresses 0-8191. The remaining address remain unchanged.
real addresses are the same as the corresponding
absolute addresses. This transformation allows each The distinction between real and absolute addresses
CPU to access all of main storage, including the first is made even when the prefix register contains all
8K bytes and the locations designated by the prefix zeros, in which case a real address and its corre-
registers of other CPUs. sponding absolute address are identical.
No change
/ / /
No change
Apply
1 2
Zeros
/ / /
Apply
2 1
Zeros
/ / /
No change
No change
(1) Real addresses in which bits 0-50 are equal to bits 0-50 of the prefix for this CPU (A or B).
(2) Absolute addresses of the block that contains for this CPU (A or B) the real locations 0-8191.
Figure 3-6. Relationship between Real and Absolute Addresses
DAT uses, at different times, the address-space-con- which are translated by means of the primary
trol elements in different control registers or specified address-space-control element (ASCE). Similarly,
by the access registers. The choice is determined by the secondary address space consists of secondary
the translation mode specified in the current PSW. virtual addresses translated by means of the second-
Four translation modes are available: primary-space ary ASCE, the AR-specified address spaces consist
mode, secondary-space mode, access-register of AR-specified virtual addresses translated by
mode, and home-space mode. Different address means of AR-specified ASCEs, and the home
spaces are addressable depending on the translation address space consists of home virtual addresses
mode. translated by means of the home ASCE. The primary
and secondary ASCEs are in control registers 1 and
At any instant when the CPU is in the primary-space 7, respectively. The AR-specified ASCEs are in con-
mode or secondary-space mode, the CPU can trans- trol registers 1 and 7 and in table entries called ASN-
late virtual addresses belonging to two address second-table entries. The home ASCE is in control
spaces — the primary address space and the sec- register 13.
ondary address space. At any instant when the CPU
is in the access-register mode, it can translate virtual Changing to Different Address Spaces
addresses of up to 16 address spaces — the primary A program can cause different address spaces to be
address space and up to 15 AR-specified address addressable by using the semiprivileged SET
spaces. At any instant when the CPU is in the home- ADDRESS SPACE CONTROL or SET ADDRESS
space mode, it can translate virtual addresses of the SPACE CONTROL FAST instruction to change the
home address space. translation mode to the primary-space mode, sec-
ondary-space mode, access-register mode, or home-
The primary address space is identified as such space mode. However, SET ADDRESS SPACE
because it consists of primary virtual addresses, CONTROL and SET ADDRESS SPACE CONTROL
• When LOAD ADDRESS SPACE PARAMETERS, • The ASN-and-LX-reuse facility includes the fol-
PROGRAM CALL, PROGRAM RETURN, PRO- lowing new instructions:
ASN
ASN Translation AFX ASX
0 10 15
ASTESN
ASN-Translation Tables 160 191
Authority-Table Length (ATL): Bits 48-59 specify The subspace-group-control bit (G), bit 118 of the
the length of the authority table in units of four bytes, ASCE field, indicates, when one, that the ASCE
thus making the authority table variable in multiples specifies an address space that is the base space or
of 16 entries. The length of the authority table, in a subspace of a subspace group. The bit is further
units of four bytes, is one more than the ATL value. described in “Subspace-Group ASN-Second-Table
The contents of the ATL field are used to establish Entries” on page 5-64.
R
I ASTO
(x64)
/ / /
R C R
I ATO B AX ATL A A ASCE ALO ALL ASTESN LTD or LFTD ASTEIN
/ / /
R Address is real
The 31-bit real address of the ASN-second-table ASN authorization is also performed as part of PRO-
entry is obtained by appending six zeros on the right GRAM RETURN when the restored secondary ASN
to bits 1-25 of the ASN-first-table entry and adding does not equal the restored primary ASN. ASN
the ASX with six rightmost and 19 leftmost zeros authorization of the restored secondary ASN is per-
appended. When a carry into bit position 0 occurs formed after ASN translation of the restored second-
during the addition, an addressing exception may be ary ASN.
recognized, or the carry may be ignored, causing the
31
table to wrap from 2 - 1 to zero. The 31-bit address When performed as part of PT-ss, the ASN authori-
is formed and used regardless of whether the current zation tests whether the ASN can be established as
PSW specifies the 24-bit, 31-bit, or 64-bit addressing the primary ASN and is called primary-ASN authori-
mode. zation. When performed as part of LOAD ADDRESS
SPACE PARAMETERS, PROGRAM RETURN, or
The fetch of the 64 bytes of the ASN-second-table SSAR-ss, the ASN authorization tests whether the
entry appears to be word concurrent as observed by ASN can be established as the secondary ASN and
other CPUs, with the leftmost word fetched first. The is called secondary-ASN authorization.
order in which the remaining 15 words are fetched is
unpredictable. The fetch access is not subject to pro- The ASN authorization is performed by means of an
tection. When the storage address which is gener- authority table in real storage which is designated by
ated for fetching the ASN-second-table entry the authority-table-origin and authority-table-length
designates a location which is not available in the fields in the ASN-second-table entry.
configuration, an addressing exception is recognized,
and the operation is suppressed.
ASN-Authorization Controls
Bit 0 of the ASN-second-table entry specifies
whether the address space is accessible. If this bit is ASN authorization uses the authority-table origin and
one, an ASX-translation exception is recognized. the authority-table length from the ASN-second-table
entry, together with an authorization index.
Recognition of Exceptions during ASN
Translation Control Register 4
The exceptions which can be encountered during the For PT-ss and SSAR-ss, the current contents of con-
ASN-translation process are collectively referred to trol register 4 include the authorization index. For
as ASN-translation exceptions. A list of these excep- LOAD ADDRESS SPACE PARAMETERS and PRO-
tions and their priorities is given in Chapter 6, “Inter- GRAM RETURN, the value which will become the
ruptions”. new contents of control register 4 is used. The regis-
ter has the following format:
… AX …
32 48
ATO B
0 1 30 31
ASN-Authorization Process
ATL …
This section describes the ASN-authorization pro-
32 48 60 64
cess as it is performed during the execution of PRO-
GRAM TRANSFER with space switching and SET
Authority-Table Origin (ATO): Bits 1-29, with two SECONDARY ASN with space switching. For these
zeros appended on the right, are used to form a two instructions, the ASN-authorization process is
31-bit real address that designates the beginning of performed by using the authorization index currently
the authority table. in control register 4. Secondary authorization for
PROGRAM RETURN, when the restored secondary
Authority-Table Length (ATL): Bits 48-59 specify ASN does not equal the restored primary ASN, and
the length of the authority table in units of four bytes, for LOAD ADDRESS SPACE PARAMETERS is the
thus making the authority table variable in multiples same, except that the value which will become the
of 16 entries. The length of the authority table, in new contents of control register 4 is used for the
units of four bytes, is equal to one more than the ATL authorization index. Also, for LOAD ADDRESS
value. The contents of the length field are used to SPACE PARAMETERS, a secondary-authority
establish whether the entry designated by the autho- exception does not occur. Instead, such a condition
rization index falls within the authority table. is indicated by the condition code.
AX
(x1/4)
ASN-Second-Table Entry
/ / /
C R
I ATO B AX ATL A A ASCE ALO ALL ASTESN LTD or LFTD ASTEIN
/ / /
(x4)
Authority
Table
R Address is real
The 31-bit real address of a byte in the authority table TERS, when the authority-table length is exceeded,
is obtained by appending two zeros on the right to condition code 2 is set.
the authority-table origin and adding the 14 leftmost
bits of the authorization index with 17 zeros The fetch access to the byte in the authority table is
appended on the left. When a carry into bit position 0 not subject to protection. When the storage address
occurs during the addition, an addressing exception which is generated for fetching the byte designates a
may be recognized, or the carry may be ignored, location which is not available in the configuration, an
causing the table to wrap from 231 - 1 to zero. The addressing exception is recognized, and the opera-
31-bit address is formed and used regardless of tion is suppressed.
whether the current PSW specifies the 24-bit, 31-bit,
or 64-bit addressing mode. The byte contains four authority-table entries of two
bits each. The rightmost two bits of the authorization
As part of the authority-table-entry-lookup process, index, bits 46 and 47 of control register 4, are used to
bits 0-11 of the authorization index are compared select one of the four entries. The left or right bit of
against the authority-table length. If the compared the entry is then tested, depending on whether the
portion is greater than the authority-table length, a authorization test is for a primary ASN or a second-
primary-authority exception or secondary-authority ary ASN. The following table shows the bit which is
exception is recognized for PT-ss or SSAR-ss, selected from the byte as a function of bits 46 and 47
respectively. For LOAD ADDRESS SPACE PARAME- of the authorization index and the instruction PT-ss,
• The DAT-protection bit is defined in bit position 54 – The enhanced-DAT facility is not installed
of each region-table entry. – The enhanced-DAT facility is installed, but
the enhanced-DAT-enablement control is
• The STE-format control is defined in bit position zero
53 of the segment-table entry. When the STE-for- – The address is not translated by means of
mat control is zero, the following apply: DAT-table entries (that is, DAT is off; DAT is
on, but the ASCE designates a real space; or
– Bits 0-52 of the segment-table entry are the instruction uses a real address such as
used to locate the page table (as occurs LOAD USING REAL ADDRESS or STORE
when the enhanced-DAT facility is not USING REAL ADDRESS).
installed or enabled) – A real address is implicitly used, for example
– Bit 53 of the page-table entry contains the in the handling of an interruption, CPU
change-recording override for the page. logout, or fetching of table entries for ART,
ASN translation, ASN authorization, DAT, or
When the STE-format control is one, the follow- PC-number translation.
ing apply:
Programming Notes:
– Bits 0-43 of the segment-table entry form the
segment-frame absolute address. There is 1. If the program changes the state of the
no designation of a page table, and no page- enhanced-DAT-enablement control, then it
table entries are used. should also clear all entries from all TLBs in the
configuration by executing any of the following
instructions:
Primary Region-Table or Segment-Table Origin Programming Note: With respect to item 1 in the
0 31 above list, when the contents of control register 1 are
a real-space designation, a one value of the com-
Primary Region-Table or
GPSXR DT TL mon-segment bit in a TLB representation of a seg-
Segment-Table Origin (continued)
ment-table entry prevents the entry and the TLB
32 52 54 55 56 57 58 59 60 62 63
page-table copy it designates from being used
regardless of the value of the private-space control in
Primary Real-Space Designation (R=1) the real-space designation.
• Condition code 3 is set by LOAD ADDRESS Primary Real-Space Token Origin: Bits 0-51 of
SPACE PARAMETERS. the primary real-space designation in control register
1, with 12 zeros appended on the right, form a 64-bit
Primary Real-Space Control (R): If bit 58 of con- address that may be used in forming and using TLB
trol register 1 is zero, the register contains a region- entries that provide a virtual-equals-real translation
table or segment-table designation. If bit 58 is one, for references to the primary address space.
the register contains a real-space designation. When Although this address is used only as a token and is
bit 58 is one, a one value of the common-segment bit not used to perform a storage reference, it still must
in a translation-lookaside-buffer (TLB) representation be a valid address; otherwise, an incorrect TLB entry
of a segment-table entry prevents the entry and the may be used when the contents of control register 1
TLB page-table copy it designates from being used are used.
when translating references to the primary address
space, even with a match between the token origin in The following bits of control register 1 are not
control register 1 and the table origin in the TLB assigned and are ignored: bits 52, 53, and 59 if the
entry. register contains a region-table designation or seg-
ment-table designation, and bits 52, 53 and 59-63 if
Primary Designation-Type Control (DT): When R the register contains a real-space designation.
is zero, the type of table designation in control regis-
ter 1 is specified by bits 60 and 61 in the register, as Control Register 7
follows: Control register 7 contains the secondary address-
space-control element (SASCE). The register has
Bits 60 one of the following two formats, depending on the
and 61 Designation Type real-space-control bit (R) in the register:
11 Region-first-table
10 Region-second-table Secondary Region-Table or
01 Region-third-table
Segment-Table Designation (R=0)
00 Segment-table
Bits 60 and 61 must identify the correct table level, When enhanced DAT applies and the STE-format
considering the type of table designation that is the control is one, the entry fetched from the segment
address-space-control element being used in the table has the following format:
translation and the number of table levels that have
so far been used; otherwise, a translation-specifica- Segment-Table Entry (TT=00, FC=1)
tion exception is recognized.
Segment-Frame Absolute Address
Region-Second-Table Length, Region-Third-Table 0 31
Length, and Segment-Table Length (TL): A
region-first-table entry contains a region-second- Segment-Frame Absolute A F C
ACC F P I C TT
Address (continued) V C O
table length. A region-second-table entry contains a
32 44 47 48 52 53 54 55 56 58 59 60 62 63
region-third-table length. A region-third-table entry
contains a segment-table length. The following
description applies to each of the three lengths. Bits The fields in the segment-table entry are allocated as
62 and 63 of the entry specify the length of the next- follows:
lower-level table in units of 4,096 bytes, thus making
the length of the table variable in multiples of 512 Page-Table Origin: When enhanced DAT does not
entries. The length of the next-lower-level table, in apply, or when enhanced DAT applies but the STE-
units of 4,096 bytes, is one more than the TL value. format control, bit 53 of the segment-table entry, is
The contents of the length field, in conjunction with zero, bits 0-52, with 11 zeros appended on the right,
the offset field, bits 56 and 57, are used to establish form a 64-bit address that designates the beginning
whether the portion of the virtual address (RSX, of a page table. It is unpredictable whether the
RTX, or SX) to be translated by means of the next- address is real or absolute.
lower-level table designates an entry that actually
exists in the table. Segment-Frame Absolute Address (SFAA):
When enhanced DAT applies and the STE-format
All other bit positions of the region-table entry are control is one, bits 0-43 of the entry, with 20 zeros
reserved for possible future extensions and should appended on the right, form the 64-bit absolute
contain zeros; otherwise, the program may not oper- address of the segment.
ate compatibly in the future. When enhanced DAT
applies, the reserved bit positions of the region-table ACCF-Validity Control (AV): When enhanced DAT
entry should contain zeros even if the table entry is applies and the STE-format control is one, bit 47 is
invalid. the access-control-bits and fetch-protection bit
(ACCF) validity control. When the AV control is zero,
Segment-Table Entries bits 48-52 of the segment-table entry are ignored.
When the AV control is one, bits 48-52 are used as
When enhanced DAT does not apply, or when
described below.
enhanced DAT applies and the STE-format control,
bit 53 of the segment-table entry is zero, the entry
Access-Control Bits (ACC): When enhanced DAT
fetched from the segment table has the following for-
applies, the STE-format control is one, and the AV
mat:
control is one, bits 48-51 of the segment-table entry
contain the access-control bits that may be used for
any key-controlled access checking that applies to
the address. It is unpredictable whether the CPU
uses these bits or the access-control bits in the stor-
2. The program must ensure that segment-table DAT-Protection Bit (P): Bit 54 controls whether
entries in which the C bit is set to one, and any store accesses can be made in the page. This pro-
region-table entries used by the DAT process to tection mechanism is in addition to the key-con-
locate such segment-table entries, are consistent trolled-protection and low-address-protection
across all address spaces. That is, if the DAT mechanisms. The bit has no effect on fetch
process can successfully locate a segment-table accesses. If the bit is zero, stores are permitted to the
entry in which the C bit is one in one non-private page, subject to the following additional constraints:
address space, then there must be no exception
condition that prevents DAT from locating the • The DAT-protection bit being zero in the seg-
segment-table entry corresponding to the same ment-table entry used in the translation,
virtual address in any other non-private address
spaces. • When enhanced DAT applies, the DAT-protection
bit being zero in all region-table entries used in
If the program alters such a segment-table entry the translation,
or region-table entry in one non-private address
space, then it must also (a) perform consistent • Other protection mechanisms
alteration to all corresponding table entries in all
other non-private address spaces, and If the bit is one, stores are disallowed. When no
(b) ensure that the affected entries are cleared higher priority exception conditions exist, an attempt
from the TLBs of all CPUs in the configuration. to store when the DAT-protection bit is one causes a
protection exception to be recognized. The DAT-pro-
3. If the program fails to maintain consistent DAT tection bit in the segment-table entry is treated as
table entries as described above, results are being ORed with bit 54 when determining whether
unpredictable and may include the presentation DAT protection applies to the page. When enhanced
Translation of a virtual address is controlled by the The table entry selected by means of the effective
DAT-mode bit and address-space-control bits in the ASCE designates the next-lower-level table to be
PSW and by the address-space-control elements used. If the current table is a region first table, region
(ASCEs) in control registers 1, 7, and 13 and as second table, or region third table, the next portion of
specified by the access registers. When the ASCE the virtual address (region second index, region third
used in a translation is a region-first-table designa- index, or segment index, respectively) is checked
Processing of portions of the virtual address by In order to eliminate the delay associated with refer-
means of successive table levels continues until a ences to translation tables in real or absolute stor-
segment-table entry has been selected. When age, the information fetched from the tables normally
enhanced DAT applies, the DAT-protection bit in any is also placed in a special buffer, the translation-
and all region-table entries used during the transla- lookaside buffer (TLB), and subsequent translations
tion are treated as being ORed with the respective bit involving the same table entries may be performed by
in segment-table entry. using the information recorded in the TLB. The TLB
may also record virtual-equals-real translations
When enhanced DAT does not apply, or when related to a real-space designation. The operation of
enhanced DAT applies but the STE-format control is the TLB is described in “Translation-Lookaside
zero, the following conditions are in effect: Buffer” on page 3-52.
• The segment-table entry contains a DAT-protec-
tion bit that applies to all pages in the specified Whenever access to real or absolute storage is made
segment; the segment-table entry also contains during the address-translation process for the pur-
a common-segment bit that controls the use of pose of fetching an entry from a region table, seg-
the TLB copies of the page table designated by ment table, or page table, key-controlled protection
the segment-table entry. does not apply.
• The segment-table entry designates the page The translation process, including the effect of the
table to be used. TLB, is shown graphically in Figure 3-11 on
page 3-47.
• The page-index portion of the virtual address is
added to the page-table origin in the segment-
table entry to select an entry in the page table. If Inspection of Real-Space Control
the I bit is one in the page-table entry, a page- When the effective address-space-control element
translation exception is recognized. The page- (ASCE) contains a real-space control, bit 58, having
table entry contains the leftmost bits of the real the value zero, the ASCE is a region-table or seg-
address that represents the translation of the vir- ment-table designation. When the real-space control
tual address, and it contains a DAT-protection bit is one, the ASCE is a real-space designation.
that applies only to the page specified by the
page-table entry; when enhanced DAT applies Inspection of Designation-Type Control
and the STE-format control is zero, the page- When the real-space control is zero, the designation-
table entry also contains a change-recording type control, bits 60 and 61 of the effective address-
override that applies only to the page. space-control element (ASCE), specifies the table-
designation type of the ASCE. Depending on the
• The byte-index field of the virtual address is used type, some number of leftmost bits of the virtual
unchanged as the rightmost bit positions of the address being translated must be zeros; otherwise,
real address. an ASCE-type exception is recognized. For each
When enhanced DAT applies and the STE-format possible value of bits 60 and 61, the table-designa-
control is one, the following conditions are in effect:
DT [ 2 True
4
and
RFX g 0
38
CR1 (PASCE) 00 False
ASTE (AR-specified ASCE) 01 DT [ 1 & True5
RFX || RSX
CR7 (SASCE) 10
g0
CR13 (HASCE) 11 RFX.0-1 True 38
>
ASCE.TL False
DT = 0 True6
39
and
False
RX g 0
Effective Address-Space Control Element
38
Region-Table or Segment-Table Origin (R = 0) G P S X R DT TL
False
(x 4096)
R=1
True
00 01 10 11 RSX.0-1 True
<
C D RFTE.TF1
3A
(RFX x 8)
False
(I=1) 12
(x 4096) 3A
(RTX x 8) RTX.0-1
>
False 2
RSTE.TL
Region-Third Table (RTT)
3 + RTTE.TT True
Region-Third-Table Entry (RTTE) 8 =1
3B
Segment-Table Origin (STO) P TF I TT TL
False
(I=1) 12
(x 4096) 3B
(SX x 8) SX.0-1
>
False RTTE.TL
2
12
(I=1)
10
See next page STE.FC See next page See next page
0 1
Explanation:
1
Examination of the table-offset (TF) is not performed when the table entry is in a table that is designated by the ASCE.
2
When the table entry is designated by the ASCE, the second comparand is the table-length field (TL) in the ASCE.
3
Table origin is one of the two pointers: either from the ASCE or from the next-higher table entry.
4
RFX is not used as a table index when ASCE.DT is less than or equal to 2.
5
RFX and RSX are not used as table indices when ASCE.DT is less than or equal to 1.
6
RFX, RSX, and RTX are not used as table indices when ASCE.DT is equal to 0.
7
STE FC and CO are valid only when enhanced DAT applies; SFAA applies only when STE.FC is one.
8
The DAT-protection bit (P) in the region-table entries is only meaningful when enhanced DAT applies.
nn Rightmost two hex digits of the program-interruption code recognized for the condition shown, or when the invalid (I) bit is on in the selected table entry.
(x 2048)
(PX x 8)
11
Note:
When enhanced DAT applies, bit position 55 of the page-table entry contains Real Address
the change-bit override; when enhanced DAT does not apply, bit position 55 of
Page-Frame Real Address BX
the page-table entry is reserved and must contain zero.
Virtual Address
RX
RFX RSX RTX SX PX BX
When enhanced DAT applies and the STE-
1
format control (FC) is one:
C
Absolute Address
Segment-Frame Absolute Address PX BX
tion type and the virtual-address bits required to be Lookup in a Table Designated by an
zeros are as follows: Address-Space-Control Element
The designation-type control, bits 60 and 61 of the
Bits 60 Virtual-Address Bits effective address-space-control element (ASCE),
and 61 Designation Type Required to be Zeros
specifies both the table-designation type of the ASCE
11 Region-first-table None and the portion of the virtual address that is to be
10 Region-second-table 0-10
01 Region-third-table 0-21
00 Segment-table 0-32
When no exceptions are recognized in the process of • When enhanced DAT does not apply, or when
region-second-table lookup, the entry fetched from enhanced DAT applies but the STE-format con-
the region second table designates the beginning trol is zero, the entry fetched from the segment
and specifies the offset and length of the correspond- table designates the beginning of the corre-
ing region third table. sponding page table, and processing continues
as described in “Page-Table Lookup”, below.
When the table entry selected by means of the ASCE
is a region-second-table entry, or if a region-second- • When enhanced DAT applies and the STE-for-
table entry has been selected by means of the con- mat control is one, the entry fetched from the
tents of a region-first-table entry, the region-third- segment table contains the leftmost bits of the
index portion of the virtual address, in conjunction segment-frame absolute address. If the DAT-pro-
with the region-third-table origin contained in the tection bit, bit 54, is one either in any region-table
region-second-table entry, is used to select an entry entry used in the translation or in the segment-
from the region third table. Bits 22 and 23 of the vir- table entry, and the storage reference for which
tual address (which are bits 0 and 1 of the region the translation is being performed is a store, a
third index) are compared against the table offset and protection exception is recognized.
table length in the region-second-table entry. A
region-third-translation exception is recognized if the Page-Table Lookup
table offset is greater than bits 22 and 23 or if the When enhanced DAT does not apply, or when
table length is less than bits 22 and 23. The region- enhanced DAT applies but the STE-format control is
third-table-lookup process is otherwise the same as zero, the page-index portion of the virtual address, in
the region-second-table-lookup process, including conjunction with the page-table origin contained in
the checking of the table-type bits in the region-third- the segment-table entry, is used to select an entry
table entry, except that a region-third-translation from the page table.
exception is recognized if bit 58 is one in the region-
third-table entry. When no exceptions are recog- The 64-bit address of the page-table entry in real or
nized, the entry fetched from the region third table absolute storage is obtained by appending 11 zeros
designates the beginning and specifies the offset and to the right of the page-table origin and adding the
length of the corresponding segment table. page index, with three rightmost and 53 leftmost
e. For the R2 operand of the LOAD PAGE- A TLB combined region-and-segment-table entry is
TABLE-ENTRY ADDRESS instruction, the in the usable state when all of the following condi-
ASCE is that specified by the M4 field. tions are met:
When the enhanced-monitor facility is installed,
the home ASCE is also considered to be an 1. The current PSW specifies DAT on.
attaching ASCE when a monitor-event counting 2. The current PSW contains no errors that would
operation occurs, regardless of whether DAT is cause an early specification exception to be rec-
on. ognized.
Each of the remaining table entries in a translation 3. The TLB combined region-and-segment-table
path is attached when the next-higher-level entry is entry meets either of the following requirements:
attached and valid and would not cause a translation-
specification exception if used for translation and the a. The common-segment bit is one in the TLB
subject entry is within the table designated by the entry.
next-higher-level entry. “Within the table” means as b. The table-origin (TO) field in the TLB entry
determined by the origin, offset, and length fields in matches the table- or token-origin field in an
the next-higher-level entry. attaching address-space-control element.
A page-table entry is attached when it is within the A TLB combined region-and-segment-table entry
page table designated by either an attached and may be used for a particular instance of implicit
valid segment-table entry that would not cause a address translation only when the entry is in the
translation-specification exception if used for transla- usable state, either the common-segment bit is one
tion or a usable TLB combined region-and-segment- in the TLB entry or the table-origin (TO) field in the
Virtual Addresses
Instruction Addresses
Logical Addresses
• Address of storage key for INSERT STORAGE KEY EXTENDED, and RESET REFERENCE BIT EXTENDED
• Address of storage key for SET STORAGE KEY EXTENDED (when the enhanced-DAT facility is not installed, or when
the enhanced-DAT facility is installed but the multiple-block control is zero)
• Address of second operand for PERFORM FRAME MANAGEMENT FUNCTION when frame-size code is 0.
• Address of storage operand for LOAD USING REAL ADDRESS, STORE USING REAL ADDRESS, and TEST BLOCK
• The translated address generated by LOAD REAL ADDRESS and STORE REAL ADDRESS
• Page-frame real address in page-table entry
• Trace-entry address in control register 12
• ASN-first-table origin in control register 14
• ASN-second-table origin in ASN-first-table entry
• Authority-table origin in ASN-second-table entry, except when used by access-register translation
• Linkage-table origin in primary ASN-second-table entry
• Entry-table origin in linkage-table entry
• Dispatchable-unit-control-table origin in control register 2
• Primary-ASN-second-table-entry origin in control register 5
• Base-ASN-second-table-entry origin and subspace-ASN-second-table-entry origin in dispatchable-unit control table
• ASN-second-table-entry address in entry-table entry and access-list entry
• Address of the doubleword into which TEST PENDING INTERRUPTION stores when the second-operand address is
zero
• Addresses of PSWs, interruption codes, and the associated information used during interruption
• Addresses used for machine-check logout and save areas
• Address of STORE FACILITY LIST operand
• Region-first-table origin, region-second-table origin, region-third-table origin, or segment-table origin in control registers
1, 7, and 13, in access-register-specified address-space-control element, and in region-first-table entry, region-second-
table entry, or region-third-table entry
• Page-table origin in segment-table entry and in INVALIDATE PAGE TABLE ENTRY
• Address of segment-table entry or page-table entry provided by LOAD REAL ADDRESS
• Address of region-first-table entry, region-second-table entry, region-third-table entry, segment-table entry, or
page-table entry provided by LOAD PAGE-TABLE-ENTRY ADDRESS
• The dispatchable-unit or primary-space access-list origin and the authority-table origin (in the ASTE designated by the
ALE used) used by access-register translation
• Prefix value
• Channel-program address in ORB
• Data address in CCW
• IDAW address in a CCW specifying indirect data addressing
• MIDAW address in a CCW specifying modified indirect data addressing
• CCW address in a CCW specifying transfer in channel
• Data address in IDAW
• Data address in MIDAW
• Measurement-block origin specified by SET CHANNEL MONITOR
• Address limit specified by SET ADDRESS LIMIT
• Addresses used by the store-status-at-address SIGNAL PROCESSOR order
• Address of storage key for RESET REFERENCE BITS MULTIPLE
• Address of storage key for SET STORAGE KEY EXTENDED (when the enhanced-DAT facility is installed and the
multiple-block control is one)
• Address of second operand for PERFORM FRAME MANAGEMENT FUNCTION when frame-size code is 1.
• Failing-storage address stored in the doubleword at real location 248
• CCW address in SCSW
Programming Note: The PER ASCE identifica- 168-175 (A8-AF hex) . . . . . . . . . . . . . .Real Address
tion may be inspected to determine whether the
PER storage-alteration event used an AR-speci- Translation-Exception Identification for DAT
fied ASCE. See “PER ASCE Identification (AI)” Exceptions: During a program interruption due
on page 4-27 for further details. to an ASCE-type, region-first-translation, region-
second-translation, region-third-translation, seg-
162 (A2 hex) . . . . . . . . . . . . . . . . . . . . Real Address ment-translation, or page-translation exception,
bits 0-51 of the virtual address causing the
Operand Access Identification: When enhanced exception are stored in bit positions 0-51 of loca-
DAT does not apply, and a program interruption tions 168-175. This address is sometimes
due to a page-translation exception is recognized referred to as the translation-exception address.
by the MOVE PAGE instruction, the contents of
the R1 field of the instruction are stored in bit When the access-exception-fetch/store-indica-
positions 0-3 of location 162, and the contents of tion facility is installed, bits 52 and 53 of locations
the R2 field are stored in bit positions 4-7. If the 168-175 are set as described below.
page-translation exception was recognized dur-
ing the execution of an instruction other than Access-Exception Fetch/Store Indication: Bit
MOVE PAGE, or if an ASCE-type, region-first- positions 52-53 of locations 168-175 contain an
translation, region-second-translation, region- indication of whether the exception was due to a
third-translation, or segment-translation excep- fetch or a store operation, as follows:
tion was recognized, the contents of location 162 Bit Bit
are unpredictable. 52 53 Meaning
0 0 Could not determine whether the exception
When enhanced DAT applies, and a program
was due to a fetch or store
interruption due to a region-first-translation,
0 1 Exception was due to a store operation
region-second-translation, region-third-transla-
1 0 Exception was due to a fetch operation
tion, segment-translation, or page-translation
1 1 Reserved
exception is recognized by the MOVE PAGE
instruction, the contents of the R1 and R2 fields When the access-exception-fetch/store-indica-
are stored in location 162 as described above. If tion facility is not installed, bits 52 and 53 of loca-
any of the exceptions listed in the preceding sen- tions 168-175 are unpredictable.
tence was recognized during the execution of an
instruction other than MOVE PAGE, or if an The access-exception fetch/store indication is
ASCE-type exception was recognized, the con- stored for ASCE-type, page-translation, protec-
tents of location 162 are unpredictable. tion, region-first-translation, region-second-trans-
lation, region-third translation, and segment-
163 (A3 hex) . . . . . . . . . . . . . . . . . Absolute Address translation exceptions.
Store-Status Architectural-Mode Identification: For a storage-operand update reference, it is
During the execution of the store-status opera- unpredictable whether a fetch or store access is
tion, zeros are stored in bit positions 0-6 of loca- indicated. When multiple access-exception con-
tion 163, and a one is stored in bit position 7. A ditions exist — for one or more operands — the
zero stored in bit position 7 indicates the condition recognized is determined based on the
ESA/390 architectural mode, and a one indicates discussion of “Multiple Program-Interruption
the z/Architecture architectural mode. Conditions” on page 6-44.
163 (A3 hex) . . . . . . . . . . . . . . . . . . . . Real Address The enhanced suppression on protection facility
is a prerequisite for the access-exception-
Machine-Check Architectural-Mode Identifica-
fetch/store-indication facility.
tion: During a machine-check interruption, zeros
are stored in bit positions 0-6 of location 163, and Bits 54-60 are unpredictable.
a one is stored in bit position 7. A zero stored in
STFL Facility List: The STORE FACILITY LIST 264-267 (108-111 hex) . . . . . . . . . . . . .Real Address
instruction stores information at real locations
200-203. The information describes which facili- Enhanced-Monitor Counter-Array Size: The word
ties are provided by the configuration. The infor- at location 264 contains a 32-bit unsigned binary
mation stored is identical in format to the first 32 value that is referenced during the execution of
bits stored by the STORE FACILITY LIST the MONITOR CALL instruction when the
• The counter designated by the first-operand Supervisor-Call New PSW: The new PSW is
location is inaccessible. fetched from locations 448-463 during a supervi-
sor-call interruption.
272-279 (110-117 hex). . . . . . . . . . . . . Real Address
464-479 (1D0-1DF hex) . . . . . . . . . . . Real Address
Breaking-Event Address: If the PER-3 facility is
installed, then, during a program interruption, the Program New PSW: The new PSW is fetched
contents of the breaking-event-address register from locations 464-479 during a program inter-
are stored in locations 272-279. If the breaking- ruption.
event-address-recording facility is not installed, 480-495 (1E0-1EF hex) . . . . . . . . . . . . Real Address
this location remains unchanged.
Machine-Check New PSW: The new PSW is
288-303 (120-12F hex) . . . . . . . . . . . . Real Address fetched from locations 480-495 during a
Restart Old PSW: The current PSW is stored as machine-check interruption.
the old PSW at locations 288-303 during a 496-511 (1F0-1FF hex) . . . . . . . . . . . . Real Address
restart interruption.
Input/Output New PSW: The new PSW is fetched
304-319 (130-13F hex) . . . . . . . . . . . . Real Address from locations 496-511 during an I/O interrup-
External Old PSW: The current PSW is stored as tion.
the old PSW at locations 304-319 during an 4544-4607 (11C0-11FF hex) . . . . . . . . Real Address
external interruption.
Available for Programming: Locations 4544-4607
320-335 (140-14F hex) . . . . . . . . . . . . Real Address are available for use by programming.
Supervisor-Call Old PSW: The current PSW is
stored as the old PSW at locations 320-335 dur-
ing a supervisor-call interruption.
4608-4735 (1200-127F hex) . . . . . . . . Real Address 4900-4903 (1324-1327 hex) . . . . . Absolute Address
4736-4863 (1280-12FF hex) . . . . . Absolute Address 4900-4903 (1324-1327 hex) . . . . . . . . .Real Address
4736-4863 (1280-12FF hex) . . . . . . . . Real Address 4904-4911 (1328-132F hex) . . . . . Absolute Address
Machine-Check General-Register Save Area: Store-Status CPU-Timer Save Area: During the
During a machine-check interruption, the con- execution of the store-status operation, the con-
tents of the general registers are stored at loca- tents of the CPU timer are stored at locations
tions 4736-4863. 4904-4911.
4864-4879 (1300-130F hex) . . . . . Absolute Address 4904-4911 (1328-132F hex) . . . . . . . . .Real Address
Store-Status PSW Save Area: During the execu- Machine-Check CPU-Timer Save Area: During a
tion of the store-status operation, the contents of machine-check interruption, the contents of the
the current PSW are stored at locations CPU timer are stored at locations 4904-4911.
4864-4879.
4913-4919 (1331-1337 hex) . . . . . Absolute Address
4864-4879 (1300-130F hex) . . . . . . . . Real Address
Store-Status Clock-Comparator Save Area: Dur-
Fixed-Logout Area: Depending on the model, ing the execution of the store-status operation,
logout information may be stored at locations the contents of bit positions 0-55 of the clock
4864-4879 during a machine-check interruption. comparator are stored at locations 4913-4919.
When this store occurs, zeros are stored at loca-
4888-4891 (1318-131B hex) . . . . . Absolute Address tion 4912.
Store-Status Prefix Save Area: During the execu- 4913-4919 (1331-1337 hex) . . . . . . . . .Real Address
tion of the store-status operation, the contents of
the prefix register are stored at locations Machine-Check Clock-Comparator Save Area:
4888-4891. During a machine-check interruption, the con-
tents of bit positions 0-55 of the clock comparator
4892-4895 (131C-131F hex) . . . . . Absolute Address are stored at locations 4913-4919. When this
Store-Status Floating-Point-Control-Register store occurs, zeros are stored at location 4912.
Save Area: During the execution of the store-sta- 4928-4991 (1340-137F hex) . . . . . Absolute Address
tus operation, the contents of the floating-point
control register are stored at locations Store-Status Access-Register Save Area: During
4892-4895. the execution of the store-status operation, the
contents of the access registers are stored at
locations 4928-4991.
A change between these four CPU states can be • CPU reset is completed. However, when the
effected by use of the operator facilities or by accep- reset operation is performed as part of initial pro-
tance of certain SIGNAL PROCESSOR orders gram loading for this CPU, then the CPU is
addressed to that CPU. The states are not controlled placed in the load state and does not necessarily
or identified by bits in the PSW. The stopped, load, enter the stopped state.
and check-stop states are indicated to the operator
• An address comparison indicates equality and
by means of the manual indicator, load indicator, and
stopping on the match is specified.
check-stop indicator, respectively. These three indi-
cators are off when the CPU is in the operating state.
The execution of resets is described in “Resets” on
page 4-50, and address comparison is described in
The CPU timer is updated when the CPU is in the
“Address-Compare Controls” on page 12-1.
operating state or the load state. The TOD clock is
not affected by the state of any CPU.
If the CPU is in the stopped state when an INVALI-
DATE PAGE TABLE ENTRY instruction is executed
Stopped State on another CPU in the configuration, the clearing of
TLB entries is completed before the CPU leaves the
The CPU changes from the operating state to the stopped state.
stopped state by means of the stop function. The
stop function is performed when: Operating State
• The stop key is activated while the CPU is in the
The CPU changes from the stopped state to the
operating state.
operating state by means of the start function or
• The CPU accepts a stop or stop-and-store-status when a restart interruption (see “Restart Interruption”
order specified by a SIGNAL PROCESSOR on page 6-49) occurs.
instruction addressed to this CPU while it is in
the operating state. The start function is performed if the CPU is in the
stopped state and (1) the start key associated with
• The CPU has finished the execution of a unit of that CPU is activated or (2) that CPU accepts the
operation initiated by performing the start func- start order specified by a SIGNAL PROCESSOR
tion with the rate control set to the instruction- instruction addressed to that CPU. The effect of per-
step position. forming the start function is unpredictable when the
stopped state has been entered by means of a reset.
When the stop function is performed, the transition
from the operating to the stopped state occurs at the
1. Except for the relationship between execution A new or modified PSW becomes active (that is, the
time and real time, the execution of a program is information introduced into the current PSW
not affected by stopping the CPU. assumes control over the CPU) when the interruption
or the execution of an instruction that changes the
2. When, because of a machine malfunction, the PSW is completed. The interruption for PER associ-
CPU is unable to end the execution of an instruc- ated with an instruction that changes the PSW
tion, the stop function is ineffective, and a reset occurs under control of the PER mask that is effec-
function has to be invoked instead. A similar situ- tive at the beginning of the operation.
ation occurs when an unending string of interrup-
tions results from a PSW with a PSW-format Bits 0-7 of the PSW are collectively referred to as the
error of the type that is recognized early, or from system mask.
– No.
1
The action takes place only if the associated R field in the instruction is nonzero.
2
In the reduced-authority state, the action takes place only if the R1 field in the instruction is nonzero.
3
The action also takes place in the 64-bit addressing mode if the R1 field in the instruction is zero.
4
PROGRAM RETURN does not change the PER mask.
5
PROGRAM TRANSFER does not change the problem-state bit from one to zero.
BAM The basic-addressing-mode bit is saved or set in the 24-bit or 31-bit addressing mode.
ANDs The logical AND of the immediate field in the instruction and the current system mask replaces the current system mask.
ORs The logical OR of the immediate field in the instruction and the current system mask replaces the current system mask.
PKC When the PSW-key-control bit, bit 131 of the entry-table entry, is zero, the PSW key remains unchanged. When the PSW-key-control bit is
one, the PSW key is set with the entry key, bits 136-139 of the entry-table entry.
24AM The condition code and program mask are saved in the 24-bit addressing mode.
31AM The basic-addressing-mode bit is saved in the 31-bit addressing mode.
Figure 4-1. Operations on PSW Fields.
I E Prog. E PSW Key: Bits 8-11 form the access key for stor-
0R000T Key 0 MW P AS CC 0000000
OX Mask A
age references by the CPU. If the reference is sub-
0 1 2 5 6 7 8 12 13 14 15 16 18 20 24 31
ject to key-controlled protection, the PSW key is
B matched with a storage key when information is
0000000000000000000000000000000
A stored or when information is fetched from a location
32 33 63 that is protected against fetching. However, for one of
Instruction Address the operands of each of MOVE TO PRIMARY, MOVE
64 95
TO SECONDARY, MOVE WITH KEY, MOVE WITH
SOURCE KEY, and MOVE WITH DESTINATION
Instruction Address (Continued) KEY, an access key specified as an operand is used
96 127 instead of the PSW key.
Figure 4-2. PSW Format
Machine-Check Mask (M): Bit 13 controls whether
the CPU is enabled for interruption by machine-check
The following is a summary of the functions of the
conditions. When the bit is zero, a machine-check
PSW fields. (See Figure 4-2.)
interruption cannot occur. When the bit is one,
machine-check interruptions due to system damage
PER Mask (R): Bit 1 controls whether the CPU is
and instruction-processing damage are permitted,
enabled for interruptions associated with program-
but interruptions due to other machine-check-sub-
event recording (PER). When the bit is zero, no PER
class conditions are subject to the subclass-mask
event can cause an interruption. When the bit is one,
bits in control register 14.
interruptions are permitted, subject to the PER-
event-mask bits in control register 9.
Wait State (W): When bit 14 is one, the CPU is
waiting; that is, no instructions are processed by the
DAT Mode (T): Bit 5 controls whether implicit
CPU, but interruptions may take place. When bit 14 is
dynamic address translation of logical and instruction
zero, instruction fetching and execution occur in the
addresses used to access storage takes place.
normal manner. The wait indicator is on when the bit
When the bit is zero, DAT is off, and logical and
is one.
instruction addresses are treated as real addresses.
When the bit is one, DAT is on, and the dynamic-
Problem State (P): When bit 15 is one, the CPU is
address-translation mechanism is invoked.
in the problem state. When bit 15 is zero, the CPU is
in the supervisor state. In the supervisor state, all
I/O Mask (IO): Bit 6 controls whether the CPU is
instructions are valid. In the problem state, only those
enabled for I/O interruptions. When the bit is zero, an
instructions are valid that provide meaningful infor-
I/O interruption cannot occur. When the bit is one, I/O
mation to the problem program and that cannot affect
interruptions are subject to the I/O-interruption sub-
system integrity; such instructions are called unprivi-
class-mask bits in control register 6. When an I/O-
leged instructions. The instructions that are never
interruption subclass-mask bit is zero, an I/O inter-
valid in the problem state are called privileged
ruption for that I/O-interruption subclass cannot
instructions. When a CPU in the problem state
occur; when the I/O-interruption subclass-mask bit is
attempts to execute a privileged instruction, a privi-
one, an I/O interruption for that I/O-interruption sub-
leged-operation exception is recognized. Another
class can occur.
group of instructions, called semiprivileged instruc-
tions, are executed by a CPU in the problem state
External Mask (EX): Bit 7 controls whether the
only if specific authority tests are met; otherwise, a
CPU is enabled for interruption by conditions
Extended Addressing Mode (EA): Bit 31 controls LOAD PSW has an eight-byte second operand. The
the size of effective addresses and effective-address operand is treated as an ESA/390 PSW, except that
generation in conjunction with bit 32, the basic- bit 31 (the z/Architecture extended-addressing-mode
addressing-mode bit. When bit 31 is zero, the bit) may be one.
addressing mode is controlled by bit 32. When bits
31 and 32 are both one, 64-bit addressing is speci- I E Prog. E
0R000T Key 1 MW P AS CC 0000000
fied. OX Mask A
0 1 2 5 6 7 8 12 13 14 15 16 18 20 24 31
The fields not listed are unassigned. The initial value for all unlisted control-register bit positions is zero.
1
This bit is not used but is initialized to one for consistency with the System/370 definition.
2
The address-space-control element (ASCE) in the control register has one of three formats, depending on bit 58
of the register, the real-space control, and bits 60 and 61 of the register, the designation-type control. When bit
58 is zero, the ASCE is a region-table designation if bits 60 and 61 are 11, 10, or 01 binary, or it is a segment-
table designation if bits 60 and 61 are 00 binary. When bit 58 is one, the ASCE is a real-space designation. Bits
0-51 are the region-table origin, the segment-table origin or the real-space token origin, depending on whether
the ASCE is a region-table designation, a segment-table designation, or a real-space designation, respectively.
3
Bits 60-63 are assigned when the ASCE in the control register is a region-table designation or a segment-table
designation.
4
See The Set-Program-Parameter and CPU-Measurement Facilities (SA23-2260) for details on these bits.
Mode tracing records a switch from a basic (24-bit or The trace entries produced by implicit tracing are
31-bit) addressing mode to the extended (64-bit) summarized in Figure 4-5.
addressing mode or from the extended mode to a
basic mode. When explicit tracing is on, execution of TRACE
(TRACE or TRACG) causes an entry to be made in
When mode tracing is on, a mode-switch trace entry the trace table. The entry for TRACE (TRACE)
is made in the trace table for each execution of the includes bits 16-63 from the TOD clock, the second
following instructions if the execution changes PSW operand of the TRACE instruction, and bits 32-63 of
bit 31: a range of general registers. The entry for TRACE
(TRACG) is the same except that it includes bits 0-79
• BRANCH AND SAVE AND SET MODE from the TOD clock and bits 0-63 of a range of gen-
• BRANCH AND SET MODE eral registers.
• PROGRAM CALL
– None.
-20 The case when PROGRAM CALL uses a 20-bit PC number.
-32 The case when PROGRAM CALL uses a 32-bit PC number.
-b The case when PROGRAM RETURN unstacks a branch state entry.
-pc The case when PROGRAM RETURN unstacks a program-call state entry.
| OR.
& AND.
B Branch trace entry. Made only if the branch is taken and a mode-switching-branch trace
entry is not made.
MS Mode-switch trace entry. Made only if PSW bit 31 is changed.
MSB Mode-switching-branch trace entry. Made only if PSW bit 31 is changed (which can occur
only if the branch is taken.
Figure 4-5. Summary of Implicit Tracing
Control-Register Allocation on or off. If the bit is zero, explicit tracing is off, which
causes the TRACE instruction to be executed as a
no-operation; if the bit is one, the execution of the
The information to control tracing is contained in con-
TRACE instruction creates an entry in the trace table,
trol register 12 and has the following format:
except that no entry is made when bit 0 of the second
operand of the TRACE instruction is one.
BM Trace-Entry Address
0 1 2 31
The entries are shown in Figure 4-6. In that figure, Figure 4-7 on page 4-19 lists the trace entries in
each entry is labeled with “Fn,” indicating a format ascending order of values in bit fields that identify the
number, to allow references to each format within a entries.
trace-entry type. Also, “Branch,” referring to the mne-
F2 Branch (Branch, RP, or TRAP2/4 when Resulting Mode Is 31-Bit, or when Resulting PSW Bit 31 is One (See
Note) and Bits 0-32 of Branch Address Are All Zeros)
1 Bits 33-63 of Branch Address
0 1 31
F3 Branch (Branch, RP, or TRAP2/4 when Resulting PSW Bit 31 Is One (See Note) and Bits 0-32 of Branch Address
Are Not All Zeros)
010100101100 All Zeros Bits 0-31 of Branch Address
0 8 12 32 63
F1 BRANCH IN SUBSPACE GROUP (if ASN Is Tracing on, in 24-Bit or 31-Bit Mode)
01000001P Bits 9-31 of ALET A Bits 33-63 of Branch Address
0 8 9 32 33 63
F1 Mode Switch (BASSM, BSM, PC, PR, RP, or SAM64 from 24-Bit or 31-Bit Mode when Resulting PSW Bit 31 is
One (See Note))
010100010011 All Zeros A Updated Instruction Address
0 8 12 32 33 63
F3 Mode Switch (BASSM, BSM, PC, PR, or RP from 64-Bit Mode to 24-Bit or 31-Bit Mode when Bits 0-31 of Updated
Instruction Address Are Not All Zeros)
010100100110 All Zeros Bits 0-31 of Updated Instruction Address
0 8 12 32 63
F2 Mode-Switching Branch (BASSM or RP from 24-Bit or 31-Bit Mode when Resulting PSW Bit 31 Is One (See Note)
and Bits 0-31 of Branch Address Are All Zeros)
010100011011 All Zeros Bits 32-63 of Branch Address
0 8 12 32 63
F3 Mode-Switching Branch (BASSM or RP from 24-Bit or 31-Bit Mode when Resulting PSW Bit 31 Is One (See Note)
and Bits 0-31 of Branch Address Are Not All Zeros)
010100101111 All Zeros Bits 0-31 of Branch Address
0 8 12 32 63
F1 PROGRAM CALL (in 24-Bit or 31-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Not Enabled)
PSW
00100001 PC Number A Bits 33-62 of Return Address P
Key
0 8 12 32 33 63
F2 PROGRAM CALL (in 64-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Not Enabled)
PSW
00100010 PC Number Bits 0-31 of Return Address
Key
0 8 12 32 63
F4 PROGRAM CALL (in 64-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Enabled and 20-Bit
PC Number Is Used)
PSW
00100010 0 Bits 1-19 of 20-Bit PC Number Bits 0-31 of Return Address
Key
0 8 12 13 32 63
F5 PROGRAM CALL (in 24-Bit or 31-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Enabled and
32-Bit PC Number is Used)
PSW
00100010 100E All Zeros A Bits 33-62 of Return Address P
Key
0 8 12 15 16 32 33 63
32-Bit PC Number
64 95
F6 PROGRAM CALL (in 64-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Enabled, 32-Bit PC
Number Is Used, and Bits 0-31 of Return Address Are All Zeros)
PSW
00100010 101E All Zeros Bits 32-62 of Return Address P
Key
0 8 12 15 16 32 63
32-Bit PC Number
64 95
F7 PROGRAM CALL (in 64-Bit Mode, Regardless of Resulting Mode, if ASN-and-LX Reuse Is Enabled, 32-Bit PC
Number Is Used, and Bits 0-31 of Return Address Are Not All Zeros)
PSW
00100011 111E All Zeros Bits 0-31 of Return Address
Key
0 8 12 15 16 32 63
F2 PROGRAM RETURN (in 64-Bit Mode when Bits 0-31 of Updated Instruction Address Are All Zeros and Resulting
Mode Is 24-Bit or 31-Bit)
PSW
00110010 0010 New PASN A Bits 33-62 of Return Address P
Key
0 8 12 16 32 33 63
F3 PROGRAM RETURN (in 64-Bit Mode when Bits 0-31 of Updated Instruction Address Are Not All Zeros and
Resulting Mode Is 24-Bit or 31-Bit)
PSW
00110011 0011 New PASN A Bits 33-62 of Return Address P
Key
0 8 12 16 32 33 63
F4 PROGRAM RETURN (in 24-Bit or 31-Bit Mode when Resulting PSW Bit 31 Is One (See Note) and Bits 0-31 of
Return Address Are All Zeros)
PSW
00110010 1000 New PASN Bits 32-62 of Return Address P
Key
0 8 12 16 32 63
F5 PROGRAM RETURN (in 64-Bit Mode when Bits 0-31 of Updated Instruction Address Are All Zeros, Resulting
PSW Bit 31 Is One (See Note), and Bits 0-31 of Return Address Are All Zeros)
PSW
00110010 1010 New PASN Bits 32-62 of Return Address P
Key
0 8 12 16 32 63
F7 PROGRAM RETURN (in 24-Bit or 31-Bit Mode when Resulting PSW Bit 31 Is One (See Note) and Bits 0-31 of
Return Address Are Not All Zeros)
PSW
00110011 1100 New PASN Bits 0-31 of Return Address
Key
0 8 12 16 32 63
F8 PROGRAM RETURN (in 64-Bit Mode when Bits 0-31 of Updated Instruction Address Are All Zeros, Resulting
PSW Bit 31 Is One (See Note), and Bits 0-31 of Return Address Are Not All Zeros)
PSW
00110011 1110 New PASN Bits 0-31 of Return Address
Key
0 8 12 16 32 63
F9 PROGRAM RETURN (in 64-Bit Mode when Bits 0-31 of Updated Instruction Address Are Not All Zeros, Resulting
PSW Bit 31 Is One (See Note), and Bits 0-31 of Return Address Are Not All Zeros)
PSW
00110100 1111 New PASN Bits 0-31 of Return Address
Key
0 8 12 16 32 63
F2 PROGRAM TRANSFER (WITH INSTANCE if N Is One) (in 64-Bit Mode when Bits 0-31 of R2 Are All Zeros)
PSW
00110001 100N New PASN Bits 32-63 of R2 before
Key
0 8 12 15 16 32 63
F3 PROGRAM TRANSFER (WITH INSTANCE if N Is One) (in 64-Bit Mode when Bits 0-31 of R2 Are Not All Zeros)
PSW
00110010 110N New PASN Bits 0-31 of R2 before
Key
0 8 12 15 16 32 63
F1 TRACE (TRACE)
0111 N 00000000 TOD-Clock Bits 16-63
0 4 8 16 63
/
TRACE Operand (R1) - (R3)
/
64 96 95 + 32(N+1)
F2 TRACE (TRACG)
0111 N 10000000 TOD-Clock Bits 0-47
0 4 8 16 63
/
(R1) - (R3)
/
128 127 + 64(N+1)
Note: The terminology “when Resulting PSW Bit 31 Is One” is used instead of “when Resulting Mode Is 64-Bit” because, if the resulting PSW
bit 32 is zero, an early specification exception will be recognized. PROGRAM RETURN can set PSW bit 31 to one and bit 32 to zero.
Figure 4-6. Trace Entries (Part 6 of 6)
Bit position 64 of a PROGRAM RETURN trace entry PC Number: Bit positions 12-31 of a PROGRAM
made in the 24-bit or 31-bit addressing mode when CALL trace entry of format 1-4 contain the value of
the return address occupies only one word in the the rightmost 20 bits of the second-operand address.
entry, (a format-1 or format-4 entry), contains the Bit positions 64-95 of a format-5 or format-6 PRO-
value of PSW bit 32 that existed before the PRO- GRAM CALL trace entry, or bit positions 96-127 of a
GRAM RETURN operation. When the return address format-7 entry, contain the value of the rightmost 32
occupies two words (a format-7 entry), bit position 96 bits of the second-operand address.
contains that value of PSW bit 32.
Return Address: Bit positions 33-62 of a PRO-
Updated Instruction Address: Bit positions 33-63 GRAM CALL trace entry made on execution in the
of a mode-switch trace entry that indicates a switch 24-bit or 31-bit addressing mode (a format-1, format-
from PSW bit 31 being off to the bit being on (a for- 3, or format-5 entry) contain bits 33-62 of the
mat-1 entry) contains bits 33-63 of the updated updated instruction address in the PSW (bits 97-126
instruction address in the PSW (bits 97-127 of the of the PSW) before that address is replaced from the
PSW) before that address is replaced, if it is entry-table entry; or, when the execution is in the
replaced, by the mode-switch operation. Bit positions 64-bit addressing mode, bit positions 32-94 of the
32-63 of a mode-switch trace entry (format 2) that trace entry (format 2, 4, or 7) contain bits 0-62 of that
indicates a switch from the 64-bit addressing mode to updated instruction address (bits 64-126 of the
the 24-bit or 31-bit addressing mode contains bits PSW), or, when bits 0-31 of the address are all zeros,
32-63 of the updated instruction address in the PSW bit positions 32-62 of the trace entry (format 6) con-
(bits 96-127 of the PSW) before that address is tain bits 32-62 of the address.
replaced, if it is replaced, by the mode-switch opera-
tion, if bits 0-31 of the updated instruction address Extended-Addressing-Mode Bit (E): Bit position
are zeros; or bit positions 32-95 of the trace entry 15 of a PROGRAM CALL trace entry made using a
(format 3) contain bits 0-63 of that updated instruc- 32-bit PC number (a format-5, format-6, or format-7
tion address (bits 64-127 of the PSW) if bits 0-31 of entry) contains the extended-addressing-mode bit
the address are not all zeros. that replaces bit 31 of the PSW.
The following description of a PROGRAM RETURN Bit positions 33-62 of a PROGRAM RETURN trace
trace entry applies when the return address in the entry made when the resulting addressing mode is
entry occupies only one word in the entry. Bit posi- the 24-bit or 31-bit mode (a format-1, format-2, or for-
tions 65-95 of the trace entry made on execution in mat-3 entry) contain bits 33-62 of the instruction
Bits 32-63 of R2 before: Bit positions 32-63 of a TRACE Operand: When the store-clock-fast facility
PROGRAM TRANSFER trace entry made on execu- is not installed, or when the TRACE TOD-clock con-
tion in the 24-bit or 31-bit addressing mode (a format- trol in bit 32 of control register 0 is zero, bit positions
1 entry) contain bits 32-63 of the general register 64-95 of the trace entry for TRACE (TRACE) and bit
designated by the R2 field of the instruction. (Bits 32 positions 96-127 of the trace entry for TRACE
and 33-62 of that register replace bits 32 and 97-126, (TRACG) contain a copy of the 32 bits of the second
respectively, of the PSW. Bit 63 of the register operand of the TRACE instruction for which the entry
replaces the problem-state bit in the PSW.) When is made.
PROGRAM TRANSFER or PROGRAM TRANSFER
WITH INSTANCE is executed in the 64-bit address- When the store-clock-fast facility is installed and the
ing mode, bit positions 32-63 of the trace entry (for- TRACE TOD-clock control in bit 32 of control register
mat 2) contain bits 32-63 of the R2 general register if 0 is one, the trace-operand field in the trace entry is
bits 0-31 of the register are zeros, or bit positions formed as follows.
32-95 of the trace entry (format 3) contain bits 0-63
3. Enabling the CPU for PER instruction-fetching An interruption for an instruction-fetching nullification
nullification may be used to determine the state event occurs before the instruction responsible for
of the CPU before execution of any instruction the event is executed, and the operation is nullified.
within the storage area designated by control
registers 10 and 11. The instruction nullified When the CPU is disabled for a particular PER event
could be the first instruction after a successful at the time it occurs, either by the PER mask in the
branch, after LOAD PSW, or after LOAD PSW PSW or by the masks in control register 9, the event
EXTENDED; or it could be the target of an exe- is not recognized.
cute-type instruction or the leftmost instruction in
the storage area and accessed in the process of A change to the PER mask in the PSW or to the PER
sequential execution. After recording the desired control fields in control registers 9, 10, and 11 affects
information, in order to allow the CPU to execute PER starting with the execution of the immediately
this instruction, either the CPU must be disabled following instruction. Thus, if, as a result of the
for instruction-fetching nullification or control reg- change, an instruction-fetching nullification event
isters 10 and 11 must be changed to designate a applies to the immediately following instruction, exe-
different storage area. This can be contrasted to cution of that instruction will be nullified and the
enabling for PER successful branching within the instruction-fetching nullification event reported.
same storage area, which causes a PER event to
be reported only in the first case mentioned A change to the storage-alteration-event bit in an
above, but does not require special action to con- address-space-control element in control register 1,
tinue. 7, or 13 also affects PER starting with the execution
of the immediately following instruction. A change to
the storage-alteration-event bit in an address-space-
Operation control element that may be obtained, during access-
register translation, from an ASN-second-table entry
PER is under control of bit 1 of the PSW, the PER in either main storage or the ALB does not necessar-
mask. When the PER mask and a particular PER- ily have an immediate, if any, effect on PER. How-
event mask bit are all ones, the CPU is enabled for ever, PER is affected immediately after either
the corresponding type of event; otherwise, it is dis- PURGE ALB or COMPARE AND SWAP AND
abled. However, the CPU is enabled for the store- PURGE that purges the ALB is executed.
PER basic events may be recognized in a trial execu- Zeros are stored in bit positions 3 and 6 of locations
tion of an instruction, and subsequently the instruc- 150-151. When PER-3 is not installed, zero is stored
tion, DAT-table entries, and operands may be in bit position 7.
refetched for the actual execution. If any refetched
field was modified by another CPU or by a channel Addressing-and-Translation-Mode Identification
program between the trial execution and the actual (ATMID): During a program interruption when a
execution, it is unpredictable whether the PER events PER event is indicated, bits 31, 32, 5, 16, and 17 of
indicated are for the trial or the actual execution. the PSW at the beginning of the execution of the
instruction that caused the event may be stored in bit
For special-purpose instructions that are not positions 8 and 10-13, respectively, of real locations
described in this publication, the operation of PER 150-151. If bits 31, 32, 5, 16, and 17 are stored, then
may not be exactly as described in this section. a one bit is stored in bit position 9 of locations
150-151. If bits 31, 32, 5, 16, and 17 are not stored,
Identification of Cause then zero bits are stored in bit positions 8-13 of loca-
tions 150-151.
A program interruption for PER sets bit 8 of the inter-
ruption code to one and places identifying informa- Bits 8-13 of real locations 150-151 are named the
tion in real storage locations 150-159.When the PER addressing-and-translation-mode identification
event is a storage-alteration event, information is also (ATMID). Bit 9 is named the ATMID-validity bit. When
stored in location 161. Additional information is pro- bit 9 is zero, it indicates that an invalid ATMID (all
vided by means of the instruction address in the pro- zeros) was stored.
gram old PSW and the ILC.
The meanings of the bits of a valid ATMID are as fol-
Locations 150-151: lows:
PER Code ATMID AI
Bit Meaning
0 8 14 15
8 PSW bit 31
9 ATMID-validity bit
PER Code: The occurrence of PER events is indi- 10 PSW bit 32
cated by ones in bit positions 0-2, 4 and 7. The bit 11 PSW bit 5
position in the PER code for a particular type of event 12 PSW bit 16
is as follows: 13 PSW bit 17
Bit PER Event A valid ATMID is necessarily stored only if the PER
0 Successful-branching event was caused by one of the following instruc-
1 Instruction-fetching tions:
2 Storage-alteration
4 Store-using-real-address • BRANCH AND SAVE AND SET MODE
7 Instruction-fetching nullification (PER-3) (BASSM)
• BRANCH AND SET AUTHORITY (BSA)
A one in bit position 2 and a zero in bit position 4 of • BRANCH AND SET MODE (BSM)
location 150 indicate a storage-alteration event, while • BRANCH IN SUBSPACE GROUP (BSG)
ones in bit positions 2 and 4 indicate a store-using- • LOAD PSW (LPSW)
real-address event. When a program interruption • LOAD PSW EXTENDED (LPSWE)
occurs, more than one type of PER basic event can • PROGRAM CALL (PC)
be concurrently indicated. Additionally, if another pro- • PROGRAM RETURN (PR)
gram-interruption condition exists, the interruption • PROGRAM TRANSFER (PT)
code for the program interruption may indicate both • PROGRAM TRANSFER WITH INSTANCE (PTI)
the PER basic events and the other condition. • RESUME PROGRAM (RP)
The contents of storage are considered to have been A PER storage-alteration event is indicated by setting
altered whenever the CPU executes an instruction bit 2 of the PER code to one and bit 4 of the PER
that causes all or part of an operand to be stored code to zero.
within the designated storage area. Alteration is con-
sidered to take place whenever storing is considered Store Using Real Address
to take place for purposes of indicating protection A store-using-real-address event occurs whenever
exceptions, except that recognition does not occur for the STORE USING REAL ADDRESS instruction is
the storing of data by a channel program. (See “Rec- executed.
ognition of Access Exceptions” on page 6-40.) Stor-
ing constitutes alteration for PER purposes even if There is no relationship between the store-using-
the value stored is the same as the original value. real-address event and the designated storage area.
Implied locations that are referred to by the CPU, A store-using-real-address event causes a PER
either in the process of performing an interruption or store-using-real-address event to be recognized if
in the formation of a trace entry, are not monitored. bits 34 and 36 of the PER-event mask are ones and
Such locations include PSW and interruption-code the PER mask in the PSW is one.
locations and the trace entry designated by control
register 12. These locations, however, are monitored A PER store-using-real-address event is indicated by
when information is stored there explicitly by an setting bits 2 and 4 of the PER code to one.
instruction. Similarly, monitoring does not apply to
the storing of data by a channel program. Implied
locations in the linkage stack, which are stored in by
Figure 4-9. Example of Instruction-Fetching PER Basic Event and Early PSW-Format Error or Odd Instruction Address
The TOD clock nominally is incremented by adding a Stopped State: The clock enters the stopped state
one in bit position 51 every microsecond. In models when SET CLOCK is executed and the execution
having a higher or lower resolution, a different bit results in the clock being set. This occurs when SET
position is incremented at such a frequency that the CLOCK is executed without encountering any excep-
rate of advancing the clock is the same as if a one tions and either any manual TOD-clock control in the
were added in bit position 51 every microsecond. configuration is set to the enable-set position or the
The resolution of the TOD clock is such that the TOD-clock-control-override control, bit 42 of control
incrementing rate is comparable to the instruction- register 14, is one. The clock can be placed in the
execution rate of the model. stopped state from the set, not-set, and error states.
The clock is not incremented while in the stopped
When incrementing of the clock causes a carry to be state.
propagated out of bit position 0, the carry is ignored,
and counting continues from zero. The program is When the clock is in the stopped state, execution of
not alerted, and no interruption condition is gener- STORE CLOCK, STORE CLOCK EXTENDED, or
ated as a result of the overflow. STORE CLOCK FAST causes condition code 3 to be
set and the value of the stopped clock to be stored.
The operation of the clock is not affected by any nor-
mal activity or event in the system. Incrementing of Set State: The clock enters the set state only from
the clock does not depend on whether the wait-state the stopped state. The change of state is under con-
bit of the PSW is one or whether the CPU is in the trol of the TOD-clock-sync-control bit, bit 34 of control
operating, load, stopped, or check-stop state. Its register 0, of the CPU which most recently caused
operation is not affected by CPU, initial-CPU, or clear the clock to enter the stopped state. If the bit is zero,
the wait state when the logical TOD clock is changed, TOD Clock (continued) Programmable Field
the CPU may or may not recognize interruption con- 96 112 127
ditions for the clock comparator until after it leaves
the wait state and one of the aforementioned instruc-
tions is executed. The CPU timer and CPU-timer At some time in the future, STORE CLOCK
interruptions are not affected by PTFF-STO and EXTENDED on new models will store a leftmost
PTFF-ATO. extension of the TOD clock in byte position 0 of its
storage operand; see programming note 14 on
The results of channel-subsystem-monitoring-facility page 4-43.
operations may be unpredictable as a result of
changes to the TOD clock. Two executions of STORE CLOCK or STORE
CLOCK EXTENDED, possibly on different CPUs in
the same configuration, always store different values
Setting and Inspecting the Clock of the clock if the clock is running.
The clock can be set to a specified value by execu-
tion of SET CLOCK if the manual TOD-clock control The values stored for a running clock by STORE
of any CPU in the configuration is in the enable-set CLOCK or STORE CLOCK EXTENDED always cor-
position or the TOD-clock-control-override control, bit rectly imply the sequence of execution of these
42 of control register 14, is one. SET CLOCK sets instructions by one or more CPUs for all cases where
bits of the clock with the contents of corresponding the sequence can be discovered by the program. To
bit positions of a doubleword operand in storage. ensure that unique values are obtained when the
value of a running clock is stored, nonzero values
Setting the clock replaces the values in all bit posi- may be stored in positions to the right of the right-
tions from bit position 0 through the rightmost posi- most incremented bit position. When the value of a
tion that is incremented when the clock is running. running clock is stored by STORE CLOCK
However, on some models, the rightmost bits starting EXTENDED, the value in bit positions 64-103 of the
at or to the right of bit 52 of the specified value are clock (bit positions 72-111 of the storage operand) is
ignored, and zeros are placed in the corresponding always nonzero; this ensures that values stored by
positions of the clock. Zeros are also placed in posi- STORE CLOCK EXTENDED are always unique
tions to the right of bit position 63 of the clock. when compared with values stored by STORE
CLOCK or STORE CLOCK FAST, extended on the
The TOD clock can be inspected by executing right with zeros.
STORE CLOCK or STORE CLOCK FAST, which
causes bits 0-63 of the clock to be stored in an eight- For the purpose of establishing uniqueness and
byte operand in storage, or by executing STORE sequence of occurrence of the results of STORE
CLOCK EXTENDED, which causes bits 0-103 of the CLOCK and STORE CLOCK EXTENDED, the 64-bit
clock to be stored in bytes 1-13 of a 16-byte operand value provided by STORE CLOCK may be consid-
in storage. STORE CLOCK EXTENDED stores zeros ered to be extended to 104 bits by appending 40
in the leftmost byte, byte 0, of its storage operand, zeros on the right, with the STORE CLOCK value
and it obtains the TOD programmable field from bit and STORE CLOCK EXTENDED bits 8-111 then
positions 16-31 of the TOD programmable register both being treated as 104-bit unsigned binary inte-
and stores it in byte positions 14 and 15 of the stor- gers.
• If the configuration is in STP timing mode, the 1. ETR TOD-clock synchronization provides for
configuration is synchronized with coordinated synchronizing and checking only bits 32 through
server time (CST). the rightmost incremented bit of the TOD clock.
Bits 0-31 of the TOD clock may be different from
A configuration that is in the local-timing or uninitial- those of the ETR.
ized-timing mode is never in the synchronized state.
2. If the configuration is part of an ETR network,
Unsynchronized State: When a configuration is in SET CLOCK must place all zeros in bit positions
the unsynchronized timing state, the TOD clock is not 32 through the rightmost incremented bit position
in synchronization with the timing network reference of the TOD clock; otherwise, an external-damage
time as defined below: machine-check-interruption condition will be rec-
ognized.
• If the configuration is in ETR-timing mode, the
configuration has lost synchronization with the
ETR.
TOD-Clock Steering
• If the configuration is in STP timing mode, the TOD-clock steering provides a means to change the
configuration has lost or has not been able to apparent stepping rate of the TOD clock without
attain synchronization with coordinated server changing the physical hardware oscillator which
time (CST). The configuration is out of synchroni- steps the physical clock. This is accomplished by
zation with CST when the TOD clock differs from means of a TOD-offset register which is added to the
CST by an amount that exceeds a model depen- physical clock to produce a logical-TOD-clock value.
dent STP-sync-check-threshold value.
The TOD-offset register nominally consists of bits
Stopped State: When a configuration is in the 0-95, which are updated every microsecond by add-
stopped state, the TOD clock is either in the stopped ing a 32-bit signed value, called the current total
state or TOD-clock recovery is in progress. After steering rate (r), aligned with bits 64-95 of the TOD-
TOD-clock recovery completes, the TOD clock enters offset register. A carry, if any, out of bit position 0 of
either the synchronized or unsynchronized state. the TOD-offset register is ignored in this addition. In
models having a higher or lower resolution, the addi-
tion is performed at such a frequency, and with r
appropriately aligned, that the rate of changing the
TOD-clock steering includes the semiprivileged TOD-clock steering includes four control functions
instruction PERFORM TIMING FACILITY FUNC- which can be issued by the timing-facility-control pro-
TION (PTFF), which is in the “E” format, provides a gram: set fine-steering rate, set gross-steering rate,
7-bit function code in general register 0 and a param- adjust TOD offset, and set TOD offset. The set-fine-
eter block address in general register 1. steering-rate and set-gross-steering-rate functions
operate on the fine-steering-rate and gross-steering-
TOD-clock steering permits the timing-facility-control rate registers, respectively, and can be issued with-
program to adjust the apparent stepping rate of the out causing any discontinuity in the logical TOD
TOD clock. The stepping rate can be adjusted !122 clock. These functions are available only to the tim-
parts per million (ppm) with precision to one part in ing-facility-control program.
244 (about 4.9 nanoseconds per day). The stepping
rate can be changed in a nondisruptive manner; that When operating at the basic-machine level, the set-
is, application programs may be running in the con- TOD-offset and adjust-TOD-offset functions permit
figuration when the change is made, with an almost the logical TOD clock to be set to any arbitrary value,
imperceptible effect on the programs. but with a discontinuity. These functions are intended
to be used by the timing-facility-control program only
The presence of the TOD-clock steering facility is for initialization, testing, and in extreme error situa-
indicated by bit 28 stored by the STORE FACILITIES tions.
LIST (STFL) instruction. STFL bit 28, when one indi-
cates that the TOD-clock steering facility is installed. When operating at the logical-partition and virtual-
The instruction PERFORM TIMING FACILITY machine levels, the set-TOD-offset function, when
FUNCTION (PTFF) is installed only in the z/Architec- issued in the supervisor state, may be emulated by
ture architectural mode. Steering, however, is not the hypervisor.
turned off if the machine is set back to ESA/390
mode. TOD-clock steering also includes several query func-
tions which may be used, not only by the timing-facil-
The total steering rate is made up of two compo- ity-control program, but also by the problem program
nents, a fine-steering rate and a gross-steering rate. to determine the quality of the TOD clock.
The fine-steering rate is used to correct that inaccu- TOD-Clock Steering Overview
racy in the local oscillator which is stable over a rela-
tively long period of time. The value will normally be Figure 4-10 on page 4-46 shows an overview of the
less than the specified tolerance of the local oscillator TOD-clock operation, including steering. TOD-clock
(typically ! 2.0 ppm), changes will occur infrequently steering is accomplished by means of three values: a
(on the order of once per day to once per week), and start time, a base offset, and a steering rate. These
changes will be small (typically less than ! 0.2 ppm). three values are used to compute a TOD offset which
is added to the physical clock to form the basic-
The gross-steering rate is used as a dynamic correc- machine TOD clock. The start time and base offset
tion for all other effects, the most predominate being
-
{64}
CTS Rate (r)
{32} {32}
abs *
Zeros abs(r)
{12} {96}
{64}
+ -
{64}
+
{64}
{64}
+
{64}
are 64-bit unsigned binary integers and are consid- TOD offset (d) and basic-machine TOD clock (Tb)
ered to be aligned with bits 0-63 of the TOD clock. from the physical clock (Tr), current start time (s), cur-
The steering rate is a 32-bit signed binary fixed-point rent base offset (b), and current total steering rate (r):
-44
value and considered to be scaled by a factor of 2 .
-44
The following formulae show the derivation of the d = b + (Tr - s) * r * 2
Current Steering Rates (f,g,r): When the machine Programming Note: Although the architecture
is operating in the old episode, the current fine-steer- defines the TOD offset as a 64-bit unsigned binary
ing rate (f) and current gross-steering rate (g) are value, it is often convenient to consider this as a
obtained from the old-episode fine-steering rate signed value. For example, if the high order 32 bits of
(old.f) and gross-steering rate (old.g), respectively; the TOD-offset register contain a value of FFFFFFFF
when in the new episode, they are obtained from the hex, and this value is added to bits 0-31 of the physi-
new-episode fine-steering rate (new.f) and gross- cal clock, the carry out of bit position 0 is ignored and
steering rate (new.g), respectively. the effect is the same as if 1.048578 seconds were
subtracted from the TOD clock.
The current total steering rate (r) is obtained from the
sum of the current fine-steering rate (f) and the cur-
rent gross-steering rate (g). A carry, if any, out of bit Clock Comparator
position 0, is ignored in this addition. The current
total steering rate (r) is a 32-bit signed binary fixed- The clock comparator provides a means of causing
point value and considered to be scaled by a factor of an interruption when the TOD-clock value exceeds a
2-44. The absolute value of r, treated as a 32-bit value specified by the program.
binary unsigned number is multiplied by the 64-bit
unsigned difference (Tr - s) to form a 96-bit unsigned In a configuration with more than one CPU, each
binary product, which is shifted right by 44 bit posi- CPU has a separate clock comparator.
tions to form a 52-bit intermediate result. Twelve
zeros are then appended on the left to form a 64-bit The clock comparator has the same format as bits
adjustment value. If r is zero, the current base offset 0-63 of the TOD clock. The clock comparator nomi-
is used directly as the TOD offset and no multiplica- nally consists of bits 0-47, which are compared with
tion is necessary. If r is positive, the adjustment value the corresponding bits of the TOD clock. In some
is added to the current base offset (b) to form the models, higher resolution is obtained by providing
TOD offset (d); if r is negative, the adjustment value more than 48 bits. The bits in positions provided in
is subtracted from the current base offset (b) to form the clock comparator are compared with the corre-
the TOD offset (d). A carry, (or borrow) occurring dur- sponding bits of the clock. When the resolution of the
ing this addition (or subtraction) is ignored. When r is clock is less than that of the clock comparator, the
negative, then each time an TOD-offset-update event contents of the clock comparator are compared with
occurs within a single episode, after computing the the clock value as this value would be stored by exe-
current TOD offset (d), the machine provides an cuting STORE CLOCK or STORE CLOCK FAST.
interlock by delaying long enough to ensure that the
logical TOD clock appears to step forwards as The clock comparator causes an external interruption
viewed by the program. with the interruption code 1004 hex. When the TOD-
clock-steering facility is not installed, a request for a
Programming Note: Bits 0 and 31 of the steering- clock-comparator interruption exists whenever either
rate represent steering rates of -2-13 and 2-44, respec- of the following conditions exists:
tively. Thus, steering rates of !122 parts per million
1
Function Performed on
CPU on Which Key Was
Key Activated Activated Other CPUs in Config. Remainder of Config.
System-reset-normal key CPU reset CPU reset Subsystem reset
System-reset-clear key Clear reset2 Clear reset2 Clear reset3
Load-normal key Initial CPU reset, followed by IPL CPU reset Subsystem reset
Load-clear key Clear reset2, followed by IPL Clear reset2 Clear reset3
Explanation:
1
Activation of a system-reset or load key may change the configuration, including the connection with I/O,
storage units, and other CPUs.
2
Only the CPU elements of this reset apply.
3
Only the non-CPU elements of this reset apply.
Figure 4-12. Manual Initiation of Resets
2. Any pending external-interruption conditions c. The current PSW is changed from 16 bytes
which are local to the CPU are cleared. Floating to eight bytes. The bits of the eight-byte PSW
external-interruption conditions are not cleared. are set as follows: bits 0-11 and 13-32 are
set equal to the same bits of the 16-byte
3. Any pending machine-check-interruption condi- PSW, bit 12 is set to one, and bits 33-63 are
tions and error indications which are local to the set equal to bits 97-127 of the 16-byte PSW.
CPU and any check-stop states are cleared.
Floating machine-check-interruption conditions A CPU reset caused by activation of the system-
are not cleared. Any machine-check condition reset-normal key or by the SIGNAL PROCES-
which is reported to all CPUs in the configuration SOR CPU-reset order, and any CPU reset in the
and which has been made pending to a CPU is ESA/390 mode, do not affect the captured-
said to be local to the CPU. z/Architecture-PSW register.
4. All copies of prefetched instructions or operands 7. The CPU is placed in the stopped state after
are cleared. Additionally, any results to be stored actions 1-6 have been completed. When the
because of the execution of instructions in the CCW-type IPL sequence follows the reset func-
current checkpoint interval are cleared. tion on that CPU, the CPU enters the load state
at the completion of the reset function and does
5. The ART-lookaside buffer and translation-looka- not necessarily enter the stopped state during
side buffer are cleared of entries. the execution of the reset operation. When the
list-directed IPL sequence follows the reset func-
6. If the reset is caused by activation of the load-
tion on that CPU, the CPU enters the operating
normal key on any CPU in the configuration, the
state and does not necessarily enter the stopped
following actions occur:
state during the execution of the reset operation.
a. The architectural mode of the CPU (and of
all other CPUs in the configuration because Registers, storage contents, and the state of condi-
tions external to the CPU remain unchanged by CPU
2. If the architectural mode is changed to the As part of I/O-system reset, pending I/O-interruption
ESA/390 mode and bit 31 of the current PSW is conditions are cleared, and system reset is signaled
one, the PSW is invalid. to all control units and devices attached to the chan-
nel subsystem (see “I/O-System Reset” on
Initial CPU Reset page 17-13). The effect of system reset on I/O con-
Initial CPU reset combines the CPU reset functions trol units and devices and the resultant control-unit
with the following clearing and initializing functions: and device state are described in the appropriate
System Library publication for the control unit or
1. If the reset is caused by activation of the load- device. A system reset, in general, resets only those
normal key, the architectural mode of the CPU functions in a shared control unit or device that are
(and of all other CPUs in the configuration) is set associated with the particular channel path signaling
to the ESA/390 mode. the reset.
3. The contents of the control registers are set to 1. The architectural mode of all CPUs in the config-
their initial z/Architecture values. All 64 bits of the uration is set to the ESA/390 mode.
control registers are set regardless of whether
the CPU is in the ESA/390 or the z/Architecture 2. The access, general, and floating-point registers
architectural mode. of all CPUs in the configuration are set to zero.
All 64 bits of the general registers are set to zero
4. The contents of the floating-point-control register regardless of whether the CPU was in the
are set to zero. ESA/390 or z/Architecture architectural mode
when the clear-reset function was initiated.
During the execution of the store-status operation, The channel subsystem, including all subchannels, in
zeros are stored in bit positions 0-6, and a one is a multiprocessing configuration can be accessed by
stored in bit position 7, of absolute location 163, the all CPUs in the configuration. I/O-interruption condi-
store-status architectural-mode identification. tions are floating and can be accepted by any CPU in
the configuration.
When the CPU is in the ESA/390 architectural mode,
the store-status operation stores all zeros at absolute
location 163.
Shared Main Storage
When bits 0-55 of the clock comparator are stored The shared-main-storage facility permits more than
beginning at absolute location 4913, zeros are stored one CPU to have access to common main-storage
at absolute location 4912. locations. All CPUs having access to a common
main-storage location have access to the entire 4K-
The contents of the registers are not changed. If an byte block containing that location and to the associ-
error is encountered during the operation, the CPU ated storage key. The channel subsystem and all
enters the check-stop state. CPUs in the configuration refer to a shared main-
storage location using the same absolute address.
The store-status operation can be initiated manually
by use of the store-status key (see “Store-Status CPU-Address Identification
Key” on page 12-5). The store-status operation can
also be initiated at the addressed CPU by executing
Each CPU has a number assigned, called its CPU
SIGNAL PROCESSOR, specifying the stop-and-
address. A CPU address uniquely identifies one CPU
store-status order. Execution of SIGNAL PROCES-
within a configuration. The CPU is designated by
SOR specifying the store-status-at-address order
specifying this address in the CPU-address field of
permits the same status information, except for the
SIGNAL PROCESSOR. The CPU signaling a mal-
store-status architectural-mode identification, to be
function alert, emergency signal, or external call is
stored at a designated address (see “Signal-Proces-
identified by storing this address in the CPU-address
sor Orders” on page 4-58).
field with the interruption. The CPU address is
assigned during system installation and is not
changed as a result of reconfiguration changes. The
Multiprocessing program can determine the address of the CPU by
using STORE CPU ADDRESS.
The multiprocessing facility provides for the intercon-
nection of CPUs, via a common main storage, in
1. Status bits 53, 54, and 55 when the order is not Not Running: This condition exists when the
set architecture, 56-59, and 61 indicate the pres- addressed CPU is not running. The condition, when
ence of the corresponding conditions in the present, is indicated only in response to the sense-
addressed CPU at the time the order code is running-status order. This condition is not reported
received. Except in response to the sense order as a result of a SIGNAL PROCESSOR instruction
and the sense-running-status order, each condi- executed by a CPU addressing itself; condition code
tion is indicated only when the condition pre- 0 is always set in this case. A CPU is running when it
cludes the successful execution of the specified is assigned to a physical CPU.
order, although invalid parameter is not neces-
sarily indicated when any other precluding condi- Incorrect State: A set-prefix or store-status-at-
tion exists. In the case of sense, all existing address order has been rejected because the
status conditions except not-running are indi- addressed CPU is not stopped, or a set-architecture
cated; the operator-intervening condition is indi- order has been rejected because not all other CPUs
cated if it precludes the execution of any installed are stopped or in the check-stop state, or a condi-
order. tional emergency-signal order has been rejected
because the addressed CPU is not in a required
2. Status bits 62 and 63 indicate that the corre- state. When applicable, this status is generated dur-
sponding conditions were detected by the ing execution of SIGNAL PROCESSOR and is indi-
addressed CPU during reception of the order. cated concurrently with other indications of
conditions which preclude execution of the order,
If the presented status is all zeros, the addressed except that this status is not generated if an invalid-
CPU has accepted the order, and condition code 0 is parameter condition exists for a set-architecture
set at the issuing CPU; if the presented status is not order.
all zeros, the order has been rejected, the status is
stored at the issuing CPU in the general register des- Invalid Parameter: This condition exists in two
ignated by the R1 field of the SIGNAL PROCESSOR cases:
instruction, zeros are stored in the unassigned posi-
tions in bit positions 32-63 of the register, bits 0-31 of 1. The parameter value supplied with a set-prefix or
the register remain unchanged, and condition code 1 store-status-at-address order designates a stor-
is set. age location which is not available in the configu-
ration. When applicable, this status is generated
When the order is set architecture, “the addressed during execution of SIGNAL PROCESSOR,
CPU” refers to each of the other CPUs in the configu- except that it is not necessarily generated when
ration. Those CPUs, in an unpredictable order, are another condition precluding execution of the
tested for a condition that causes setting of condition order also exists.
code 1, 2, or 3. Conditions are prioritized for a single
CPU as if it were the only CPU addressed, but there 2. The parameter value supplied with a set-archi-
is no prioritization across CPUs. If a condition is rec- tecture order either is not 0 or 1 or specifies the
ognized, no further CPUs are tested, the condition current architectural mode. When applicable, this
code corresponding to the condition is set, and the status is generated during execution of SIGNAL
execution of SIGNAL PROCESSOR is completed. PROCESSOR, and no other status is generated.
The status conditions are defined as follows: External Call Pending: This condition exists when
an external-call interruption condition is pending in
Equipment Check: This condition exists when the the addressed CPU because of a previously issued
CPU executing the instruction detects equipment SIGNAL PROCESSOR order. The condition exists
malfunctioning that has affected only the execution of from the time an external-call order is accepted until
this instruction and the associated order. The order the resultant external interruption has been com-
Stopped: This condition exists when the Receiver Check: This condition exists when the
addressed CPU is in the stopped state. The condi- addressed CPU detects malfunctioning of equipment
tion, when present, is indicated only in response to during the communications associated with the exe-
sense. This condition cannot be reported as a result cution of SIGNAL PROCESSOR. When this condi-
of a SIGNAL PROCESSOR instruction executed by a tion is indicated, the order has not been initiated,
CPU addressing itself. and, since the malfunction may have affected the
generation of the remaining receiver status bits,
Operator Intervening: This condition exists when these bits are not necessarily valid. A machine-check
the addressed CPU is executing certain operations condition may or may not have been generated at the
initiated from local or remote operator facilities. The addressed CPU.
particular manually initiated operations that cause
this condition to be present depend on the model and The following chart summarizes which status condi-
on the order specified. The operator-intervening con- tions are presented to the issuing CPU in response
dition may exist when the addressed CPU uses to each order code.
reloadable control storage to perform an order and
the required licensed internal code has not been Status Condition
loaded by the IML function. The operator-intervening
58 – Operator intervening#
56 – External call pending
condition, when present, can be indicated in
55 – Invalid parameter
63 – Receiver checkg
response to all orders. Operator intervening is indi-
54 – Incorrect state
62 – Invalid order
53 – Not running
cated in response to sense if the condition is present
59 – Check stop
61 – Inoperative
57 – Stopped
and precludes the acceptance of any of the installed
orders. The condition may also be indicated in
response to unassigned or uninstalled orders. This
Order
condition cannot arise as a result of a SIGNAL PRO-
CESSOR instruction executed by a CPU addressing Sense 0 0 0 X X X X 0 0 X
itself. External call 0 0 0 X 0 X X 0 0 X
Emergency signal 0 0 0 0 0 X X 0 0 X
Check Stop: This condition exists when the Start 0 0 0 0 0 X X X 0 X
addressed CPU is in the check-stop state. The condi- Stop 0 0 0 0 0 X X X 0 X
tion, when present, is indicated only in response to Restart 0 0 0 0 0 X X X 0 X
sense, external call, emergency signal, conditional Stop and store status 0 0 0 0 0 X X X 0 X
emergency signal, start, stop, restart, set prefix, Initial CPU reset 0 0 0 0 0 X 0 X 0 X
store status at address, and stop and store status. CPU reset 0 0 0 0 0 X 0 X 0 X
The condition may also be indicated in response to
Set prefix 0 X X 0 0 X X X 0 X
unassigned or uninstalled orders. This condition can-
Store status at address 0 X X 0 0 X X X 0 X
not be reported as a result of a SIGNAL PROCES-
Set architecture 0 X X 0 0 X 0 X 0 X
SOR instruction executed by a CPU addressing itself.
Conditional emergency signal 0 X 0 0 0 X X 0 0 X
Inoperative: This condition indicates that the exe- Sense running status X 0 0 0 0 0 0 0 0 0
cution of the operation specified by the order code Unassigned order 0 0 0 0 0 X E X 1 X
requires the use of a service processor which is inop- Figure 4-18. Status Conditions in Response to Order Code
erative. The failure of the service processor may
have been previously reported by a service-proces-
sor-damage machine-check condition. The inopera-
tive condition cannot occur for the conditional
emergency signal, emergency-signal, external-call,
or sense order code.
58 – Operator intervening#
56 – External call pending
enabled, and enter the stopped state.
55 – Invalid parameter
63 – Receiver checkg
54 – Incorrect state
e. Restart provides a means to store the cur-
62 – Invalid order
53 – Not running
59 – Check stop
61 – Inoperative
rent PSW.
57 – Stopped
f. Stop and store status causes the machine to
stop and store all current status.
Order
Explanation 2. Two CPUs can simultaneously execute SIGNAL
PROCESSOR, with each CPU addressing the
# The current state of the operator-intervening condition may other. When this occurs, one CPU, but not both,
depend on the order code that is being interpreted. can find the access path busy because of the
g If a one is presented in the receiver-check bit position, the transmission of the order code or status bits
values presented in the other bit positions are not
associated with SIGNAL PROCESSOR that is
necessarily valid.
being executed by the other CPU. Alternatively,
0 A zero is presented in this bit position regardless of the
current state of this condition. both CPUs can find the access path available
1 A one is presented in this bit position. and transmit the order codes to each other. In
X A zero or a one is presented in this bit position, reflecting particular, two CPUs can simultaneously stop,
the current state of the corresponding condition. restart, or reset each other.
E Either a zero or the current state of the corresponding
condition is indicated. 3. To obtain status from another CPU which is in
the check-stop state by means of the store-sta-
Figure 4-18. Status Conditions in Response to Order Code tus-at-address order, a CPU reset operation
should first be used to bring the CPU to the
If the presented status bits are all zeros, the order
stopped state. This reset order does not alter the
has been accepted, and the issuing CPU sets condi-
status, and, depending on the nature of the mal-
tion code 0. If one or more ones are presented, the
function, provides the best chance of establish-
order has been rejected, and the issuing CPU stores
ing conditions in the addressed CPU which allow
the status in the general register designated by the
status to be obtained.
R1 field of the SIGNAL PROCESSOR instruction and
sets condition code 1.
b. External call and emergency signal cause STORE FACILITY LIST EXTENDED stores a vari-
the corresponding interruption conditions to able number of doublewords containing facility bits in
be generated. External call can be rejected a program-specified location. STFLE is described in
because of a previously generated external- Chapter 7, “General Instructions”.
call condition.
Figure 4-19 shows the meanings of the assigned
c. Start sets condition code 0 and has no other
facility bits.
effect.
A bit is set to one regardless of the current architec-
tural mode if its meaning is true. A meaning applies
0 The instructions marked “N3” in the instruction- 18 The long-displacement facility is installed in the
summary figures in Chapters 7 and 10 are installed. z/Architecture architectural mode.
1 The z/Architecture architectural mode is installed. 19 The long-displacement facility has high
performance. Bit 18 is one if bit 19 is one.
2 The z/Architecture architectural mode is active.
When this bit is zero, the ESA/390 architectural 20 The HFP-multiply-and-add/subtract facility is
mode is active. installed.
3 The DAT-enhancement facility is installed in the 21 The extended-immediate facility is installed in the
z/Architecture architectural mode. The DAT- z/Architecture architectural mode.
enhancement facility includes the INVALIDATE DAT
TABLE ENTRY (IDTE) and COMPARE AND SWAP 22 The extended-translation facility 3 is installed in the
AND PURGE (CSPG) instructions. z/Architecture architectural mode.
4 INVALIDATE DAT TABLE ENTRY (IDTE) performs 23 The HFP-unnormalized-extension facility is installed
the invalidation-and-clearing operation by in the z/Architecture architectural mode.
selectively clearing combined region-and-segment-
table entries when a segment-table entry or entries 24 The ETF2-enhancement facility is installed.
are invalidated. IDTE also performs the clearing-by-
ASCE operation. Unless bit 4 is one, IDTE simply 25 The store-clock-fast facility is installed in the
purges all TLBs. Bit 3 is one if bit 4 is one. z/Architecture architectural mode.
5 INVALIDATE DAT TABLE ENTRY (IDTE) performs 26 The parsing-enhancement facility is installed in the
the invalidation-and-clearing operation by z/Architecture architectural mode.
selectively clearing combined region-and-segment-
table entries when a region-table entry or entries 27 The move-with-optional-specifications facility is
are invalidated. Bits 3 and 4 are ones if bit 5 is one. installed in the z/Architecture architectural mode.
6 The ASN-and-LX reuse facility is installed in the 28 The TOD-clock-steering facility is installed in the
z/Architecture architectural mode. z/Architecture architectural mode.
Figure 4-19. Assigned Facility Bits (Part 1 of 3) Figure 4-19. Assigned Facility Bits (Part 2 of 3)
• E denotes an operation using implied operands In the I, RR, RS, RSI, RX, SI, and SS formats, the
and an extended op-code field. first byte of an instruction contains the op code. In the
• I denotes an immediate operation. E, RRE, RRF, S, SIL, and SSE formats, the first two
Register Operands
In the RR, RRD, RRE, RRF, RX, RXE, RXF, RXY, RS, Immediate Operands
RSY, RSI, RI, RIE, and RIL formats, the contents of In the I format, the contents of the eight-bit immedi-
the register designated by the R1 field are called the ate-data field, the I field of the instruction, are directly
first operand. The register containing the first oper- used as the operand.
and is sometimes referred to as the “first-operand
location,” and sometimes as “register R1”. In the RR, In the SI format, the contents of the eight-bit immedi-
RRD, RRE, and RRF formats, the R2 field designates ate-data field, the I2 field of the instruction, are used
the register containing the second operand, and the directly as the second operand. The B1 and D1 fields
R2 field may designate the same register as R1. In the specify the first operand, which is one byte in length.
RRD, RRF, RXF, RS, RSY,RSI, and RIE formats, the In the SIY format, the operation is the same except
use of the R3 field depends on the instruction. In the that DH1 and DL1 fields are used instead of a D1 field.
The index (X) is a 64-bit number contained in a gen- A zero in any of the B1, B2, X2, or B4 fields indicates
eral register designated by the program in a four-bit the absence of the corresponding address compo-
field, called the X field, in the instruction. It is nent. For the absent component, a zero is used in
included only in the address specified by the RX-, forming the intermediate sum, regardless of the con-
RXE-, RXF-, and RXY-format instructions. The RX-, tents of general register 0. A displacement of zero
RXE-, RXF-, and RXY-format instructions permit dou- has no special significance.
ble indexing; that is, the index can be used to provide
the address of an element within an array. When an instruction description specifies that the
contents of a general register designated by an R
The displacement (D) is a 12-bit or 20-bit number field are used to address an operand in storage, the
contained in a field, called the D field, in the instruc- register contents are used as the 64-bit intermediate
tion. A 12-bit displacement is unsigned and provides value.
for relative addressing of up to 4,095 bytes beyond
the location designated by the base address. A 20-bit An instruction can designate the same general regis-
displacement is signed and provides for relative ter both for address computation and as the location
addressing of up to 524,287 bytes beyond the base- of an operand. Address computation is completed
address location or of up to 524,288 bytes before it. before registers, if any, are changed by the operation.
In array-type calculations, the displacement can be
used to specify one of many items associated with an Unless otherwise indicated in an individual instruc-
element. In the processing of records, the displace- tion definition, the generated operand address desig-
ment can be used to identify items within a record. nates the leftmost byte of an operand in storage.
— The address does not exist, or the bit has no special effect.
* The action associated with the R2 field is not performed if the field is zero.
** The action associated with the R1 or R2 field is not performed if the field is zero.
*** The instruction-length code, condition code, and program mask are saved in bit positions 32-39 of the link
address, and bits 40-63 of the updated instruction address are saved in bit positions 40-63.
0/1 Bit 63 can be zero or one.
1G0 Bit 63 is one and is left one, but the branch address is generated as if the bit is zero.
BAM Bit 32 of the link address is set with the basic-addressing-mode bit, bit 32 of the PSW.
FZ Bits 0-32 of the second-operand address are forced to zeros in the 24-bit or 31-bit addressing mode.
IA Bits of the link address are set with the updated instruction address as shown.
LSExc A late specification exception is recognized if the bit is one.
NLA The instruction does not produce a link address. (The instruction is shown simply as an example of a non-linkage
branch instruction.)
Op2Ad Bits of the address in general register R1 are set with the corresponding bits of the second-operand address as
shown.
R232 The basic-addressing-mode bit, bit 32 of the PSW, is set with bit 32 of general register R2
SIA Bits 0-63 of the branch address are used to set the instruction address in the PSW. Bits 0-39 of the branch
address are forced to zeros in the 24-bit addressing mode. Bits 0-32 are forced to zeros in the 31-bit addressing
mode.
SR1 Bits of the second-operand address are used to set the corresponding bits of the address in the R1 general
register as shown. Bits 0-39 of the second-operand address are forced to zeros in the 24-bit addressing mode.
Bits 0-32 are forced to zeros in the 31-bit addressing mode.
U Unchanged.
Figure 5-2. Summary of Simple Branch Linkage Instructions and Other Instructions
31-bit mode.) BASSM always correctly indicates vides addressability to the entry point, bit 63 of
the addressing mode of the calling program. the entry-point register must be zeroed to ensure
compatible operation regardless of whether the
3. If an entry point can be branched to in the 64-bit linkage instruction changes the addressing
addressing mode either by BAS or BASR or by mode. For example, if general register 15 is the
BASSM or BSM, and a USING statement pro-
PROGRAM TRANSFER WITH INSTANCE is not fur- PROGRAM TRANSFER specifies the address space
ther referred to in this section. which is to become the new primary address space.
When the primary address space is changed, the
Linkage between a problem-state program and the operation is called PROGRAM TRANSFER with
supervisor or monitoring program is provided by space switching (PT-ss). When the primary address
means of the SUPERVISOR CALL and MONITOR space is not changed, the operation is called PRO-
CALL instructions. GRAM TRANSFER to current primary (PT-cp).
The instructions PROGRAM CALL and PROGRAM Basic PROGRAM CALL, and PROGRAM TRANS-
TRANSFER provide the facility for linkage between FER, can be executed successfully in either a basic
programs of different authority and in different (24-bit or 31-bit) addressing mode or the extended
address spaces. PROGRAM CALL permits linkage (64-bit) addressing mode. They do not provide a
to a number of preassigned programs that may be in change between a basic addressing mode and the
either the problem or the supervisor state and may extended addressing mode.
be in either the same address space or an address
space different from that of the caller. It permits a The BRANCH AND SET AUTHORITY instruction
change between the 24-bit and 31-bit addressing can improve performance by replacing a PT-cp
modes, and it permits an increase of PSW-key-mask instruction used to perform a calling linkage in which
authority, which authorizes the execution of the SET PSW-key-mask authority is reduced, and by replac-
PSW KEY FROM ADDRESS instruction and also ing a PC-cp instruction used to perform the associ-
other functions. In general, PROGRAM CALL is used ated return linkage in which PSW-key-mask authority
to transfer control to a program of higher authority. is restored. BRANCH AND SET AUTHORITY also
PROGRAM TRANSFER permits a change of the permits changes between the supervisor and prob-
instruction address and address space and a change lem states, and it can replace SET PSW KEY FROM
between the 24-bit and 31-bit addressing modes. ADDRESS by changing the PSW key during the link-
PROGRAM TRANSFER also permits a reduction of age. The calling-linkage operation is called BRANCH
PSW-key-mask authority and a change from the AND SET AUTHORITY in the base-authority state
supervisor to the problem state. In general, it is used (BSA-ba), and the return-linkage operation is called
to transfer control from one program to another of BRANCH AND SET AUTHORITY in the reduced-
equal or lower authority. authority state (BSA-ra).
When a calling linkage is to increase authority, the The BRANCH IN SUBSPACE GROUP instruction
calling linkage can be performed by PROGRAM allows linkage within a group of address spaces
The SET ADDRESSING MODE (SAM24, SAM31, With respect to System/370 programs, it is assumed
SAM64) instruction can assist in linkage by setting that old, unmodified programs operate in the 24-bit
the 24-bit, 31-bit, or 64-bit addressing mode either addressing mode and call, or directly communicate
before or after a linkage operation. with, other programs operating in the 24-bit address-
ing mode only. Modified programs normally operate
The RESUME PROGRAM instruction is intended for in the 24-bit addressing mode but may have called
use by a problem-state interruption-handling program programs which operate in either the 24-bit or 31-bit
- No
* In the 24-bit addressing mode, the instruction-length code, condition code, and program mask are saved in bit
positions 32-39 of the R1 general register.
** A change from the supervisor to the problem state is allowed; a privileged-operation exception is recognized
when a change from the problem to the supervisor state is specified.
# Monitor-mask bits provide a means of disallowing linkage, or enabling linkage, for selected classes of events.
When the enhanced-monitor facility is installed, the enhanced-monitor-mask bits are also used in controlling
linkage (by means of a monitor-event program interruption).
1
The action takes place only if the associated R field in the instruction is nonzero.
2
MC and SVC, as part of the interruption, save the entire current PSW and load a new PSW.
3
The primary address-space-control element is set even though the PASN is not set.
4
The problem state is set
5
The PSW key also is set from general register R1
BAM The basic-addressing-mode bit is saved or set only in the 24-bit or 31-bit addressing mode.
BAM31 The basic-addressing-mode bit is saved only in the 31-bit addressing mode.
BAM64 The extended-addressing-mode bit is saved only in the 64-bit addressing mode.
R1 The field or bit is saved in general register R1.
R2 The field or bit is set from general register R2.
Figure 5-3. Summary of Linkage Instructions without the Linkage Stack
addressing mode. They and also modified 370-XA, The return from such a routine normally is:
ESA/370, and ESA/390 programs now may call pro-
grams that operate in the 24-bit, 31-bit, or 64-bit BSM 0,14
addressing mode. New programs may be written to
operate in any addressing mode, and, in some It is assumed that the A-type address constant will be
cases, a program may be written such that it can be extended so it may be an eight-byte field containing a
invoked in any addressing mode. 64-bit entry-point address, with bit 63 of the address
indicating, when one, that the entry is in the 64-bit
BRANCH AND SAVE AND SET MODE (BASSM) is addressing mode. This extended constant is shown
intended to be the principal calling instruction to sub- here as “ACONE”. The calling sequence would nor-
routines outside of an assembler/linkage-editor con- mally be:
trol section (CSECT), for use by all new programs
and particularly by programs that must change the LG 15,ACONE
addressing mode during the linkage. The calling BASSM 14,15
…
sequence has normally been:
EXTRN SUB
ACONE DC AD(X'1'+SUB)
L 15,ACON
BASSM 14,15
… The return from such a routine would normally be:
EXTRN SUB
ACON DC A(X'80000000'+SUB) BSM 0,14
where ACON is an A-type address constant, and the When a change of the addressing mode is not
X’80000000’ should be present to give control in the required, BRANCH AND LINK or BRANCH AND
31-bit addressing mode or should be omitted to give SAVE should be used instead of BASSM.
control in the 24-bit addressing mode.
The BRANCH AND LINK (BAL, BALR) instruction is
provided primarily for compatibility with System/370.
L 15,OLDACON
BALR 14,15
•
•
•
EXTRN GLUE
OLDACON DC A(GLUE)
GLUE CSECT
USING *,15
L 15,NEWACON
BSM 14,15
EXTERN NEW
NEWACON DC A(NEW)
NEW CSET
USING *,15
•
•
•
BSM 0,14
Figure 5-4. Glue Module for Linkage from the 24-Bit Mode to the 31-Bit Mode
When (a) the AFP-register (additional floating-point For the following instructions, referred to as interrupt-
register) control bit, bit 45 of control register 0, is one, ible instructions, an interruption is permitted also
(b) either an IEEE-invalid-operation condition or an after partial completion of the instruction:
IEEE-division-by-zero condition is recognized, and
(c) the respective IEEE mask bit in the floating-point- • COMPARE AND FORM CODEWORD
control (FPC) register is one, then the resulting data- • COMPARE LOGICAL LONG
exception program interruption is considered to be • COMPARE UNTIL SUBSTRING EQUAL
suppressing, even though the FPC is altered. See • COMPRESSION CALL
“Data-Exception Code (DXC)” on page 6-14 for • INVALIDATE PAGE TABLE ENTRY (when the
details. IPTE-range facility is installed, and the R3 field is
nonzero)
Nullification • MOVE LONG
Nullification of instruction execution has the same • PERFORM FRAME MANAGEMENT FUNCTION
effect as suppression, except that when an interrup- (when the enhanced-DAT facility is installed, and
tion occurs after the execution of an instruction has the frame-size code designates a 1M-byte frame)
been nullified, the instruction address in the old PSW • SET STORAGE KEY EXTENDED (when the
designates the instruction whose execution was nulli- enhanced-DAT facility is installed, and the multi-
fied (or an execute-type instruction, as appropriate) ple-block control is one)
instead of the next sequential instruction. • TEST BLOCK
• UPDATE TREE
Termination
Termination of instruction execution causes the con- Unit of Operation
tents of any fields due to be changed by the instruc- Whenever points of interruption that include those
tion to be unpredictable. The operation may replace occurring within the execution of an interruptible
all, part, or none of the contents of the designated instruction are discussed, the term “unit of operation”
result fields and may change the condition code if is used. For a noninterruptible instruction, the entire
such change is called for by the instruction. Unless execution consists, in effect, in the execution of one
the interruption is caused by a machine-check condi- unit of operation.
tion, the validity of the instruction address in the
PSW, the interruption code, and the ILC are not The execution of an interruptible instruction is consid-
affected, and the state or the operation of the ered to consist in the execution of a number of units
machine is not affected in any other way. The instruc- of operation, and an interruption is permitted
tion address in the old PSW on an interruption after between units of operation. The amount of data pro-
termination designates the next sequential instruc- cessed in a unit of operation depends on the particu-
tion. lar instruction and may depend on the model and on
the particular condition that causes the execution of
Programming Note: Although the execution of an the instruction to be interrupted.
instruction is treated as a no-operation when sup-
pression or nullification occurs, stores may be per- When an instruction execution consists of a number
formed as the result of the implicit tracing action of units of operation and an interruption occurs after
associated with some instructions. See “Tracing” on some, but not all, units of operation have been com-
page 4-10. pleted, the instruction is said to be partially com-
pleted. In this case, the type of ending (completion,
nullification, or suppression) is associated with the
Interruptible Instructions unit of operation. In the case of termination, the
entire instruction is terminated, not just the unit of
operation.
Point of Interruption
For most instructions, the entire execution of an
An exception may exist that causes the first unit of
instruction is one operation. An interruption is permit-
operation of an interruptible instruction not to be
ted between operations; that is, an interruption can
At the time of an interruption, changes to storage The differences among the four types of ending for a
locations or register contents which are due to be unit of operation are summarized in Figure 5-5 on
made by instructions following the interrupted page 5-21.
instruction have not yet been made.
Unit of Instruction Operand Current Result
Operation Is Address Parameters Location
Completion: On completion of the last unit of oper-
ation of an interruptible instruction, the instruction Completed
address in the old PSW designates the next sequen-
Last unit of Next Depends on the Changed
tial instruction. The result location for the current unit
operation instruction instruction
of operation has been updated. It depends on the
particular instruction how the operand parameters Any other Current Next unit of Changed
are adjusted. On completion of a unit of operation unit of operation instruction operation
other than the last one, the instruction address in the
Nullified Current Current unit of Unchanged
old PSW designates the interrupted instruction or an Instruction operation
execute-type instruction, as appropriate. The result
location for the current unit of operation has been Suppressed Next Current unit of Unchanged
updated. The operand parameters are adjusted such Instruction operation
that the execution of the interrupted instruction is Terminated Next Unpredictable Unpredictable
resumed from the point of interruption when the old instruction
PSW stored during the interruption is made the cur-
rent PSW. Figure 5-5. Types of Ending for a Unit of Operation
Nullification: When a unit of operation is nullified, If an instruction is defined to set the condition code,
the instruction address in the old PSW designates the execution of the instruction makes the condition
the interrupted instruction or an execute-type instruc- code unpredictable except when the last unit of oper-
tion, as appropriate. The result location for the cur- ation has been completed.
rent unit of operation remains unchanged. The
In certain unusual situations, the result fields of an When, for an instruction having a store-type operand,
instruction having a store-type operand are changed a DAT-associated access exception is recognized for
in spite of the occurrence of an exception which any operand of the instruction, that portion, if any, of
would normally result in nullification or suppression. the store-type operand which would not cause an
These situations are exceptions to the general rule exception may be changed to an intermediate value
that the operation is treated as a no-operation when but is then restored to the original value.
an exception requiring nullification or suppression is
recognized. Each of these situations may result in the The accesses associated with storage change and
turning on of the change bit associated with the restoration for DAT-associated access exceptions are
store-type operand, even though the final result in only observable by channel programs and are not
storage may appear unchanged. Depending on the observable by other CPUs in a multiprocessing con-
particular situation, additional effects may be observ- figuration. Except for instructions which are defined
able. The extent of these effects is described along to have multiple-access operands, the intermediate
with each of the situations. value, if any, is always equal to what would have
been the final value if the DAT-associated access
All of these situations are limited to the extent that a exception had not occurred.
store access does not occur and the change bit is not
set when the store access is prohibited. For the CPU, Programming Notes:
a store access is prohibited whenever an access
exception exists for that access, or whenever an 1. Storage change and restoration for DAT-associ-
exception exists which is of higher priority than the ated access exceptions occur in two main situa-
priority of an access exception for that access. tions:
SO-PAH CPU must be in the primary-space, Effective Address when ASN-and-LX Reuse Is Not
access-register, or home-space mode; Enabled
special-operation exception if the CPU is
in the secondary-space or real mode. 0 31
LX EX
SO-PS CPU must be in the primary-space or
32 44 56 63
secondary-space mode; special-opera-
tion exception if the CPU is in the home-
space, access-register, or real mode. Bit 44 of the effective address has no special mean-
ing and may be zero or one.
SO-PSAH CPU must be in the primary-space, sec-
ondary-space, access-register, or home- When ASN-and-LX reuse is enabled, the linkage
space mode; special-operation excep- index is further divided into a linkage first index (LFX)
tion if the CPU is in the real mode. and a linkage second index (LSX). The linkage sec-
ond index is always the five bits immediately on the
sPC Stacking PROGRAM CALL.
left of the entry index. The size and format of the link-
X1 When bit 57 of control register 1 is one, a age first index depend on whether the PC number is
space-switch event is recognized. The 20 bits or 32 bits, which in turn depends on whether
operation is completed. bit 44 of the effective address is zero or one, respec-
tively. In these cases, the effective address has the
X2 When bit 57 of control register 1 or 13 is following formats:
one and the instruction space is
changed to or from the home address Effective Address when ASN-and-LX Reuse Is Enabled
space, a space-switch event is recog- and Bit 44 Is Zero
nized. The operation is completed.
0 31
LX
PC-Number Translation LFX
1. Bit 44 of a PROGRAM CALL effective address The ASN-and-LX-reuse control in control register 0 is
specifying a 32-bit PC number is not a numeric examined in both the problem and the supervisor
part of the PC number. states. Other uses of this control, related to the ASN-
second-table-entry instance number, are summa-
2. The effective address from which a PC number is rized in “ASN-Second-Table-Entry Instance Number
derived is subject to the addressing mode in the and ASN Reuse” on page 3-21.
current PSW. Therefore, bits 0-39 of the effective
address in the 24-bit addressing mode, and bits This use of the LSTESN allows a linkage index asso-
0-32 in the 31-bit addressing mode, are treated ciated with a particular LSTESN to be made unus-
as containing zeros. able when the linkage index is reassigned to specify
a different (different origin) or conceptually different
(different contents, or containing ASNs that desig-
PC-Number Translation Control nate conceptually different address spaces) entry
table. The LX-and-LSTESN combination can be
PC-number translation is controlled by means of the made unusable by changing the LSTESN in the link-
ASN-and-LX-reuse control in control register 0 and a age-second-table entry.
linkage-table designation or linkage-first-table desig-
Bit 128 of the entry-table entry (T) is the PC-type bit. Entry Parameter (Part 2)
When bit 128 is zero, PROGRAM CALL is to perform 224 255
the basic (nonstacking) operation. When bit 128 is
one, PROGRAM CALL is to perform the stacking The fields in the entry-table entry are allocated as fol-
operation. lows:
Bit 129 of the entry-table entry (G) is the entry- Entry Basic Addressing Mode (A): When bit 129
extended-addressing-mode bit. In the basic PRO- is zero, bit 32 replaces the basic-addressing-mode
GRAM CALL operation, bit 31 of the current PSW, bit, bit 32 of the current PSW, as part of the PRO-
the extended-addressing-mode bit, must equal bit GRAM CALL operation. In this case if bit 32 is zero,
129; otherwise, a special-operation exception is rec- bits 33-39 must also be zeros; otherwise, a PC-trans-
ognized. In the stacking operation when bit 129 is lation-specification exception is recognized. When bit
zero, bit 31 of the current PSW is set to zero, and bit 129 is one, bit 32 is a bit of the entry instruction
32 of the PSW, the basic-addressing-mode bit, is set address, and bit 32 of the PSW remains or is set to
with the value of bit 32 of the entry-table entry (A), one.
the entry-basic-addressing-mode bit. In the stacking
operation when bit 129 is one, bits 31 and 32 of the Entry Instruction Address: When bit 129 is zero,
current PSW both are set to one. Thus, the basic bits 33-62, with 33 zeros appended on the left and a
PROGRAM CALL operation does not switch between zero appended on the right, form the instruction
the extended and a basic addressing mode but can address which replaces the instruction address in the
switch between the 24-bit and 31-bit modes, and the PSW as part of the PROGRAM CALL operation.
stacking operation can set any addressing mode. When bit 129 is one, bits 0-62, with a zero appended
on the right, form the instruction address.
The 32-byte entry-table entry has the following for-
mat: Entry Problem State (P): Bit 63 replaces the prob-
lem-state bit, bit 15 of the current PSW, as part of the
If Bit 129 is Zero PROGRAM CALL operation.
Explanation:
1
A 20-bit PC number can specify an entry only within the first unit. Bits 0-3 of a 32-bit PC number specify
entries beyond the end of the largest possible table.
When ASN-and-LX reuse is not enabled, the LX is When ASN-and-LX reuse is enabled, a linkage-sec-
used to select an entry from the linkage table, the ond-table-entry sequence number (LSTESN) in gen-
starting address and length of which are specified by eral register 15 is compared to the LSTESN in the
the linkage-table designation in the primary ASTE. linkage-second-table entry if the LSTESN in the entry
This entry designates the entry table to be used. The is nonzero.
EX field of the PC number is used to select an entry
from the entry table. When, for the purposes of PC-number translation,
accesses are made to main storage to fetch entries
When ASN-and-LX reuse is enabled, the LFX is used from the primary ASTE, linkage table, linkage first
to select an entry from the linkage first table, the table, linkage second table, and entry table, key-con-
starting address and length of which are specified by trolled protection does not apply.
the linkage-first-table designation in the primary
ASTE. This entry designates the linkage second The PC-number-translation process is shown in
table to be used. The LSX is then used to select an Figure 5-8 on page 5-37 for when ASN-and-LX-reuse
entry from the linkage second table, which entry des- is not enabled and in Figure 5-9 on page 5-38 for
ignates the entry table to be used. The EX field of the when it is enabled.
PC number is then used to select an entry from the
entry table.
Linkage Table
Linkage-Table Entry
R I Entry-Table Origin ETL
(x64)
Entry Table
R: Address is real.
**: First word and A of ETE are bits 0-32 of entry-instruction address (EIA) if G is one.
Linkage-First-Table Entry
R I Linkage 2nd Tbl. Origin
(x256)
=
Linkage-Second-Table Entry
if LSTESN
R I Entry-Table Origin ETL LSTESN in LSTE is
(x64) g0
No
LSTE-Sequence
Exception
+
Entry Table
R: Address is real.
*: PC Number is 32 bits if bit 44 of the effective address is one. Bit 44 is not shown in this case.
**: First word and A of ETE are bits 0-32 of entry-instruction address (EIA) if G is one.
All four bytes of the linkage-first-table entry appear to When no exceptions are recognized in the process of
be fetched concurrently as observed by other CPUs. linkage-second-table lookup, the entry fetched from
The fetch access is not subject to protection. When the linkage second table designates the origin of the
the storage address which is generated for fetching corresponding entry table. The linkage-second-table
the linkage-first-table entry designates a location entry contains a linkage-second-table-entry
which is not available in the configuration, an sequence number that may be used to test the cor-
addressing exception is recognized, and the opera- rectness of the use of the linkage index.
tion is suppressed.
Linkage-Second-Table-Entry-Sequence-
Bit 0 of the linkage-first-table entry specifies whether
Number Comparison
the linkage second table corresponding to the linkage
The linkage-second-table entry contains a linkage-
first index is available. This bit is inspected, and, if it
second-table-entry sequence number (LSTESN) in
is one, an LFX-translation exception is recognized.
bit positions 32-63. If this LSTESN is nonzero, it is
compared to an LSTESN in bit positions 0-31 of gen-
When no exceptions are recognized in the process of
eral register 15, and an LSTE-sequence exception is
linkage-first-table lookup, the entry fetched from the
recognized if the two LSTESNs are not equal.
linkage first table designates the origin of the corre-
sponding linkage second table.
Entry-Table Lookup
When the ASN-and-LX-reuse facility is not installed
Linkage-Second-Table Lookup
or is not enabled, the entry-table entry is located from
When the ASN-and-LX-reuse facility is installed and
a linkage-table entry. When the ASN-and-LX-reuse
the ASN-and-LX-reuse-control bit, bit 44 of control
facility is installed and enabled, the entry-table entry
register 0, is one, a linkage-second-table lookup is
is located from a linkage-second-table entry.
performed after a linkage-first-table entry has been
fetched. The linkage-second-index (LSX) portion of
The entry-index (EX) portion of the PC number, in
the PC number, in conjunction with the linkage-sec-
conjunction with the entry-table origin contained in
ond-table origin, is used to select an entry from the
the linkage-table or linkage-second-table entry, is
linkage second table.
used to select an entry from the entry table.
The use that is made of the information fetched from The home-address-space facilities include:
the entry-table entry is described in the definition of
the PROGRAM CALL instruction. • The home address-space-control element
(HASCE) in control register 13. The HASCE is
used by DAT in the same way as the primary
Recognition of Exceptions during PC- address-space-control element (PASCE) in con-
Number Translation trol register 1 and the secondary address-space-
The exceptions which can be encountered during the control element (SASCE) in control register 7.
PC-number-translation process and their priority are
described in the definition of the PROGRAM CALL • Home-space mode, which results when DAT is
instruction. on and the address-space control, PSW bits 16
and 17, has the value 11 binary. When the CPU
Programming Note: The linkage-table or linkage- is in the home-space mode, instruction and logi-
first-table designation is fetched successfully from cal addresses are home virtual addresses and
the primary ASN-second-table entry regardless of are translated by DAT by means of the HASCE.
the value of bit 0, the ASX-invalid bit, in the primary
• The ability of the RESUME PROGRAM, SET
ASTE. A one value of this bit may cause an excep-
ADDRESS SPACE CONTROL, and SET
tion to be recognized in other circumstances.
ADDRESS SPACE CONTROL FAST instructions
to set the home-space mode in the supervisor
state, and the ability of the INSERT ADDRESS
• The home space-switch-event control, bit 57 of • Instructions for examining and changing the con-
control register 13. tents of the access registers.
• Recognition of a space-switch event upon com- In addition, control and authority mechanisms are
pletion of a RESUME PROGRAM, SET incorporated to control these functions.
ADDRESS SPACE CONTROL, or SET
ADDRESS SPACE CONTROL FAST instruction Access registers allow a sequence of instructions, or
if the CPU was in the home-space mode before even a single instruction such as MOVE (MVC) or
or after the operation but not both before and MOVE LONG (MVCL), to operate on storage oper-
after the operation, if any of the following is true: ands in multiple address spaces, without the require-
(1) the primary space-switch-event control, bit 57 ment of changing either the translation mode or other
of control register 1, is one, (2) the home space- control information. Thus, a program residing in one
switch-event control is one, or (3) a PER event is address space can use the complete instruction set
to be indicated. to operate on data in that address space and in up to
15 other address spaces, and it can move data
The space-switch event can be used to enable or dis- between any and all pairs of these address spaces.
able PER or tracing when fetching of instructions Furthermore, the program can change the contents
begins or ends in particular address spaces. of the access registers in order to access still other
address spaces.
• A maximum of 16 address spaces, including the Access registers are used in a special way by the
instruction space, for immediate and simulta- BRANCH IN SUBSPACE GROUP instruction. The
neous use by a semiprivileged program; the use of access registers by that instruction is
The COMPARE AND FORM CODEWORD and Access register 0 is treated in a special way by
UPDATE TREE instructions specify storage oper- access-register translation; it is treated as containing
ands by means of implicitly designated general regis- 00000000 hex, and its actual contents are not exam-
ters and access registers. ined. Thus, a logical address specified by means of a
zero B or R field in the access-register mode is
The MOVE TO PRIMARY and MOVE TO SECOND- always relative to the primary address space, regard-
ARY instructions specify storage operands by means less of the contents of access register 0. However,
of primary virtual and secondary virtual addresses, there is one exception to how access register 0 is
and access registers do not apply to these instruc- treated: the TEST ACCESS instruction uses the
tions. An exception is recognized when either of actual contents of access register 0, instead of treat-
these instructions is executed in the access-register ing access register 0 as containing 00000000 hex.
mode. The MOVE WITH KEY instruction can be used
in place of MOVE TO PRIMARY and MOVE TO SEC- The treatment of an access register containing the
ONDARY in the access-register mode. The MOVE value 00000000 hex as designating the current pri-
WITH SOURCE KEY and MOVE WITH DESTINA- mary address space allows that address space to be
TION KEY instructions also can be used. addressed, in the access-register mode, without
requiring the use of an access-list entry. This is use-
An instruction R field may designate an access regis- ful when the primary address space is changed by a
ter for other than the purpose of access-register space-switching PROGRAM CALL (PC-ss), PRO-
translation. GRAM RETURN (PR-ss), or PROGRAM TRANS-
FER (PT-ss) instruction. Similarly, the treatment of an
The fields which may designate access registers, access register containing the value 00000001 hex
whether or not for access-register translation, are as designating the secondary address space allows
indicated in the summary figure at the beginning of that space to be addressed after a space-switching
each instruction chapter.
Access List
ASTE for Space 36
4 PB=0
The figure shows an access list — assume it is a dis- numbers used to identify the address spaces (36, 25,
patchable-unit access list — in which the entries of 62, and 17) are arbitrary. They may be the ASNs of
interest are entries 4, 7, 9, and 12. Each access-list the address spaces; however, ASNs are in no way
entry contains a private bit, an ALEAX, and the real used in access-register translation. Only the authority
origin of the ASTE for an address space. The private table for address space 17 is shown. In it, the sec-
bit in entry 4 is zero, and, therefore, the value of the ondary bit selected by EAX 10 is one. Assume that
ALEAX in entry 4 is immaterial and is not shown. The no secondary bits are ones in the authority tables for
private bits in entries 7, 9, and 12 are ones, and the the other spaces.
ALEAX values in these entries are as shown. The
Each of programs A, B, and C can use access-list The entry-table entry and linkage stack can be used
entry (ALE) 4 to access address space 36 since the to assign EAXs to programs and to change the EAX
private bit in ALE 4 is zero. Program B can use ALE 7 in control register 8 during program linkages. These
to access space 25 because the ALEAX in the ALE components are introduced in “Linkage-Stack Intro-
equals the EAX for the program, and no other pro- duction” on page 5-66. The privileged EXTRACT
gram can use this ALE. Similarly, only program C can AND SET EXTENDED AUTHORITY instruction also
use ALE 9. Program B can use ALE 12 because the is available for saving and changing the EAX in con-
ALEAX and EAX are equal, and program C can use it trol register 8.
because A’s EAX selects a secondary bit that is one
in the authority table for space 17. The SET SECONDARY ASN instruction and the
authorization index (AX), bits 32-47 of control register
The example would be the same if programs A, B, 4, can play a role in the use of access registers. The
and C were all in the same address space and the space-switching form of SET SECONDARY ASN
access list were the primary-space access list for that (SSAR-ss) establishes a new secondary address
space. space if the secondary bit selected by the AX is one
in the authority table associated with the new sec-
An ALE in which the private bit is zero may be called ondary space. The secondary space can be
public because the ALE can be used by any program, addressed by means of an ALET having the value
regardless of the value of the current EAX. An ALE in 00000001 hex.
which the private bit is one may be called private
because the ability of a program to use the ALE Revoking Accessing Capability: Another mech-
depends on the current EAX. anism, which is a combined authority and integrity
mechanism, is part of access-register translation,
Notes on the Authorization Mechanism: An and it is described in this section.
access list is a kind of capability list, in the sense in
which the word “capability” is used in computer sci- An access-list entry (ALE) contains an ASN-second-
ence. It is up to the control program to formulate the table-entry sequence number (ASTESN), and so
policies that are used to allocate entries in an access does the ASTE designated by the ALE. During
list, and the programmed authorization checking access-register translation, the ASTESN in the ALE
required during allocation may be very complex and must equal the ASTESN in the designated ASTE;
lengthy. After a valid entry has been made in an otherwise, an exception is recognized.
access list, the access-register-translation process
enforces the control-program policies in a well-per- When the control program allocates an ALE, it should
forming way by means of the authorization mecha- copy the ASTESN from the designated ASTE into the
nism described above. ALE. Subsequently, the control program can, in
effect, revoke the addressing capability represented
Using access lists has an advantage over using only by the ALE by changing the ASTESN in the ASTE.
ASNs and authority tables. For example, assume that Changing the ASTESN in the ASTE makes all previ-
an access register could contain an ASN and that ously usable ALEs that designate the ASTE unus-
access-register translation would do ASN translation able.
of the ASN and then use the EAX to test the authority
table. This would make the EAX relevant to all exist- Making an ALE unusable may be required in either of
ing address spaces, and, therefore, it would make two cases:
the management of EAXs and their assignment to
programs more difficult. With the actual definitions of 1. Some element of the control-program policy for
the ALET and access-register translation, an EAX is determining the authority of a program to have
field are not all zeros, the results in the target general DUCTO
register and access register are unpredictable. 32 33 58 63
The fields in the ALET are allocated as follows: Access register 0 usually is treated in access-register
translation as containing 00000000 hex, and its
Primary-List Bit (P): When the ALET is not actual contents are not examined; the access-regis-
00000000 or 00000001 hex, bit 7 specifies the ter translation done as part of TEST ACCESS is the
access list to be used by access-register translation. only exception. Access register 0 is also treated as
When bit 7 is zero, the dispatchable-unit access list is containing 00000000 hex when it is designated by
used; this is specified by the dispatchable-unit the B field of LOAD ADDRESS EXTENDED when
access-list designation in the dispatchable-unit con- PSW bits 16 and 17 are 01 binary. When access reg-
trol table designated by the contents of control regis- ister 0 is specified for TEST ACCESS or as a source
ter 2. When bit 7 is one, the primary-space access for COPY ACCESS, EXTRACT ACCESS, or STORE
list is used; this is specified by the primary-space ACCESS MULTIPLE, the actual contents of the
access-list designation in the primary ASTE desig- access register are used. Access register 0, like any
nated by the contents of control register 5. other access register, can be loaded by COPY
Tables C 12 SSASTESN
10 16 DUALD (see below)
When the ALET being translated is not 00000000 or 14 20 PSW R
PSW-Key Mask P
00000001 hex, access-register translation performs Key A
a two-level lookup to locate first the effective access- 18 24
list designation and then an entry in the effective 1C 28 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
access list. The effective access-list designation In the 24-Bit or 31-Bit Addressing Mode
resides in real storage. The effective access list 20 32
resides in real or absolute storage.
24 36 B
Bits 33-63 of Return Address
A
Access-register translation uses an origin in the
In the 64-Bit Addressing Mode
access-list entry to locate an ASN-second-table
entry, and it may perform a one-level lookup to locate 20 32 Bits 0-31 of Return Address
an entry in an authority table. The ASN-second-table 24 36 Bits 32-63 of Return Address
entry resides in real storage. The authority table
resides in real or absolute storage. 28 40
2C 44 Trap-Control-Block Address E
Authority-table entries are described in “Authority-
30 48
Table Entries” on page 3-32. Access-list designa-
tions, access-list entries, and ASN-second-table 34 52
entries are described in the following sections. 38 56
3C 60
Dispatchable-Unit Control Table and
Access-List Designations Bytes 0-7 (BASTEO, SA, and SSASTEO) and 12-15
When the ALET being translated is not 00000000 or (SSASTESN) of the DUCT are described in “Sub-
00000001 hex, access-register translation obtains space-Group Dispatchable-Unit Control Table” on
the dispatchable-unit access-list designation if bit 7 of page 5-62. Bytes 20-23 (PSW key mask, PSW key,
the ALET is zero, or it obtains the primary-space RA, and P) and 32-39 (BA and return address) are
access-list designation if bit 7 is one. The obtained described in “BRANCH AND SET AUTHORITY” on
access-list designation is called the effective access- page 10-6. Bytes 44-47 (trap-control-block address
list designation. and E) are described in “TRAP” on page 10-159.
Bytes 8-11, 24-27, 40-43, and 48-63 are reserved for
The dispatchable-unit access-list designation possible future extensions and should contain all
(DUALD) is located in bytes 16-19 of a 64-byte area zeros. Bytes 28-31 are available for use by program-
called the dispatchable-unit control table (DUCT). ming.
The DUCT resides in real storage, and its location is
specified by the DUCT origin in control register 2. The primary-space access-list designation (PSALD)
is located in bytes 16-19 of a 64-byte area called the
primary ASN-second-table entry. The primary ASTE
resides in real storage, and its location is specified by
the primary-ASTE origin in control register 5. The for-
mat of the primary ASTE is described in “ASN-Sec-
ond-Table Entries” on page 5-54.
ASTESN
Access-List Origin: Bits 1-24 of the access-list 96 127
designation, with seven zeros appended on the right,
form a 31-bit address that designates the beginning
of the access list. This address is treated unpredict- The fields in the access-list entry are allocated as fol-
ably as either a real address or an absolute address. lows:
Access-List Length (ALL): Bits 25-31 of the ALEN-Invalid Bit (I): Bit 0, when zero, indicates
access-list designation specify the length of the that the access-list entry specifies an address space.
access list in units of 128 bytes, thus making the When bit 0 is one during access-register translation,
length of the access list variable in multiples of eight an ALEN-translation exception is recognized.
16-byte entries. The length of the access list, in units
of 128 bytes, is one more than the value in bit posi- Fetch-Only Bit (FO): Bit 6 controls which types of
tions 25-31. The access-list length, with six zeros operand references are permitted to the address
appended on the left, is compared against bits 0-12 space specified by the access-list entry. When bit 6 is
of an access-list-entry number (bits 16-28 of an zero, both fetch-type and store-type references are
access-list-entry token) to determine whether the permitted. When bit 6 is one, only fetch-type refer-
access-list-entry number designates an entry in the ences are permitted, and an attempt to store causes
access list. a protection exception for access-list-controlled pro-
tection to be recognized and the operation to be sup-
Bit 0 is reserved for a possible future extension and pressed.
should be zero.
Private Bit (P): Bit 7, when zero, specifies that any
Programming Note: The maximum number of program is authorized to use the access-list entry in
access-list entries allowed by an access-list designa- access-register translation. When bit 7 is one, autho-
tion is 1,024. There are two access lists available for rization is determined as described for bits 16-31.
use at any time. Therefore, a maximum of 2,048 16E-
byte address spaces can be addressable without Access-List-Entry Sequence Number (ALESN):
control-program intervention, which is a total of 2
75 Bits 8-15 are compared against the ALESN in the
bytes. ALET during access-register translation. Inequality
causes an ALE-sequence exception to be recog-
nized. It is intended that the control program change
Access-List Entries bits 8-15 each time it reallocates the access-list
The effective access list is the dispatchable-unit entry.
access list if bit 7 of the ALET being translated is
zero, or it is the primary-space access list if bit 7 is Access-List-Entry Authorization Index
(ALEAX): Bits 16-31 may be used to determine
whether the program for which access-register trans-
lation is being performed is authorized to use the
access-list entry. The program is authorized if any of
the following conditions is met:
1. Bit 7 is zero.
(x 128) (x 16)
1
Control Register 7
+
SASCE
Access List
=?
=0 if
store? =0?
Control Register 8
EAX
=?
=?
ASN-Second-Table Entry
/
(x 1/4) I ATO ATL ASCE ASTESN
/
(x 4)
+
Authority ALB
Table
2
3
P S S=1?
Obtained ASCE
Explanation:
1 The appropriate ALD is obtained:
When P in the ALET is zero (and the ALET is not zero or one), the DUALD in the DUCT is obtained.
When P in the ALET is one, the PSALD in the primary ASTE is obtained.
2 Information, which may include the ALD-source origin, ALET, ALO, and EAX, is used to search the ALB. This information, along with information
from the ALE, ASTE, and ATE, may be placed in the ALB.
3 The appropriate ASCE is obtained:
When the ALET is zero, the PASCE in CR 1 is obtained.
When the ALET is one, the SASCE in CR 7 is obtained.
When the ALET is larger than one:
- If a match exists, the ASCE from the ALB is used.
- If no match exists, tables from real or absolute storage are fetched. The resulting ASCE from the ASTE is obtained, and entries may be formed
in the ALB.
When bit 0 is zero, the ASTE sequence number When the private bit is one, the ALEAX is not equal
(ASTESN) in bit positions 160-191 of the ASTE is to the EAX, and the secondary bit in the authority-
compared against the ASTESN in bit positions table entry selected by the EAX is not one, an
96-127 of the access-list entry to determine whether extended-authority exception is recognized, and the
the addressing capability represented by the access- operation is nullified.
list entry has been revoked. Inequality causes an
ASTE-sequence exception to be recognized and the
operation to be nullified.
An access-list designation is attached to a CPU An ALB ALE may be used for a particular instance of
when the designation is within the dispatchable-unit access-register translation when all of the following
control table designated by the dispatchable-unit- conditions are met:
control-table origin in control register 2 or is within
the primary ASTE designated by the primary-ASTE 1. The ALET to be translated has a value larger
origin in control register 5. than 1. (If the ALET is 0 or 1, the contents of CR
1 or CR 7 are used.)
An access-list entry is attached to a CPU when the 2. The ALO field in the ALB ALE matches the ALO
entry is within the access list specified by either an field in the ALD or ALB ALD being used in the
attached access-list designation (ALD) or a usable translation.
ALB ALD. A usable ALB ALD is explained in the next
section. 3. The ALEN field in the ALB ALE matches the
ALEN field in the ALET to be translated.
An ASN-second-table entry is attached to a CPU
when it is designated by the ASTE origin in either an An ALB ASTE is in the usable state when the ASTEO
attached and valid access-list entry (ALE) or a usable field in the ALB ASTE matches the ASTEO field in an
ALB ALE. A usable ALB ALE is explained in the next attached and valid ALE or a usable ALB ALE.
section.
An ALB ASTE may be used for a particular instance
An authority-table entry is attached to a CPU when it of access-register translation when the ASTEO field
is within the authority table designated by either an in the ALB ASTE matches the ASTEO field in the
attached and valid ASN-second-table entry (ASTE) ALE or ALB ALE being used in the translation.
or a usable ALB ASTE. A usable ALB ASTE is
explained in the next section. An ALB ATE may be used for a particular instance of
access-register translation when both of the following
Use of ALB Entries conditions are met:
The usable state of an ALB entry denotes that the
CPU can attempt to use the ALB entry for access- 1. The ATO field in the ALB ATE matches the ATO
register translation. A usable ALB entry attaches the field in the ASTE or ALB ASTE being used in the
next-lower-level table, if any, and may be usable for a translation.
particular instance of access-register translation. 2. The EAX field in the ALB ATE matches the cur-
rent EAX.
An ALB ALD is in the usable state when the ALDSO
field in the ALB ALD matches the current dispatch-
able-unit-control-table origin or the current primary- Modification of ART Tables
ASTE origin. When an attached but invalid ART-table entry is
made valid, or when an unattached but valid ART-
If ASN-and-LX Reuse Is Not Enabled Authorization Index (AX): Bits 32-47 are not used
LTD by BRANCH IN SUBSPACE GROUP.
V LTO LTL
Authority-Table Length (ATL): Bits 48-59 are not
192 217 223
used by BRANCH IN SUBSPACE GROUP.
If ASN-and-LX Reuse Is Enabled
LFTD Controlled-ASN Bit (CA): Bit 62 is not used by
V LFTO LFTL BRANCH IN SUBSPACE GROUP.
192 216 223
Reusable-ASN Bit (RA): Bit 63 is not used by
Available for programming BRANCH IN SUBSPACE GROUP.
224 255
Access-List Designation (ALD): When this ASTE Programming Note: All unused fields in the ASTE,
is designated by the primary-ASTE origin in control including the unused fields in bytes 0-31 and all of
register 5, bits 128-159 are the primary-space bytes 32-63, should be set to zeros. These fields are
access-list designation (PSALD). During access-reg- reserved for future extensions, and programs which
ister translation when the primary-list bit, bit 7, in the place nonzero values in these fields may not operate
ALET being translated is one, the PSALD is the compatibly on future machines.
effective access-list designation.
Key-controlled protection does not apply to any 2. A branch-type linkage mechanism that uses the
accesses to the DUCT or subspace ASTE. linkage stack.
A space-switching operation occurs when the For PROGRAM RETURN, a space-switching opera-
address-space number (ASN) specified in the entry- tion occurs when the restored primary ASN is not
table entry is nonzero. When space switching occurs, equal to the primary ASN existing before the opera-
Each of the header entry, trailer entry, and state entry When, during the unstacking process in PROGRAM
has a common eight-byte area at its end, called the RETURN, the current linkage-stack entry is a state
entry descriptor. The linkage-stack-entry address in entry, the process operates on that entry and then
control register 15 designates the leftmost byte of the updates the linkage-stack-entry address so that it
entry descriptor of the last linkage-stack entry, other designates the entry descriptor of the preceding
than the trailer entry, in a linkage-stack section. This entry in the same linkage-stack section. The preced-
entry is called the current linkage-stack entry, and the ing entry thus becomes the current entry. The new
section is called the current linkage-stack section. current entry may be another state entry, or it may be
a header entry.
Each entry descriptor in a linkage-stack section,
except the one in the trailer entry of the section, The header entry of a linkage-stack section indicates
includes a field that specifies the amount of space whether there is a preceding section. If there is a pre-
existing between the end of the entry descriptor and ceding section, the header entry contains the
the beginning of the trailer entry. This field is named address of the last linkage-stack entry, other than the
the remaining-free-space field. The remaining-free- trailer entry, in the preceding section. That last entry
space field in a trailer entry is unused. should be a state entry (not another header entry),
unless there is an error in the linkage stack.
When a new state entry is to be formed in the linkage
stack during the stacking process, the new entry is If the unstacking process is performed when the cur-
placed immediately after the entry descriptor of the rent linkage-stack entry is a header entry, and if the
current linkage-stack entry, provided that there is header entry indicates that a preceding linkage-stack
enough remaining free space in the current linkage- section exists, the unstacking process proceeds by
stack section to contain the new entry. If there is not treating the entry designated in the preceding section
enough remaining free space in the current section, as if it were the current entry, provided that this entry
and if the trailer entry in the current section indicates is a state entry. If the header entry does not indicate
that another section follows the current section, the a preceding section, or if the entry designated in the
new entry is placed immediately after the entry preceding section is not a state entry, an exception is
descriptor of the header entry of that following sec- recognized.
tion, provided that there is enough remaining free
space in that section. If the trailer entry indicates that When the unstacking process is performed in
there is not a following section, an exception is recog- EXTRACT STACKED REGISTERS, EXTRACT
nized, and a program interruption occurs. It is then STACKED STATE, or MODIFY STACKED STATE, the
the responsibility of the control program to allocate process locates a state entry but does not change
another section, chain it to the current section, and the linkage-stack-entry address in control register 15.
cause the BRANCH AND STACK or stacking PRO-
GRAM CALL instruction to be reexecuted. If there is Each entry descriptor in a linkage-stack section
a following section but there is not enough remaining includes a field that specifies the length of the next
free space in it, an exception is recognized. linkage-stack entry, other than the trailer entry, in the
section. When a state entry is created during the
If the remaining-free-space value that is used to stacking process, zeros are placed in this field in the
locate a trailer entry is not a multiple of 8, an excep- created entry, and the length of the state entry is
tion is recognized. The remaining-free-space value in placed in this field in the preceding entry. When a
the header entry of a linkage-stack section must be state entry is logically deleted during the unstacking
set to a multiple of 8 to ensure that the remaining- process in PROGRAM RETURN, zeros are placed in
free-space value that may be used to locate the this field in the preceding entry. This field is named
trailer entry of the section will be a multiple of 8. the next-entry-size field.
When the stacking process is successful in forming a When the stacking or unstacking process operates
new state entry, it updates the linkage-stack-entry on the linkage stack, key-controlled protection does
The fields in the first eight bytes of the header entry Entry Descriptor (Part 2)
96 127
are allocated as follows:
Backward Stack-Entry Validity Bit (B): Bit 63 The fields in the first eight bytes of the trailer entry
when one, specifies that the preceding linkage-stack are allocated as follows:
section is available and that the backward stack-entry
address, bits 0-60 is valid. Bit 63 is set to one during Forward-Section Validity Bit (F): Bit 63 when
the stacking process when the process proceeds to one, specifies that the next linkage-stack section is
this section from the preceding one because there is available and that the forward-section-header
not enough space available in the preceding section address, bits is valid. During the stacking process
to perform the process. During the unstacking pro- when there is not enough space available in the cur-
cess when this header entry is the current linkage- rent linkage-stack section to perform the process, a
If the PROGRAM CALL operation was the to-current- All zeros are placed in bytes 160-167 by BRANCH
primary operation, the CSI is all zeros. AND STACK and stacking PROGRAM CALL.
The current linkage-stack entry is a state entry. If the Updating the Preceding Entry
unstack-suppression bit in the entry is one, a stack- Zeros are stored in the next-entry-size field, bits
operation exception is recognized, and the operation 32-47, of the entry descriptor of the preceding link-
is nullified. age-stack entry. The remainder of the preceding
entry remains unchanged. The address of the entry
When there is not an exception due to the unstack- descriptor of the preceding entry is determined by
suppression bit, a portion of the contents of the cur- subtracting the size in bytes of the current entry from
rent linkage-stack entry are restored to the CPU reg- the address of the entry descriptor of the current
isters. The contents of general registers 2-14 and entry.
access registers 2-14 are restored to those registers
from where they were saved in the current entry by The order of the store into the preceding entry and
the stacking process. When the entry-type code in the fetches from the current entry is unpredictable.
the current entry is 0001101 binary, indicating a pro-
gram-call state entry, the PSW-key mask and sec- Updating Control Register 15
ondary ASN in control register 3, extended Bits 0-60 of the 64-bit home virtual address of the
authorization index in control register 8, and primary entry descriptor of the preceding linkage-stack entry
ASN in control register 4 are similarly restored. Dur- are placed in bit positions 0-60 of control register 15,
ing this restoration, the authorization index in control the linkage-stack-entry address. Zeros are placed in
register 4 and the monitor masks and enhanced- bit positions 61-63 of control register 15. Thus, the
monitor masks in control register 8 remain
Any change to the storage key appears to be com- Figure 5-13 on page 5-88 summarizes the cases of
pleted before the conceptually following reference to overlap and the specified results, including when
the associated storage block is made, regardless of
Effective space designations may be represented by 3. In the access-register mode, different address
ALB entries, and the test for whether two effective spaces may be selected by means of each
space designations are the same may be performed access register. In addition, the primary address
by comparing ALB entries. If the program changes space is selected for instruction fetching and the
an attached and valid ART-table entry without subse- target of an execute-type instruction.
quently causing the execution of PURGE ALB or a
COMPARE AND SWAP AND PURGE instruction that 4. STORE USING REAL ADDRESS performs a
purges the ALB, two effective space designations store by means of a real address.
that are the same may have different representations 5. Certain other instructions also use real
in the ALB, and failure to recognize operand overlap addresses (even when a logical address is not
may result. The use of the ALB never causes overlap translated by means of a real-space designation,
to be recognized when the effective space designa- which is a situation covered in case 1), and the
tions are different. instructions MOVE TO PRIMARY and MOVE TO
SECONDARY access two address spaces.
Programming Note:
6. Accesses to storage for the purpose of storing
A single main-storage location can be accessed by and fetching information for interruptions is per-
means of more than one address in several ways: formed by means of real addresses, and, for the
store-status function, by means of absolute
1. The DAT tables may be set up such that multiple addresses, whereas accesses by the program
addresses in a single address space, or may be by means of virtual addresses.
addresses in different address spaces, including
the real address specified by a real-space desig- 7. The real-to-absolute mapping may be changed
nation, map to a single real address. by means of the SET PREFIX instruction or a
reset.
2. The translation of logical, instruction, and virtual
addresses may be changed by loading the DAT 8. A main-storage location may be accessed by
parameters in the control registers, by changing channel programs by means of an absolute
the address-space-control bits in the PSW, or, for address and by the CPU by means of an abso-
logical and instruction addresses, by turning DAT lute, a real, or a virtual address.
on or off. 9. A main-storage location may be accessed by
another CPU by means of one type of address
The primary purpose of this section on interlocks is Instructions are not necessarily fetched in the
to describe the effects caused in cases 1, 3, and 4, sequence in which they are conceptually executed
above. and are not necessarily fetched each time they are
executed. In particular, the fetching of an instruction
For case 2, no effect is observable because may precede the storage-operand references for an
prefetched instructions are discarded when the trans- instruction that is conceptually earlier. The instruction
lation parameters are changed, and the delay of fetch occurs prior to all storage-operand references
stores by a CPU is not observable by the CPU itself. for all instructions that are conceptually later.
For case 5, for those instructions which fetch by An instruction may be prefetched by using a virtual
using real addresses (for example, LOAD REAL address only when the associated DAT table entries
ADDRESS, which fetches a segment-table entry and are attached and valid or when entries which qualify
a page-table entry, and may fetch a region-table for substitution for the table entries exist in the TLB.
entry), no effect is observable because only operand An instruction that has been prefetched may be inter-
accesses between instructions are involved. All preted for execution only for the same virtual address
instructions that store by using a real address, except for which the instruction was prefetched.
STORE USING REAL ADDRESS, or that store
across address spaces, except in the access-register No limit is established on the number of instructions
mode, cause prefetched instructions to be discarded, which may be prefetched, and multiple copies of the
and no effect is observable. contents of a single storage location may be fetched.
As a result, the instruction executed is not necessar-
Cases 6 and 7 are situations which are defined to ily the most recently fetched copy. Storing caused by
cause serialization, with the result that prefetched other CPUs and by channel programs does not nec-
instructions are discarded. In these cases, no effect essarily change the copy of prefetched instructions.
is observable. However, if a store that is conceptually earlier is
made by the same CPU using the same effective
The handling of cases 8 and 9 involves accesses as address as that by which the instruction is subse-
observed by other CPUs and by channel programs quently fetched, the updated information is obtained,
and is covered in the following sections in this chap- except as noted below. If the effective addresses are
ter. different, the updated information is not necessarily
obtained. However, the updated information is
obtained if either execution is in the real mode since
Instruction Fetching prefetched instructions are discarded if DAT is turned
on or off.
Instruction fetching consists in fetching the one, two,
or three halfwords designated by the instruction All copies of prefetched instructions are discarded
address in the current PSW. The immediate field of when:
an instruction is accessed as part of an instruction
fetch. If, however, an instruction designates a storage • A serializing function is performed. However, for
operand at the location occupied by the instruction PROGRAM TRANSFER, PROGRAM TRANS-
itself, the location is accessed both as an instruction FER WITH INSTANCE, SET SECONDARY ASN,
and as a storage operand. The fetch of the target SET SECONDARY ASN WITH INSTANCE, and
instruction of an execute-type instruction is consid- TRACE, it is unpredictable whether or not a store
ered to be an instruction fetch. into a trace-table entry from which a subsequent
instruction is fetched will be observed by the
The bytes of an instruction may be fetched piecemeal CPU that performed the store; for PROGRAM
and are not necessarily accessed in a left-to-right CALL and PROGRAM RETURN it is unpredict-
direction. The instruction may be fetched multiple able whether or not a store into a trace-table
times for a single execution; for example, it may be entry or linkage-stack entry from which a subse-
fetched for testing the addressability of operands or quent instruction is fetched will be observed by
the CPU that performed the store. Additionally,
When enhanced DAT applies and the storage is • The store was performed by a CPU and is or
accessed by means of a segment-table entry in will be completed, and any CPU in the con-
which both the STE-format control and ACCF- figuration executes a COMPARE AND SWAP
validity control are one, it is unpredictable AND PURGE, INVALIDATE DAT TABLE
whether bits 0-4 of the storage key or bits 48-52 ENTRY, or INVALIDATE PAGE TABLE
of the segment-table entry provide the access- ENTRY instruction that clears from the ALB
control bits and fetch-protection bit. Furthermore, or TLB of the storing CPU any entry used to
when the segment-table entry provides the complete the store. Completion of the clear-
access-control bits and fetch-protection bit, a ing instruction is delayed until the subject
buffered copy from the translation-lookaside store and change-bit setting have been com-
buffer may be used. pleted.
For accesses made by the channel subsystem, • The store was performed by a CPU, and that
the access-control bits and fetch-protection bits CPU examines the subject change bit by
are in bits 0-4 of the storage key for the 4K-byte means of an INSERT STORAGE KEY
block. EXTENDED or RESET REFERENCE BIT
EXTENDED instruction. See “Relation
2. When storing is performed by a CPU, the change between Operand Accesses” on page 5-98.
bit is set to one in the associated storage key
concurrently with the completion of the store When enhanced DAT applies, and either (a) the
access, as observed by the CPU itself. When STE-format control is zero, and the change-
storing is performed by a CPU or a channel pro- recording override is one in the page-table entry
gram, the change bit is set to one in the associ- used by DAT, or (b) the STE-format control is
ated storage key either before or after the one, and the change-recording override is one in
completion of the store access, as observed by the segment-table entry used by DAT, it is unpre-
other (if the store was performed by a CPU) or all dictable whether the CPU sets the change bit
(if the store was performed by a channel pro- when performing a store operation. The change-
gram) CPUs. As observed by other or all CPUs, recording override may be buffered in the transla-
the change bit is set no earlier than (1) after the tion-lookaside-buffer copy of the PTE or STE.
The CPU does not fetch operands, ART-table entries, • ADD IMMEDIATE (ASI and AGSI), when the
or DAT-table entries from a storage location until all interlocked-update facility is installed and the first
information destined for that location by the CPU has operand is aligned on an integral boundary cor-
been stored. Prefetched instructions may appear to responding to its size
be updated before the information appears in stor- • ADD LOGICAL WITH SIGNED IMMEDIATE,
age. when the interlocked-update facility is installed
1. The first operand is accessed in a left-to-right The operands of COMPARE LOGICAL STRING
direction, and all bytes accessed within a double- appear to be accessed doubleword concurrent, as
word appear to be accessed concurrently as observed by other CPUs, when both operands start
observed by other CPUs. on doubleword boundaries. The operands of
SEARCH STRING and SEARCH STRING UNI-
2. The second operand is accessed in a left-to-right CODE appear to be accessed doubleword concur-
direction, and all bytes within a doubleword in the rent, as observed by other CPUs, when it starts on a
second operand that are moved into a single doubleword boundary.
doubleword in the first operand appear to be
fetched concurrently as observed by other CPUs. For EXCLUSIVE OR (XC), the operands are pro-
Thus, if the first and second operands begin on cessed in a left-to-right direction, and, when the first
the same byte offset within a doubleword, the and second operands coincide, all bytes accessed
fetch of the second operand appears to be dou- within a doubleword appear to be accessed concur-
bleword concurrent as observed by other CPUs. rently as observed by other CPUs.
If the offsets within a doubleword differ by 4, the
fetch of the second operand appears to be word Programming Note: In the case of EXCLUSIVE OR
concurrent as observed by other CPUs. (XC) designating operands which coincide exactly,
the bytes within the field may appear to be accessed
Destructive overlap is said to exist when the result as many as three times, by two fetches and one
location is used as a source after the result has been store: once as the fetch portion of the first operand
stored, assuming processing to be performed one update, once as the second-operand fetch, and then
byte at a time. once as the store portion of the first-operand update.
Each of the three accesses appears to be double-
The operands of MOVE WITH SOURCE KEY, MOVE word concurrent as observed by other CPUs, but the
WITH DESTINATION KEY, and MOVE STRING are three accesses do not necessarily appear to occur
accessed the same as those of MOVE (MVC), except one immediately after the other. One or both fetch
that destructive overlap is assumed not to exist. accesses may be omitted since the instruction can
be completed without fetching the operands.
Except as noted in the individual instruction descrip-
tions, accesses to operands of MOVE LONG, MOVE
LONG EXTENDED, and MOVE LONG UNICODE do Relation between Operand
not necessarily appear to occur in a left-to-right Accesses
direction as observed by other CPUs and by channel
programs. The operands of these instructions do
As observed by other CPUs and by channel pro-
appear to be accessed doubleword concurrent, as
grams, storage-operand fetches associated with one
observed by other CPUs, when all of the following
instruction execution appear to precede all storage-
are true:
operand references for conceptually subsequent
instructions. A storage-operand store specified by
• Both operands start on doubleword boundaries
one instruction appears to precede all storage-oper-
and are an integral number of doublewords in
and stores specified by conceptually subsequent
length.
instructions, but it does not necessarily precede stor-
• The operands do not overlap. age-operand fetches specified by conceptually sub-
sequent instructions. However, a storage-operand
• The nonpadding part of the operation is being store appears to precede a conceptually subsequent
executed. storage-operand fetch from the same main-storage
location.
The operands of COMPARE LOGICAL LONG, COM-
PARE LOGICAL LONG EXTENDED, and COMPARE When an instruction has two storage operands both
LOGICAL LONG UNICODE appear to be accessed of which cause fetch references, it is unpredictable
doubleword concurrent, as observed by other CPUs, which operand is fetched first, or how much of one
I Size % 2 J
counter array in the home address space.
I Size % 4 J
occurs regardless of whether DAT is on. The access
to the counters may be performed with the use of the
translation-lookaside buffer (TLB), and TLB entries
may be formed, regardless of whether DAT is on.
0 16 32 48 64 80 96 112 127
The enhanced-monitor-counter-array-size field at
real location 264 specifies the number of halfword Explanation:
and word entries in the array; the halfword entries in
the array appear first, followed immediately by the CAO Enhanced-monitor counter-array origin
word entries. CAL Enhanced-monitor counter-array size
EC Enhanced-monitor exception count
The monitor code multiplied by two is added to the Figure 5-14. Monitor-Event-Counting Structures
enhanced-monitor counter-array origin to form the
virtual address of a halfword to which one is logically Programming Notes:
added. If this addition results in a carry out of bit posi-
tion 0 of the halfword, then one is logically added to 1. It is recommended that the enhanced-monitor
the corresponding word. The enhanced-monitor- counter array be allocated on a cache-line
counter-array-size value multiplied by two is added to boundary of the CPU’s first-level data cache. The
the monitor code multiplied by four; this value is cache line size may be determined by the
added to the enhanced-monitor counter-array origin EXTRACT CACHE ATTRIBUTES (ECAG)
to form the address of the word. Any carry in the instruction.
word addition is ignored.
2. The enhanced-monitor counters may be incre-
Key-controlled protection does not apply to any mented using a non-interlocked update. There-
accesses made in the process of incrementing the fore, each enhanced-monitor counter array
counters. Any other access exception recognized in should be processor unique.
the process of incrementing the counters results in
3. It is recommended that the enhanced-monitor-
(a) one being logically added to the enhanced-moni-
counter-array be allocated in fixed storage such
tor exception count contained in the word at real
The interruption mechanism permits the CPU to the CPU itself. To permit fast response to conditions
change its state as a result of conditions external to of high priority and immediate recognition of the type
the configuration, within the configuration, or within of condition, interruption conditions are grouped into
Mask Bits in
PSW- Control
Mask Registers ILC Execution of Instruction
Source Identification Interruption Code Bits Reg Bit Set Identified by Old PSW
MACHINE CHECK Locations 232-2391
(old PSW 352,
new PSW 480)
Exigent condition 13 u terminated or nullified2
Repressible condition 13 14 35-39 u unaffected2
SUPERVISOR CALL Locations 138-139
(old PSW 320,
new PSW 448)
Instruction bits 00000000 ssssssss 1, 2, 3 completed
PROGRAM Locations 142-143
(old PSW 336,
new PSW 464) Binary Hex3
Operation 00000000 p0000001 0001 1, 2, 3 suppressed
Privileged operation 00000000 p0000010 0002 2, 3 suppressed
Execute 00000000 p0000011 0003 2, 3 suppressed
Protection 00000000 p0000100 0004 1, 2, 3 suppressed or terminated
Addressing 00000000 p0000101 0005 1, 2, 3 suppressed or terminated
Specification 00000000 p0000110 0006 0, 1, 2, 3 suppressed or completed
Data 00000000 p0000111 0007 1, 2, 3 suppressed, terminated
or completed
Fixed-point overflow 00000000 p0001000 0008 20 1, 2, 3 completed
Fixed-point divide 00000000 p0001001 0009 1, 2, 3 suppressed or completed
Decimal overflow 00000000 p0001010 000A 21 2, 3 completed
Decimal divide 00000000 p0001011 000B 2, 3 suppressed
HFP exp. overflow 00000000 p0001100 000C 1, 2, 3 completed
HFP exp. underflow 00000000 p0001101 000D 22 1, 2, 3 completed
Figure 6-1. Interruption Action (Part 1 of 3)
For machine-check interruptions, the interruption 1. Mask bits in the PSW provide a means of disal-
code consists of 64 bits and is stored at real locations lowing most maskable interruptions; thus, subse-
232-239. Additional information for identifying the quent interruptions can be disallowed by the new
cause of the interruption and for recovering the state PSW introduced by an interruption. Furthermore,
of the machine may be provided by the contents of the mask bits can be used to establish a hierar-
the machine-check failing-storage address and the chy of interruption priorities, where a condition in
contents of the fixed-logout and machine-check-save one class can interrupt the program handling a
areas. (See Chapter 11, “Machine-Check Handling.”) condition in another class but not vice versa. To
prevent an interruption-handling routine from
For program interruptions, the interruption code is being interrupted before the necessary house-
stored at real locations 142-143, and the instruction- keeping steps are performed, the new PSW must
length code is stored in bit positions 5 and 6 of real disable the CPU for further interruptions within
location 141. Further information may be provided in the same class or within a class of lower priority.
the form of the data-exception code (DXC), monitor-
class number, PER code, addressing-and-transla- 2. Because the mask bits in control registers are
tion-mode identification, PER address, exception not changed as part of the interruption proce-
access identification, PER access identification, dure, these masks cannot be used to prevent an
operand-access identification, translation-exception interruption immediately after a previous inter-
identification, and monitor code, which are stored at ruption in the same class. The mask bits in con-
real locations 144-162 and 168-183. trol registers provide a means for selectively
enabling the CPU for some sources and dis-
abling it for others within the same class.
Enabling and Disabling
3. Controlling bits exist for several program interrup-
tions, but with no mask bit in the PSW. Such bits
By means of mask bits in the current PSW, floating-
include the IEEE mask bits in the FPC register,
point-control (FPC) register, and control registers, the
the monitor masks in bit positions 48-63 of con-
CPU may be enabled or disabled for all external, I/O,
trol register 8, and the primary space-switch-
and machine-check interruptions and for some pro-
event-control bits, bit 57 of control registers 1 and
gram interruptions. When a mask bit is one, the CPU
13, respectively. A bit of this nature is somewhat
is enabled for the corresponding class of interrup-
arbitrarily considered to be a “mask” bit only if the
tions, and those interruptions can occur.
Thus, for example, the SSM-suppression-control The ILC for program and supervisor-call interruptions
bit, bit 33 of control register 0, is considered to be is stored in bit positions 5 and 6 of the bytes at real
a mask bit, while the AFP-register-control bit, bit locations 141 and 137, respectively. For external, I/O,
45 of control register 0, is not. Regardless of the machine-check, and restart interruptions, the ILC is
polarity of such control bits, to avoid another pro- not stored since it cannot be related to the length of
gram interruption, an interruption-handling rou- the last-executed instruction.
tine must avoid issuing instructions subject to
these bits until they have been set appropriately. For supervisor-call and program interruptions, a non-
The enhanced-monitor masks in bit positions zero ILC identifies in halfwords the length of the
16-31 of control register 8 are an exception to the instruction that was last executed. That instruction
above definition of a mask in that they work in may be one for which a specification exception was
conjunction with the monitor masks in bit posi- recognized due to an odd instruction address or for
tions 48-63 of control register 8. When both a which an access exception (addressing, ASCE-type,
monitor mask bit and its corresponding page-translation, protection, region-translation, seg-
enhanced-monitor mask bit are one, a monitor- ment-translation, or translation-specification) was
event counting operation occurs rather than an recognized during the fetching of the instruction.
interruption. Whenever an instruction is executed by means of
EXECUTE, instruction-length code 2 is set to indi-
cate the length of EXECUTE and not that of the tar-
Handling of Floating Interruption get instruction. Similarly, when an instruction is
Conditions executed by means of EXECUTE RELATIVE LONG,
instruction length code 3 is set.
An interruption condition which can be presented to The value of a nonzero instruction-length code is
any CPU in the configuration is called a floating inter- related to the leftmost two bits of the instruction. The
ruption condition. The condition is presented to the value does not depend on whether the operation
first CPU in the configuration which is enabled for the code is assigned or on whether the instruction is
corresponding interruption and which can perform installed. The following table summarizes the mean-
the interruption, and then the condition is cleared and ing of the instruction-length code:
not presented to any other CPU in the configuration.
A CPU cannot perform the interruption when it is in
ILC Instruction
the check-stop state, has an invalid prefix, is in a Instruction Length
Decimal Binary Bits 0-1
string of program interruptions due to a specification
exception of the type which is recognized early or is 0 00 Not available
in the stopped state. However, a CPU with the rate 1 01 00 One halfword
control set to instruction step can perform the inter- 2 10 01 Two halfwords
ruption when the start key is activated. 2 10 10 Two halfwords
3 11 11 Three halfwords
Service signal, I/O, and certain machine-check con-
ditions are floating interruption conditions.
Zero ILC
Instruction-length code 0, after a program interrup-
Instruction-Length Code tion (other than for an instruction-fetching nullification
event), indicates that the instruction address stored
The instruction-length code (ILC) occupies two bit in the old PSW does not identify the instruction caus-
positions and provides the length of the last instruc- ing the interruption. In the case of a program inter-
tion executed. It permits identifying the instruction ruption due to an instruction-fetching nullification
causing the interruption when the instruction address event, the ILC is set to zero. The remainder of this
in the old PSW designates the next sequential section discusses zero ILC due to cases other than
instruction. The ILC is provided also by the BRANCH for instruction-fetching nullification events.
In the case of a PROGRAM RETURN instruction that 1. A nonzero instruction-length code for a program
causes both a space-switch event and a PSW-format interruption indicates the number of halfword
error, the space-switch event is recognized, but it is locations by which the instruction address in the
unpredictable whether the ILC is 0 or 1, or 0 or 2 if program old PSW must be reduced to obtain the
EXECUTE was used, or 0 or 3 if EXECUTE RELA- instruction address of the last instruction exe-
TIVE LONG was used. cuted, unless one of the following situations
exists:
ILC on Instruction-Fetching Exceptions a. The interruption is caused by an exception
When a program interruption occurs because of an resulting in nullification.
exception that prohibits access to the instruction, the
instruction is considered to have been executed with- b. An interruption for a PER event occurs
out being fetched, and the instruction-length code before the execution of an interruptible
cannot be set on the basis of the first two bits of the instruction is completed, and no other pro-
instruction. As far as the significance of the ILC for gram-interruption condition is indicated con-
this case is concerned, the following two situations currently.
are distinguished:
c. The interruption is caused by a PER event or
1. When an odd instruction address causes a spec- space-switch event due to LOAD PSW,
ification exception to be recognized or when an LOAD PSW EXTENDED, or a branch or link-
addressing, protection, or translation-specifica- age instruction, including SUPERVISOR
tion exception is encountered on fetching an CALL (but not including MONITOR CALL).
instruction, the ILC is set to 1, 2, or 3, indicating
the multiple of 2 by which the instruction address d. The interruption is caused by an addressing
has been incremented. It is unpredictable exception or protection exception for the stor-
whether the instruction address is incremented age operand of a LOAD CONTROL instruc-
by 2, 4, or 6. By reducing the instruction address tion that loads the control register (1 or 13)
in the old PSW by the number of halfword loca- containing the address-space-control ele-
tions indicated in the ILC, the instruction address ment that specifies the address space from
originally appearing in the PSW may be which instructions are fetched.
obtained. For situations a and b above, the instruction
2. When an ASCE-type, region-translation, seg- address in the PSW is not incremented, and the
ment-translation, or page-translation exception is instruction designated by the instruction address
recognized while fetching an instruction, the ILC is the same as the last one executed. These situ-
For situation c, the instruction address has been For situation c, the address of the last instruction
replaced as part of the operation, and the executed is available, but the corresponding real
address of the last instruction executed cannot address is unknown.
be calculated using the one appearing in the pro- 4. The address of the last instruction executed is
gram old PSW. not available when an interruption is caused by
For situation d, the effective address of the last an early specification exception due to a LOAD
instruction executed can be calculated, but, since PSW, LOAD PSW EXTENDED, or PROGRAM
the address-space-control element for the RETURN instruction or an interruption.
instruction address space is unpredictable, the
corresponding real address is unknown. Exceptions Associated with the
2. The instruction-length code (ILC) is redundant PSW
when a PER event is indicated since the PER
address in the doubleword at real location 152 Exceptions associated with erroneous information in
identifies the instruction causing the interruption the current PSW may be recognized when the infor-
(or the execute-type instruction, as appropriate). mation is introduced into the PSW or may be recog-
Similarly, the ILC is redundant when the opera- nized as part of the execution of the next instruction.
tion is nullified, since in this case the instruction Errors in the PSW which are specification-exception
address in the PSW is not incremented. If the conditions are called PSW-format errors.
ILC value is required in this case, it can be
derived from the operation code of the instruction
identified by the old PSW.
Early Exception Recognition
For the following error conditions, a program interrup-
3. The address of the last instruction executed tion for a specification exception occurs immediately
before a program interruption is insufficient to after the PSW becomes active:
locate the program problem if one of the following
• Any of the unassigned bits (0, 2-4, 24-30, or
situations exists:
33-63) is a one.
a. The interruption is caused by an access
exception encountered in fetching an instruc- • Bit 12 is a one.
tion, and the instruction address was intro- • Bits 31 and 32 are zero and one, respectively,
duced into the PSW by a means other than and bits 64-96 are not all zeros.
sequential operation (by a branch or linkage
instruction, LOAD PSW, LOAD PSW • Bits 31 and 32 are both zero, and bits 64-103 are
EXTENDED, an interruption, or conclusion of not all zeros.
an IPL sequence).
• Bits 31 and 32 are one and zero, respectively.
b. The interruption is caused by a specification
exception due to an odd instruction address, The interruption occurs regardless of whether the
which necessarily also results from introduc- wait state is specified. If the invalid PSW causes the
tion of an instruction address into the PSW. CPU to become enabled for a pending I/O, external,
or machine-check interruption, the program interrup-
c. The interruption is caused by an early speci- tion occurs instead, and the pending interruption is
fication exception due to a STORE THEN subject to the mask bits of the new PSW introduced
OR SYSTEM MASK or SET SYSTEM MASK by the program interruption.
instruction that switches to or from the real
The priorities for external-interruption requests in When the TOD-clock-steering facility is not installed,
descending order are as follows: and the TOD clock is set or changes state, interrup-
tion conditions, if any, that are due to the clock com-
• Interrupt key parator may or may not be recognized for up to
• Malfunction alert 1.048576 seconds after the change.
• Emergency signal
• External call When the TOD-clock-steering facility is installed and
• Clock comparator the physical clock is set or changes state, or the logi-
• CPU timer cal TOD clock is changed by PTFF-ATO or PTFF-
• Timing alert STO, the CPUs in the configuration do not necessar-
• Service signal ily recognize this change for purposes of clock com-
parator interruptions until one of the following
All requests are honored one at a time. When more instructions is issued: SET CLOCK COMPARATOR
than one emergency-signal request exists at a time (SCKC), STORE CLOCK (STCK), or STORE
or when more than one malfunction-alert request CLOCK EXTENDED (STCKE). If a CPU is in the wait
exists at a time, the request associated with the state when this change occurs, it may not recognize
smallest CPU address is honored first.
The subclass-mask bit is in bit position 52 of control Facilities are provided for holding a separate emer-
register 0. This bit is initialized to zero. gency-signal request pending in the receiving CPU
for each CPU in the configuration, including the
The clock-comparator condition is indicated by an receiving CPU itself.
external-interruption code of 1004 hex.
The subclass-mask bit is in bit position 49 of control
register 0. This bit is initialized to zero.
CPU Timer
The emergency-signal condition is indicated by an
An interruption request for the CPU timer exists external-interruption code of 1201 hex. The address
whenever the CPU-timer value is negative (bit 0 of of the CPU that executed the SIGNAL PROCESSOR
the CPU timer is one). If the value is made positive instruction is stored at real locations 132-133.
before the request is honored, the request does not
remain pending, and no interruption occurs. Con-
versely, the request is not cleared by the interruption, External Call
and, if the condition persists, more than one interrup-
tion may occur from a single occurrence of the condi- An interruption request for an external call is gener-
tion. ated when the CPU accepts the external-call order
specified by a SIGNAL PROCESSOR instruction
When the TOD-clock-steering facility is not installed, addressing this CPU. The instruction may have been
and the TOD clock is set or changes state, interrup- executed by this CPU or by another CPU in the con-
tion conditions, if any, that are due to the CPU timer figuration. The request is preserved and remains
may or may not be recognized for up to 1.048576 pending in the receiving CPU until it is cleared. The
seconds after the change. pending request is cleared when it causes an inter-
ruption and by CPU reset.
When the TOD-clock-steering facility is installed,
CPU timer interruptions may or may not be recog- Only one external-call request, along with the pro-
nized while the physical clock is in the stopped state. cessor address, may be held pending in a CPU at a
After the physical clock enters the set state, interrup- time.
tion conditions for the CPU timer are not necessarily
recognized until SET CPU TIMER (SPT) is issued. The subclass-mask bit is in bit position 50 of control
CPU timer interruptions are not affected by changes register 0. This bit is initialized to zero.
to the logical TOD clock.
The external-call condition is indicated by an exter-
The subclass-mask bit is in bit position 53 of control nal-interruption code of 1202 hex. The address of the
register 0. This bit is initialized to zero. CPU that executed the SIGNAL
The CPU-timer condition is indicated by an external- PROCESSOR instruction is stored at real locations
interruption code of 1005 hex. 132-133.
Emergency Signal
An interruption request for an emergency signal is Interrupt Key
generated when the CPU accepts the emergency-
signal order specified by a SIGNAL PROCESSOR An interruption request for the interrupt key is gener-
instruction addressing this CPU. The instruction may ated when the operator activates that key. The
have been executed by this CPU or by another CPU request is preserved and remains pending in the
in the configuration. The request is preserved and CPU until it is cleared. The pending request is
remains pending in the receiving CPU until it is cleared when it causes an interruption and by CPU
reset.
• Total-time offset (the combination of time-zone An I/O interruption causes the old PSW to be stored
offset and DST offset) at real locations 368-383 and a new PSW to be
• Leap seconds offset fetched from real locations 496-511.Additional infor-
• Time-zone offset mation, in the form of an eight-byte I/O-interruption
• Daylight-savings-time (DST) offset code, is stored at real locations 184-195. The I/O-
• Scheduled changes to any of the above interruption code consists of a 32-bit subsystem-
identification word, a 32-bit interruption parameter,
A 32-bit parameter is associated with the interruption and a 32-bit I/O-interruption identification word.
and is stored at real locations 128-131. The field is
defined as shown below: An I/O interruption can occur only while a CPU is
enabled for the interruption subclass presenting the
Bit Meaning request. The I/O-mask bit, bit 6 of the PSW, and the
I/O-interruption subclass mask in control register 6
0-13 Reserved
determine whether the CPU is enabled for a particu-
14 Timing-status change lar I/O interruption.
15 Link-availability change
I/O interruptions are grouped into eight I/O-interrup-
16 Time-control-parameter change
tion subclasses, numbered from 0-7. Each I/O-inter-
17-31 Reserved ruption subclass has an associated I/O-interruption
subclass-mask bit in bit positions 32-39 of control
Multiple alert conditions may be indicated concur- register 6. Each subchannel has an I/O-interruption
rently in the external-interruption parameter field. subclass value associated with it. The CPU is
enabled for I/O interruptions of a particular I/O-inter-
ruption subclass only when PSW bit 6 is one and the
I/O Interruption associated I/O-interruption subclass-mask bit in con-
trol register 6 is also one. If the corresponding I/O-
The input/output (I/O) interruption provides a means interruption subclass-mask bit is zero, then the CPU
by which the CPU responds to conditions originating is disabled for I/O interruptions with that subclass
in I/O devices and the channel subsystem. value. I/O interruptions for all subclasses are disal-
lowed when PSW bit 6 is zero.
The cause and severity of the malfunction are identi- The crypto-operation exception is indicated by an
fied by a 64-bit machine-check-interruption code interruption code of 0119 hex, or 0199 hex if a PER
stored at real locations 232-239. Further information event is also indicated.
identifying the cause of the interruption and the loca-
tion of the fault may be stored at real locations When there is a corresponding mask bit, a program
244-255 and 4608-5119. interruption can occur only when that mask bit is one.
The program mask in the PSW controls four of the
The interruption action and the storing of the associ- exceptions, the IEEE masks in the FPC register con-
ated information are under the control of PSW bit 13 trol the IEEE exceptions, bit 33 in control register 0
and bits in control register 14. See Chapter 11, controls whether SET SYSTEM MASK causes a spe-
“Machine-Check Handling” for more detailed informa- cial-operation exception, bits 48-63 in control register
tion. 8 control interruptions due to monitor events, and a
hierarchy of masks control interruptions due to PER
events. When any controlling mask bit is zero, the
Program Interruption condition is ignored; the condition does not remain
pending.
DXC 2 and 3 are mutually exclusive and are of higher 0C IEEE inexact and incremented
priority than any other DXC. Thus, for example, DXC 10 IEEE underflow, exact
2 (BFP instruction) takes precedence over any IEEE 13 Simulated IEEE underflow, exact
exception; and DXC 3 (DFP instruction) takes prece-
18 IEEE underflow, inexact and truncated
dence over any IEEE exception or simulated IEEE
exception. As another example, if the conditions for 1B Simulated IEEE underflow, inexact
both DXC 3 (DFP instruction) and DXC 1 (AFP regis- 1C IEEE underflow, inexact and incremented
ter) exist, DXC 3 is reported. 20 IEEE overflow, exact
23 Simulated IEEE overflow, exact
When both a specification exception and an AFP-
register data exception apply, it is unpredictable 28 IEEE overflow, inexact and truncated
which one is reported. 2B Simulated IEEE overflow, inexact
2C IEEE overflow, inexact and incremented
40 IEEE division by zero
43 Simulated IEEE division by zero
80 IEEE invalid operation
83 Simulated IEEE invalid operation
FF Compare-and-trap instruction
DXC DXC
Applicable Placed in Placed in
Instruction FPC FPC DXC Instruction Real FPC
Exception Types CR0.45 Mask Flag (Binary) Action Loc. 147 Byte 2
1
Decimal operand Decimal 0 none none 0000 0000 Suppress or Yes No
1 Terminate Yes Yes
AFP register FPS & HFP 0* none none 0000 0001 Suppress Yes No
BFP instruction BFP 0* none none 0000 0010 Suppress Yes No
DFP instruction DFP 0* none none 0000 0011 Suppress Yes No
2
IEEE invalid operation ICMP 1* 0.0 1.0 1000 0000 Suppress Yes Yes
2
IEEE division by zero ICMP 1* 0.1 1.1 0100 0000 Suppress Yes Yes
IEEE overflow ICMP 1* 0.2 1.2 0010 xy00 Complete Yes Yes
IEEE underflow ICMP 1* 0.3 1.3 0001 xy00 Complete Yes Yes
IEEE inexact ICMP 1* 0.4 1.4 0000 1y00 Complete Yes Yes
Programming Note: The data-exception code the first instruction that is subject to the AFP con-
(DXC) in bits 16-23 of the floating-point control regis- trol to be executed by the task.
ter (FPCR) is primarily intended for use by floating-
point applications that rely on the enablement of the This unpredictability is the result of the control pro-
advanced-floating-point (AFP) control, bit 45 of con- gram or task being dispatched with the AFP control
trol register 0. When a data-exception program inter- initially set to zero, and only applies to DXC 255 in
ruption occurs as a result of the execution of a the FPCR. Subsequent inspections of the DXC in the
compare-and-trap instruction (DXC 255), the DXC in FPCR will yield predictable values.
the FPCR may contain an unpredictable value under
the following conditions. If the program always needs to observe a predictable
compare-and-trap DXC value in the FPCR, it should
• For a control program, an instruction examining first issue any instruction that is subject to the AFP
the FPCR (for example, EXTRACT FPC) is the control (for example EXTRACT FPC) before issuing
first instruction that is subject to the AFP control an instruction that causes the data-exception pro-
to be executed since the last initial-CPU reset. gram interruption for the compare-and-trap condition.
Alternatively, the program can inspect the DXC
• For a task running under a control program such stored in real location 147, as copied into a control-
as z/OS, an instruction examining the FPCR is
Action on
Table-Entry Table-Entry Instruction
Exception Fetch1 Store2 Fetch Operand Reference
Addressing exception Suppress Suppress Suppress Suppress for IPTE, LASP, LPSW, LPSWE, MSCH, PLO6,
RP, SCKC, SPT, SPX, SSCH, SSM, STCRW, STNSM,
STOSM, TPI, and TPROT
4
Terminate for all others.
Figure 6-4. Summary of Action for Addressing and Protection Exceptions
3. During ASN translation in SET SECONDARY In the first and second cases, the number of the
ASN WITH INSTANCE with space switching, the access register is stored in bit positions 4-7 at real
ASTEIN in bit positions 0-31 of general register location 160, and bits 0-3 are set to zeros. In the third
R1 is not equal to the ASTEIN in the located case, all zeros are stored at real location 160.
ASTE.
The operation is nullified.
4. During SASN translation in PROGRAM
RETURN to current primary or with space
The instruction-length code is 1, 2, or 3.
switching, the ASN-and-LX-reuse control in con-
trol register 0 is one, and the SASTEIN in the
The ASTE-sequence exception is indicated by a pro-
linkage-stack state entry is not equal to the
gram-interruption code of 002C hex (or 00AC hex if a
ASTEIN in the located ASTE.
concurrent PER event is indicated).
Information is stored as follows:
Programming Note: The storing of zeros at real
location 160 in the case of an ASTE-sequence
• In cases 1 and 2, bit 2 of real location 160 is set
exception recognized during a subspace-replace-
to one, and bits 0, 1, and 3-7 are set to zeros.
ment operation is a unique indication since the use of
• In cases 3 and 4, bit 3 of real location 160 is set access register 0 in access-register translation can-
to one, and bits 0-2 and 4-7 are set to zeros. not result in the exception.
The ASN being translated is stored at real locations Each of the IEEE exceptions is controlled by a mask
174 and 175, and real locations 172 and 173 are set bit in the floating-point-control (FPC) register. The
with zeros. handling of these exceptions is described in the sec-
tion “IEEE Exceptions” on page 9-17.
The operation is nullified.
A data exception is recognized for the following
The instruction-length code is 1 or 2, except that cases:
when the exception occurs during the fetching of the
target of EXECUTE RELATIVE LONG, the ILC is 3. • Decimal-operand data exception is recognized
when an instruction which operates on decimal
The ASX-translation exception is indicated by a pro- operands encounters invalid decimal digit or sign
gram-interruption code of 0021 hex (or 00A1 hex if a codes or has its operands specified improperly.
concurrent PER event is indicated). The operation is suppressed, except that, for
EDIT and EDIT AND MARK, it is model depen-
Crypto-Operation Exception dent whether the operation is suppressed or ter-
A crypto-operation exception is recognized when a minated. See the section “Decimal-Operand
crypto-facility instruction is executed while bit 61 of Data Exception” on page 8-4 for details. A deci-
control register 0 is zero on a CPU which has the mal-operand data exception is also recognized
The EX-translation exception is indicated by a pro- 2. In signed or unsigned binary division when the
gram-interruption code of 0023 hex (or 00A3 hex if a result is defined to be 64 bits, the divisor is zero,
concurrent PER event is indicated). or the quotient cannot be expressed as a 64-bit
signed or unsigned, respectively, binary integer.
Extended-Authority Exception 3. The result of CONVERT TO BINARY cannot be
An extended-authority exception is recognized during expressed as a 32-bit signed binary integer for a
access-register translation when all of the following 32-bit result or as a 64-bit signed binary integer
are true: for a 64-bit result.
1. The private bit in the access-list entry used is
one. In the case of division, the operation is suppressed.
The execution of CONVERT TO BINARY (CVB,
2. The access-list-entry authorization index CVBY) is completed by ignoring the leftmost bits that
(ALEAX) in the access-list entry is not equal to cannot be placed in the register. The execution of
the extended authorization index (EAX) in control CONVERT TO BINARY (CVBG) is suppressed.
register 8.
The instruction-length code is 1, 2, or 3.
3. Either of the following is true:
a. The authority-table entry designated by the The fixed-point-divide exception is indicated by a pro-
EAX is beyond the length of the authority gram-interruption code of 0009 hex (or 0089 hex if a
table used. The authority table is the one concurrent PER event is indicated).
An LFX-translation exception is recognized during The instruction-length code is 2, except that when
PC-number translation in PROGRAM CALL when the exception occurs during the fetching of the target
either: of EXECUTE RELATIVE LONG, the ILC is 3.
1. The linkage-first-table entry specified by the link- The LSTE-sequence exception is indicated by a pro-
age-first-index part of the PC number is beyond gram-interruption code of 002E hex (or 00AE hex if a
the end of the linkage first table as designated by concurrent PER event is indicated).
the linkage-first-table designation used.
LSX-Translation Exception
2. Bit 0 of the linkage-first-table entry is not zero. An LSX-translation exception may be recognized
only when the ASN-and-LX-reuse facility is installed
When bit 44 of the second-operand address used by and the ASN-and-LX-reuse control in control register
PROGRAM CALL is zero, bits 44-63 of the address 0 is one.
(a 20-bit PC number), with 12 zeros appended on the
left, are stored in the word at real location 172. When An LSX-translation exception is recognized during
bit 44 of the second-operand address is one, bits PC-number translation in PROGRAM CALL when bit
32-63 of the address (a 32-bit PC number) are stored 0 of the linkage-second-table entry specified by the
in the word at real location 172. linkage-second-index part of the PC number is not
zero.
The operation is nullified.
When bit 44 of the second-operand address used by
The instruction-length code is 2, except that when PROGRAM CALL is zero, bits 44-63 of the address
the exception occurs during the fetching of the target (a 20-bit PC number), with 12 zeros appended on the
of EXECUTE RELATIVE LONG, the ILC is 3. left, are stored in the word at real location 172. When
bit 44 of the second-operand address is one, bits
The LFX-translation exception is indicated by a pro- 32-63 of the address (a 32-bit PC number) are stored
gram-interruption code of 0026 hex (or 00A6 hex if a in the word at real location 172.
concurrent PER event is indicated).
The operation is nullified.
LSTE-Sequence Exception
An LSTE-sequence exception may be recognized The instruction-length code is 2, except that when
only when the ASN-and-LX-reuse facility is installed the exception occurs during the fetching of the target
and the ASN-and-LX-reuse control in control register of EXECUTE RELATIVE LONG, the ILC is 3.
0 is one.
The LSX-translation exception is indicated by a pro-
An LSTE-sequence exception is recognized during gram-interruption code of 0027 hex (or 00A7 hex if a
PC-number translation in PROGRAM CALL when the concurrent PER event is indicated).
linkage-second-table-entry sequence number
(LSTESN) in the linkage-second-table entry used is LX-Translation Exception
nonzero and not equal to the LSTESN in bit positions An LX-translation exception may be recognized only
0-31 of general register 15. when the ASN-and-LX-reuse facility is not installed or
the ASN-and-LX-reuse control in control register 0 is
zero.
When the exception occurs during a reference to an Information identifying the event is stored at real
operand location, the instruction-length code (ILC) is locations 150-159 and conditionally at real location
1, 2, or 3 and indicates the length of the instruction 161.
causing the exception.
The instruction-length code is 0, 1, 2, or 3. Code 0 is
The page-translation exception is indicated by a pro- set for the PER instruction-fetching basic event only if
gram-interruption code of 0011 hex (or 0091 hex if a a specification exception is indicated concurrently.
concurrent PER event is indicated). Code 0 is always set when the PER instruction-fetch-
ing nullification event is indicated.
PC-Translation-Specification Exception
A PC-translation-specification exception is recog- The PER event is indicated by setting bit 8 of the pro-
nized during PC-number translation in PROGRAM gram-interruption code to one.
CALL when either of the following is true for the
entry-table entry (ETE) used: See “Program-Event Recording” on page 4-23 for a
detailed description of the PER event and the associ-
1. The PROGRAM CALL operation is the basic ated interruption information.
operation (bit 128 of the ETE is zero) in the 24-bit
or 31-bit addressing mode (bit 31 of the PSW is
Primary-Authority Exception
zero), bit 32 of the ETE is zero (specifying the
24-bit mode), and bits 33-39 of the ETE are not
A primary-authority exception is recognized during
all zeros.
ASN authorization in PROGRAM TRANSFER with
2. The PROGRAM CALL operation is the stacking space switching (PT-ss) or PROGRAM TRANSFER
operation (bit 128 of the ETE is one), bits 32 and WITH INSTANCE with space switching (PTI-ss)
129 of the ETE are zeros (specifying the 24-bit when either:
mode), and bits 33-39 of the ETE are not all
zeros. 1. The authority-table entry indicated by the autho-
rization index in control register 4 is beyond the
The operation is suppressed. end of the authority table used. The authority
table is the one designated by the ASN-second-
The instruction-length code is 2, except that when table entry for the ASN used.
the exception occurs during the fetching of the target
2. The primary-authority bit indicated by the autho-
of EXECUTE RELATIVE LONG, the ILC is 3.
rization index is zero.
The PC-translation-specification exception is indi-
The ASN used is stored at real locations 174-175,
cated by a program-interruption code of 001F hex (or
and real locations 172-173 are set to zeros.
009F hex if a concurrent PER event is indicated).
The operation is nullified.
7. In the problem state, the result of ANDing the The privileged-operation exception is indicated by a
authorization key mask (AKM) with the PSW-key program-interruption code of 0002 hex (or 0082 hex if
a concurrent PER event is indicated).
2. RESUME PROGRAM, SET ADDRESS SPACE 1. The space-switch event permits the control pro-
CONTROL, or SET ADDRESS SPACE CON- gram to gain control whenever a program enters
TROL FAST is executed, the CPU is in the home- or leaves a particular address space. The pri-
space mode either before or after the operation, mary space-switch-event-control bit is loaded
but not both before and after the operation, and into control register 1, along with the remaining
any of the following is true: bits of the primary address-space-control ele-
a. The primary space-switch-event-control bit, ment, whenever control register 1 is loaded.
bit 57 of control register 1, is one. 2. The space-switch event may be useful in obtain-
b. The home space-switch-event-control bit, bit ing programmed authorization checking, in caus-
57 of control register 13, is one. ing additional trace information to be recorded, or
in enabling or disabling the CPU for PER or trac-
c. A PER event is indicated. ing.
For PROGRAM CALL, PROGRAM RETURN, PRO- 3. Bit 121 of the ASN-second-table entry (ASTE) is
GRAM TRANSFER, and PROGRAM TRANSFER loaded into bit position 57 of control register 1 as
WITH INSTANCE, and for a RESUME PROGRAM, part of the PC-ss, PR-ss, PT-ss, and PTI-ss oper-
SET ADDRESS SPACE CONTROL, or SET ations. If bit 121 of the ASTE for a particular
ADDRESS SPACE CONTROL FAST instruction that address space is set to one, then a space-switch
changes the translation mode to the home-space event is recognized when a program enters or
mode, the old PASN, which is in bit positions 48-63 of leaves the address space by means of any of
control register 4 before the operation, is stored at PC-ss, PR-ss, PT-ss, or PTI-ss.
real locations 174-175, and the old primary space- 4. The occurrence of a space-switch event at the
switch-event-control bit is placed in bit position 0 and completion of a PC-ss, PR-ss, PT-ss, or PTI-ss
zeros are placed in bit positions 1-15 at real locations operation when any PER event is indicated, or at
172-173. the completion of execution of a RESUME PRO-
GRAM, SET ADDRESS SPACE CONTROL, or
For a RESUME PROGRAM, SET ADDRESS SPACE SET ADDRESS SPACE CONTROL FAST
CONTROL, or SET ADDRESS SPACE CONTROL instruction that changes to or from the home-
FAST instruction that changes the translation mode space mode when any PER event is indicated,
away from the home-space mode, zeros are stored permits the control program to determine the
at real locations 174-175, and the home space- address space from which the instruction caus-
switch-event-control bit is placed in bit position 0 and ing the PER event was fetched.
zeros are placed in bit positions 1-15 at real locations
172-173.
Special-Operation Exception
For a PROGRAM RETURN instruction that intro- A special-operation exception is recognized when
duces a PSW-format error, it is unpredictable any of the following is true:
whether the instruction-length code is 0 or 1, or 0 or 2 1. Execution of any of the following instructions is
if EXECUTE was used, or 0 or 3 if EXECUTE RELA- attempted with DAT off:
TIVE LONG was used.
• EXTRACT PRIMARY ASN
The operation is completed. • EXTRACT SECONDARY ASN
6. Execution of LOAD ADDRESS SPACE PARAM- – Bit 63 of general register 0 is zero, and
ETERS, PROGRAM CALL with space switching bits 16-17 of the current PSW are 10
(PC-ss), PROGRAM TRANSFER with space binary.
switching (PT-ss), PROGRAM TRANSFER WITH
INSTANCE with space switching (PT-ss), SET
• The store characteristic specifies an unas- 20. Execution of DIVIDE TO INTEGER is attempted,
signed value. and the M4 field does not designate a valid modi-
fier.
• The function code is 0, and the first operand
is not designated on a word boundary. 21. Execution of EXECUTE is attempted, and the
target address is odd.
• The function code is 1, and the first operand 22. Execution of EXTRACT STACKED STATE is
is not designated on a doubleword boundary. attempted, and the code in bit positions 56-63 of
general register R2 is greater than 4 when the
• The function code is 2, and any of the follow- ASN-and-LX-reuse facility is not installed or is
ing is true: greater than 5 when the facility is installed.
28. Execution of LOAD PSW is attempted and bit 12 37. Execution of PROGRAM TRANSFER or PRO-
of the doubleword at the second-operand GRAM TRANSFER WITH INSTANCE is
address is zero. It is model dependent whether attempted, and all of the following are true:
or not this exception is recognized. • The extended-addressing-mode bit in the
29. Execution of MONITOR CALL is attempted, and PSW is zero.
bit positions 8-11 of the instruction do not contain • The basic-addressing-mode bit, bit 32, in the
zeros. general register designated by the R2 field of
30. Execution of MOVE PAGE is attempted, and bit the instruction is zero.
positions 48-51 of general register 0 do not con- • Bits 33-39 of the instruction address in the
tain zeros or bits 52 and 53 of the register are same register are not all zeros.
both one.
38. Execution of RESUME PROGRAM is attempted,
31. Execution of PACK ASCII is attempted, and the and either of the following is true:
L2 field is greater than 31.
• Bits 31, 32, and 64-127 of the PSW field in
32. Execution of PACK UNICODE is attempted, and the second operand are not valid for place-
the L2 field is greater than 63 or is even. ment in the current PSW. The exception is
33. Execution of PERFORM FLOATING POINT recognized if any of the following is true:
OPERATION is attempted, bit 32 of general reg- – Bits 31 and 32 are both zero and bits
ister 0 is zero, and one or more fields in bits 33- 64-103 are not all zeros.
63 are invalid or designate an uninstalled func-
tion. – Bits 31 and 32 are zero and one, respec-
tively, and bits 64-96 are not all zeros.
34. Execution of PERFORM FRAME MANAGE-
MENT FUNCTION is attempted, and either or – Bits 31 and 32 are one and zero, respec-
both of the following are true: tively.
• The T bit, bit 55 of general register 0 is zero, 40. Execution of SET ADDRESS SPACE CONTROL
and the function code in bits 56-63 of the or SET ADDRESS SPACE CONTROL FAST is
register is invalid. attempted, and bits 52 and 53 of the second-
operand address are not both zeros.
• Bits 32-54 of general register 0 are not all
zeros. 41. Execution of SET ADDRESSING MODE
(SAM24) is attempted, and bits 0-39 of the unup-
• In the access-register mode, for function dated instruction address in the PSW, bits
codes that cause use of a parameter list con- 64-103 of the PSW, are not all zeros.
taining an ALET, the R3 field is zero.
42. Execution of SET ADDRESSING MODE
36. Execution of PERFORM TIMING FACILITY (SAM31) is attempted, and bits 0-32 of the unup-
FUNCTION is attempted, and either of the follow- dated instruction address in the PSW, bits 64-96
ing is true: of the PSW, are not all zeros.
46. Execution of TRANSLATE AND TEST Programming Note: See “Exceptions Associated
EXTENDED or TRANSLATE AND TEST with the PSW” on page 6-8 for a definition of when
REVERSE EXTENDED is attempted, the A bit, the exceptions associated with the PSW are recog-
bit 0 of the M3 field, is one, and the argument- nized.
character length in general register R1 + 1 is not
an even number. Stack-Empty Exception
A stack-empty exception is recognized during the
47. Execution of TRANSLATE TWO TO ONE or unstacking process in EXTRACT STACKED REGIS-
TRANSLATE TWO TO TWO is attempted, and TERS, EXTRACT STACKED STATE, MODIFY
the length in general register R1 + 1 does not STACKED STATE, or PROGRAM RETURN when the
specify an even number of bytes. current linkage-stack entry is a header entry and the
48. Execution of UNPACK ASCII is attempted, and backward stack-entry validity bit in the header entry
the L1 field is greater than 31. is zero.
1. In the lookup in the table designated by the Programming Note: When a translation-specifica-
address-space-control element used for the tion exception is recognized in the process of trans-
translation, the table-type bits in the selected lating an instruction address, the operation is
table entry do not equal the designation-type bits suppressed. In this case, the instruction-length code
in the address-space-control element. (ILC) is needed to derive the address of the instruc-
tion, as the instruction address in the old PSW has
2. In a lookup in a table designated by an entry in a been incremented by the amount indicated by the
region first table, region second table, or region ILC. In the case of region-first-translation, region-
third table, the value of the table-type bits in the second-translation, region-third-translation, segment-
selected table entry is not one less than the translation, and page-translation exceptions, the
value of the same bits in the designating table operation is nullified, the instruction address in the
entry. old PSW identifies the instruction, and the ILC may
3. The private-space control, bit 55 in the address- be arbitrarily set to 1, 2, or 3.
space-control element used for the translation, is
one, the segment-table entry used for the trans- Collective Program-Interruption
lation is valid, and the common-segment bit, bit
59, in the segment-table entry is one. Names
4. The page-table entry used for the translation is For the sake of convenience, certain program excep-
valid, and bit position 52 does not contain zero. tions are grouped together under a single collective
5. The page-table entry used for the translation is name. These collective names are used when it is
valid, enhanced DAT does not apply, and bit posi- necessary to refer to the complete set of exceptions,
tion 55 does not contain zero. such as in instruction definitions. Four collective
names are used:
Any of the above reasons is referred to by saying that
• Access exceptions
the DAT-table entry has a format error.
• ASN-translation exceptions
• Subspace-replacement exceptions
The exception is recognized only as part of the exe-
• Trace exceptions
cution of an instruction using address translation,
that is, when DAT is on and a logical address, instruc-
The individual exceptions and their priorities are
tion address, or virtual address must be translated, or
listed in “Multiple Program-Interruption Conditions”
when LOAD PAGE-TABLE-ENTRY ADDRESS,
on page 6-44.
LOAD REAL ADDRESS or STORE REAL ADDRESS
is executed.
Recognition of Access Exceptions
The unit of operation is suppressed.
Figure 6-5 on page 6-41 summarizes the conditions
When the exception occurs during fetching of an
that can cause access exceptions and the action
instruction, it is unpredictable whether the ILC is 1, 2,
taken when they are encountered.
or 3. When the exception occurs during the fetching
of the target of EXECUTE, the ILC is 2. When the
Any access exception is recognized as part of the
exception occurs during the fetching of the target of
execution of the instruction with which the exception
EXECUTE RELATIVE LONG, the ILC is 3.
is associated. An access exception is not recognized
when the CPU attempts to prefetch from an unavail-
Access-list entry3
Access-list-length violation cc3 Complete cc3 Complete cc3 Complete AT Nullify
Invalid address of entry A Suppress A Suppress A Suppress A Suppress
I bit on cc3 Complete cc3 Complete cc3 Complete AT Nullify
Sequence number in access register cc3 Complete cc3 Complete cc3 Complete ALQ Nullify
not equal to sequence number in entry
ASN-second-table entry3
Invalid address of entry A Suppress A Suppress A Suppress A Suppress
I bit on cc3 Complete cc3 Complete cc3 Complete AV Nullify
Sequence number in access-list entry cc3 Complete cc3 Complete cc3 Complete ASQ Nullify
not equal to sequence number in entry
Authority-table entry3 4
Authority-table-length violation cc3 Complete cc3 Complete cc3 Complete EA Nullify
Invalid address of entry A Suppress A Suppress A Suppress A Suppress
Second-authority bit not one cc3 Complete cc3 Complete cc3 Complete EA Nullify
Address-space-control element
Bits 0-10, 0-21, or 0-32 of instruction or cc3 Complete cc3 Complete cc3 Complete ATY Nullify
operand address not all zeros when
address-space-control element is a
region-second-table designation,
region-third-table designation, or
segment-table designation, respectively
Region-table-entry designation by
address-space-control element or
region-table-entry
Entry outside of table cc3 Complete cc3 Complete cc3 Complete RT Nullify
Invalid address of entry A Suppress A Suppress A Suppress A Suppress
I bit on cc2 Complete cc3 Complete cc3 Complete RT Nullify
TT in entry not equal DT in address- TS Suppress TS Suppress TS Suppress TS Suppress
space-control element or not one less
than TT in next-higher-level entry
Page-table entry
Invalid address of entry - - A Suppress A Suppress A Suppress
I bit on (except as follow) - - cc2 Complete cc3 Complete PT Nullify
I bit on (LRA in 24-bit or 31-bit mode - - cc3 Complete cc3 Complete PT Nullify
when bits 0-32 of entry address not all
zeros)
One in a bit position which is checked - - TS Suppress TS Suppress TS Suppress
for zeros5
able location or detects some other access-exception additional halfwords according to the instruction
condition, but a branch instruction or an interruption length specified by the first two bits of the instruction;
changes the instruction sequence such that the however, when the operation can be performed with-
instruction is not executed. out accessing the second or third halfwords of the
instruction, it is unpredictable whether the access
Every instruction can cause an access exception to exception is indicated for the unused part. Since the
be recognized because of instruction fetch. Addition- indication of access exceptions for instruction fetch is
ally, access exceptions associated with instruction common to all instructions, it is not covered in the
execution may occur because of an access to an individual instruction definitions.
operand in storage.
Except where otherwise indicated in the individual
An access exception due to fetching an instruction is instruction description, the following rules apply for
indicated when the first instruction halfword cannot exceptions associated with an access to an operand
be fetched without encountering the exception. When location. For a fetch-type operand, access exceptions
the first halfword of the instruction has no access are necessarily indicated only for that portion of the
exceptions, access exceptions may be indicated for operand which is required for completing the opera-
1. Specification exception due to any PSW error of the type that causes an immediate interruption.1
2. Specification exception due to an odd instruction address in the PSW.
2
3. Access exceptions for first halfword of an execute-type instruction.
4.A Access exceptions for second halfword of an execute-type instruction.2
4.B Access exceptions for third halfword of EXECUTE RELATIVE LONG.2
5. Specification exception due to target instruction of EXECUTE not being specified on halfword boundary.2
(Without PER-3)
5.1 PER event due to instruction-fetching nullification on EXECUTE or EXECUTE RELATIVE LONG. (With PER-3)
2
5.2 Specification exception due to target instruction of EXECUTE not being specified on halfword boundary. (With
PER-3)
6. Access exceptions for first instruction halfword. (Without PER-3)
6.1 Access exceptions for first instruction halfword. (With PER-3)
3
6.2.A Access exceptions for second instruction halfword. (With PER-3)
3
6.2.B Access exceptions for third instruction halfword. (With PER-3)
6.3 PER event due to instruction-fetching nullification. (PER-3)
3
7.A Access exceptions for second instruction halfword. (Without PER-3)
3
7.B Access exceptions for third instruction halfword. (Without PER-3)
7.C.1 Operation exception.
7.C.2 Privileged-operation exception for privileged instructions.
7.C.3 Execute exception.
4
7.C.4 Special-operation exception.
8.A Specification exception due to conditions other than those included in 1, 2, and 5 above.
5
8.B Access exceptions for an access to an operand in storage.6
8.C5 Access exceptions for any other access to an operand in storage.6
7
8.D Data exception.
8.E Decimal-divide exception.8
8.F Trace exceptions.
Access Exceptions
The access exceptions consist of those exceptions
which can be encountered while using an absolute,
instruction, logical, real, or virtual address to access
A. Protection exception (low-address protection) due to a store-type operand reference with an effective address
in the range 0-511 or 4096-4607. Not recognized if DAT is on and the address-space-control element to be
used in the translation cannot be obtained because of another exception.
1
B.1.A.1 ALET-specification exception due to bits 0-6 of access register not being all zeros.
B.1.A.2 Addressing exception for access to effective access-list designation.2
B.1.A.3 ALEN-translation exception due to access-list entry being outside the list.1
B.1.A.4 Addressing exception for access to access-list entry.2
B.1.A.5 ALEN-translation exception due to I bit in access-list entry having the value one.1
B.1.A.6 ALE-sequence exception due to access-list-entry sequence number (ALESN) in access register not being
equal to ALESN in access-list entry.1
B.1.A.8 ASTE-validity exception due to I bit in ASN-second-table entry having the value one.1
B.1.A.9 ASTE-sequence exception due to ASN-second-table-entry sequence number (ASTESN) in access-list entry
1
not being equal to ASTESN in ASN-second-table entry.
Note: Exceptions B.1.A.10 through B.1.A.12 are recognized only when the private bit in the access-list entry is
one and the ALEAX in the entry is not equal to the EAX in control register 8.
1
B.1.A.10 Extended-authority exception due to authority-table entry being outside table.
B.1.A.11 Addressing exception for access to authority-table entry.2
B.2.A Protection exception (access-list-controlled protection) due to store-type operand reference to a virtual address
1
which is protected against stores.
B.2.B.1 ASCE-type exception due to bits 0-10, 0-21, or 0-32 of instruction or operand address not being zeros when
address-space-control element is a region-second-table designation, region-third-table designation, or
3
segment-table designation, respectively.
B.2.B.2 Region-first-, region-second-, region-third-, or segment-translation exception due to required entry in table
designated by address-space-control element being outside of table.3
Note: Exceptions B.2.B.3 through B.2.B.6 are recognized for a region-first-table, region-second- table, region-
third-table, and segment-table entry in the order in which the entries are used.
B.2.B.4 Region-first-, region-second-, region-third-, or segment-translation exception due to I bit in table entry having
the value one.3
B.2.B.5 Translation-specification exception due to (1) TT in table entry not equal to DT in designating address-space-
control element or not one less than TT in designating next-higher-level table entry or (2) invalid one in
segment-table entry if this entry is a segment-table entry (common-segment bit if private- space bit in address-
space-control element is one).
B.2.B.6 Region-second-, region-third-, or segment-translation exception due to required entry in next-lower-level table
3
entry, if any, being outside of table.
B.2.B.7 Addressing exception for access to page-table entry.5
B.2.B.8 Page-translation exception due to I bit in page-table entry having the value one.3, 7
B.2.B.9 Translation-specification exception due to invalid ones in page-table entry in which I bit is zero.8 A one in bit
position 52 of a valid PTE always causes the exception. When enhanced DAT does not apply, a one in bit
position 55 of a valid PTE causes the exception.
B.3.A Protection exception (DAT protection) due to a store-type operand reference to a virtual address which is
6
protected against stores.
B.3.B Addressing exception for access to instruction or operand.
B.4 Protection exception (key-controlled protection) due to attempt to access a protected instruction or operand
location.
Explanation:
1
Not applicable when not in the access-register mode; not applicable for execution of TEST ACCESS and for
translation of operand address of LOAD PAGE-TABLE-ENTRY ADDRESS, LOAD REAL ADDRESS, and TEST
PROTECTION.
2
Not applicable when not in the access-register mode, except applicable for execution of TEST ACCESS and,
when PSW bits 16 and 17 are 01 binary, for translation of operand address of LOAD REAL ADDRESS and
second-operand address of STORE REAL ADDRESS; also applicable for LOAD PAGE-TABLE-ENTRY
ADDRESS when the M4 field is 0001 binary or when the M4 field is 0100 binary and PSW bits 16-17 are 01
binary.
3
Not applicable when DAT is off except for translation of second-operand address of STORE REAL ADDRESS;
not applicable to operand addresses of LOAD PAGE-TABLE-ENTRY ADDRESS, LOAD REAL ADDRESS and
TEST PROTECTION.
If the CPU is in the operating state, the exchange of The interruption code is placed at real locations
the PSWs occurs at the completion of the current unit 138-139; the instruction-length code is placed in bit
of operation and after all other pending interruption positions 5 and 6 of the byte at real location 137, with
conditions for which the CPU is enabled have been the other bits set to zeros; and zeros are stored at
honored. If the CPU is in the stopped state, the CPU real location 136.
enters the operating state and exchanges the PSWs
without first honoring any other pending interruptions.
This chapter includes most of the unprivileged In an unsigned binary integer, all bits are used to
instructions described in this publication. Other express the absolute value of the number. When two
unprivileged instructions are described in chapters unsigned binary integers of different lengths are
8-9 and 18-20. added, the shorter number is considered to be
extended on the left with zeros.
2. The numeric bits of a signed binary integer may Addition and Subtraction
be considered to represent a positive value, with Addition of signed binary integers is performed by
the sign representing a value of either zero or the adding all bits of each operand, including the sign
maximum negative number. bits. When one of the operands is shorter, the shorter
operand is considered to be extended on the left to
the length of the longer operand by propagating the
sign-bit value.
Programming Notes:
Unsigned Binary Arithmetic
1. Logical addition and subtraction may be used to
Addition of unsigned binary integers is performed by perform arithmetic on multiple-precision binary-
adding all bits of each operand. Subtraction is per- integer operands. Thus, for multiple-precision
formed by adding the one’s complement of the sec- addition, ADD LOGICAL can be used to add the
ond operand (the subtractor) and a value of one to lowest-order corresponding parts of the oper-
the first operand (the subtrahend). In any case, when ands, and ADD LOGICAL WITH CARRY can be
one of the operands is shorter, the shorter operand is used to add the other corresponding parts of the
considered to be extended on the left with zeros. operands, moving from right to left in the oper-
During subtraction, this extension applies before an ands. If the multiple-precision operands are
signed, ADD should be used on the highest-
7. The following additional general instructions are 11. When the ETF2-enhancement facility is
available when the extended-translation facility 3 installed, new functions are provided for the
is installed: TRANSLATE ONE TO ONE, TRANSLATE ONE
TO TWO, TRANSLATE TWO TO ONE, and
• CONVERT UTF-16 TO UTF-32 TRANSLATE TWO TO TWO instructions.
• CONVERT UTF-32 TO UTF-16
• CONVERT UTF-32 TO UTF-8 12. When the ETF3-enhancement facility is
• CONVERT UTF-8 TO UTF-32 installed, improved well-formedness checking is
• SEARCH STRING UNICODE provided for the CONVERT UTF-16 TO UTF-32,
• TRANSLATE AND TEST REVERSE CONVERT UTF-16 TO UTF-8, CONVERT UTF-
8 TO UTF-16, and CONVERT UTF-8 TO UTF-32
Additionally, CONVERT UNICODE TO UTF-8 instructions.
(CUUTF) and CONVERT UTF-8 TO UNICODE
(CUTFU) are renamed to CONVERT UTF-16 TO 13. The COMPARE AND SWAP AND STORE gen-
UTF-8 (CU21) and CONVERT UTF-8 TO eral instruction is available if the compare-and-
UTF-16 (CU12), respectively, in order to conform swap-and-store facility is installed.
to the names used by this facility. The old names
continue to be recognized. 14. The EXTRACT CPU TIME general instruction is
available if the extract-CPU-time facility is
8. The following additional general instructions are installed.
available when the extended-immediate facility is
installed: 15. The following additional general instructions are
• ADD IMMEDIATE (AFI, AGFI) available when the parsing-enhancement facility
• ADD LOGICAL IMMEDIATE (ALFI, ALGFI) is installed:
• AND IMMEDIATE (NIHF, NILF) • TRANSLATE AND TEST EXTENDED
• COMPARE IMMEDIATE (CFI, CGFI) • TRANSLATE AND TEST REVERSE
• COMPARE LOGICAL IMMEDIATE (CLFI, EXTENDED
CLGFI)
• EXCLUSIVE OR IMMEDIATE (XIHF, XILF) 16. The EXECUTE RELATIVE LONG general
• FIND LEFTMOST ONE (FLOGR) instruction is available when the execute-exten-
• INSERT IMMEDIATE (IIHF, IILF) sion facility is installed.
• LOAD AND TEST (LT, LTG)
• LOAD BYTE (LBR, LGBR) 17. The following additional general instructions are
• LOAD HALFWORD (LHR, LGHR) available when the general-instructions-exten-
• LOAD IMMEDIATE (LGFI) sion facility is installed:
• LOAD LOGICAL CHARACTER (LLC, LLCR, • ADD IMMEDIATE (AGSI, ASI)
LLGCR) • ADD LOGICAL WITH SIGNED IMMEDIATE
• LOAD LOGICAL HALFWORD (LLGHR, LLH, (ALGSI, ALSI)
LLHR) • COMPARE AND BRANCH (CGRB, CRB)
• LOAD LOGICAL IMMEDIATE (LLIHF, LLILF) • COMPARE AND BRANCH RELATIVE
• OR IMMEDIATE (OIHF, OILF) (CGRJ, CRJ)
• SUBTRACT LOGICAL IMMEDIATE (SLFI, • COMPARE AND TRAP (CGRT, CRT)
SLGFI)
21. The following additional general instructions are 22. The POPULATION COUNT general instruction
available when the distinct-operands facility is is available when the population-count facility is
installed: installed.
• ADD (ARK, AGRK) 23. The following additional general instructions are
• ADD IMMEDIATE (AHIK, AGHIK) available when the message-security-assist
• ADD LOGICAL (ALRK, ALGRK) extension 4 is installed:
• ADD LOGICAL WITH SIGNED IMMEDIATE
(ALHSIK, ALGHSIK) • CIPHER MESSAGE WITH CFB
• AND (NRK, NGRK) • CIPHER MESSAGE WITH COUNTER
• EXCLUSIVE OR (XRK, XGRK) • CIPHER MESSAGE WITH OFB
• OR (ORK, OGRK) • PERFORM CRYPTOGRAPHIC COMPUTA-
• SHIFT LEFT SINGLE (SLAK) TION
• SHIFT LEFT SINGLE LOGICAL (SLLK)
• SHIFT RIGHT SINGLE (SRAK)
Mne- Op-
Name monic Characteristics code Page
ADD (32) A RX-a C A IF B2 5A 7-25
ADD (32) AR RR C IF 1A 7-24
ADD (32) ARK RRF-a C DO IF B9F8 7-25
ADD (32) AY RXY-a C LD A IF B2 E35A 7-25
ADD (64) AG RXY-a C N A IF B2 E308 7-25
ADD (64) AGR RRE C N IF B908 7-25
ADD (64) AGRK RRF-a C DO IF B9E8 7-25
ADD (64I32) AGF RXY-a C N A IF B2 E318 7-25
ADD (64I32) AGFR RRE C N IF B918 7-25
ADD HALFWORD AH RX-a C A IF B2 4A 7-27
ADD HALFWORD AHY RXY-a C LD A IF B2 E37A 7-27
ADD HALFWORD IMMEDIATE (32) AHI RI-a C IF A7A 7-27
ADD HALFWORD IMMEDIATE (64) AGHI RI-a C N IF A7B 7-27
ADD HIGH (32) AHHHR RRF-a C HW IF B9C8 7-27
ADD HIGH (32) AHHLR RRF-a C HW IF B9D8 7-27
ADD IMMEDIATE (32) AFI RIL-a C EI IF C29 7-25
ADD IMMEDIATE (32I16) AHIK RIE-d C DO IF ECD8 7-25
ADD IMMEDIATE (32I8) ASI SIY C GE A IF ST B1 EB6A 7-25
ADD IMMEDIATE (64I16) AGHIK RIE-d C DO IF ECD9 7-25
ADD IMMEDIATE (64I32) AGFI RIL-a C EI IF C28 7-25
ADD IMMEDIATE (64I8) AGSI SIY C GE A IF ST B1 EB7A 7-25
ADD IMMEDIATE HIGH (32) AIH RIL-a C HW IF CC8 7-25
ADD LOGICAL (32) AL RX-a C A B2 5E 7-28
ADD LOGICAL (32) ALR RR C 1E 7-28
ADD LOGICAL (32) ALRK RRF-a C DO B9FA 7-28
ADD LOGICAL (32) ALY RXY-a C LD A B2 E35E 7-28
ADD LOGICAL (64) ALG RXY-a C N A B2 E30A 7-28
ADD LOGICAL (64) ALGR RRE C N B90A 7-28
ADD LOGICAL (64) ALGRK RRF-a C DO B9EA 7-28
ADD LOGICAL (64I32) ALGF RXY-a C N A B2 E31A 7-28
ADD LOGICAL (64I32) ALGFR RRE C N B91A 7-28
ADD LOGICAL HIGH (32) ALHHHR RRF-a C HW B9CA 7-29
ADD LOGICAL HIGH (32) ALHHLR RRF-a C HW B9DA 7-29
ADD LOGICAL IMMEDIATE (32) ALFI RIL-a C EI C2B 7-28
Figure 7-1. Summary of General Instructions (Part 1 of 12)
Mne- Op-
Name monic Characteristics code Page
LD Long-displacement facility.
ME Monitor event.
MS Message-security assist.
M4 Message-security-assist extension 4.
N Instruction is new in z/Architecture as compared to ESA/390.
N3 Instruction is new in z/Architecture and has been added to ESA/390. Any RSY or RXY instructions still use the RSE or RXE format and 12-bit
displacements in ESA/390.
PE Parsing-enhancement facility.
PK Population-count facility
R1 R1 field designates an access register in the access-register mode.
R2 R2 field designates an access register in the access-register mode.
R3 R3 field designates an access register in the access-register mode.
RI RI instruction format.
RIE RIE instruction format.
RIL RIL instruction format.
RM R1 field designates an access register in the access-register mode, and access-register 1 also is used in the access-register mode.
RR RR instruction format.
RRE RRE instruction format.
RRF RRF instruction format.
RRS RRS instruction format.
RS RS instruction format.
RSI RSI instruction format.
RSY RSY instruction format.
RX RX instruction format.
RXY RXY instruction format.
S S instruction format.
SC Store-clock-fast facility.
SI SI instruction format.
SIL SIL instruction format.
SIY SIY instruction format.
SP Specification exception.
SS SS instruction format.
SSF SSF instruction format.
ST PER storage-alteration event.
T Trace exceptions (includes trace table, addressing, and low-address protection).
U1 R1 field designates an access register unconditionally.
U2 R2 field designates an access register unconditionally.
UB R1 and R3 fields designate access registers unconditionally, and B2 field designates an access register in the access-register mode.
XX Execute-extension facility.
Figure 7-1. Summary of General Instructions (Part 12 of 12)
ADD IMMEDIATE
'B908' / / / / / / / / R1 R2 'EC' R1 R3 I2 //////// 'D8'
0 16 24 28 31 0 8 12 16 32 40 47
A R1,D2(X2,B2) [RX-a] For ADD (A, AG, AGF, AGFR, AGR, AR, and AY) and
'5A' R1 X2 B2 D2 for ADD IMMEDIATE (AFI, AGFI, AGSI, and ASI), the
0 8 12 16 20 31
second operand is added to the first operand, and
the sum is placed at the first-operand location. For
ADD (AGRK and ARK) and for ADD IMMEDIATE
AY R1,D2(X2,B2) [RXY-a]
(AGHIK and AHIK), the second operand is added to
'E3' R1 X2 B2 DL2 DH2 '5A' the third operand, and the sum is placed at the first-
0 8 12 16 20 32 40 47 operand location.
AG R1,D2(X2,B2) [RXY-a] For ADD (A, AR, ARK, and AY) and for ADD IMME-
DIATE (AFI), the operands and the sum are treated
'E3' R1 X2 B2 DL2 DH2 '08' as 32-bit signed binary integers. For ADD (AG, AGR,
0 8 12 16 20 32 40 47 and AGRK), they are treated as 64-bit signed binary
integers. For ADD (AGFR, AGF) and for ADD IMME-
AGF R1,D2(X2,B2) [RXY-a] DIATE (AGFI), the second operand is treated as a
32-bit signed binary integer, and the first operand
'E3' R1 X2 B2 DL2 DH2 '18'
and the sum are treated as 64-bit signed binary inte-
0 8 12 16 20 32 40 47
gers. For ADD IMMEDIATE (ASI), the second oper-
and is treated as an 8-bit signed binary integer, and
the first operand and the sum are treated as 32-bit
ADD IMMEDIATE signed binary integers. For ADD IMMEDIATE (AGSI),
the second operand is treated as an 8-bit signed
Register-and-immediate formats:
binary integer, and the first operand and the sum are
AFI R1,I2 [RIL-a] treated as 64-bit signed binary integers. For ADD
IMMEDIATE (AHIK), the first and third operands are
'C2' R1 '9' I2 treated as 32-bit signed binary integers, and the sec-
0 8 12 16 47 ond operand is treated as a 16-bit signed binary inte-
ger. For ADD IMMEDIATE (AGHIK), the first and third
AGFI R1,I2 [RIL-a] operands are treated as 64-bit signed binary inte-
gers, and the second operand is treated as a 16-bit
'C2' R1 '8' I2
signed binary integer.
0 8 12 16 47
allowing any carry into the sign-bit position and ignor- installed, or when the first operand is not aligned
ing any carry out of the sign-bit position, and condi- on an integral boundary corresponding to its
tion code 3 is set. If the fixed-point-overflow mask is size, the fetch and store accesses to the first
one, a program interruption for fixed-point overflow operand do not necessarily occur one immedi-
occurs. ately after the other. Under such conditions, ADD
IMMEDIATE (AGSI and ASI) cannot be safely
When the interlocked-access facility is installed and used to update a location in storage if the possi-
the first operand of ADD IMMEDIATE (ASI, AGSI) is bility exists that another CPU or a channel pro-
aligned on an integral boundary corresponding to its gram may also be updating the location. An
size, then the fetch and store of the first operand are example of this effect is shown in “Multiprogram-
performed as an interlocked update as observed by ming and Multiprocessing Examples” in Appen-
other CPUs, and a specific-operand-serialization dix A, “Number Representation and Instruction-
operation is performed. When the interlocked-access Use Examples.”
facility is not installed, or when the first operand of
ADD IMMEDIATE (ASI, AGSI) is not aligned on an When the interlocked-access facility is installed
integral boundary corresponding to its size, then the and the first operand is aligned on an integral
fetch and store of the operand are not performed as boundary corresponding to its size, the operand
an interlocked update. is accessed using a block-concurrent interlocked
update.
The displacement for A is treated as a 12-bit 3. For certain programming languages which ignore
unsigned binary integer. The displacement for AY, overflow conditions on arithmetic operations, the
AG, AGF, AGSI and ASI, is treated as a 20-bit signed setting of condition code 3 obscures the sign of
binary integer. the result. However, for ADD IMMEDIATE, the
sign of the I2 field (which is known at the time of
Resulting Condition Code: code generation) may be used in setting a
branch mask which will accurately determine the
0 Result zero; no overflow resulting sign, as shown below.
1 Result less than zero; no overflow
2 Result greater than zero; no overflow Result to be Tested
3 Overflow
I2 Value Positive Negative Zero
a
Program Exceptions: Positive 0010 0101 1000
b
Negative 0011 0100 1000c
• Access (fetch and store, operand 1 of AGSI and Zero 0010 0100 1000
ASI only; fetch, operand 2 of A, AY, AG, and AGF
only) Explanation:
• Fixed-point overflow a
If the first operand was positive, then a mask
• Operation (AY, if the long-displacement facility is
of 0001 covers that case (overflow). If the
not installed; AFI and AGFI, if the extended-
first operand was negative, then a mask of
immediate facility is not installed; AGSI and ASI, 0100 is appropriate. Combining the two
if the general-instructions-extension facility is not gives a mask of 0101.
installed; ARK, AGRK, AHIK, and AGHIK, if the b
Similarly, a mask of 0010 (first operand was
distinct-operands facility is not installed) positive) and mask of 0001 (first operand
was negative) yields a mask of 0011 which
Programming Notes: covers both cases.
c
A separate test for zero may be required
1. Accesses to the first operand of ADD IMMEDI- when the I2 field contains 80000000 hex.
ATE (AGSI and ASI) consist in fetching a first- Figure 7-2. Branch Masks to Determine Resulting Sign for
operand from storage and subsequently storing ADD IMMEDIATE
the updated value.
The technique described above is also applica-
ble to ADD HALFWORD IMMEDIATE.
ADD HIGH
• Fixed-point overflow
AH R1,D2(X2,B2) [RX-a] • Operation (AHY, if the long-displacement facility
is not installed)
'4A' R1 X2 B2 D2
0 8 12 16 20 31 Programming Notes:
'B91A' / / / / / / / / R1 R2
• Fixed-point overflow
0 16 24 28 31
• Operation (if the high-word facility is not installed)
ALGR R1,R2 [RRE] For ADD LOGICAL (AL, ALG, ALGF, ALGFR, ALGR,
ALR, and ALY) and for ADD LOGICAL IMMEDIATE
'B90A' / / / / / / / / R1 R2 (ALGFI and ALFI), the second operand is added to
0 16 24 28 31 the first operand, and the sum is placed at the first-
operand location. For ADD LOGICAL (ALGRK and
ALRK), the second operand is added to the third
Programming Notes: For ALHSIK, the first and third operands are treated
as 32-bit unsigned binary integers. For ALGHSIK, the
1. A carry is represented by a one value of bit 18 of first and third operands are treated as 64-bit
the current PSW. Bit 18 is the leftmost bit of the unsigned binary integers. For both ALGHSIK and
two-bit condition code in the PSW. Bit 18 is set to ALHSIK, the second operand is treated as a 16-bit
one by an execution of an ADD LOGICAL or signed binary integer.
ADD LOGICAL WITH CARRY instruction that
produces a carry out of bit position 0 of the When the interlocked-access facility is installed and
result. the first operand is aligned on an integral boundary
corresponding to its size, then the fetch and store of
2. ADD and ADD LOGICAL may provide better per- the first operand is performed as an interlocked
formance than ADD LOGICAL WITH CARRY, update as observed by other CPUs, and a specific-
depending on the model. operand-serialization operation is performed. When
the interlocked-access facility is not installed, or
ADD LOGICAL WITH SIGNED when the first operand of ADD LOGICAL WITH
SIGNED IMMEDIATE (ALSI, ALGSI) is not aligned
IMMEDIATE on an integral boundary corresponding to its size,
then the fetch and store of the operand are not per-
Storage-and-immediate formats:
formed as an interlocked update.
ALSI D1(B1),I2 [SIY]
When the second operand contains a negative value,
'EB' I2 B1 DL1 DH1 '6E' the condition code is set as though a SUBTRACT
0 8 16 20 32 40 47 LOGICAL operation was performed. Condition code
0 is never set when the second operand is negative.
ALGSI D1(B1),I2 [SIY]
The displacement is treated as a 20-bit signed binary
'EB' I2 B1 DL1 DH1 '7E'
integer.
0 8 16 20 32 40 47
AND
unsigned binary integers. The second operand is
1. When the second operand contains a negative treated as a 32-bit signed binary integer. The first
value, the condition-code setting can also be operand is in bits 0-31 of general register R1; bits
interpreted as indicating the presence or 32-63 of the register are unchanged.
absence of a borrow, as follows:
Resulting Condition Code:
1 Result not zero; borrow
2 Result zero; no borrow For ALSIH, the code is set as follows:
3 Result not zero; no borrow
'CC' R1 'B' I2
N R1,D2(X2,B2) [RX-a]
0 8 12 16 47
'54' R1 X2 B2 D2
0 8 12 16 20 31
The second operand is added to the first operand,
and the sum is placed at the first-operand location.
'E3' R1 X2 B2 DL2 DH2 '54' NC are treated as 12-bit unsigned binary integers.
The displacement for NY, NIY, and NG is treated as a
0 8 12 16 20 32 40 47
20-bit signed binary integer.
Programming Notes:
Storage-and-storage format:
For AND (N, NR, NRK, and NY), the operands are 32
NIHH R1,I2 [RI-a]
bits, and for AND (NG, NGR, and NGRK), they are
64 bits. 'A5' R1 '4' I2
0 8 12 16 31
Program Exceptions:
Information from the current PSW, including the • Trace (R2 field nonzero)
updated instruction address, is saved as link informa-
tion at the first-operand location. Subsequently, if the Programming Notes:
R2 field is nonzero, the addressing-mode bits and
instruction address in the PSW are replaced as spec- 1. An example of the use of the BRANCH AND
ified by the second operand. SAVE AND SET MODE instruction is given in
Appendix A, “Number Representation and
In the 24-bit or 31-bit addressing mode, the link infor- Instruction-Use Examples.”
mation is bits 32 and 97-127 of the PSW, consisting
of the basic-addressing-mode bit and the rightmost 2. BRANCH AND SAVE AND SET MODE is
31 bits of the updated instruction address. The link intended to be the principal calling instruction to
information is placed in bit positions 32 and 33-63, subroutines which may operate in a different
respectively, of the first-operand location, and bits addressing mode from that of the caller. See the
0-31 of the location remain unchanged. In the 64-bit programming notes on pages 5-12 and 5-15 in
addressing mode, the link information is bits 64-126 the section “Subroutine Linkage without the Link-
of the PSW with a one appended on the right, placed age Stack” for a detailed discussion of this and
in bit positions 0-63 of the first-operand location. other linkage instructions.
The new value for the PSW is computed before gen- In the RX format, the second-operand address is
eral register R1 is changed. used as the branch address. In the RR format, the
contents of general register R2 are used to generate
Condition Code: The code remains unchanged. the branch address; however, when the R2 field is
zero, the operation is performed without branching.
Program Exceptions:
BRANCH ON COUNT
dition codes (0, 1, 2, and 3) correspond, left to right, with a value of 07F0 hex) may result in significant
with the four bits of the mask, as follows: performance degradation. To ensure optimum
performance, the program should avoid use of
Instruction Bit Mask BCR 15,0 except in cases when the serialization
Condition Number of Position or checkpoint-synchronization function is actually
Code Mask Value required.
0 8 8
When the fast-BCR-serialization facility is
1 9 4
installed, and the program only needs the serial-
2 10 2 ization function (without the checkpoint synchro-
3 11 1 nization function), then BCR 14,0 should be
used. Depending on the model, this may be
The current condition code is used to select the cor- faster than BCR 15,0.
responding mask bit. If the mask bit selected by the
condition code is one, the branch is successful. If the 5. Note that the relation between the RR and RX
mask bit selected is zero, normal instruction formats in branch-address specification is not the
sequencing proceeds with the next sequential same as in operand-address specification. For
instruction. branch instructions in the RX format, the branch
address is the address specified by X2, B2, and
When the M1 and R2 fields of BRANCH ON CONDI- D2; in the RR format, the branch address is con-
TION (BCR) are 1111 binary and 0000 binary, tained in the register designated by R2. For oper-
respectively, a serialization and checkpoint-synchro- ands, the address specified by X2, B2, and D2 is
nization function is performed. When the fast-BCR- the operand address, but the register designated
serialization facility is installed and the M1 and R2 by R2 contains the operand, not the operand
fields of BRANCH ON CONDITION (BCR) are 1110 address.
binary and 0000 binary, respectively, a serialization
function is performed. BRANCH ON COUNT
Condition Code: The code remains unchanged. Register-and-register formats:
3. An initial count of one results in zero, and no For BRANCH ON INDEX HIGH, when the sum is
branching takes place; an initial count of zero high, the instruction address in the current PSW is
results in -1 and causes branching to be per- replaced by the branch address. When the sum is
formed; an initial count of -1 results in -2 and low or equal, normal instruction sequencing pro-
causes branching to be performed; and so on. In ceeds with the updated instruction address.
a loop, branching takes place each time the
instruction is executed until the result is again For BRANCH ON INDEX LOW OR EQUAL, when the
zero. Note that for BCT or BCTR, because of the sum is low or equal, the instruction address in the
number range, an initial count of -231 results in a current PSW is replaced by the branch address.
positive value of 231 - 1, or, for BCTG or BCTGR, When the sum is high, normal instruction sequencing
an initial count of -263 results in a positive value proceeds with the updated instruction address.
of 263 - 1.
4. Counting is performed without branching when When the R3 field is even, it designates a pair of reg-
the R2 field in the RR or RRE format contains isters; the contents of the even and odd registers of
zero. the pair are used as the increment and the compare
value, respectively. When the R3 field is odd, it desig-
nates a single register, the contents of which are
used as both the increment and the compare value.
The original contents of the compare-value register BRANCH RELATIVE AND SAVE
are used as the compare value even when that regis-
ter is also specified to be the first-operand location. BRAS R1,RI2 [RI-b]
The branch address is generated before general reg- 'A7' R1 '5' RI2
ister R1 is changed. 0 8 12 16 31
The contents of the I2 field are a signed binary inte- BRXHG R1,R3,RI2 [RIE-e]
ger specifying the number of halfwords that is added 'EC' R1 R3 RI2 //////// '44'
to the address of the instruction to generate the
0 8 12 16 32 40 47
branch address.
CHECKSUM
to the first operand proceeds left to right, four-byte
CKSM R1,R2 [RRE] element by four-byte element, and ends as soon as
(1) the entire second operand has been processed or
'B241' / / / / / / / / R1 R2 (2) a lesser CPU-determined amount of the second
0 16 24 28 31 operand has been processed. In either case, the
result in bit positions 32-63 of general register R1 is a
Successive four-byte elements of the second oper- 32-bit checksum for the part of the second operand
and are added to the first operand in bit positions that has been processed. When the second operand
32-63 of general register R1 to form a 32-bit check- is not a multiple of four bytes, the final second-oper-
sum in those bit positions. The first operand and the and bytes in excess of a multiple of four are concep-
four-byte elements are treated as 32-bit unsigned tually appended on the right with an appropriate
binary integers. After each addition of an element, a number of all-zeros bytes to form the final four-byte
carry out of bit position 32 of the first operand is element.
added to bit position 63 of the first operand. Bits 0-31
of general register R1 always remain unchanged. If If the operation ends because the entire second
the second operand is not a multiple of four bytes, its operand has been processed, the condition code is
last one, two, or three bytes are treated as appended set to 0. If the operation ends because a lesser CPU-
on the right with the number of all-zeros bytes determined amount of the second operand has been
needed to form a four-byte element. The four-byte processed, the condition code is set to 3. When the
elements are added to the first operand until either operation is to end with a setting of condition code 3,
the entire second operand or a CPU-determined any carry out of bit position 32 of the first operand is
amount of the second operand has been processed. added to bit position 63 of the first operand before
The result is indicated in the condition code. the operation ends.
The R2 field designates an even-odd pair of general At the completion of the operation, the 32-bit or 64-bit
registers and must designate an even-numbered reg- operand-length field in the R2 + 1 register is decre-
ister; otherwise, a specification exception is recog- mented by the number of actual second-operand
nized. bytes added to the first operand (not including any
conceptually appended all-zeros bytes), and the
The location of the leftmost byte of the second oper- address in the R2 register is incremented by the
and is specified by the contents of the R2 general same number. Thus, the 32-bit or 64-bit operand-
register. The number of bytes in the second-operand length field contains a zero value if the condition
location is specified by the 32-bit or 64-bit unsigned code is set to 0, or it contains a nonzero value if the
binary integer in the R2 + 1 general register. condition code is set to 3. In the 24-bit or 31-bit
addressing mode, bits 0-31 of the R2 + 1 register
The handling of the address in general register R2 always remain unchanged.
and the length in general register R2 + 1 is depen-
dent on the addressing mode. In the 24-bit address- When condition code 3 is set, the general registers
ing mode, the contents of bit positions 40-63 of used by the instruction have been set so that the
general register R2 constitute the address, and the remainder of the second operand can be processed
contents of bit positions 0-39 are ignored. In the by simply branching back to reexecute the instruc-
31-bit addressing mode, the contents of bit positions tion.
33-63 of the register constitute the address, and the
contents of bit positions 0-32 are ignored. In the The amount of processing that results in the setting
64-bit addressing mode, the contents of bit positions of condition code 3 is determined by the CPU on the
0-63 of the register constitute the address. In the basis of improving system performance, and it may
24-bit or 31-bit addressing mode, the length is a be a different amount each time the instruction is
32-bit unsigned binary integer in bit positions 32-63 executed. The minimum amount is four bytes or the
of general register R2 + 1, and the contents of bit number of bytes specified in the R2 + 1 general regis-
positions 0-31 are ignored. In the 64-bit addressing ter, whichever is smaller.
mode, the length is a 64-bit unsigned binary integer
in the register. At the completion of the operation in the 24-bit or
31-bit addressing mode, the leftmost bits which are
eral register R2 may be set to zeros or may remain represented as A,B, meaning the value A in bit
unchanged, even when the initial length in register positions 32-47 and the value B in bit positions
R2 + 1 is zero. Bits 0-31 of general register R2 remain 48-63. The value C is a carry from A + B. Note
unchanged. that bit positions 32-63 of register R2 + 1 are
known to contain all zeros when CHECKSUM
When the R1 register is the same register as the R2 has set condition code 0.
or R2 + 1 register, the results are unpredictable.
R2 Bits R2 + 1 Bits
Access exceptions for the portion of the second oper- Program 32-63 32-63
and to the right of the last byte processed may or LR R2,R1 A,B 0,0
may not be recognized. For a second operand longer SRDL R2,16 0,A B,0
than 4K bytes, access exceptions are not recognized ALR R2,R2+1 B,A B,0
for locations more than 4K bytes beyond the last byte ALR R2,R1 A+B+C,A+B B,0
processed. SRL R2,16 0,A+B+C B,0
Access exceptions are not recognized if the R2 field 3. The CHECKSUM instruction may be used in
is odd. When the length of the second operand is computing hash values as illustrated in the fol-
zero, no access exceptions are recognized. lowing programming example. The variable KEY
contains a string to be mapped into a slot in a
Resulting Condition Code: hash table. The variable SIZE is a prime number
designating the size of the hash table. The value
0 Entire second operand processed of SIZE is determined by (a) the number of
1 -- strings to be hashed into the table divided by the
2 -- acceptable number of hash collisions, and (b) a
3 CPU-determined amount of second operand pro- value that is not too close to a power of two. Fol-
cessed lowing the DIVIDE (D) instruction, the remainder
in register 0 represents the resulting hash value.
Program Exceptions:
SR 1,1 Zero accumulator
• Access (fetch, operand 2) LA 2,KEY Point to string
• Specification LA 3,L'KEY Load string length
LOOP CKSM 1,2 Compute checksum
Programming Notes: BNZ LOOP Repeat if not done
SR 0,0 Zero for divide
1. The initial contents of bit positions 32-63 of the D 0,SIZE Compute hash value
R1 general register contribute to the 32-bit check- …
sum. The program normally should set those KEY DS CL64 String to be hashed
contents to all zeros before issuing the CHECK- SIZE DS F Size of hash table
SUM instruction.
4. In the access-register mode, access register 0
2. A 16-bit checksum is used in, for example, the designates the primary address space regard-
TCP/IP application. The following program can less of the contents of access register 0.
be executed after the CHECKSUM instruction to
produce in bit positions 32-63 of general register 5. The storage-operand references of CHECKSUM
R2 a 16-bit checksum from the 32-bit checksum may be multiple-access references. (See “Stor-
in bit positions 32-63 of general register R1. The age-Operand Consistency” on page 5-95.)
program is annotated to show the contents of bit
6. Figure 7-3 on page 7-45 contains a summary of
positions 32-63 of the R2 and R2 + 1 registers
the operation.
after the execution of each instruction. The con-
INC I LEN
ELEMENT I INC bytes at ADR
No
LEN >= 4 followed by 4-INC
all-zero bytes
Yes
INC I 4
ELEMENT I 4 bytes at ADR
CHECKSUM I CHECKSUM +
ELEMENT
Carry Yes
from CHECKSUM I CHECKSUM + 1
addition
No
LEN = 0
No or CPU-determined
reason to end
operation
Yes
No
LEN = 0
Yes
follows.
KM R1,R2 [RRE]
Parm. Data
'B92E' / / / / / / / / R1 R2 Block Block
0 16 24 28 31 Size Size
Code Function (bytes) (bytes)
0 KM-Query 16 —
CIPHER MESSAGE WITH 1 KM-DEA 8 8
CHAINING 2 KM-TDEA-128 16 8
3 KM-TDEA-192 24 8
KMC R1,R2 [RRE]
9 KM-Encrypted-DEA 32 8
'B92F' / / / / / / / / R1 R2
10 KM-Encrypted-TDEA-128 40 8
0 16 24 28 31
11 KM-Encrypted-TDEA-192 48 8
18 KM-AES-128 16 16
A function specified by the function code in general
register 0 is performed. 19 KM-AES-192 24 16
20 KM-AES-256 32 16
Bits 16-23 of the instruction are ignored. 26 KM-Encrypted-AES-128 48 16
27 KM-Encrypted-AES-192 56 16
Bit positions 57-63 of general register 0 contain the
function code. Figure 7-4 and 7-5 show the assigned 28 KM-Encrypted-AES-256 64 16
function codes for CIPHER MESSAGE and CIPHER 50 KM-XTS-AES-128 32 16
MESSAGE WITH CHAINING, respectively. All other 52 KM-XTS-AES-256 48 16
function codes are unassigned. For cipher functions,
58 KM-XTS-Encrypted-AES-128 64 16
bit 56 is the modifier bit which specifies whether an
encryption or a decryption operation is to be per- 60 KM-XTS-Encrypted-AES-256 80 16
formed. The modifier bit is ignored for all other func- Explanation:
tions. All other bits of general register 0 are ignored.
— Not applicable
General register 1 contains the logical address of the
Figure 7-4. Function Codes for CIPHER MESSAGE
leftmost byte of the parameter block in storage. In the
24-bit addressing mode, the contents of bit positions
The function codes for CIPHER MESSAGE WITH
40-63 of general register 1 constitute the address,
CHAINING are as follows.
and the contents of bit positions 0-39 are ignored. In
the 31-bit addressing mode, the contents of bit posi-
Parm. Data
tions 33-63 of general register 1 constitute the
Block Block
address, and the contents of bit positions 0-32 are
Size Size
ignored. In the 64-bit addressing mode, the contents Code Function (bytes) (bytes)
of bit positions 0-63 of general register 1 constitute
0 KMC-Query 16 —
the address.
1 KMC-DEA 16 8
2 KMC-TDEA-128 24 8
3 KMC-TDEA-192 32 8
9 KMC-Encrypted-DEA 40 8
10 KMC-Encrypted-TDEA-128 48 8
11 KMC-Encrypted-TDEA-192 56 8
18 KMC-AES-128 32 16
19 KMC-AES-192 40 16
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 33 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 First-Operand Address
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
The result is obtained as if processing starts at the progress. However, the CPU protects against end-
left end of both the first and second operands and less reoccurrence of this no-progress case.
proceeds to the right, block by block. The operation is
ended when the number of bytes in the second oper- The results in the first-operand location, the chaining-
and as specified in general register R2 + 1 have been value field, or the XTS parameter field are unpredict-
processed and placed at the first-operand location able if any of the following situations occur:
(called normal completion) or when a CPU-deter-
mined number of blocks that is less than the length of 1. The cryptographic-key field or the encrypted
the second operand have been processed (called cryptographic-key field overlaps any portion of
partial completion). The CPU-determined number of the first operand.
blocks depends on the model, and may be a different
number each time the instruction is executed. The 2. The XTS parameter field overlaps any portion of
CPU-determined number of blocks is usually non- the first operand.
zero. In certain unusual situations, this number may 3. The chaining-value field overlaps any portion of
be zero, and condition code 3 may be set with no the first operand or the second operand.
Access exceptions may be reported for a larger por- Figure 7-8. Symbol For XTS Multiplication Operation Over
tion of an operand than is processed in a single exe- GF(2128)
cution of the instruction; however, access exceptions
are not recognized for locations beyond the length of
an operand nor for locations more than 4K bytes
beyond the current location being processed.
Figure 7-9. Symbols for DEA Encryption and Decryption Figure 7-11. Symbols for AES-192 Encryption and
Decryption
The parameter block used for the function has the fol-
lowing format:
0
Status Word
8
0 63
Operand 1 ...
The parameter block used for the KM-DEA function in C1 <8> C2 <8> C3 <8> Cn <8>
has the following format: Storage ...
0 Cryptographic Key (K) Figure 7-16. KM-DEA Encipher Operation Using 64-Bit Key
0 63
Figure 7-14. Parameter Block for KM-DEA When the modifier bit in general register 0 is one, a
decipher operation is performed. The 8-byte cipher-
For the KM-DEA function, the cryptographic key is in text blocks (C1, C2, …, Cn) in operand 2 are deci-
byte offsets 0-7 of the parameter block. phered using the DEA algorithm with the 64-bit
cryptographic key. Each ciphertext block is indepen-
The parameter block used for the KM-Encrypted- dently deciphered; that is, the decipher operation is
DEA function has the following format: performed without chaining. The plaintext blocks (P1,
P2, …, Pn) are stored in operand 1. The operation is
shown in Figure 7-17.
0 Encrypted Cryptographic Key (WKd(K))
8 DEA Wrapping-Key
16 Verification Pattern
(WKdVP) Operand 2 ...
24 in C1 <8> C2 <8> C3 <8> Cn <8>
Storage ...
0 63
Figure 7-15. Parameter Block for KM-Encrypted-DEA K DEA K DEA K DEA K DEA
<8> d <8> d <8> d <8> d
For the KM-Encrypted-DEA function, the contents of
byte offsets 8-31 of the parameter block are com- Operand 1 ...
in P1 <8> P2 <8> P3 <8> Pn <8>
pared with the contents of the DEA wrapping-key ver- Storage ...
ification-pattern register. If they mismatch, the
operation is completed by setting condition code 1. If
they match, the contents of byte offsets 0-7 of the Figure 7-17. KM-DEA Decipher Operation Using 64-Bit Key
parameter block are deciphered using the DEA wrap-
ping key to obtain the 64-bit cryptographic key. (See KM-TDEA-128 (KM Function Code 2)
the section, “Protection of Cryptographic Key” on
page 7-339, for details.) KM-Encrypted-TDEA-128 (KM Function
Code 10)
The following description applies to both functions.
The locations of the operands and addresses used
by the instruction are as shown in Figure 7-6 on
page 7-48.
function has the following format: encipher operation is performed. The 8-byte plaintext
blocks (P1, P2, …, Pn) in operand 2 are enciphered
0 Cryptographic Key 1 (K1) using the TDEA (triple DEA) algorithm with the two
8 Cryptographic Key 2 (K2) 64-bit cryptographic keys. Each plaintext block is
0 63
independently enciphered; that is, the encipher oper-
ation is performed without chaining. The ciphertext
Figure 7-18. Parameter Block for KM-TDEA-128 blocks (C1, C2, …, Cn) are stored in operand 1. The
operation is shown in Figure 7-20.
For the KM-TDEA-128 function, the cryptographic
key is in byte offsets 0-15 of the parameter block.
Operand 2 ...
in P1 <8> P2 <8> P3 <8> Pn <8>
The parameter block used for the KM-Encrypted- Storage ...
TDEA-128 function has the following format:
K1 DEA K1 DEA K1 DEA K1 DEA
0 Encrypted Cryptographic Key <8> e e e e
8 (WKd(K))
16 DEA Wrapping-Key K2 DEA K2 DEA K2 DEA K2 DEA
24 Verification Pattern d d d d
<8>
32 (WKdVP)
0 63
K1 DEA K1 DEA K1 DEA K1 DEA
<8> e e e e
Figure 7-19. Parameter Block for KM-Encrypted-TDEA-128
Operand 1 ...
For the KM-Encrypted-TDEA-128 function, the con- in C1 <8> C2 <8> C3 <8> Cn <8>
Storage ...
tents of byte offsets 16-39 of the parameter block are
compared with the contents of the DEA wrapping-key
verification-pattern register. If they mismatch, the K = K1 || K2, where || means concatenation
operation is completed by setting condition code 1. If
Figure 7-20. KM-TDEA Encipher Operation Using 128-Bit
they match, the contents of byte offsets 0-15 of the
Key
parameter block are deciphered using the DEA wrap-
ping key to obtain the 128-bit cryptographic key, K =
When the modifier bit in general register 0 is one, a
K1 || K2, where K1 is the leftmost 64 bits of K and K2
decipher operation is performed. The 8-byte cipher-
is the rightmost 64 bits of K. (See the section, “Pro-
text blocks (C1, C2, …, Cn) in operand 2 are deci-
tection of Cryptographic Key” on page 7-339, for phered using the TDEA algorithm with the two 64-bit
details.) cryptographic keys. Each ciphertext block is indepen-
dently deciphered; that is, the decipher operation is
The following description applies to both functions. performed without chaining. The plaintext blocks (P1,
0 Encrypted
K1 DEA K1 DEA K1 DEA K1 DEA 8 Cryptographic
<8> d d d d
16 Key (WKd(K))
24 DEA Wrapping-Key
K2 DEA K2 DEA K2 DEA K2 DEA 32 Verification Pattern
<8> e e e e
40 (WKdVP)
0 63
K1 DEA K1 DEA K1 DEA K1 DEA
<8> d d d d Figure 7-23. Parameter Block for KM-Encrypted-TDEA-192
Figure 7-24. KM TDEA Encipher Operation Using 192-Bit Figure 7-25. KM TDEA Decipher Operation Using 192-Bit
Key Key
When the modifier bit in general register 0 is one, a KM-AES-128 (KM Function Code 18)
decipher operation is performed. The 8-byte cipher-
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the TDEA algorithm with the three KM-Encrypted-AES-128 (KM Function
64-bit cryptographic keys. Each ciphertext block is Code 26)
independently deciphered; that is, the decipher oper- The locations of the operands and addresses used
ation is performed without chaining. The plaintext by the instruction are as shown in Figure 7-6 on
page 7-48.
0
Cryptographic Key
8
0 63
When the modifier bit in general register 0 is zero, an The parameter block used for the KM-AES-192 func-
encipher operation is performed. The 16-byte plain- tion has the following format:
text blocks (P1, P2, …, Pn) in operand 2 are enci-
phered using the AES algorithm with the 128-bit 0
cryptographic key. Each plaintext block is indepen- 8 Cryptographic Key
dently enciphered; that is, the encipher operation is 16
performed without chaining. The ciphertext blocks 0 63
(C1, C2, …, Cn) are stored in operand 1. The opera-
tion is shown in Figure 7-28. Figure 7-30. Parameter Block for KM-AES-192
0 Encrypted
Operand 1 ...
in C1 <16> C2 <16> C3 <16> Cn <16>
8 Cryptographic
Storage ... Key (WKa(K))
16
Figure 7-28. KM-AES Encipher Operation Using 128-Bit 24
Key 32 AES Wrapping-Key
Verification Pattern
40 (WKaVP)
When the modifier bit in general register 0 is one, a
48
decipher operation is performed. The 16-byte cipher-
0 63
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the AES algorithm with the 128-bit Figure 7-31. Parameter Block for KM-Encrypted-AES-192
cryptographic key. Each ciphertext block is indepen-
tents of byte offsets 24-55 of the parameter block are shown Figure 7-33.
compared with the contents of the AES wrapping-key
verification-pattern register. If they mismatch, the
operation is completed by setting condition code 1. If Operand 2 ...
in C1 <16> C2 <16> C3 <16> Cn <16>
they match, the contents of byte offsets 0-23 of the Storage ...
parameter block are deciphered using the AES wrap-
ping key to obtain the 192-bit cryptographic key, K. K AES K AES K AES K AES
(See the section, “Protection of Cryptographic Key” <24> d <24> d <24> d <24> d
When the modifier bit in general register 0 is zero, an Figure 7-33. KM AES Decipher Operation Using 192-Bit
Key
encipher operation is performed. The 16-byte plain-
text blocks (P1, P2, …, Pn) in operand 2 are enci-
phered using the AES algorithm with the 192-bit KM-AES-256 (KM Function Code 20)
cryptographic key. Each plaintext block is indepen-
dently enciphered; that is, the encipher operation is KM-Encrypted-AES-256 (KM Function
performed without chaining. The ciphertext blocks Code 28)
(C1, C2, …, Cn) are stored in operand 1. The opera-
The locations of the operands and addresses used
tion is shown in Figure 7-32.
by the instruction are as shown in Figure 7-6 on
page 7-48.
Operand 2 ...
in P1 <16> P2 <16> P3 <16> Pn <16> The parameter block used for the KM-AES-256 func-
Storage ...
tion has the following format:
When the modifier bit in general register 0 is one, a For the KM-AES-256 function, the cryptographic key
decipher operation is performed. The 16-byte cipher- is in byte offsets 0-31 of the parameter block.
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the AES algorithm with the 192-bit The parameter block used for the KM-Encrypted-
cryptographic key. Each ciphertext block is indepen- AES-256 function has the following format:
dently deciphered; that is, the decipher operation is
performed without chaining. The plaintext blocks (P1, 0 Encrypted
8 Cryptographic
16 Key
24 (WKa(K))
32
40 AES Wrapping-Key
Verification Pattern
48 (WKaVP)
56
0 63
encrypted-AES-128 function has the following for- obtain the XTS parameter for the next block. The
mat: operation is shown in Figure 7-40.
The plaintext blocks (P1, P2, …, Pn) are stored in For the KM-XTS-Encrypted-AES-256 function, the
operand 1. The XTS parameter for the next block, contents of byte offsets 32-63 of the parameter block
called output XTS parameter (output XTSP) is stored are compared with the contents of the AES wrap-
into the initial XTS parameter field of the parameter ping-key verification-pattern register. If they mis-
block. match, the operation is completed by setting
condition code 1. If they match, byte offsets 64-79 of
KM-XTS-AES-256 (KM Function Code 52) the parameter block contain the initial XTS parame-
ter, and the contents of byte offsets 0-31 of the
parameter block are deciphered using the AES wrap-
KM-XTS-Encrypted-AES-256 (KM
ping key to obtain the 256-bit cryptographic key. (See
Function Code 60) the section “Protection of Cryptographic Key” on
The locations of the operands and addresses used page 7-339 for details.)
by the instruction are as shown in Figure 7-6 on
page 7-48. The following description applies to both functions.
The parameter block used for the KM-XTS-AES-256 When the modifier bit in general register 0 is zero, an
function has the following format: encipher operation is performed. The 16-byte plain-
text blocks (P1, P2, …, Pn) in operand 2 are enci-
0 phered using the AES-encryption algorithm with the
8 256-bit cryptographic key and the 128-bit initial XTS
Cryptographic Key (K)
16 parameter.
24
Except for the first block, the XTS parameter used is
32
Initial XTS Parameter the XTS parameter for the previous block multiplied
40
by the value of 2 in GF(2128). To encrypt the first block
0 63
of plaintext, the initial XTS parameter is used.
Figure 7-42. Parameter Block for KM-XTS-AES-256
The XTS parameter for each block is exclusive-ORed
For the KM-XTS-AES-256 function, the cryptographic with the corresponding plaintext block. The result of
key is in byte offsets 0-31 of the parameter block, and the exclusive-OR operation is then encrypted using
the AES-encryption algorithm with the 256-bit crypto-
Initial Output
XTSP * ... * * XTSP C1 XOR C2 XOR ... Cn XOR
<16> <16>
<16> <16> <16>
P1 P2 ... Pn
XOR XOR XOR <16> <16> <16>
<16> <16> <16> The plaintext blocks (P1, P2, …, Pn) are stored in
operand 1. The XTS parameter for the next block,
Figure 7-44. KM-XTS-AES-256 Encipher Operation
called output XTS parameter (output XTSP) is stored
The ciphertext blocks (C1, C2, …, Cn) are stored in into the initial XTS parameter field of the parameter
operand 1. The XTS parameter for the next block, block.
called output XTS parameter (output XTSP) is stored
into the initial XTS parameter field of the parameter KMC-Query (KMC Function Code 0)
block. The locations of the operands and addresses used
by the instruction are as shown in Figure 7-6 on
When the modifier bit in general register 0 is one, a page 7-48.
decipher operation is performed. The 16-byte cipher-
text blocks (C1, C2, …, Cn) in operand 2 are deci- The parameter block used for the function has the fol-
phered using the AES-decryption algorithm with the lowing format:
256-bit cryptographic key and the 128-bit initial XTS
parameter. 0
Status Word
8
Except for the first block, the XTS parameter used is 0 63
the XTS parameter for the previous block multiplied
128 Figure 7-46. Parameter Block for KMC-Query
by the value of 2 in GF(2 ). To decrypt the first block
of ciphertext, the initial XTS parameter is used.
A 128-bit status word is stored in the parameter
The XTS parameter for each block is exclusive-ORed block. Bits 0-127 of this field correspond to function
with the corresponding ciphertext block. The result of codes 0-127, respectively, of the CIPHER MESSAGE
the exclusive-OR operation is then decrypted using WITH CHAINING instruction. When a bit is one, the
the AES-decryption algorithm with the 256-bit crypto- corresponding function is installed; otherwise, the
graphic key. The result of the encryption is then function is not installed.
exclusive-ORed with the XTS parameter to produce
the plaintext block. The XTS parameter for this block Condition code 0 is set when execution of the KMC-
128
is multiplied by the value of 2 in GF(2 ) to obtain the Query function completes; condition code 3 is not
applicable to this function.
0 63
Figure 7-49. KMC DEA Encipher Operation Using 64-Bit
Figure 7-48. Parameter Block for KMC-Encrypted-DEA Key
For the KMC-Encrypted-DEA function, the contents When the modifier bit in general register 0 is one, a
of byte offsets 16-39 of the parameter block are com- decipher operation is performed. The 8-byte cipher-
pared with the contents of the DEA wrapping-key ver- text blocks (C1, C2, …, Cn) in operand 2 are deci-
ification-pattern register. If they mismatch, the phered using the DEA algorithm with the 64-bit
operation is completed by setting condition code 1. If cryptographic key and the 64-bit chaining value.
they match, the contents of byte offsets 8-15 of the
parameter block are deciphered using the DEA wrap- The chaining value, called the initial chaining value
ping key to obtain the 64-bit cryptographic key. (See (ICV), for deriving the first plaintext block is in the
the section, “Protection of Cryptographic Key” on parameter block; the chaining value for deriving each
page 7-339, for details.) The chaining value is in byte subsequent plaintext block is the corresponding pre-
offsets 0-7 of the parameter block. vious ciphertext block. The plaintext blocks (P1, P2,
…, Pn) are stored in operand 1. The last ciphertext
block is the output chaining value (OCV) and is
block. The operation is shown in Figure 7-50. TDEA-128 function has the following format:
ICV xor xor xor ... xor K1 DEA K1 DEA K1 DEA K1 DEA
<8> <8> d d d d
Figure 7-53. KMC TDEA Encipher Operation Using 128-Bit Figure 7-54. KMC TDEA Decipher Operation Using 128-Bit
Key Key
When the modifier bit in general register 0 is one, a KMC-TDEA-192 (KMC Function Code 3)
decipher operation is performed. The 8-byte cipher-
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the TDEA algorithm with the two 64-bit KMC-Encrypted-TDEA-192 (KMC
cryptographic keys and the 64-bit chaining value. Function Code 11)
The locations of the operands and addresses used
The chaining value, called the initial chaining value by the instruction are as shown in Figure 7-6 on
(ICV), for deriving the first plaintext block is in the page 7-48.
parameter block; the chaining value for deriving each
subsequent plaintext block is the corresponding pre- The parameter block used for the KMC-TDEA-192
vious ciphertext block. The plaintext blocks (P1, P2, function has the following format:
…, Pn) are stored in operand 1. The last ciphertext
block is the output chaining value (OCV) and is 0 Chaining Value (CV)
8 Cryptographic Key 1 (K1)
16 Cryptographic Key 2 (K2)
24 Cryptographic Key 3 (K3)
0 63
TDEA-192 function has the following format: field of the parameter block. The operation is shown
in Figure 7-57.
0 Chaining Value (CV)
8
Operand 2 ...
Encrypted Cryptographic Key
16 in P1 <8> P2 <8> P3 <8> Pn <8>
(WKd(K)) Storage ...
24
32 DEA Wrapping-Key ...
ICV xor xor xor xor
40 Verification Pattern <8>
48 (WKdVP)
0 63 K1 DEA K1 DEA K1 DEA K1 DEA
<8> e e e e
Figure 7-56. Parameter Block for KMC-Encrypted-TDEA-
192
K2 DEA K2 DEA K2 DEA K2 DEA
<8> d d d d
For the KMC-Encrypted-TDEA-192 function, the con-
tents of byte offsets 32-55 of the parameter block are
compared with the contents of the DEA wrapping-key K3 DEA K3 DEA K3 DEA K3 DEA
verification-pattern register. If they mismatch, the <8>
e e e e
operation is completed by setting condition code 1. If OCV
they match, the contents of byte offsets 8-31 of the Operand 1 ...
in C1 <8> C2 <8> C3 <8> Cn <8>
parameter block are deciphered using the DEA wrap- Storage ...
ping key to obtain the 192-bit cryptographic key. (See
the section, “Protection of Cryptographic Key” on
K = K1 || K2 || K3, where || means concatenation
page 7-339, for details.) The chaining value is in byte
offsets 0-7 of the parameter block. Figure 7-57. KMC TDEA Encipher Operation Using 192-Bit
Key
The following description applies to both functions.
When the modifier bit in general register 0 is one, a
When the modifier bit in general register 0 is zero, an decipher operation is performed. The 8-byte cipher-
encipher operation is performed. The 8-byte plaintext text blocks (C1, C2, …, Cn) in operand 2 are deci-
blocks (P1, P2, …, Pn) in operand 2 are enciphered phered using the TDEA algorithm with the three
using the TDEA algorithm with the three 64-bit cryp- 64-bit cryptographic keys and the 64-bit chaining
tographic keys and the 64-bit chaining value. value.
The chaining value, called the initial chaining value The chaining value, called the initial chaining value
(ICV), for deriving the first ciphertext block is the (ICV), for deriving the first plaintext block is in the
chaining value in the parameter block; the chaining parameter block; the chaining value for deriving each
value for deriving each subsequent ciphertext block subsequent plaintext block is the corresponding pre-
is the corresponding previous ciphertext block. The vious ciphertext block. The plaintext blocks (P1, P2,
ciphertext blocks (C1, C2, …, Cn) are stored in oper- …, Pn) are stored in operand 1. The last ciphertext
and 1. The last ciphertext block is the output chaining block is the output chaining value (OCV) and is
<8>
Figure 7-60. Parameter Block for KMC-Encrypted-AES-128
Operand 1 ...
in P1 <8> P2 <8> P3 <8> Pn <8>
Storage ... For the KMC-Encrypted-AES-128 function, the con-
tents of byte offsets 32-63 of the parameter block are
K = K1 || K2 || K3, where || means concatenation
compared with the contents of the AES wrapping-key
verification-pattern register. If they mismatch, the
Figure 7-58. KMC TDEA Decipher Operation Using 192-Bit operation is completed by setting condition code 1. If
Key they match, the contents of byte offsets 16-31 of the
parameter block are deciphered using the AES wrap-
KMC-AES-128 (KMC Function Code 18) ping key to obtain the 128-bit cryptographic key, K.
(See the section, “Protection of Cryptographic Key”
KMC-Encrypted-AES-128 (KMC Function on page 7-339, for details.) The chaining value is in
byte offsets 0-15 of the parameter block.
Code 26)
The locations of the operands and addresses used
The following description applies to both functions.
by the instruction are as shown in Figure 7-6 on
page 7-48. When the modifier bit in general register 0 is zero, an
encipher operation is performed. The 16-byte plain-
The parameter block used for the KMC-AES-128 text blocks (P1, P2, …, Pn) in operand 2 are enci-
function has the following format: phered using the AES algorithm with the 128-bit
cryptographic key and the 128-bit chaining value.
0
Chaining Value (CV)
8 The chaining value, called the initial chaining value
16 (ICV), for deriving the first ciphertext block is the
Cryptographic Key (K)
24 chaining value in the parameter block; the chaining
0 63 value for deriving each subsequent ciphertext block
is the corresponding previous ciphertext block. The
Figure 7-59. Parameter Block for KMC-AES-128 ciphertext blocks (C1, C2, …, Cn) are stored in oper-
and 1. The last ciphertext block is the output chaining
value (OCV) and is stored into the chaining-value
in Figure 7-61.
KMC-Encrypted-AES-192 (KMC Function
Operand 2 ... Code 27)
in P1 <16> P2 <16> P3 <16> Pn <16> The locations of the operands and addresses used
Storage ...
by the instruction are as shown in Figure 7-6 on
page 7-48.
ICV xor xor xor ... xor
<16>
The parameter block used for the KMC-AES-192
function has the following format:
K AES K AES K AES K AES
<16> e <16> e <16> e <16> e
OCV 0
Chaining Value (CV)
Operand 1 ... 8
in C1 <16> C2 <16> C3 <16> Cn <16>
Storage ... 16
24 Cryptographic Key (K)
Figure 7-61. KMC AES Encipher Operation Using 128-Bit
Key 32
0 63
...
40
Operand 2
in C1 <16> C2 <16> C3 <16> Cn <16> 48 AES Wrapping-Key
Storage ... Verification Pattern
OCV 56 (WKaVP)
K AES K AES K AES K AES
64
<16> d <16> d <16>
d <16> d 0 63
The chaining value, called the initial chaining value K AES K AES K AES K AES
(ICV), for deriving the first ciphertext block is the <24> d <24> d <24> d <24> d
0
Chaining Value (CV) Operand 2 ...
8 in P1 <16> P2 <16> P3 <16> Pn <16>
Storage ...
16
24 Encrypted Cryptographic Key
ICV xor xor xor ... xor
32 (WKa(K))
<16>
40
48 K AES K AES K AES K AES
AES Wrapping-Key <32> e <32> e e <32> e
56 <32>
Verification Pattern OCV
64 (WKaVP) Operand 1 ...
72 in C1 <16> C2 <16> C3 <16> Cn <16>
Storage ...
0 63
The parameter block used for the function has the fol- Parameter
Block in CV <8> K1 <8> K2 <8> K3 <8>
lowing format: Storage
Operand 1 ...
in C1 <8> C2 <8> C3 <8> Cn <8>
Storage ...
Programming Notes:
part of the operation. operands, and the contents of bit positions 0-31 are
ignored; bits 32-63 of the updated value replace the
The R1 field designates a general register and must corresponding bits in general register R2 + 1. In the
designate an even-numbered register; otherwise, a 64-bit addressing mode, the contents of bit positions
specification exception is recognized. 0-63 of general register R2 + 1 form a 64-bit unsigned
binary integer which specifies the number of bytes in
The R2 field designates an even-odd pair of general the first and second operands; and the updated value
registers and must designate an even-numbered reg- replaces the contents of general register R2 + 1.
ister; otherwise, a specification exception is recog-
nized. In the 24-bit or 31-bit addressing mode, the contents
of bit positions 0-31 of general registers R1, R2, and
The location of the leftmost byte of the first and sec- R2 + 1, always remain unchanged.
ond operands is specified by the contents of the R1
and R2 general registers, respectively. The number of Figure 7-6 on page 7-48 shows the contents of the
bytes in the second-operand location is specified in general registers just described.
general register R2 + 1. The first operand is the same
length as the second operand. In the access-register mode, access registers 1, R1,
and R2 specify the address spaces containing the
As part of the operation, the addresses in general parameter block, first, and second operands, respec-
registers R1 and R2 are incremented by the number tively.
of bytes processed, and the length in general register
R2 + 1 is decremented by the same number. The for- The result is obtained as if processing starts at the
mation and updating of the addresses and length is left end of both the first and second operands and
dependent on the addressing mode. proceeds to the right, block by block. The operation is
ended when the number of bytes in the second oper-
In the 24-bit addressing mode, the contents of bit and as specified in general register R2 + 1 have been
positions 40-63 of general registers R1 and R2 consti- processed and placed at the first-operand location
tute the addresses of the first and second operands, (called normal completion) or when a CPU-deter-
respectively, and the contents of bit positions 0-39 mined number of blocks that is less than the length of
are ignored; bits 40-63 of the updated addresses the second operand have been processed (called
replace the corresponding bits in general registers R1 partial completion). The CPU-determined number of
and R2, carries out of bit position 40 of the updated blocks depends on the model, and may be a different
address are ignored, and the contents of bit positions number each time the instruction is executed. The
32-39 of general registers R1 and R2 are set to zeros. CPU-determined number of blocks is usually non-
In the 31-bit addressing mode, the contents of bit zero. In certain unusual situations, this number may
positions 33-63 of general registers R1 and R2 consti- be zero, and condition code 3 may be set with no
tute the addresses of the first and second operands, progress. However, the CPU protects against end-
respectively, and the contents of bit positions 0-32 less reoccurrence of this no-progress case.
are ignored; bits 33-63 of the updated addresses
replace the corresponding bits in general registers R1 The results in the first-operand location and the
and R2, carries out of bit position 33 of the updated chaining-value field are unpredictable if any of the fol-
address are ignored, and the content of bit position lowing situations occur:
32 of general registers R1 and R2 is set to zero. In the
64-bit addressing mode, the contents of bit positions 1. The cryptographic-key field or the encrypted
0-63 of general registers R1 and R2 constitute the cryptographic-key field overlaps any portion of
addresses of the first and second operands, respec- the first operand.
tively; bits 0-63 of the updated addresses replace the
contents of general registers R1 and R2, and carries 2. The chaining-value field overlaps any portion of
out of bit position 0 are ignored. the first operand or the second operand.
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 33 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 First-Operand Address
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
a source after data would have been moved into accessed, general registers R1, R2, and R2 + 1 are
it, assuming processing to be performed from left not changed, and condition code 0 is set.
to right and one byte at a time.
When the contents of the R1 and R2 fields are the
When the operation ends due to normal completion, same, the contents of the designated registers are
condition code 0 is set and the resulting value in incremented only by the number of bytes processed,
R2 + 1 is zero. When the operation ends due to par- not by twice the number of bytes processed.
tial completion, condition code 3 is set and the result-
ing value in R2 + 1 is nonzero. As observed by other CPUs and channel programs,
references to the parameter block and storage oper-
When a storage-alteration PER event is recognized, ands may be multiple-access references, accesses
fewer than 4K additional bytes are stored into the to these storage locations are not necessarily block-
first-operand locations before the event is reported. concurrent, and the sequence of these accesses or
references is undefined.
When the second-operand length is initially zero, the
parameter block, first, and second operands are not
B xor
C
C = A XOR B
The parameter block used for the function has the fol- For the KMF-Encrypted-DEA function, the contents
lowing format: of byte offsets 16-39 of the parameter block are com-
pared with the contents of the DEA wrapping-key ver-
0 ification-pattern register. If they mismatch, the
Status Word
8 operation is completed by setting condition code 1. If
0 63 they match, byte offsets 0-7 of the parameter block
contain the chaining value, and the contents of byte
Figure 7-81. Parameter Block for KMF-Query
offsets 8-15 of the parameter block are deciphered
using the DEA wrapping key to obtain the 64-bit cryp-
Symbol Explanation
tographic Key” on page 7-339 for details.)
|| Concatenation
b Block size; 8 bytes for DEA
The following description applies to both functions. Ij Input block j to DEA
RB(Ij) Rightmost (b-s) bytes of input block j
When the modifier bit in general register 0 is zero, an Figure 7-84. KMF-DEA Encipher Operation (Continued)
encipher operation is performed. The s-byte plaintext
When the modifier bit in general register 0 is one, a
segments (P1, P2, …, Pn) in operand 2 are enci-
decipher operation is performed. The s-byte cipher-
phered using the DEA-encryption algorithm with the
text segments (C1, C2, …, Cn) in operand 2 are deci-
64-bit cryptographic key and the 64-bit chaining
phered using the DEA-encryption algorithm with the
value, where s is the length of cipher feedback in
64-bit cryptographic key and the 64-bit chaining
bytes.
value, where s is the length of cipher feedback in
bytes.
The first input block to the DEA-encryption algorithm
is the initial chaining value (ICV) in the parameter
The first input block to the DEA-encryption algorithm
block. Each input block is enciphered to produce an
is the initial chaining value (ICV) in the parameter
output block. The s leftmost bytes of each output
block. Each input block is enciphered to produce an
block are exclusive-ORed with the corresponding s-
output block. The s leftmost bytes of each output
byte plaintext segment to form a s-byte ciphertext
block are exclusive-ORed with the corresponding s-
segment. The remaining (8 - s) bytes of each output
byte ciphertext segment to form a s-byte plaintext
block are ignored. Each ciphertext segment is con-
segment. The remaining (8 - s) bytes of each output
catenated to the right of the (8 - s) rightmost bytes of
block are ignored. Each ciphertext segment is con-
the previous input block to form the next input block.
catenated to the right of the (8 - s) rightmost bytes of
the previous input block to form the next input block.
The process is repeated with the successive input
blocks until a ciphertext segment is produced for
The process is repeated with the successive input
every plaintext segment, or until a CPU-determined
blocks until a plaintext segment is produced for every
number of ciphertext segments have been produced.
ciphertext segment, or until a CPU-determined num-
ber of plaintext segments have been produced.
The ciphertext segments (C1, C2, …, Cn) are stored
in operand 1. The next input block is stored into the
The plaintext segments (P1, P2, …, Pn) are stored in
chaining-value field of the parameter block. The oper-
operand 1. The next input block (OCV) is stored into
ation is shown in Figure 7-49.
…
I1 I2 In
ICV <8> RB(I1) C1 … RB(In-1) Cn-1
…
<s> <s> <s>
C1 C2 … Cn
OCV = RB(In) || Cn
For the KMF-TDEA-128 function, the chaining value The process is repeated with the successive input
is in byte offset 0-7 of the parameter block and the blocks until a ciphertext segment is produced for
cryptographic key is in byte offsets 8-23 of the every plaintext segment, or until a CPU-determined
parameter block. number of ciphertext segments have been produced.
ation is shown in Figure 7-88. blocks until a plaintext segment is produced for every
ciphertext segment, or until a CPU-determined num-
ber of plaintext segments have been produced.
…
I1 I2 In The plaintext segments (P1, P2, …, Pn) are stored in
ICV <8> RB(I1) C1 … RB(In-1) Cn-1 operand 1. The next input block (OCV) is stored into
the chaining-value field of the parameter block. The
operation is shown in Figure 7-89.
K1 DEA K1 DEA … K1 DEA
<8> e <8> e <8> e
…
K2 DEA K2 DEA … K2 DEA
I1 I2 In
<8> d <8> d <8> d
ICV <8> RB(I1) C1 … RB(In-1) Cn-1
…
<s> <s> <s> K2 DEA K2 DEA … K2 DEA
<8> d <8> d <8> d
C1 C2 … Cn
…
K = K1 || K2 OCV = RB(In) || Cn <s> <s> <s>
Symbol Explanation
XOR C1 XOR C2 … XOR Cn
|| Concatenation
b Block size; 8 bytes for TDEA <s> <s> <s>
Ij Input block j to TDEA
RB(Ij) Rightmost (b-s) bytes of input block j
P1 P2 … Pn
Figure 7-88. KMF-TDEA-128 Encipher Operation
K = K1 || K2 OCV = RB(In) || Cn
When the modifier bit in general register 0 is one, a
Symbol Explanation
decipher operation is performed. The s-byte cipher-
text segments (C1, C2, …, Cn) in operand 2 are deci- || Concatenation
b Block size; 8 bytes for TDEA
phered using the TDEA-encryption algorithm with the Ij Input block j to TDEA
128-bit cryptographic key and the 64-bit chaining RB(Ij) Rightmost (b-s) bytes of input block j
value, where s is the length of cipher feedback in Figure 7-89. KMF-TDEA-128 Decipher Operation
bytes.
KMF-TDEA-192 (Function Code 3)
The first input block to the TDEA-encryption algo-
rithm is the initial chaining value (ICV) in the parame-
ter block. Each input block is enciphered to produce KMF-Encrypted-TDEA-192 (Function
an output block. The s leftmost bytes of each output Code 11)
block are exclusive-ORed with the corresponding s- The locations of the operands and addresses used
byte ciphertext segment to form a s-byte plaintext by the instruction are as shown in Figure 7-6 on
segment. The remaining (8 - s) bytes of each output page 7-48.
block are ignored. Each ciphertext segment is con-
catenated to the right of the (8 - s) rightmost bytes of
the previous input block to form the next input block.
For the KMF-TDEA-192 function, the chaining value The process is repeated with the successive input
is in byte offset 0-7 of the parameter block and the blocks until a ciphertext segment is produced for
cryptographic key is in byte offsets 8-31 of the every plaintext segment, or until a CPU-determined
parameter block. number of ciphertext segments have been produced.
The parameter block used for the KMF-Encrypted- The ciphertext segments (C1, C2, …, Cn) are stored
TDEA-192 function has the following format: in operand 1. The next input block (OCV) is stored
into the chaining-value field of the parameter block.
0 Chaining Value (CV) The operation is shown in Figure 7-92.
8
Encrypted Cryptographic Key
16 …
(WKd(K))
24 I1 I2 In
32 ICV <8> RB(I1) C1 … RB(In-1) Cn-1
DEA Wrapping-Key
40 Verification Pattern
48 (WKdVP)
K1 DEA K1 DEA … K1 DEA
0 63 <8> e <8> e <8> e
Symbol Explanation
When the modifier bit in general register 0 is zero, an || Concatenation
encipher operation is performed. The s-byte plaintext b Block size; 8 bytes for TDEA
Ij Input block j to TDEA
segments (P1, P2, …, Pn) in operand 2 are enci- RB(Ij) Rightmost (b-s) bytes of input block j
phered using the TDEA-encryption algorithm with the
Figure 7-92. KMF-TDEA-192 Encipher Operation
192-bit cryptographic key and the 64-bit chaining
value, where s is the length of cipher feedback in
When the modifier bit in general register 0 is one, a
bytes.
decipher operation is performed. The s-byte cipher-
Symbol Explanation
phered using the TDEA-encryption algorithm with the
|| Concatenation
192-bit cryptographic key and the 64-bit chaining b Block size; 8 bytes for TDEA
value, where s is the length of cipher feedback in Ij Input block j to TDEA
RB(Ij) Rightmost (b-s) bytes of input block j
bytes.
Figure 7-93. KMF-TDEA-192 Decipher Operation
The first input block to the TDEA-encryption algo-
rithm is the initial chaining value (ICV) in the parame- KMF-AES-128 (Function Code 18)
ter block. Each input block is enciphered to produce
an output block. The s leftmost bytes of each output KMF-Encrypted-AES-128 (Function Code
block are exclusive-ORed with the corresponding s- 26)
byte ciphertext segment to form a s-byte plaintext
The locations of the operands and addresses used
segment. The remaining (8 - s) bytes of each output
by the instruction are as shown in Figure 7-6 on
block are ignored. Each ciphertext segment is con-
page 7-48.
catenated to the right of the (8 - s) rightmost bytes of
the previous input block to form the next input block.
The parameter block used for the KMF-AES-128
function has the following format:
The process is repeated with the successive input
blocks until a plaintext segment is produced for every
0
ciphertext segment, or until a CPU-determined num- Chaining Value (CV)
ber of plaintext segments have been produced. 8
16
Cryptographic Key (K)
The plaintext segments (P1, P2, …, Pn) are stored in 24
operand 1. The next input block is stored into the 0 63
chaining-value field of the parameter block.The oper-
Figure 7-94. Parameter Block for KMF-AES-128
ation is shown in Figure 7-93.
For the KMF-AES-128 function, the chaining value is
… in byte offset 0-15 of the parameter block and the
I1 I2 In
cryptographic key is in byte offsets 16-31 of the
ICV <8> RB(I1) C1 … RB(In-1) Cn-1
parameter block.
0
K2 DEA K2 DEA … K2 DEA Chaining Value (CV)
<8> d <8> d <8> d 8
16 Encrypted Cryptographic Key
24 (WKa(K))
K3 DEA K3 DEA … K3 DEA
<8> e <8> e <8> e
32
40 AES Wrapping-Key
Verification-Pattern
… 48 (WKaVP)
<s> <s> <s>
56
0 63
XOR C1 XOR C2 … XOR Cn
Figure 7-95. Parameter Block for KMF-Encrypted-AES-128
<s> <s> <s>
The first input block to the AES-encryption algorithm <s> <s> <s>
The process is repeated with the successive input When the modifier bit in general register 0 is one, a
blocks until a ciphertext segment is produced for decipher operation is performed. The s-byte cipher-
every plaintext segment, or until a CPU-determined text segments (C1, C2, …, Cn) in operand 2 are deci-
number of ciphertext segments have been produced. phered using the AES-encryption algorithm with the
128-bit cryptographic key and the 128-bit chaining
The ciphertext segments (C1, C2, …, Cn) are stored value, where s is the length of cipher feedback in
in operand 1. The next input block is stored into the bytes.
operand 1. The next input block (OCV) is stored into parameter block.
the chaining-value field of the parameter block. The
operation is shown in Figure 7-97. The parameter block used for the KMF-Encrypted-
AES-192 function has the following format:
… 0
Chaining Value (CV)
I1 I2 In 8
ICV <16> RB(I1) C1 … RB(In-1) Cn-1 16
Encrypted Cryptographic Key
24
(WKa(K))
K AES K AES … K AES 32
<16> e <16> e <16> e
40
48 AES Wrapping-Key
… Verification Pattern
56 (WKaVP)
<s> <s> <s>
64
XOR C1 XOR C2 … XOR Cn 0 63
|| Concatenation
P1 P2 … Pn
b Block size; 16 bytes for AES
Ij Input block j to AES
RB(Ij) Rightmost (b-s) bytes of input block j OCV = RB(In) || Cn
Figure 7-100. KMF-AES-192 Encipher Operation
Symbol Explanation
phered using the AES-encryption algorithm with the Figure 7-101. KMF-AES-192 Decipher Operation
192-bit cryptographic key and the 128-bit chaining
value, where s is the length of cipher feedback in KMF-AES-256 (Function Code 20)
bytes.
The first input block to the AES-encryption algorithm KMF-Encrypted-AES-256 (Function Code
is the initial chaining value (ICV) in the parameter 28)
block. Each input block is enciphered to produce an The locations of the operands and addresses used
output block. The s leftmost bytes of each output by the instruction are as shown in Figure 7-6 on
block are exclusive-ORed with the corresponding s- page 7-48.
function has the following format: 256-bit cryptographic key and the 128-bit chaining
value, where s is the length of cipher feedback in
0 bytes.
Chaining Value (CV)
8
The first input block to the AES-encryption algorithm
16
is the initial chaining value (ICV) in the parameter
24
Cryptographic Key (K) block. Each input block is enciphered to produce an
32 output block. The s leftmost bytes of each output
40 block are exclusive-ORed with the corresponding s-
0 63 byte plaintext segment to form a s-byte ciphertext
segment. The remaining (16 - s) bytes of each output
Figure 7-102. Parameter Block for KMF-AES-256
block are ignored. Each ciphertext segment is con-
catenated to the right of the (16 - s) rightmost bytes
For the KMF-AES-256 function, the chaining value is
of the previous input block to form the next input
in byte offset 0-15 of the parameter block and the
block.
cryptographic key is in byte offsets 16-47 of the
parameter block.
The process is repeated with the successive input
blocks until a ciphertext segment is produced for
The parameter block used for the KMF-Encrypted-
every plaintext segment, or until a CPU-determined
AES-256 function has the following format:
number of ciphertext segments have been produced.
0
Chaining Value (CV) The ciphertext segments (C1, C2, …, Cn) are stored
8 in operand 1. The next input block (OCV) is stored
16 into the chaining-value field of the parameter
24 Encrypted Cryptographic Key block.The operation is shown in Figure 7-104.
32 (WKa(K))
40
…
48
AES Wrapping-Key I1 I2 In
56 …
Verification Pattern ICV <16> RB(I1) C1 RB(In-1) Cn-1
64 (WKaVP)
72
0 63
K AES K AES … K AES
<32> e <32> e <32> e
The process is repeated with the successive input 3. Bits 57-63 of general register 0 specify an unas-
blocks until a plaintext segment is produced for every signed or uninstalled function code.
ciphertext segment, or until a CPU-determined num-
4. The R1 or R2 field designates an odd-numbered
ber of plaintext segments have been produced.
register or general register 0.
The plaintext segments (P1, P2, …, Pn) are stored in 5. The second operand length is not a multiple of
operand 1. The next input block is stored into the the length of cipher feedback. This specification-
chaining-value field of the parameter block. The oper- exception condition does not apply to the query
ation is shown in Figure 7-105. functions.
P1 P2 … Pn
OCV = RB(In) || Cn
0 are ignored.
1.-6. Exceptions with the same priority as the priority
of program-interruption conditions for the general General register 1 contains the logical address of the
case. leftmost byte of the parameter block in storage. In the
24-bit addressing mode, the contents of bit positions
7.A Access exceptions for second instruction
40-63 of general register 1 constitute the address,
halfword.
and the contents of bit positions 0-39 are ignored. In
7.B Operation exception. the 31-bit addressing mode, the contents of bit posi-
tions 33-63 of general register 1 constitute the
8. Specification exception due to invalid function address, and the contents of bit positions 0-32 are
code or invalid register number.
ignored. In the 64-bit addressing mode, the contents
9. Specification exception due to invalid operand of bit positions 0-63 of general register 1 constitute
length. the address.
10. Condition code 0 due to second-operand length The function codes for CIPHER MESSAGE WITH
originally zero.
COUNTER are as follows.
11. Access exceptions for an access to the
parameter block, first, or second operand. Parm. Data
Block Block
12. Condition code 1 due to verification pattern Size Size
mismatch. Code Function (bytes) (bytes)
13. Condition code 0 due to normal completion 0 KMCTR-Query 16 —
(second-operand length originally nonzero, but 1 KMCTR-DEA 8 8
stepped to zero).
2 KMCTR-TDEA-128 16 8
14. Condition code 3 due to partial completion 3 KMCTR-TDEA-192 24 8
(second-operand length still nonzero).
9 KMCTR-Encrypted-DEA 32 8
Figure 7-106. Priority of Execution: KMF 10 KMCTR-Encrypted-TDEA-128 40 8
11 KMCTR-Encrypted-TDEA-192 48 8
Programming Note: See the programming notes for
18 KMCTR-AES-128 16 16
CIPHER MESSAGE WITH CHAINING.
19 KMCTR-AES-192 24 16
20 KMCTR-AES-256 32 16
CIPHER MESSAGE WITH
26 KMCTR-Encrypted-AES-128 48 16
COUNTER 27 KMCTR-Encrypted-AES-192 56 16
KMCTR R1,R3,R2 [RRF-b] 28 KMCTR-Encrypted-AES-256 64 16
‘B92D’ R 3 / / / / R1 R2 Explanation:
0 16 20 24 28 31
— Not applicable
The R1 field designates a general register and must In both the 24-bit and the 31-bit addressing modes,
designate an even-numbered register; otherwise, a the contents of bit positions 32-63 of general register
specification exception is recognized. R2 + 1 form a 32-bit unsigned binary integer which
specifies the number of bytes in the first, second, and
The R2 field designates an even-odd pair of general third operands, and the contents of bit positions 0-31
registers and must designate an even-numbered reg- are ignored; bits 32-63 of the updated value replace
ister; otherwise, a specification exception is recog- the corresponding bits in general register R2 + 1. In
nized. the 64-bit addressing mode, the contents of bit posi-
tions 0-63 of general register R2 + 1 form a 64-bit
The R3 field designates a general register and must unsigned binary integer which specifies the number
designate an even-numbered register; otherwise, a of bytes in the first, second, and third operands; and
specification exception is recognized. the updated value replaces the contents of general
register R2 + 1.
The location of the leftmost byte of the first, second,
and third operands is specified by the contents of the In the 24-bit or 31-bit addressing mode, the contents
R1, R2, and R3 general registers, respectively. The of bit positions 0-31 of general registers R1, R2,
number of bytes in the second-operand location is R2 + 1, and R3 always remain unchanged.
specified in general register R2 + 1. The first operand
and the third operand are the same length as the Figure 7-108 on page 7-88 shows the contents of the
second operand. general registers just described.
As part of the operation, the addresses in general In the access-register mode, access registers 1, R1,
registers R1, R2, and R3 are incremented by the num- R2, and R3 specify the address spaces containing the
ber of bytes processed, and the length in general parameter block, first, second, and third operands,
register R2 + 1 is decremented by the same number. respectively.
The formation and updating of the addresses and
length is dependent on the addressing mode. The result is obtained as if processing starts at the
left end of the first, second, and third operands and
In the 24-bit addressing mode, the contents of bit proceeds to the right, block by block. The operation is
positions 40-63 of general registers R1, R2, and R3 ended when the number of bytes in the second oper-
constitute the addresses of the first, second, and and as specified in general register R2 + 1 have been
third operands, respectively, and the contents of bit processed and placed at the first-operand location
positions 0-39 are ignored; bits 40-63 of the updated (called normal completion) or when a CPU-deter-
addresses replace the corresponding bits in general mined number of blocks that is less than the length of
registers R1, R2, and R3, carries out of bit position 40 the second operand have been processed (called
of the updated address are ignored, and the contents partial completion). The CPU-determined number of
of bit positions 32-39 of general registers R1, R2, and blocks depends on the model, and may be a different
R3 are set to zeros. In the 31-bit addressing mode, number each time the instruction is executed. The
the contents of bit positions 33-63 of general regis- CPU-determined number of blocks is usually non-
ters R1, R2, and R3 constitute the addresses of the zero. In certain unusual situations, this number may
first, second, and third operands, respectively, and be zero, and condition code 3 may be set with no
the contents of bit positions 0-32 are ignored; bits progress. However, the CPU protects against end-
33-63 of the updated addresses replace the corre- less reoccurrence of this no-progress case.
sponding bits in general registers R1, R2, and R3, car-
ries out of bit position 33 of the updated address are The results in the first-operand location are unpre-
ignored, and the content of bit position 32 of general dictable if any of the following situations occurs:
registers R1, R2, and R3 is set to zero. In the 64-bit
addressing mode, the contents of bit positions 0-63 1. The cryptographic-key field or the encrypted
of general registers R1, R2, and R3 constitute the cryptographic-key field overlaps any portion of
addresses of the first, second, and third operands, the first operand.
respectively; bits 0-63 of the updated addresses
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 33 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 First-Operand Address
0 63
R2 Second-Operand Address
0 63
R3 Third-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
2. The first and second operands overlap destruc- processing to be performed from left to right and one
tively. byte at a time.
3. The first and third operands overlap destructively. When the operation ends due to normal completion,
condition code 0 is set and the resulting value in
Operands are said to overlap destructively when the R2 + 1 is zero. When the operation ends due to par-
first-operand location would be used as a source tial completion, condition code 3 is set and the result-
after data would have been moved into it, assuming ing value in R2 + 1 is nonzero.
Figure 7-112. Symbols for AES-192 Encryption The parameter block used for the KMCTR-DEA func-
tion has the following format:
K <32> P <16>
0 Cryptographic Key (K)
0 63
AES
e Figure 7-115. Parameter Block for KM-DEA
...
Operand 3 0 Cryptographic Key 1 (K1)
in Storage R1 <8> R2 <8> R3 <8> Rn <8>
...
8 Cryptographic Key 2 (K2)
0 63
K DEA K DEA K DEA ... K DEA
<8> e <8> e <8> e <8> e Figure 7-119. Parameter Block for KMCTR-TDEA-128
When the modifier bit in general register 0 is one, a 0 Encrypted Cryptographic Key
decipher operation is performed. The 8-byte cipher- 8 (WKd(K))
text blocks (C1, C2, …, Cn) in operand 2 are deci- 16 DEA Wrapping-Key
phered using the DEA algorithm with the 64-bit 24 Verification Pattern
cryptographic key and using 8-byte counter-value (WKdVP)
32
blocks (R1, R2, …, Rn) in operand 3. Each ciphertext
0 63
block is independently deciphered; that is, the deci-
pher operation is performed without chaining. The Figure 7-120. Parameter Block for KMCTR Encrypted-
plaintext blocks (P1, P2, …, Pn) are stored in oper- TDEA-128
and 1. The operation is shown in Figure 7-118.
For the KMCTR-Encrypted-TDEA-128 function, the
contents of byte offsets 16-39 of the parameter block
Operand 2
...... are compared with the contents of the DEA wrap-
in Storage C1 <8> C2 <8> C3 <8> Cn <8> ping-key verification-pattern register. If they mis-
...
match, the operation is completed by setting
...
Operand 3
R1 <8> R2 <8> R3 <8> Rn <8>
condition code 1. If they match, the contents of byte
in Storage ...
offsets 0-15 of the parameter block are deciphered
using the DEA wrapping key to obtain the 128-bit
K DEA K DEA K DEA ... K DEA cryptographic key, K = K1 || K2, where K1 is the left-
<8> e <8> e <8> e <8> e
most 64 bits of K and K2 is the rightmost 64 bits of K.
(See the section “Protection of Cryptographic Key”
C1 C2 C3 ... Cn on page 7-339 for details.)
<8> XOR <8> XOR <8> XOR <8> XOR
64-bit cryptographic keys and using 8-byte counter- and 1. The operation is shown in Figure 7-122.
value blocks (R1, R2, …, Rn) in operand 3. Each
plaintext block is independently enciphered; that is,
...
the encipher operation is performed without chaining. Operand 2
C1 <8> C2 <8> C3 <8> Cn <8>
in Storage ...
The ciphertext blocks (C1, C2, …, Cn) are stored in
operand 1. The operation is shown in Figure 7-121. ...
Operand 3
in Storage R1 <8> R2 <8> R3 <8> Rn <8>
...
...
Operand 2
in Storage P1 <8> P2 <8> P3 <8> Pn <8> K1 DEA K1 DEA K1 DEA ... K1 DEA
...
<8> e <8> e <8> e <8> e
...
Operand 3
in Storage R1 <8> R2 <8> R3 <8> Rn <8>
... K2 DEA K2 DEA K2 DEA ... K1 DEA
<8> d <8> d <8> d <8> d
...
Operand 1
in Storage C1 <8> C2 <8> C3 <8>
...
Cn <8> KMCTR-TDEA-192 (Function Code 3)
Figure 7-121. KMCTR TDEA Encipher Operation Using
128-Bit Key
KMCTR-Encrypted-TDEA-192 (Function
Code 11)
When the modifier bit in general register 0 is one, a The locations of the operands and addresses used
decipher operation is performed. The 8-byte cipher- by the instruction are as shown in Figure 7-108 on
text blocks (C1, C2, …, Cn) in operand 2 are deci- page 7-88.
phered using the TDEA algorithm with the two 64-bit
cryptographic keys and using 8-byte counter-value The parameter block used for the KMCTR-TEDA-192
blocks (R1, R2, …, Rn) in operand 3. Each ciphertext function has the following format:
block is independently deciphered; that is, the deci-
pher operation is performed without chaining. The 0 Cryptographic Key 1 (K1)
8 Cryptographic Key 2 (K2)
16 Cryptographic Key 3 (K3)
0 63
operand 1. The operation is shown in Figure 7-126. key is in byte offsets 0-15 of the parameter block.
0
P1 P2 P3 ... Pn 8 Cryptographic Key (K)
<16> XOR <16> XOR <16> XOR <16> XOR
16
... 0 63
Operand 1
in Storage C1 <16> C2 <16> C3 <16> Cn <16>
...
Figure 7-131. Parameter Block for KMCTR-AES-192
Figure 7-129. KMCTR AES Encipher Operation Using 128-
Bit Key For the KMCTR-AES-192 function, the cryptographic
key is in byte offsets 0-23 of the parameter block.
When the modifier bit in general register 0 is one, a
decipher operation is performed. The 16-byte cipher- The parameter block used for the KMCTR-
text blocks (C1, C2, …, Cn) in operand 2 are deci- Encrypted-AES-192 function has the following for-
phered using the AES algorithm with the 128-bit mat:
cryptographic key and using 16-byte counter-value
blocks (R1, R2, …, Rn) in operand 3. Each ciphertext 0 Encrypted
block is independently deciphered; that is, the deci- 8 Cryptographic
pher operation is performed without chaining. The 16 Key (WKa(K))
plaintext blocks (P1, P2, …, Pn) are stored in oper-
24
and 1. The operation is shown in Figure 7-130. AES Wrapping-Key
32
Verification Pattern
40 (WKaVP)
Operand 2
... 48
in Storage C1 <16> C2 <16> C3 <16> Cn <16>
... 0 63
Operand 3
... Figure 7-132. Parameter Block for KMCTR-Encrypted-
in Storage R1 <16> R2 <16> R3 <16> Rn <16> AES-192
...
phered using the AES algorithm with the 192-bit and 1. The operation is shown Figure 7-134.
cryptographic key and using 16-byte counter-value
blocks (R1, R2, …, Rn) in operand 3. Each plaintext
block is independently enciphered; that is, the enci- Operand 2
...
C1 <16> C2 <16> C3 <16> Cn <16>
pher operation is performed without chaining. The in Storage ...
ciphertext blocks (C1, C2, …, Cn) are stored in oper-
...
and 1. The operation is shown in Figure 7-133. Operand 3
R1 <16> R2 <16> R3 <16> Rn <16>
in Storage ...
... C1 C2 C3 Cn
Operand 3 ...
in Storage R1 <16> R2 <16> R3 <16> Rn <16> <16> XOR <16> XOR <16> XOR <16> XOR
...
...
K DEA K DEA K DEA K DEA Operand 1
... P1 <16> P2 <16> P3 <16> Pn <16>
<24> e <24> e <24> e <24> e in Storage ...
Operand 1
... KMCTR-AES-256 (Function Code 20)
in Storage C1 <16> C2 <16> C3 <16> Cn <16>
...
KMCTR-Encrypted-AES-256 (Function
Figure 7-133. KMCTR AES Encipher Operation Using 192-
Bit Key Code 28)
The locations of the operands and addresses used
When the modifier bit in general register 0 is one, a by the instruction are as shown in Figure 7-108 on
decipher operation is performed. The 16-byte cipher- page 7-88.
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the AES algorithm with the 192-bit The parameter block used for the KMCTR-AES-256
cryptographic key and using 16-byte counter-value function has the following format:
blocks (R1, R2, …, Rn) in operand 3. Each ciphertext
block is independently deciphered; that is, the deci- 0
pher operation is performed without chaining. The 8
Cryptographic Key (K)
16
24
0 63
C1 C2 C3 ... Cn
<16> XOR <16> XOR <16> XOR <16> XOR
...
Operand 1
in Storage P1 <16> P2 <16> P3 <16> Pn <16>
...
• Access (fetch, operand 2,operand 3, and crypto- 13. Condition code 0 due to normal completion
graphic key; store, operand 1) (second-operand length originally nonzero, but
• Operation (if the message-security-assist exten- stepped to zero).
sion 4 facility is not installed) 14. Condition code 3 due to partial completion
• Specification (second-operand length still nonzero).
The function codes for CIPHER MESSAGE WITH The location of the leftmost byte of the first and sec-
OFB are as follows. ond operands is specified by the contents of the R1
and R2 general registers, respectively. The number of
Parm. Data bytes in the second-operand location is specified in
Block Block general register R2 + 1. The first operand is the same
Size Size length as the second operand.
Code Function (bytes) (bytes)
0 KMO-Query 16 — As part of the operation, the addresses in general
1 KMO-DEA 16 8 registers R1 and R2 are incremented by the number
of bytes processed, and the length in general register
2 KMO-TDEA-128 24 8
R2 + 1 is decremented by the same number. The for-
3 KMO-TDEA-192 32 8 mation and updating of the addresses and length is
9 KMO-Encrypted-DEA 40 8 dependent on the addressing mode.
10 KMO-Encrypted-TDEA-128 48 8
In the 24-bit addressing mode, the contents of bit
11 KMO-Encrypted-TDEA-192 56 8
positions 40-63 of general registers R1 and R2 consti-
18 KMO-AES-128 32 16 tute the addresses of the first and second operands,
19 KMO-AES-192 40 16 respectively, and the contents of bit positions 0-39
20 KMO-AES-256 48 16 are ignored; bits 40-63 of the updated addresses
replace the corresponding bits in general registers R1
26 KMO-Encrypted-AES-128 64 16
and R2, carries out of bit position 40 of the updated
27 KMO-Encrypted-AES-192 72 16 address are ignored, and the contents of bit positions
28 KMO-Encrypted-AES-256 80 16 32-39 of general registers R1 and R2 are set to zeros.
In the 31-bit addressing mode, the contents of bit
Explanation:
positions 33-63 of general registers R1 and R2 consti-
— Not applicable tute the addresses of the first and second operands,
respectively, and the contents of bit positions 0-32
Figure 7-140. Function Codes for CIPHER MESSAGE are ignored; bits 33-63 of the updated addresses
WITH OFB replace the corresponding bits in general registers R1
and R2, carries out of bit position 33 of the updated
All other function codes are unassigned. address are ignored, and the content of bit position
32 of general registers R1 and R2 is set to zero. In the
The query function provides the means of indicating 64-bit addressing mode, the contents of bit positions
the availability of the other functions. The contents of 0-63 of general registers R1 and R2 constitute the
general registers R1, R2, and R2 + 1 are ignored for addresses of the first and second operands, respec-
the query function. tively; bits 0-63 of the updated addresses replace the
contents of general registers R1 and R2, and carries
For all other functions, the second operand is out of bit position 0 are ignored.
ciphered as specified by the function code using a
cryptographic key and an initial chaining value in the In both the 24-bit and the 31-bit addressing modes,
parameter block, and the result is placed in the first- the contents of bit positions 32-63 of general register
R2 + 1 form a 32-bit unsigned binary integer which
operands, and the contents of bit positions 0-31 are of bit positions 0-31 of general registers R1, R2, and
ignored; bits 32-63 of the updated value replace the R2 + 1, always remain unchanged.
corresponding bits in general register R2 + 1. In the
64-bit addressing mode, the contents of bit positions Figure 7-141 on page 7-100 shows the contents of
0-63 of general register R2 + 1 form a 64-bit unsigned the general registers just described.
binary integer which specifies the number of bytes in
the first and second operands; and the updated value
replaces the contents of general register R2 + 1.
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Address
0 33 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 First-Operand Address
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
In the access-register mode, access registers 1, R1, The result is obtained as if processing starts at the
and R2 specify the address spaces containing the left end of both the first and second operands and
parameter block, first, and second operands, respec- proceeds to the right, block by block. The operation is
tively. ended when the number of bytes in the second oper-
and as specified in general register R2 + 1 have been
K <16> P <16>
The parameter block used for the function has the fol-
lowing format:
0
Status Word
8
0 63
0 63 …
C1 C2 Cn
Figure 7-149. Parameter Block for KMO-Encrypted-DEA <8> <8> <8>
is the initial chaining value (ICV) in the parameter is in byte offset 0-7 of the parameter block and the
block. Each input block is enciphered to produce an cryptographic key is in byte offsets 8-23 of the
output block. Each output block is exclusive-ORed parameter block.
with the corresponding ciphertext block to form a
plaintext block. Each output block is also used as the The parameter block used for the KMO-Encrypted-
next input block. TDEA-128 function has the following format:
The process is repeated with the successive input 0 Chaining Value (CV)
blocks until a plaintext block is produced for every 8 Encrypted Cryptographic Key
ciphertext block, or until a CPU-determined number (WKd(K))
16
of plaintext blocks have been produced.
24 DEA Wrapping-Key
The plaintext blocks (P1, P2, …, Pn) are stored in 32 Verification Pattern
operand 1. The next input block, called the output 40 (WKdVP)
chaining value (OCV), is stored into the chaining- 0 63
Figure 7-151. KMO-DEA Decipher Operation When the modifier bit in general register 0 is zero, an
encipher operation is performed. The 8-byte plaintext
KMO-TDEA-128 (Function Code 2) blocks (P1, P2, …, Pn) in operand 2 are enciphered
using the TDEA-encryption algorithm with the 128-bit
cryptographic key and the 64-bit chaining value.
KMO-Encrypted-TDEA-128 (Function
Code 10) The first input block to the TDEA-encryption algo-
The locations of the operands and addresses used rithm is the initial chaining value (ICV) in the parame-
by the instruction are as shown in Figure 7-141 on ter block. Each input block is enciphered to produce
page 7-100. an output block. Each output block is exclusive-ORed
with the corresponding plaintext block to form a
The parameter block used for the KMO-TDEA-128 ciphertext block. Each output block is also used as
function has the following format: the next input block.
0 Chaining Value (CV) The process is repeated with the successive input
8 Cryptographic Key 1 (K1) blocks until a ciphertext block is produced for every
16 Cryptographic Key 2 (K2) plaintext block, or until a CPU-determined number of
0 63 ciphertext blocks have been produced.
Figure 7-152. Parameter Block for KMO-TDEA-128 The ciphertext blocks (C1, C2, …, Cn) are stored in
operand 1. The next input block, called the output
ICV <8>
ICV <8>
…
…
K1 DEA K1 DEA … K1 DEA
<8> e <8> e <8> e
K1 DEA K1 DEA … K1 DEA
<8> e <8> e <8> e
TDEA-192 function has the following format: value field of the parameter block. The operation is
The operation is shown in Figure 7-158.
0 Chaining Value (CV)
8
Encrypted Cryptographic Key ICV <8>
16
(WKd(K)) …
24
32 DEA Wrapping-Key K1 DEA K1 DEA … K1 DEA
<8> e <8> e <8> e
40 Verification Pattern
48 (WKdVP)
0 63 K2 DEA K2 DEA … K2 DEA
<8> d <8> d <8> d
Figure 7-157. Parameter Block for KMO-Encrypted-TDEA-
192
K3 DEA K3 DEA … K3 DEA
<8> e <8> e <8> e
For the KMO-Encrypted-TDEA-192 function, the con- OCV
tents of byte offsets 32-55 of the parameter block are
compared with the contents of the DEA wrapping-key XOR P1 XOR P2
… XOR Pn
verification-pattern register. If they mismatch, the <8> <8> <8>
operation is completed by setting condition code 1. If
they match, byte offsets 0-7 of the parameter block …
C1 C2 Cn
contain the chaining value, and the contents of byte <8> <8> <8>
offsets 8-31 of the parameter block are deciphered K = K1 || K2 || K3, where || means concatenation
using the DEA wrapping key to obtain the 192-bit
Figure 7-158. KMO-TDEA-192 Encipher Operation
cryptographic key. (See the section “Protection of
Cryptographic Key” on page 7-339 for details.)
When the modifier bit in general register 0 is one, a
decipher operation is performed. The 8-byte cipher-
The following description applies to both functions.
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the DEA-encryption algorithm with the
When the modifier bit in general register 0 is zero, an
192-bit cryptographic key and the 64-bit chaining
encipher operation is performed. The 8-byte plaintext
value.
blocks (P1, P2, …, Pn) in operand 2 are enciphered
using the TDEA-encryption algorithm with the 192-bit
The first input block to the TDEA-encryption algo-
cryptographic key and the 64-bit chaining value.
rithm is the initial chaining value (ICV) in the parame-
ter block. Each input block is enciphered to produce
The first input block to the TDEA-encryption algo-
an output block. Each output block is exclusive-ORed
rithm is the initial chaining value (ICV) in the parame-
with the corresponding ciphertext block to form a
ter block. Each input block is enciphered to produce
plaintext block. Each output block is also used as the
an output block. Each output block is exclusive-ORed
next input block.
with the corresponding plaintext block to form a
ciphertext block. Each output block is also used as
The process is repeated with the successive input
the next input block.
blocks until a plaintext block is produced for every
ciphertext block, or until a CPU-determined number
The process is repeated with the successive input
of plaintext blocks have been produced.
blocks until a ciphertext block is produced for every
plaintext block, or until a CPU-determined number of
The plaintext blocks (P1, P2, …, Pn) are stored in
ciphertext blocks have been produced.
operand 1. The next input block, called the output
chaining value (OCV), is stored into the chaining-
The ciphertext blocks (C1, C2, …, Cn) are stored in
operand 1. The next input block, called the output
0
ICV <8> Chaining Value (CV)
8
… 16 Encrypted Cryptographic Key
24 (WKa(K))
K1 DEA K1 DEA … K1 DEA
<8> e <8> e <8> e 32
40 AES Wrapping-Key
Verification-Pattern
K2 DEA K2 DEA … K2 DEA 48 (WKaVP)
<8> d <8> d <8> d
56
0 63
K3 DEA K3 DEA … K3 DEA
<8> e <8> e <8> e Figure 7-161. Parameter Block for KMO-Encrypted-AES-
OCV 128
XOR C1 XOR C2
… XOR Cn For the KMO-Encrypted-AES-128 function, the con-
<8> <8> <8> tents of byte offsets 32-63 of the parameter block are
compared with the contents of the AES wrapping-key
…
P1 P2 Pn verification-pattern register. If they mismatch, the
<8> <8> <8> operation is completed by setting condition code 1. If
K = K1 || K2 || K3, where || means concatenation they match, byte offsets 0-15 of the parameter block
contain the chaining value, and the contents of byte
Figure 7-159. KMO-TDEA-192 Decipher Operation
offsets 16-31 of the parameter block are deciphered
using the AES wrapping key to obtain the 128-bit
KMO-AES-128 (Function Code 18) cryptographic key. (See the section “Protection of
Cryptographic Key” on page 7-339 for details.)
KMO-Encrypted-AES-128 (Function
Code 26) The following description applies to both functions.
The locations of the operands and addresses used
by the instruction are as shown in Figure 7-141 on When the modifier bit in general register 0 is zero, an
page 7-100. encipher operation is performed. The 16-byte plain-
text blocks (P1, P2, …, Pn) in operand 2 are enci-
The parameter block used for the KMO-AES-128 phered using the AES-encryption algorithm with the
function has the following format: 128-bit cryptographic key and the 128-bit chaining
value.
0
Chaining Value (CV) The first input block to the AES-encryption algorithm
8
is the initial chaining value (ICV) in the parameter
16 block. Each input block is enciphered to produce an
Cryptographic Key (K)
24 output block. Each output block is exclusive-ORed
0 63 with the corresponding plaintext block to form a
ciphertext block. Each output block is also used as
Figure 7-160. Parameter Block for KMO-AES-128
the next input block.
For the KMO-AES-128 function, the chaining value is
The process is repeated with the successive input
in byte offset 0-15 of the parameter block and the
blocks until a ciphertext block is produced for every
cryptographic key is in byte offsets 16-31 of the
plaintext block, or until a CPU-determined number of
parameter block.
ciphertext blocks have been produced.
… …
XOR P1 XOR P2
… XOR Pn XOR C1 XOR C2
… XOR Cn
<16> <16> <16> <16> <16> <16>
… …
C1 C2 Cn P1 P2 Pn
<16> <16> <16> <16> <16> <16>
Figure 7-162. KMO-AES-128 Encipher Operation Figure 7-163. KMO-AES-128 Decipher Operation
When the modifier bit in general register 0 is one, a KMO-AES-192 (Function Code 19)
decipher operation is performed. The 16-byte cipher-
text blocks (C1, C2, …, Cn) in operand 2 are deci-
phered using the AES-encryption algorithm with the KMO-Encrypted-AES-192 (Function
128-bit cryptographic key and the 128-bit chaining Code 27)
value. The locations of the operands and addresses used
by the instruction are as shown in Figure 7-141 on
The first input block to the AES-encryption algorithm page 7-100.
is the initial chaining value (ICV) in the parameter
block. Each input block is enciphered to produce an The parameter block used for the KMO-AES-192
output block. Each output block is exclusive-ORed function has the following format:
with the corresponding ciphertext block to form a
plaintext block. Each output block is also used as the 0
Chaining Value (CV)
next input block. 8
16
The process is repeated with the successive input
24 Cryptographic Key (K)
blocks until a plaintext block is produced for every
32
ciphertext block, or until a CPU-determined number
0 63
of plaintext blocks have been produced.
Figure 7-164. Parameter Block for KMO-AES-192
The plaintext blocks (P1, P2, …, Pn) are stored in
operand 1. The next input block, called the output For the KMO-AES-192 function, the chaining value is
chaining value (OCV), is stored into the chaining- in byte offset 0-15 of the parameter block and the
cryptographic key is in byte offsets 16-39 of the
parameter block.
0
Chaining Value (CV)
ICV <16> 8
… 16
24 Encrypted Cryptographic Key
K AES K AES … K AES
(WKa(K))
<24> e <24> e <24> e 32
OCV 40
48
XOR C1 XOR C2
… XOR Cn AES Wrapping-Key
56
<16> <16> <16> Verification Pattern
64 (WKaVP)
… 72
P1 P2 Pn
<16> <16> <16> 0 63
Figure 7-167. KMO-AES-192 Decipher Operation Figure 7-169. Parameter Block for KMO-AES-256
ICV <16>
ICV <16>
…
…
K AES K AES … K AES
<32> e <32> e <32> e
K AES K AES … K AES
<32> e <32> e <32> e OCV
OCV
XOR C1 XOR C2
… XOR Cn
XOR P1 XOR P2
… XOR Pn <16> <16> <16>
<16> <16> <16>
…
P1 P2 Pn
… <16> <16> <16>
C1 C2 Cn
<16> <16> <16>
Figure 7-171. KMO-AES-256 Decipher Operation
Figure 7-170. KMO-AES-256 Encipher Operation
Special Conditions
When the modifier bit in general register 0 is one, a
decipher operation is performed. The 16-byte cipher- A specification exception is recognized and no other
text blocks (C1, C2, …, Cn) in operand 2 are deci- action is taken if any of the following occurs:
phered using the AES-encryption algorithm with the
256-bit cryptographic key and the 128-bit chaining 1. Bits 57-63 of general register 0 specify an unas-
value. signed or uninstalled function code.
The first input block to the AES-encryption algorithm 2. The R1 or R2 field designates an odd-numbered
is the initial chaining value (ICV) in the parameter register or general register 0.
block. Each input block is enciphered to produce an 3. The second operand length is not a multiple of
output block. Each output block is exclusive-ORed the data block size of the designated function
with the corresponding ciphertext block to form a (see Figure 7-140 on page 7-99 to determine the
plaintext block. Each output block is also used as the data block sizes for CIPHER MESSAGE WTH
next input block. OFB functions). This specification-exception con-
dition does not apply to the query functions.
The process is repeated with the successive input
blocks until a plaintext block is produced for every Resulting Condition Code:
ciphertext block, or until a CPU-determined number
of plaintext blocks have been produced. 0 Normal completion
1 Verification pattern mismatch
The plaintext blocks (P1, P2, …, Pn) are stored in 2 --
operand 1. The next input block, called the output 3 Partial completion
chaining value (OCV), is stored into the chaining-
Program Exceptions:
C R1,D2(X2,B2) [RX-a]
1.-6. Exceptions with the same priority as the priority
of program-interruption conditions for the general '59' R1 X2 B2 D2
case. 0 8 12 16 20 31
The first operand is compared with the second oper- Condition Code: The code remains unchanged.
and. If the mask bit in the M3 field corresponding to
the comparison result is one, the instruction address Program Exceptions:
in the current PSW is replaced by the branch address
specified by the fourth operand; otherwise, normal • Operation (if the general-instructions-extension
instruction sequencing proceeds with the updated facility is not installed).
instruction address.
Programming Notes:
For COMPARE AND BRANCH (CRB), COMPARE
AND BRANCH RELATIVE (CRJ), COMPARE IMME- 1. When bit positions 0-2 of the M3 field contain
DIATE AND BRANCH (CIB) and COMPARE IMME- zeros, the instruction acts as a NOP, however
DIATE AND BRANCH RELATIVE (CIJ), the first this is not the preferred instruction with which to
operand is treated as a 32-bit signed binary integer. create a NOP. When bit positions 0-2 of the M3
For COMPARE AND BRANCH (CGRB), COMPARE field contain 111 binary, a branch always occurs.
AND BRANCH RELATIVE (CGRJ), COMPARE 2. When COMPARE AND BRANCH RELATIVE or
IMMEDIATE AND BRANCH (CGIB) and COMPARE COMPARE IMMEDIATE AND BRANCH RELA-
IMMEDIATE AND BRANCH RELATIVE (CGIJ), the TIVE are the target of an execute-type instruc-
first operand is treated as a 64-bit signed binary inte- tion, the branch is relative to the target address.
ger. See “Branch-Address Generation” on page 5-10.
For COMPARE AND BRANCH (CRB) and COM- 3. The high-level assembler (HLASM) provides
PARE AND BRANCH RELATIVE (CRJ), the second extended-mnemonic formats for all of the multi-
operand is treated as a 32-bit signed binary integer. ple-operation instructions which perform a com-
For COMPARE AND BRANCH (CGRB) and COM- pare (arithmetic or logical) followed by a branch
PARE AND BRANCH RELATIVE (CGRJ), the sec- or trap. In the extended-mnemonic format, the
ond operand is treated as a 64-bit signed binary mask field is not explicitly coded; rather the
integer. For COMPARE IMMEDIATE AND BRANCH branch mask is implicitly indicated by the
and COMPARE IMMEDIATE AND BRANCH RELA- extended mnemonic.
TIVE, the second operand is treated as an 8-bit
signed binary integer. The extended-mnemonic names are formed by
concatenating the base mnemonic, followed by
The comparison results and corresponding M3 bits one of the suffix characters, as shown below.
are as follows:
Suffix Mask
Chars Meaning Field
Comparison Result M3 Bit
E Equal 8
Equal 0
H First operand high 2
First operand low 1
L First operand low 4
First operand high 2
NE Not equal 6
NH First operand not high 12
bits 32-63 of general registers 1 and 3 are inter- bits 0-63 of general registers 1 and 3 are inter-
changed. If the operand-control bit is one, (1) the changed.
lower halfword is placed in bit positions 48-63 of gen-
eral register 2, and (2) if operand 1 was lower, bits For the purpose of recognizing access exceptions,
32-63 of general registers 1 and 3 are interchanged. operand 1 and operand 3 are both considered to
have a length equal to 6 more than the value of the
For the purpose of recognizing access exceptions, index limit minus the index.
operand 1 and operand 3 are both considered to
have a length equal to 2 more than the value of the Specifications Independent of Addressing Mode
index limit minus the index.
The condition code is unpredictable if the instruction
Operation in the 64-bit Addressing Mode is interrupted.
The operation consists in comparing the first and When the index is initially larger than the index limit,
third operands in units of six bytes at a time and access exceptions are not recognized for the storage
incrementing the index until an unequal pair of six- operands. For operands longer than 4K bytes,
byte units is found or the index exceeds the index access exceptions are not recognized more than 4K
limit. This proceeds in units of operation, between bytes beyond the byte being processed. Access
which interruptions may occur. exceptions are not recognized when a specification-
exception condition exists.
At the start of a unit of operation, the index, bits
48-63 of general register 2, is logically compared with If the B2 field designates general register 2, it is
the index limit. If the index is larger, the instruction is unpredictable whether or not the index limit is recom-
completed by placing bits 0-63 of general register 3, puted; thus, in this case the operand length is unpre-
with bit 0 set to one, in bit positions 0-63 of general dictable. However, in no case can the operands
register 2, and by setting condition code 0. exceed 215 bytes in length.
If the index is less than or equal to the index limit, the Resulting Condition Code:
index is applied to the first-operand and third-oper-
and base addresses to locate the current pair of six- 0 Operands equal
byte units to be compared. The index, with 48 left- 1 Operand-control bit zero and operand 1 low, or
most zeros appended, and bits 0-63 of general regis- operand-control bit one and operand 3 low
ter 1 are added to form the 64-bit address of the 2 Operand-control bit zero and operand 1 high, or
current first-operand six-byte unit. A carry out of bit operand-control bit one and operand 3 high
position 0, if any, is ignored. The address of the cur- 3 --
rent third-operand six-byte unit is formed in the same
manner by adding bits 0-63 of general register 3 and Program Exceptions:
the index.
• Access (fetch, operands 1 and 3)
The current first-operand and third-operand six-byte • Specification
units are logically compared. If they are equal, the
contents of general register 2 are incremented by 6, Programming Notes:
and a unit of operation ends.
1. An example of the use of COMPARE AND
If the compare values are unequal, the contents of FORM CODEWORD is given in “Sorting Instruc-
general register 2 are incremented by 6 and then tions” in Appendix A, “Number Representation
shifted left logically by 48 bit positions. If the oper- and Instruction-Use Examples.”
and-control bit is zero, (1) the one’s complement of
the higher six-byte unit is placed in bit positions 2. The offset of the halfword or six-byte unit
16-63 of general register 2, and (2) if operand 1 was (depending on the addressing mode) of the first
higher, bits 0-63 of general registers 1 and 3 are and third operands at which comparison is to
interchanged. If the operand-control bit is one, (1) the begin should be placed in bit positions 48-63 of
lower six-byte unit is placed in bit positions 16-63 of general register 2 before executing COMPARE
Bit 63 of No
GR1, GR2 and GR3 Specification
all zeros exception
Yes
No
GR2 I GR3 *
1st-operand address I GR1 + *
bits 48-63 of GR2 Bit 32 of GR2 I 1
3rd-operand address I GR3 + *
Condition code I 0
bits 48-63 of GR2
Fetch halfwords from current 1st- and
3rd-operand locations End operation
GR2 I GR2 + 2 *
1st op low
TEMPHW I One's comp- TEMPHW I 1st-op HW TEMPHW I One's comp- TEMPHW I 3rd-op HW
lement of 3rd-op HW lement of 1st-op HW
Exchange GR1 and GR3 * Condition code I 1
Condition code I 1 Exchange GR1 and GR3 *
Condition code I 2
Condition code I 2
Figure 7-174. Execution of COMPARE AND FORM CODEWORD in the 24-Bit or 31-bit Addressing Mode
Bit 63 of No
GR1, GR2 and GR3 Specification
all zeros exception
Yes
No
1st op low
TEMP6 I One's comp- TEMP6 I 1st-op six TEMP6 I One's comp- TEMP6 I 3rd-op six
lement of 3rd-op bytes lement of 1st-op bytes
six bytes six bytes
Exchange GR1 and GR3 * Condition code I 1
Condition code I 1 Exchange GR1 and GR3 *
Condition code I 2
Condition code I 2
Figure 7-176. Execution of COMPARE AND FORM CODEWORD in the 64-bit Addressing Mode
For COMPARE AND SWAP (CS, CSY), the first and The second operand of COMPARE AND SWAP (CS,
third operands are 32 bits in length, with each oper- CSY) must be designated on a word boundary. The
and occupying bit positions 32-63 of a general regis- second operand of COMPARE AND SWAP (CSG)
ter. The second operand is a word in storage. and COMPARE DOUBLE AND SWAP (CDS, CDSY)
must be designated on a doubleword boundary. The
For COMPARE AND SWAP (CSG), the first and third second operand of COMPARE DOUBLE AND SWAP
operands are 64 bits in length, with each operand (CDSG) must be designated on a quadword bound-
occupying bit positions 0-63 of a general register. ary. The R1 and R3 fields for COMPARE DOUBLE
The second operand is a doubleword in storage. AND SWAP must each designate an even-numbered
register. Otherwise, a specification exception is rec-
ognized.
3. COMPARE AND SWAP can be used by CPU 4. COMPARE DOUBLE AND SWAP can be used in
programs sharing common storage areas in a manner similar to that described for COMPARE
either a multiprogramming or multiprocessing AND SWAP. In addition, it has another use. Con-
environment. Two examples are: sider a chained list, with a control word used to
address the first message in the list, as
a. By performing the following procedure, a described in programming note 3.b above. If mul-
CPU program can modify the contents of a tiple CPU programs are to be permitted to delete
storage location even though the possibility messages by using COMPARE AND SWAP (and
exists that the CPU program may be inter- not just the single CPU program which has
rupted by another CPU program that will seized the common area), there is a possibility
update the location or that another CPU pro- the list will be incorrectly updated. This would
gram may simultaneously update the loca- occur if, for example, after one CPU program has
tion. First, the entire word containing the byte fetched the address of the most recent message
or bytes to be updated is loaded into a gen- in order to remove the message, another CPU
eral register. Next, the updated value is com- program removes the first two messages and
puted and placed in another general register. then adds the first message back into the chain.
Then COMPARE AND SWAP is executed The first CPU program, on continuing, cannot
with the R1 field designating the register that easily detect that the list is changed. By increas-
contains the original value and the R3 field ing the size of the control word to a doubleword
designating the register that contains the containing both the first message address and a
updated value. If the update has been suc- word with a change number that is incremented
cessful, condition code 0 is set. If the storage for each modification of the list, and by using
location no longer contains the original COMPARE DOUBLE AND SWAP to update both
value, the update has not been successful, fields together, the possibility of the list being
the general register designated by the R1 incorrectly updated is reduced to a negligible
field of the COMPARE AND SWAP instruc-
if the first CPU program is delayed while changes If they are equal, the replacement value is stored into
exactly equal in number to a multiple of 232 take the first-operand location, and subsequently, the
place and only if the last change places the origi- store value is placed into the second-operand loca-
nal message address in the control word. tion. If they are not equal, then the first operand is
loaded into the third-operand location, and the sec-
5. COMPARE AND SWAP and COMPARE DOU- ond operand is not changed. The result is indicated
BLE AND SWAP do not interlock against storage by the condition code.
accesses by channel programs. Therefore, the
instructions should not be used to update a loca- The size of the first and third operands, the size of
tion at which a channel program may store, since the replacement value, and the alignment of the first
the channel-program data may be lost. operand are determined by the contents of a function
6. To ensure successful updating of a common stor- code in bits 56-63 of general register 0. The assigned
age field by two or more CPUs, all updates must function codes are as follows:
be done by means of an interlocked-update ref-
erence (the section “Interlocked-Update Refer- • When the function code is 0, the operands are 32
ences” on page 5-94 lists the instructions that bits in length. The first operand is a word in stor-
perform an interlocked-update reference). For age, and the third operand is in bits 32-63 of gen-
example, if one CPU executes OR IMMEDIATE eral register R3. The replacement value is in
and another CPU executes COMPARE AND bytes 0-3 of the parameter list.
SWAP to update the same byte, the fetch by OR
IMMEDIATE may occur either before the fetch by • When the function code is 1, the operands are 64
COMPARE AND SWAP or between the fetch and bits in length. The first operand is a doubleword
the store by COMPARE AND SWAP, and then in storage, and the third operand is in bits 0-63 of
the store by OR IMMEDIATE may occur after the general register R3. The replacement value is
store by COMPARE AND SWAP, in which case bytes 0-7 of the parameter list.
the change made by COMPARE AND SWAP is
lost. • When the function code is 2 and the compare-
and-swap-and-store facility 2 is installed, the
7. For the case of a condition-code setting of 1, operands are 128 bits in length. The first operand
COMPARE AND SWAP and COMPARE DOU- is a quadword in storage, and the third operand
BLE AND SWAP may or may not, depending on is in bits 0-63 of general registers R3 and R3 + 1.
the model, cause any of the following to occur for The replacement value is in bytes 0-15 of the
the second-operand location: a PER storage- parameter list.
alteration event may be recognized; a protection
exception for storing may be recognized; and, The size of the store value and the alignment of the
provided no access exception exists, the change second operand are determined by a store character-
bit may be set to one. Because the contents of istic (SC) in bits 48-55 of general register 0. The
storage remain unchanged, the change bit may store characteristic is expressed as a power of two;
or may not be one when a PER storage-alter- the assigned store characteristics are 0, 1, 2, and 3.
ation event is recognized. An SC of 0 means that one byte is stored on a byte
boundary; an SC of 1 means that two bytes are
8. The performance of CDSG on some models may stored on a halfword boundary, an SC of 2 means
be significantly slower than that of CSG. When that four bytes are stored on a word boundary, and
quadword consistency is not required by the pro- an SC of 3 means that eight bytes are stored on a
gram, alternate code sequences should be used. doubleword boundary. When the CSST facility 2 is
installed, an SC of 4 is also assigned; an SC of 4
COMPARE AND SWAP AND STORE means that sixteen bytes are stored on a quadword
boundary. The store value begins at byte 16 of the
CSST D1(B1),D2(B2),R3 [SSF] parameter list.
'C8' R3 '2' B1 D1 B2 D2 Bits 0-31 of general register 0 are ignored. Bits 32-47
of general register 0 and bits 60-63 of general regis-
0 8 12 16 20 32 36 47
ter 1 are reserved and should contain zeros; other-
The handling of the parameter-list address is depen- The contents of the registers and parameter list just
dent on the addressing mode. In the 24-bit address- described are shown below.
ing mode, the contents of bit positions 40-59 of
Parameter List
0 Replacement Value / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
8 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
16 Store Value
24 (1, 2, 4, 8, or 16 bytes)
0 32 63
Parameter List
0 Replacement Value
8 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
16 Store Value
24 (1, 2, 4, 8, or 16 bytes)
0 63
Parameter List
0
Replacement Value
8
16 Store Value
24 (1, 2, 4, 8, or 16 bytes)
0 63
Figure 7-177. Register Contents for COMPARE AND SWAP AND STORE
When an equal comparison occurs, the replacement A specification exception is recognized for any of the
value is stored at the first-operand location, and the following conditions:
store value is stored at the second-operand location.
The fetch of the first operand for purposes of compar- • The function code specifies an unassigned
ison, and the store of the replacement value into the value.
first-operand location, both appear to be a block-con-
current interlocked-update reference as observed by • The store characteristic specifies an unassigned
other CPUs. The store of the store value appears to value.
be block-concurrent as observed by other CPUs.
• The function code is 0, and the first operand is
When the result of the comparison is unequal, the not designated on a word boundary.
first operand is loaded into the third-operand location,
and the first operand remains unchanged. However, • The function code is 1, and the first operand is
on some models, the contents of the first operand not designated on a doubleword boundary.
may be fetched and subsequently stored back
unchanged at the first-operand location. This update • The function code is 2, and any of the following is
appears to be a block-concurrent interlocked-update true:
reference as observed by other CPUs.
– The compare-and-swap-and-store facility 2
As observed by this CPU and by other CPUs, all is not installed.
fetches appear to occur before all stores, and the
store into the first operand appears to occur before – The first operand is not designated on a
the store into the second operand. Access-exception quadword boundary.
conditions are recognized for the entire 32-byte
parameter list and for the second operand, regard- – The R3 field does not designate the even-
less of whether the first and third operands are or are numbered register of an even-odd register
not equal. For the second operand, a PER storage- pair.
alteration event is recognized, and a change bit is
set, only if a store occurs. • The second operand is not designated on an
integral boundary corresponding to the size of
A serialization function is performed before the oper- the store value.
ation begins and again after the operation is com-
pleted. For all of the above conditions, and for all addressing
and protection exceptions, the operation is sup-
Special Conditions pressed.
• Access (fetch, parameter list; fetch and store, CGIT R1,I2,M3 [RIE-a]
operand 1; store, operand 2)
• Operation (if the compare-and-swap-and-store 'EC' R1 / / / / I2 M3 / / / / '70'
facility is not installed) 0 8 12 16 32 36 40 47
• Specification
The first operand is compared with the second oper-
Programming Notes: and. If the mask bit in the M3 field corresponding to
the comparison result is one, a compare-and-trap-
1. COMPARE AND SWAP AND STORE may be instruction data exception is recognized, and the
used in conjunction with other COMPARE AND operation is completed; otherwise, normal instruction
SWAP or COMPARE DOUBLE AND SWAP sequencing proceeds with the updated instruction
instructions to manipulate locks, queue pointers, address.
or other fields that require interlocked updates.
The comparison results and corresponding M3 bits
2. COMPARE AND SWAP AND STORE should not are as follows:
be used to manipulate fields that are also manip-
ulated by PERFORM LOCKED OPERATION. Comparison Result M3 Bit
Equal 0
3. The store value is intended to provide a separate First operand low 1
“footprint” of the interlocked-update operation in First operand high 2
a location apart from the first operand in a single
unit of operation.
Bit 3 of the M3 field is reserved and should be zero;
otherwise, the program may not operate compatibly
4. The performance of COMPARE AND SWAP
in the future.
AND STORE may be significantly slower than the
that of separate COMPARE AND SWAP,
For COMPARE AND TRAP (CRT) and COMPARE
BRANCH ON CONDITION, and STORE instruc-
IMMEDIATE AND TRAP (CIT), the first operand is
tions.
treated as a 32-bit signed binary integer. For COM-
PARE AND TRAP (CGRT) and COMPARE IMMEDI-
5. COMPARE AND SWAP AND STORE should
ATE AND TRAP (CGIT), the first operand is treated
only be used when an interruption between the
as a 64-bit signed binary integer.
compare-and-swap operation and the store oper-
ation cannot be tolerated, and other means of
For COMPARE IMMEDIATE AND TRAP, the second
disabling for interruptions are not practical.
operand is treated as a 16-bit signed binary integer.
For COMPARE AND TRAP (CRT), the second oper-
COMPARE AND TRAP and is treated as a 32-bit signed binary integer. For
COMPARE AND TRAP (CGRT), the second operand
CRT R1,R2,M3 [RRF-c] is treated as a 64-bit signed binary integer.
'B972' M3 / / / / R1 R2
Condition Code: The code remains unchanged.
0 16 20 24 28 31
• Data IMMEDIATE
• Operation (if the general-instructions-extension
Register-and-immediate formats:
facility is not installed)
CHI R1,I2 [RI-a]
Programming Notes:
'A7' R1 'E' I2
1. Possible uses of COMPARE AND TRAP and 0 8 12 16 31
3. When bit positions 0-2 of the M3 field contain CHSI D1(B1),I2 [SIL]
zeros, the instruction acts as a NOP, however 'E55C' B1 D1 I2
this is not the preferred instruction with which to
0 16 20 32 47
create a NOP. When bit positions 0-2 of the M3
field contain 111 binary, a data exception is
always recognized. CGHSI D1(B1),I2 [SIL]
'E558' B1 D1 I2
4. When a data exception is recognized, the com-
0 16 20 32 47
pare-and-trap data-exception code (DXC FF hex)
is stored, as described in “Data Exception” on
page 6-21.
COMPARE HALFWORD RELATIVE
5. The discussion of extended mnemonics in pro- LONG
gramming note 3 for COMPARE AND BRANCH
on page 7-114 also applies to the compare-and- CHRL R1,RI2 [RIL-b]
trap instructions.
'C6' R1 '5' RI2
0 8 12 16 47
COMPARE HALFWORD
CGHRL R1,RI2 [RIL-b]
CH R1,D2(X2,B2) [RX-a]
'C6' R1 '4' RI2
'49' R1 X2 B2 D2
0 8 12 16 47
0 8 12 16 20 31
0 Operands equal
1 First operand low
2 First operand high COMPARE IMMEDIATE HIGH
3 --
CIH R1,I2 [RIL-a]
Program Exceptions: 'CC' R1 'D' I2
0 8 12 16 47
• Access (fetch, operand 1 of CGHSI, CHHSI, and
CHSI only; fetch, operand 2 of CGH, CGHRL,
CH, CHRL, CHY only) The first operand is compared with the second oper-
• Operation (CHY, if the long-displacement facility and, and the result is indicated in the condition code.
is not installed; CGH, CHRL, CGHRL, CGHSI,
CHHSI, and CHSI, if the general-instructions- The operands are treated as 32-bit signed binary
extension facility is not installed) integers. The first operand is in bit positions 0-31 of
general register R1; bit positions 32-63 of the register
Programming Notes: are ignored. For COMPARE HIGH (CHHR), the sec-
ond operand is in bit positions 0-31 of general regis-
1. An example of the use of the COMPARE HALF- ter R2; bit positions 32-63 of the register are ignored.
WORD instruction is given in Appendix A, “Num- For COMPARE HIGH (CHLR), the second operand is
ber Representation and Instruction-Use in bit positions 32-63 of general register R2; bit posi-
Examples.” tions 0-31 of the register are ignored.
2. For COMPARE HALFWORD RELATIVE LONG, The displacement for CHF is treated as a 20-bit
the second operand is necessarily aligned on an signed binary integer.
Register-and-register formats:
CLGFI R1,I2 [RIL-a]
CLR R1,R2 [RR]
'C2' R1 'E' I2
'15' R1 R2
0 8 12 16 47
0 8 12 15
Storage-and-immediate formats:
CLGR R1,R2 [RRE]
CLI D1(B1),I2 [SI]
'B921' / / / / / / / / R1 R2
0 16 24 28 31 '95' I2 B1 D1
0 8 16 20 31
Register-and-storage formats:
CLFHSI D1(B1),I2 [SIL]
CL R1,D2(X2,B2) [RX-a]
'E55D' B1 D1 I2
'55' R1 X2 B2 D2
0 16 20 32 47
0 8 12 16 20 31
'EC' R1 M3 B4 D4 I2 'FD'
0 8 12 16 20 32 40 47
For COMPARE LOGICAL AND BRANCH and COM- COMPARE LOGICAL IMMEDIATE
PARE LOGICAL IMMEDIATE AND BRANCH, the
fourth operand is used as the branch address. For AND TRAP
COMPARE LOGICAL AND BRANCH RELATIVE and
COMPARE LOGICAL IMMEDIATE AND BRANCH CLFIT R1,I2,M3 [RIE-a]
RELATIVE, the contents of the I4 field are a signed 'EC' R1 / / / / I2 M3 / / / / '73'
binary integer specifying the number of halfwords 0 8 12 16 32 36 40 47
that is added to the address of the instruction to gen-
erate the branch address.
CLGIT R1,I2,M3 [RIE-a]
Program Exceptions:
The first operand is compared with the second oper-
• Operation (if the general-instructions-extension and. If the mask bit in the M3 field corresponding to
facility is not installed). the comparison result is one, a compare-and-trap-
instruction data exception is recognized, and the
Programming Notes: operation is completed; otherwise, normal instruction
sequencing proceeds with the updated instruction
1. When bit positions 0-2 of the M3 field contain address.
zeros, the instruction acts as a NOP, however
this is not the preferred instruction with which to The comparison results and corresponding M3 bits
create a NOP. When bit positions 0-2 of the M3 are as follows:
field contain 111 binary, a branch always occurs.
Comparison Result M3 Bit
2. When COMPARE LOGICAL AND BRANCH
RELATIVE or COMPARE LOGICAL IMMEDIATE Equal 0
AND BRANCH RELATIVE are the target of an First operand low 1
execute-type instruction, the branch is relative to First operand high 2
the target address. See “Branch-Address Gener-
ation” on page 5-10. Bit 3 of the M3 field is reserved and should be zero;
otherwise, the program may not operate compatibly
3. The discussion of extended mnemonics in pro- in the future.
gramming note 3 for COMPARE AND BRANCH
on page 7-114 also applies to the compare-logi- For COMPARE LOGICAL AND TRAP (CLRT) and
cal-and-branch instructions. COMPARE LOGICAL IMMEDIATE AND TRAP
(CLFIT), the first operand is treated as a 32-bit
unsigned binary integer. For COMPARE LOGICAL
AND TRAP (CLGRT) and COMPARE LOGICAL
IMMEDIATE AND TRAP (CLGIT), the first operand is
treated as a 64-bit unsigned binary integer.
'B9CF' / / / / / / / / R1 R2
0 16 24 28 31 COMPARE LOGICAL LONG
CLCL R1,R2 [RR]
CLHLR R1,R2 [RRE]
'0F' R1 R2
'B9DF' / / / / / / / / R1 R2
0 8 12 15
0 16 24 28 31
Register-and-storage format: The first operand is compared with the second oper-
and, and the result is indicated in the condition code.
CLHF R1,D2(X2,B2) [RXY-a] The shorter operand is considered to be extended on
'E3' R1 X2 B2 DL2 DH2 'CF' the right with padding bytes.
0 8 12 16 20 32 40 47
The R1 and R2 fields each designate an even-odd
pair of general registers and must designate an even-
numbered register; otherwise, a specification excep-
COMPARE LOGICAL IMMEDIATE tion is recognized.
HIGH
The location of the leftmost byte of the first operand
CLIH R1,I2 [RIL-a] and second operand is designated by the contents of
'CC' R1 'F' I2 general registers R1 and R2, respectively. The num-
ber of bytes in the first-operand and second-operand
0 8 12 16 47
locations is specified by unsigned binary integers in
bit positions 40-63 of general registers R1 + 1 and
R2 + 1, respectively. Bit positions 32-39 of general
tents of bit positions 0-39 of general register R1 + 1 0-39 are ignored. In the 31-bit addressing mode, the
and of bit positions 0-31 of general register R2 + 1 contents of bit positions 33-63 of the registers consti-
are ignored. tute the address, and the contents of bit positions
0-32 are ignored. In the 64-bit addressing mode, the
The handling of the addresses in general registers R1 contents of bit positions 0-63 constitute the address.
and R2 is dependent on the addressing mode.
The contents of the registers just described are
In the 24-bit addressing mode, the contents of bit shown in Figure 7-178 on page 7-136.
positions 40-63 of general registers R1 and R2 consti-
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 Second-Operand Address
0 63
The comparison proceeds left to right, byte by byte, If both operands are of zero length, the operands are
and ends as soon as an inequality is found or the end considered to be equal.
of the longer operand is reached. If the operands are
not of the same length, the shorter operand is con- The execution of the instruction is interruptible. When
sidered to be extended on the right with the appropri- an interruption occurs, other than one that follows ter-
ate number of padding bytes. mination, the lengths in general registers R1 + 1 and
R2 + 1 are decremented by the number of bytes com-
pared, and the addresses in general registers R1 and
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 40 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 33 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R3 Third-Operand Address
0 63
R3 + 1 Third-Operand Length
0 63
Figure 7-179. Register Contents and Second-Operand Address for COMPARE LOGICAL LONG EXTENDED
The padding byte may be formed from D2(B2) multi- At the completion of the operation in the 24-bit or
ple times during the execution of the instruction, and 31-bit addressing mode, the leftmost bits which are
the registers designated by R1 and R3 may be not part of the address in bit positions 32-63 of gen-
updated multiple times. Therefore, if B2 equals R1, eral registers R1 and R3 may be set to zeros or may
R1 + 1, R3, or R3 + 1 and is subject to change during remain unchanged from their original values, even
the execution of the instruction, the results are unpre- when one or both of the initial length values are zero.
dictable.
Access exceptions for the portion of a storage oper-
The amount of processing that results in the setting and to the right of the first unequal byte may or may
of condition code 3 is determined by the CPU on the not be recognized. For operands longer than 4K
basis of improving system performance, and it may bytes, access exceptions are not recognized more
be a different amount each time the instruction is than 4K bytes beyond the byte being processed.
executed. The maximum amount is approximately 4K Access exceptions are not indicated for locations
bytes of either operand. more than 4K bytes beyond the first unequal byte.
exceptions are recognized for that operand. Access be set regardless of the operand length.
exceptions are not recognized for an operand if the R
field associated with that operand is odd. 5. In the access-register mode, access register 0
designates the primary address space regard-
Resulting Condition Code: less of the contents of access register 0.
0 All bytes compared; operands equal, or both zero COMPARE LOGICAL LONG
length
1 All bytes compared, first operand low UNICODE
2 All bytes compared, first operand high
3 CPU-determined number of bytes compared CLCLU R1,R3,D2(B2) [RSY-a]
without finding an inequality 'EB' R1 R3 B2 DL2 DH2 '8F'
0 8 12 16 20 32 40 47
Program Exceptions:
• Access (fetch, operands 1 and 3) The first operand is compared with the third operand
• Specification until unequal two-byte Unicode characters are com-
pared, the end of the longer operand is reached, or a
Programming Notes: CPU-determined number of characters have been
compared, whichever occurs first. The shorter oper-
1. COMPARE LOGICAL LONG EXTENDED is and is considered to be extended on the right with
intended for use in place of COMPARE LOGICAL two-byte padding characters. The result is indicated
LONG when the operand lengths are specified in the condition code.
as 32-bit or 64-bit binary integers. COMPARE
LOGICAL LONG EXTENDED sets condition The R1 and R3 fields each designate an even-odd
code 3 in cases in which COMPARE LOGICAL pair of general registers and must designate an even-
LONG would be interrupted. numbered register; otherwise, a specification excep-
tion is recognized.
2. When condition code 3 is set, the program can
simply branch back to the instruction to continue The location of the leftmost character of the first
the comparison. The program need not deter- operand and third operand is designated by the con-
mine the number of bytes that were compared. tents of general registers R1 and R3, respectively. In
the 24-bit or 31-bit addressing mode, the number of
3. The function of not processing more than bytes in the first-operand and third-operand locations
approximately 4K bytes of either operand is is specified by the contents of bit positions 32-63 of
intended to permit software polling of a flag that general registers R1 + 1 and R3 + 1, respectively, and
may be set by a program on another CPU during those contents are treated as 32-bit unsigned binary
long operations. integers. In the 64-bit addressing mode, the number
4. When the R1 and R3 fields are the same, the of bytes in the first-operand and third-operand loca-
operation proceeds in the same way as when two tions is specified by the contents of bit positions 0-63
distinct pairs of registers having the same con- of general registers R1 + 1 and R3 + 1, respectively,
tents are specified, except that the contents of and those contents are treated as 64-bit unsigned
the designated registers are incremented or dec- binary integers.
remented only by the number of bytes compared,
not by twice the number of bytes compared. In The contents of general registers R1 + 1 and R3 + 1
the absence of dynamic modification of the oper- must specify an even number of bytes; otherwise, a
and area by another CPU or by a channel pro- specification exception is recognized.
gram, the condition code is finally set to 0 after
possible settings to 3. However, it is unpredict- The handling of the addresses in general registers R1
able whether access exceptions are recognized and R3 is dependent on the addressing mode.
for the operand since the operation can be com-
pleted without storage being accessed. If storage In the 24-bit addressing mode, the contents of bit
positions 40-63 of general registers R1 and R3 consti-
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 40 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 33 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R3 Third-Operand Address
0 63
R3 + 1 Third-Operand Length
0 63
Figure 7-180. Register Contents and Second-Operand Address for COMPARE LOGICAL LONG UNICODE
The comparison proceeds left to right, character by sidered to be extended on the right with the appropri-
character, and ends as soon as an inequality is ate number of two-byte padding characters.
found, the end of the longer operand is reached, or a
CPU-determined number of characters have been If both operands are of zero length, the operands are
compared, whichever occurs first. If the operands are considered to be equal.
not of the same length, the shorter operand is con-
general register R1, and the address of the second- Instruction-Use Examples.”
operand byte corresponding in position to the first-
operand byte is placed in general register R2. When 2. When condition code 0 is set, no indication is
condition code 2 is set, the address of the ending given of the position of either ending character.
character or first unequal byte in the second oper- 3. When condition code 3 is set, the program can
and, whichever was encountered, is placed in gen- simply branch back to the instruction to continue
eral register R2, and the address of the first-operand the comparison. The program need not deter-
byte corresponding in position to the second-operand mine the number of bytes that were compared.
byte is placed in general register R1. When condition
code 3 is set, the address of the next byte to be pro- 4. R1 or R2 may be zero, in which case general reg-
cessed in the first and second operands is placed in ister 0 is treated as containing an address and
general registers R1 and R2, respectively. Whenever also the ending character.
an address is placed in a general register, bits 32-39
of the register, in the 24-bit addressing mode, or bit 5. In the access-register mode, access register 0
32 in the 31-bit addressing mode, are set to zeros. designates the primary address space regard-
Bits 0-31 of the R1 and R2 registers always remain less of the contents of access register 0.
unchanged in the 24-bit or 31-bit mode.
COMPARE UNTIL SUBSTRING
When condition code 0 is set, the contents of general
registers R1 and R2 remain unchanged. EQUAL
The amount of processing that results in the setting CUSE R1,R2 [RRE]
of condition code 3 is determined by the CPU on the 'B257' / / / / / / / / R1 R2
basis of improving system performance, and it may 0 16 24 28 31
be a different amount each time the instruction is
executed.
The first operand is compared with the second oper-
Access exceptions for the first and second operands and until equal substrings (sequences of bytes) of a
are recognized only for that portion of the operand specified length are found, the end of the longer
which is necessarily examined in the operation. operand is reached, or a CPU-determined number of
unequal bytes have been compared, whichever
Resulting Condition Code: occurs first. The shorter operand is considered to be
extended on the right with padding bytes. The CPU-
0 Entire operands equal; general registers R1 and determined number is at least 256. The result is indi-
R2 unchanged cated in the condition code.
1 First operand low; general registers R1 and R2
updated with addresses of last bytes processed The R1 and R2 fields each designate an even-odd
2 First operand high; general registers R1 and R2 pair of general registers and must designate an even-
updated with addresses of last bytes processed numbered register; otherwise, a specification excep-
3 CPU-determined number of bytes equal; general tion is recognized.
registers R1 and R2 updated with addresses of
next bytes The location of the leftmost byte of the first operand
and second operand is specified by the contents of
Program Exceptions: the R1 and R2 general registers, respectively. In the
24-bit or 31-bit addressing mode, the number of
• Access (fetch, operands 1 and 2) bytes in the first-operand and second-operand loca-
• Specification tions is specified by the 32-bit signed binary integer
in bit positions 32-63 of general registers R1 + 1 and
Programming Notes: R2 + 1, respectively. In the 64-bit addressing mode,
the number of bytes is specified by the 64-bit signed
1. Several examples of the use of the COMPARE binary integer in bit positions 0-63 of those registers.
LOGICAL STRING instruction are given in When an operand length is negative, it is treated as
The handling of the addresses in general registers R1 The contents of the registers just described are
and R2 is dependent on the addressing mode. In the shown in Figure 7-181 on page 7-145.
24-bit addressing mode, the contents of bit positions
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
GR1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Pad
0 56 63
Figure 7-181. Register Contents and Second-Operand Address for COMPARE UNTIL SUBSTRING EQUAL
cessed from left to right. However, multiple accesses shorter operand. In the 24-bit or 31-bit addressing
may be made to all or some of the bytes of each mode, the leftmost bits which are not part of the
operand. addresses in bit positions 32-63 of registers R1 and
R2 are set to zeros, even if the substring length is
The comparison proceeds left to right, byte by byte, zero or both operand lengths are initially zero.
and ends as soon as (1) equal substrings of the
specified length are found, (2) the end of the longer Thus, when condition code 0 or 1 is set, the resulting
operand is reached without finding equal substrings addresses in the R1 and R2 registers designate the
of the specified length, or (3) the last bytes compared first bytes of equal substrings in the two operands,
are unequal, and a CPU-determined number of bytes and the lengths in the R1 + 1 and R2 + 1 registers
have been compared. The CPU-determined number have been decremented by the number of bytes pre-
is at least 256. If the operands are not of the same ceding the equal substrings, except when the equal
length, the shorter operand is considered to be substring in the shorter operand begins with the pad-
extended on the right with the appropriate number of ding byte, in which case the length field for the
padding bytes. shorter operand is zero, and the corresponding
address field has been incremented by the operand
If the operation ends because equal substrings of the length. When condition code 2 is set, each address
specified length were found, the condition code is set field designates the first byte after the corresponding
to 0. If the operation ends because the end of the operand, and both length fields are zero. When con-
longer operand was reached without finding equal dition code 3 is set, each address field designates
substrings of the specified length, the condition code the first byte after the last compared byte of the cor-
is set to 1 if equal bytes were the last bytes com- responding operand, and both length fields have
pared, or it is set to 2 if unequal bytes were the last been decremented by the number of bytes com-
bytes compared. If the operation ends because pared, except that a length field is not decremented
unequal bytes were compared when a CPU-deter- below zero.
mined number of bytes had been compared, the con-
dition code is set to 3. When the contents of the R1 and R2 fields are the
same, the first and second operands may be com-
If the specified substring length is zero, it is consid- pared, or the condition code may be set to 0 or 1
ered that equal substrings of the specified length without comparing the operands.
were found, and condition code 0 is set.
In the 24-bit or 31-bit addressing mode, the contents
If both operands are of zero length but the specified of bit positions 0-31 of general registers R1, R1 + 1,
substring length is not zero, it is considered that the R2, and R2 + 1, always remain unchanged.
end of the longer operand was reached when
unequal bytes were the last bytes compared, and The substring length and padding byte may be
condition code 2 is set. fetched from general registers 0 and 1 multiple times
during the execution of the instruction, and the regis-
If equal bytes have been compared but then unequal ters designated by R1 and R2 may be updated multi-
bytes are compared, it is considered that all bytes so ple times. Therefore, if R1 or R2 is zero, the results
far compared are unequal. are unpredictable.
At the completion of the operation, the operand- When condition code 3 is set, the general registers
length fields in the R1 + 1 and R2 + 1 registers are used by the instruction have been set so that the
decremented by the number of unequal bytes com- remainder of the operands can be processed by sim-
pared (including equal bytes before unequal bytes ply branching back and reexecuting the instruction.
compared), and the addresses in the R1 and R2 reg-
isters are incremented by the same number. How- The amount of processing that results in the setting
ever, in the case when a byte of the longer operand is of condition code 3 is determined by the CPU on the
compared against the padding byte, the length field basis of improving system performance, and it may
for the shorter operand is not decremented below be a different amount each time the instruction is
zero, and the corresponding address is not incre- executed.
COMPRESSION CALL
the last bytes compared are unequal; it is not inter- out storage being accessed.
ruptible when the last bytes compared are equal.
When an interruption occurs, other than one that fol- 2. If the contents of the R1 and R2 fields are the
lows termination, the contents of the registers desig- same and the operand length is nonzero, and
nated by the R1 and R2 fields are updated the same provided that another CPU or a channel program
as upon normal completion of the instruction, so that is not changing an operand, condition code 0 is
the instruction, when reexecuted, resumes at the set if the operand length is equal to or greater
point of interruption. The condition code is unpredict- than the specified substring length, or condition
able. code 1 is set if the operand length is less than
the specified substring length. Whether or not R1
Access exceptions for the portion of a storage oper- equals R2, if both operand lengths are zero, con-
and to the right of the last byte processed may or dition code 0 is set if the specified substring
may not be recognized. For operands longer than 4K length is zero, or condition code 2 is set if the
bytes, access exceptions are not recognized for loca- specified substring length is nonzero. In all of
tions more than 4K bytes beyond the last byte pro- these cases, the addresses in the R1 and R2 reg-
cessed. isters and the lengths in the R1 + 1 and R2 + 1
registers remain unchanged.
When the length of an operand is zero, no access 3. Special precautions should be taken when COM-
exceptions are recognized for that operand. Access PARE UNTIL SUBSTRING EQUAL is made the
exceptions are not recognized for an operand if the R target of an execute-type instruction. See the
field associated with that operand is odd. Although programming note concerning interruptible
the operand address and length fields remain instructions under EXECUTE.
unchanged when a zero substring length is specified,
the recognition of access exceptions is not necessar- 4. Other programming notes concerning interrupt-
ily prevented. ible instructions are included in “Interruptible
Instructions” on page 5-20.
Resulting Condition Code:
5. In the access-register mode, access register 0
0 Equal substrings of specified length found designates the primary address space regard-
1 End of longer operand reached when last bytes less of the contents of access register 0.
compared are equal 6. The storage-operand references of COMPARE
2 End of longer operand reached when last bytes UNTIL SUBSTRING EQUAL may be multiple-
compared are unequal access references. (See “Storage-Operand Con-
3 Last bytes compared are unequal, and CPU- sistency” on page 5-95.)
determined number of bytes compared
1. When the R1 and R2 fields are the same, the This definition assumes knowledge of the introduc-
operation proceeds in the same way as when two tory information and information about dictionary for-
distinct pairs of registers having the same con- mats in Enterprise Systems Architecture/390 Data
tents are specified, and, in the absence of Compression, SA22-7208-01.
dynamic modification of the operand area by
another CPU or by a channel program, condition The second operand is compressed or expanded,
code 0, 1, or 2 is set (as explained in the next depending on a specification in general register 0,
note). However, it is unpredictable whether and the results are placed at the first-operand loca-
access exceptions are recognized for the oper- tion. The compressed-data operand normally con-
sists of index symbols corresponding to entries in a
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
1 2
GR1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Dictionary Origin STT Offset CBN
0 40 52 61 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
1 2
GR1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Dictionary Origin STT Offset CBN
0 33 52 61 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
1 2
GR1 Dictionary Origin STT Offset CBN
0 52 61 63
Explanation:
1
Compression dictionary during compression, or expansion dictionary during expansion
2
STT offset field is only meaningful during compression when the ST bit is one. When the ST bit is zero during compression, or during
expansion, the STT-offset field is ignored.
CBN Compressed-data bit number
CDSS Compressed-data symbol size, and dictionary size when symbol translation not specified
CDSS Symbol Dictionary
(binary) Size Size
0000 Causes a specification exception to be recognized
0001 9 bits 512 entries, 4K bytes
0010 10 bits 1K entries, 8K bytes
0011 11 bits 2K entries, 16K bytes
0100 12 bits 4K entries, 32K bytes
0101 13 bits 8K entries, 64K bytes
0110-1111Causes a specification exception to be recognized
E Expansion operation
F1 Format-1 sibling descriptors (ignored during expansion)
ST Symbol-translation option (ignored during expansion)
STT Symbol-translation-table (STT offset ignored during expansion)
ZP Zero padding control (when the CMPSC-enhancement facility is installed).
Figure 7-182. Register Contents for COMPRESSION CALL (Part 2 of 2)
The handling of the addresses in general registers 52-63 are ignored. In the 31-bit addressing mode, the
R1, R2, and 1 is dependent on the addressing mode. contents of bit positions 33-51 of register 1, with 12
In the 24-bit addressing mode, the contents of bit rightmost zeros appended, constitute the address,
positions 40-63 of registers R1 and R2 constitute the and the contents of bit positions 0-32 and 52-63 are
address, and the contents of bit positions 0-39 are ignored. In the 64-bit addressing mode, the contents
ignored. In the 31-bit addressing mode, the contents of bit positions 0-51 of register 1, with 12 rightmost
of bit positions 33-63 of registers R1 and R2 consti- zeros appended, constitute the address, and the con-
tute the address, and the contents of bit positions tents of bit positions 52-63 are ignored.
0-32 are ignored. In the 64-bit addressing mode, the
contents of bit positions 0-63 of registers R1 and R2 Although the contents of bit positions 52-63 of gen-
constitute the address. In the 24-bit addressing eral register 1 are ignored as just described, those
mode, the contents of bit positions 40-51 of register contents are used as follows. The contents of bit
1, with 12 rightmost zeros appended, constitute the positions 61-63 of the register are the compressed-
address, and the contents of bit positions 0-39 and data bit number (CBN). At the beginning of the oper-
leftmost byte of the compressed-data operand. The translation is not specified, bits 48-51 also specify, as
compressed-data operand is the first operand during shown in the figure, the number of eight-byte entries
compression, or it is the second operand during in each of the compression and expansion dictionar-
expansion. When the symbol-translation option is ies, and, thus, they specify the size in bytes of each
specified during compression, the contents of bit of the dictionaries. When symbol translation is speci-
positions 52-60 of the register, with seven rightmost fied, the compression dictionary is considered to
zeros appended, are the byte offset from the begin- extend to the beginning of the symbol-translation
ning of the compression dictionary to the leftmost table, that is, the size in bytes of the compression dic-
byte of the symbol-translation table. Symbol transla- tionary is the offset in bit positions 52-60 of general
tion cannot be specified during expansion, and the register 1, with seven rightmost zeros appended. The
contents of bit positions 52-60 are ignored during size in bytes of the symbol-translation table is consid-
expansion. ered to be one fourth that of the compression dictio-
nary. However, the offset in general register 1 must
The contents of the registers just described and also be at least as large as the size of the compression
of general register 0 are shown in Figure 7-182 on dictionary would be if symbol translation were not
page 7-148. specified and the CDSS were one less than it actu-
ally is, and, when the CDSS is 0001 binary, the offset
Bit 55 (E) of general register 0 specifies the compres- must be at least 2K bytes; otherwise, the results are
sion operation if zero or the expansion operation if unpredictable. For example, if the CDSS is 0101, the
one. offset must be at least 32K bytes.
When the CMPSC-enhancement facility is installed, Bit 54 (F1) of general register 0 specifies that the
bit 46 of general register 0 is the zero-padding (ZP) compression dictionary contains format-0 sibling
control. When the ZP control is zero, zero padding of descriptors if the bit is zero or format-1 sibling
the first operand is not performed. When the ZP con- descriptors if the bit is one. Sibling descriptors are
trol is one, zero padding of the first operand may be used during the compression operation. A format-0
performed, as described below. When the CMPSC- sibling descriptor is eight bytes at an index position in
enhancement facility is not installed, bit 46 of general the compression dictionary. A format-1 sibling
register 0 is ignored. descriptor is 16 bytes, with the first eight bytes at an
index position in the compression dictionary and the
Bit 47 (ST) of general register 0 is the symbol-trans- second eight bytes at the same index position in the
lation-option bit. During compression when bit 47 is expansion dictionary. During compression when bit
zero, the operation produces indexes, called index 54 is one, an expansion dictionary is considered to
symbols, to compression-dictionary entries that rep- immediately follow the compression dictionary speci-
resent character strings, and the operation then fied by the address in general register 1. Bit 54 is
places the index symbols in the compressed-data ignored during expansion.
operand. During compression when bit 47 is one, the
operation still produces index symbols but then trans- Bits 47 and 54 of general register 0 must not both be
lates the index symbols to other symbols, called ones; otherwise, the results are unpredictable.
interchange symbols, that it then places in the com-
pressed-data operand. This symbol translation is The unused bit positions in general register 0 are
done by using the symbol-translation table specified reserved for possible future extensions and should
by the address and offset in general register 1. Bit 47 contain zeros; otherwise, the program may not oper-
and the offset in general register 1 are ignored during ate compatibly in the future.
expansion. During expansion, the compressed-data
operand always contains index symbols that desig- In the access-register mode, the contents of access
nate entries in the expansion dictionary. register R1 are used for accessing the first operand,
and the contents of access register R2 are used for
Bits 48-51 (CDSS) of general register 0 specify the accessing the second operand and the dictionaries
number of bits in the index symbols or interchange and the symbol-translation table.
symbols in the compressed-data operand, as shown
in the figure. Bits 48-51 must not have any of the val- The operation starts at the left end of both operands
ues 0000 or 0110-1111 binary; otherwise, a specifi- and proceeds to the right. The operation is ended
COMPRESSION CALL
CPU-determined amount of data has been pro- data, the bits in the byte to the right of the rightmost
cessed, whichever occurs first. bit of compressed data in the byte either are
unchanged or are set to zeros.
During a compression operation, the end of the first
operand is considered to be reached when the num- The length in general register R2 + 1 is decremented
ber of unused bit positions remaining in the first-oper- by the number of complete bytes processed at the
and location is not sufficient to contain additional second-operand location, and the address in general
compressed data. register R2 is incremented by the same amount. Dur-
ing expansion, a complete byte is considered to be
During an expansion operation, the end of the first- processed only if all of its bits have been used to pro-
operand location is considered to be reached when duce expanded data.
either of the following two conditions is met:
The leftmost bits which are not part of the address in
1. The number of unused byte positions remaining general registers R1 and R2 may be set to zeros or
in the first-operand location is not sufficient to may remain unchanged. However, in the 24-bit or
contain all the characters that would result from 31-bit addressing mode, bits 0-31 of these registers
expansion of the next index symbol. and also of general registers R1 + 1 and R2 + 1
always remain unchanged.
2. Immediately when the number of unused byte
positions is zero, that is, immediately when the When all of the following conditions are met, zero
expansion of an index symbol completely fills the padding may be performed, as described below.
first-operand location.
• The CMPSC-enhancement facility is installed.
During an expansion operation, the end of the sec-
ond-operand location is considered to be reached • The zero-padding (ZP) control, bit 46 of general
when the next index symbol does not reside entirely register 0, is one.
within the second-operand location. The second-
operand location ends at the beginning of the byte • Any of the following is true:
designated by the sum of the address in general reg- – The end of the first operand is reached
ister R2 and the length in general register R2 + 1, (CC1).
regardless of the compressed-data bit number in bit
positions 61-63 of general register 1. – The end of the second operand is reached
(CC0).
If the operation is ended because the end of the sec-
ond operand is reached, condition code 0 is set. If – A CPU-determined amount of data has been
the operation is ended because the end of the first processed (CC3).
operand is reached, condition code 1 is set, except • The last byte of compressed or expanded data
that condition code 0 is set if the end of the second does not coincide with the rightmost byte of a
operand is also reached. If the operation is ended model-dependent integral storage boundary.
because a CPU-determined amount of data has
been processed, condition code 3 is set. • The remaining length in general register R1 + 1 is
sufficient to store up to the model-dependent
At the completion of the operation, the length in gen- integral storage boundary.
eral register R1 + 1 is decremented by the number of
complete bytes stored at the first-operand location, It is model dependent whether zero padding is per-
and the address in general register R1 is incremented formed. When any of the conditions listed above are
by the same amount. During compression, a com- not met, zero padding is not performed.
plete byte is considered to be stored only if all of its
bit positions contain bits of compressed data. During Zero padding consists of storing zeros to the right of
compression when the first bit of compressed data the last compressed or expanded byte, up to a
stored is not in bit position 0 of a byte, the bits in the model-dependent integral storage boundary. The
byte to the left of the first bit of compressed data address in general register R1 and the length in gen-
remain unchanged. During compression if the last eral register R1 + 1 are not updated to account for the
ognized for stores that occur as a result of zero pad- tions are not recognized for locations more than 4K
ding. The model-dependent integral storage bytes beyond the current location being processed.
boundary is no larger than 4,096. Access exceptions may be recognized for all loca-
tions in the dictionaries and symbol-translation table
When the R1 and R2 fields do not designate general if those areas are specified to be used and even if the
register 0, the handling of general register 1 is as fol- locations would not be used during the operation.
lows. The bit number of the bit following the last bit of Access exceptions are not recognized for an oper-
compressed data processed is placed in bit positions and, the dictionaries, or the symbol-translation table
61-63 of general register 1, and bits 52-60 of the reg- if the R field associated with that operand is odd.
ister and the leftmost bits which are not part of the Also, when the R1 field is odd, PER storage-alteration
address in the register may be set to zeros or may events are not recognized, and no change bits are
remain unchanged, except that when one or both of set.
the original length values are so small that no com-
pressed data can be processed, all bits in the regis- If an access exception is due to be recognized for
ter may remain unchanged. However, when bit 47 of either of the operands or for a dictionary or the sym-
general register 0 is one, bits 52-60 of general regis- bol-translation table, the result is that either the
ter 1 always remain unchanged. Also, in the 24-bit or exception is recognized or condition code 3 is set. If
31-bit addressing mode, bits 0-31 of the register condition code 3 is set, the exception will be recog-
always remain unchanged. nized when the instruction is executed again to con-
tinue processing the same operands, assuming that
If (a) the operands overlap one another, (b) the first the exception condition still exists.
operand overlaps the dictionaries or the symbol-
translation table in storage in any way, or (c) either During compression, regardless of whether the
the R1 or the R2 field designates general register 0, exception is recognized or condition code 3 is set, a
the results are unpredictable. nullifying access-exception condition or a suppress-
ing DAT-protection exception conditionis handled so
When symbol translation is specified, the symbol- that an index symbol is generated only if it is the one
translation table consists of two-byte entries, and an that would result if there were no access-exception
entry contains an interchange symbol in the right- condition.
most bit positions of the entry. The length of the inter-
change symbol is specified by bits 48-51 of general During compression or expansion, regardless of
register 0. The left-hand bits that are not part of the whether the exception is recognized or condition
interchange symbol in a symbol-translation-table code 3 is set, a nullifying or suppressing access-
entry must be zeros; otherwise, the results are exception condition may result in data having been
unpredictable. stored at the first-operand location at or to the right of
the location designated by the final address in gen-
To translate an index symbol to an interchange sym- eral register R1, which result is not true nullification or
bol, the index symbol is multiplied by 2 and then suppression. The amount of data stored depends on
added to the address of the beginning of the symbol- the reason for the access-exception condition. If the
translation table to locate an entry in the table, and condition is due to a reference to a dictionary or the
then the interchange symbol is obtained from the symbol-translation table, up to 4K bytes of data may
entry. have been stored at or to the right of the location des-
ignated by the final address. If the condition is due to
The execution of the instruction is interruptible. When a reference to the first or second operand, part of one
an interruption occurs, other than one that follows ter- index or interchange symbol, during compression, or
mination, the contents of the registers designated by part of one character symbol, during expansion, may
the R1 and R2 fields and of general register 1 are have been stored at or to the right of the location des-
updated the same as upon normal completion of the ignated by the final address. In all cases, the storing
instruction, so that the instruction, when reexecuted, will be repeated when the instruction is executed
resumes at the point of interruption. The condition again to continue processing the same operands.
code is unpredictable.
If the end of the first operand is reached and an
access exception is due to be recognized for the sec-
COMPRESSION CALL
code 1 is set or the access exception is recognized.
0 End of second operand reached
During expansion when the expansion dictionary is 1 End of first operand reached and end of second
not logically correct, unusual storing may occur as operand not reached
described in the section “Expansion Process” in 2 --
Chapter 1 of Enterprise Systems Architecture/390 3 CPU-determined amount of data processed
Data Compression, SA22-7208-01. The results of an
access exception in this case may not be true nullifi- Program Exceptions:
cation or suppression.
• Access (fetch, operand 2, dictionaries, and sym-
Special Conditions bol-translation table; store, operand 1)
• Data
During compression of each character symbol, either • Specification
the characters in the symbol or the dictionary charac-
ter entries (not sibling descriptors) representing char- Programming Notes:
acters of the symbol are counted, and a data
exception is recognized if this count becomes too 1. When condition code 3 is set, the program can
large. The count can reach at least 260 without the simply branch back to the instruction to continue
exception being recognized. the operation. The program need not determine
the amount of data processed.
During compression, the number of child characters
or sibling characters processed during the process- 2. During compression when a nullifying access
ing of each parent entry are counted, and a data exception is due to be recognized, an index sym-
exception is recognized if this count becomes too bol is generated only if it is the one that would
large. The count can reach at least 260 without the result if there were no access-exception condi-
exception being recognized. That is, a parent must tion. The result of this is that compression of the
not have more than 260 children; otherwise, a data same expanded data by means of one or more
exception may be recognized. executions of the instruction and by using the
same dictionary always results in the same com-
During expansion of each character symbol, either pressed data. That is, (1) the best possible
the characters in the symbol or the dictionary entries matches in the dictionary are always found for
representing characters of the symbol are counted, the characters in the second operand, or else the
and a data exception is recognized if this count execution is ended by either setting CC3 or rec-
becomes too large. If the characters in the symbol ognizing the exception, and (2) the results of
are counted, the count can reach at least 260 without compression are repeatable (although possibly
the exception being recognized. If the dictionary by means of a different number of executions of
entries representing characters of the symbol are the instruction) and predictable.
counted, the count can reach at least 127 without the For example, if the next characters of the string
exception being recognized. being compressed are ABC, and dictionary entry
A has a child B, which has a child C, the normal
Certain error conditions in the dictionaries cause a operation is to compress ABC as a single index
data exception to be recognized and the operation to symbol, but if the C of the string is in the first byte
be either suppressed or terminated. Some of these of an invalid page (a page-translation exception
error conditions are described in the sections is due to be recognized), no index symbol is gen-
“Expansion Process” and “Results of Dictionary erated. More specifically, an index symbol corre-
Errors” in Chapter 1 of SA22-7208-01. The others sponding to the character symbol AB is not
are described in Chapter 2 of SA22-7208-01. generated because this is not the index symbol
that would be generated if the access-exception
condition did not exist.
are the last two characters of the second oper- ter, such as 0 (F0 hex), that would appear to be
and, the best possible match is on AB, even an invalid partial symbol length in a character
though there could be a match on ABC if the sec- entry.
ond operand included one more byte containing
C. 4. A nullifying access-exception condition due to a
reference to a dictionary or the symbol-transla-
Expansion is normally always repeatable. An tion table may result in the storing of data at or to
index symbol is always expanded to exactly the the right of the location designated by the final
character symbol it represents unless an excep- address in general register R1. This storing and
tion that causes termination is recognized. the processing needed to produce the data
stored will be repeated when COMPRESSION
3. During expansion, if at least one unused byte CALL is executed again to continue processing
position remains in the first operand location, the same operands. The repeated processing
COMPRESSION CALL may completely process will reduce the performance of the instruction
the next index symbol in the second operand execution, and it should be avoided by ensuring
before it determines that the first-operand loca- that the environment in which the program is exe-
tion does not have sufficient unused byte posi- cuted is one in which page-translation-exception
tions to contain the expanded data that would conditions for the dictionaries and symbol-trans-
result from the next index symbol. If that next lation table are infrequent.
index symbol causes encountering of bad dictio-
nary entries, the result can be either a data 5. Following is an example of how the compressed-
exception or condition code 1. data bit number (CBN) is used and set. In this
example:
COMPRESSION CALL immediately sets condi-
tion code 1 when processing of an index symbol • The operation is an expansion operation.
exactly fills the first-operand location, except that
it sets condition code 0 if the end of the second- • The CDSS in general register 0 is 0010
operand location also has been reached. Imme- binary. Therefore, there are 1K entries in the
diately setting condition code 1 has the advan- expansion dictionary, and the length of an
tage that data can be compressed using one index symbol is 10 bits.
dictionary and then followed immediately, possi- • The second operand (compressed-data
bly on a bit boundary, by a different type of data operand) begins at location 6000 hex and
compressed using another dictionary. The com- has a length of five bytes. The initial CBN is
pressed data can be successfully expanded if, 7. Therefore, there are three index symbols
during the expansion of the data compressed to be expanded, and the final CBN will be 5.
using the first dictionary, the length of the first-
operand location is specified to be exactly the • The compressed data beginning at location
length of the expanded data that will be pro- 6000 hex is 0081FF9FF8 hex. Therefore, the
duced. Condition code 1 will then be set when three index symbols are 103, 3FC, and 3FF
the first-operand location is full, at which time the hex.
specification of the dictionary can be changed in
order to expand the remainder of the com- • The first operand (expanded-data operand)
pressed data using the second dictionary. If the begins at location 5000 hex and has a length
definition allowed condition code 1 not to be set, of 64 bytes. The three index symbols are
it might be attempted to expand the next index expanded to a total of 14 bytes of expanded
symbol, which resulted from use of the second data.
dictionary, by means of the first dictionary, and The following figure shows the initial and final
this might cause recognition of a data exception. contents of general registers R1, R1 + 1, R2, and
For example, the next index symbol, which prop- R2 + 1, the contents of locations 6000-6004 hex
erly designates a character entry in the second in binary, and the way a cursor corresponding to
dictionary, might designate the second half of a
format-1 sibling descriptor in the first dictionary,
COMPRESSION CALL
ation. PRESSION CALL dictionary because the latter
requires that some of the entries be sibling
Initial Final descriptors. Therefore, VTAM must have an 8K-
Contents Contents entry dictionary for use in the basic compression
Register in Hex in Hex operation. Only the first hundred or so entries in
R1 5000 500E the second 4K of the 8K need to be used, and
R1+1 40 32 these entries compensate for (take the place of)
R2 6000 6004 the entries in the first 4K that must be sibling
R2+1 5 1 descriptors. The STT can and should, to save
space, begin immediately after those hundred or
Contents of Locations 6000-6004 Hex in Binary so entries in the second 4K. In this example, the
index symbols will be 13 bits but will be trans-
00000000 10000001 11111111 10011111 11111000
formed to 12-bit interchange symbols.
K K K K
Initial Final 8. A program may place the dictionaries in pages
CBN CBN that are managed by means of chaining fields at
(7) (5) their beginnings. In this case, either the parts of a
dictionary have to be moved to be compacted
6. The reason for allowing a parent to have no more into contiguous locations or there have to be
than 260 children is as follows. The parent can holes in the dictionaries. The definition of COM-
contain five identical child characters. Then, 255 PRESSION CALL contains nothing explicitly to
different sibling characters are possible — all of support holes. However, assuming there is at
these must be different from the child characters least one character that never appears in the
and each other, or else they may be wasted expanded data, that character can be used as a
(never matched against), depending on the child character in a parent entry or as a sibling
implementation. Thus, every possible child is character in a sibling descriptor to specify a child
permitted. or children that will never be referenced, thus
creating a hole.
7. Symbol translation is for use by VTAM. VTAM will
begin by doing compression by means of soft- 9. The references to the operands, dictionaries, and
ware and an adaptive dictionary. When the adap- symbol-translation table for COMPRESSION
tive dictionary has matured such that the degree CALL may be multiple-access references. (See
of compression becomes sufficiently good “Storage-Operand Consistency” on page 5-95.)
(crosses some threshold), VTAM will “freeze”
(stop adapting) its dictionary, inform the other 10. Setting the ZP control to one may provide
end of the session to freeze also, transform its improved performance on models in which the
adaptive dictionary to the dictionary form used by CMPSC-enhancement facility is installed.
COMPRESSION CALL, and then use COM-
11. Zero padding is not necessarily performed in
PRESSION CALL to continue on with the com-
every case where it is permissible.
pression. The other end of the session can
continue to use its frozen adaptive dictionary. 12. Figure 7-183 on page 7-156 and Figure 7-184
on page 7-158 show possible forms (not the only
Following is clarification about the STT offset.
possible forms) of the compression and expan-
Assume VTAM uses a 4K-entry adaptive dictio-
sion processes. The figures do not show testing
nary, which is the largest size VTAM uses. All of
for or the results of dictionary errors.
the entries in this dictionary correspond to char-
acter symbols because there are no sibling
descriptors in the VTAM dictionary. The VTAM
Perform model-
Another SRC No
dependent zero Set CC0 and endop.
char exists?
padding, as needed
Yes
3
Yes Store parent index in DST.
CCT=0? 9 1
Advance 1 index in DST.
No
4
Yes
Repeat for each CC. Note: See the definition for how CCT specifies
number of CCs and more children.
5
No
No
No
Another CC? 8
Note: The preferred path for Y=0
SCT is shown, but the other
No Yes
indicates more 8 5 path may be taken
children?
Enough
SRC chars for No
8
comparison?
Yes
No Perform model-
Another SRC
dependent zero Set CC0 and endop
index exists?
padding, as needed
Yes
Yes
SYMLEN DST No
byte positions Set CC1 and endop
exist?
Yes
The result is indicated in the condition code. of bit positions 0-31 of general registers R2 and
R2 + 1, always remain unchanged.
The R2 field designates an even-odd pair of general
registers and must designate an even-numbered reg- Figure 7-187 on page 7-161 shows the contents of
ister; otherwise, a specification exception is recog- the general registers just described.
nized.
In the access-register mode, access registers 1 and
The location of the leftmost byte of the second oper- R2 specify the address spaces containing the param-
and is specified by the contents of the R2 general eter block and second operand, respectively.
register. The number of bytes in the second-operand
location is specified in general register R2 + 1. The result is obtained as if processing starts at the
left end of the second operand and proceeds to the
As part of the operation, the address in general regis- right, block by block. The operation is ended when all
ter R2 is incremented by the number of bytes pro- source bytes in the second operand have been pro-
cessed from the second operand, and the length in cessed (called normal completion), or when a CPU-
general register R2 + 1 is decremented by the same determined number of blocks that is less than the
number. The formation and updating of the address length of the second operand have been processed
and length is dependent on the addressing mode. (called partial completion). The CPU-determined
number of blocks depends on the model, and may be
In the 24-bit addressing mode, the contents of bit a different number each time the instruction is exe-
positions 40-63 of general register R2 constitute the cuted. The CPU-determined number of blocks is usu-
address of second operand, and the contents of bit ally nonzero. In certain unusual situations, this
positions 0-39 are ignored; bits 40-63 of the updated number may be zero, and condition code 3 may be
address replace the corresponding bits in general set with no progress. However, the CPU protects
register R2, carries out of bit position 40 of the against endless reoccurrence of this no-progress
updated address are ignored, and the contents of bit case.
positions 32-39 of general register R2 are set to
zeros. In the 31-bit addressing mode, the contents of When the chaining-value field overlaps any portion of
bit positions 33-63 of general register R2 constitute the second operand, the result in the chaining-value
the address of second operand, and the contents of field is unpredictable.
bit positions 0-32 are ignored; bits 33-63 of the
updated address replace the corresponding bits in For COMPUTE INTERMEDIATE MESSAGE
general register R2, carries out of bit position 33 of DIGEST, normal completion occurs when the number
the updated address are ignored, and the content of of bytes in the second operand as specified in gen-
bit position 32 of general register R2 is set to zero. In eral register R2 + 1 have been processed. For COM-
the 64-bit addressing mode, the contents of bit posi- PUTE LAST MESSAGE DIGEST, after all bytes in
tions 0-63 of general register R2 constitute the the second operand as specified in general register
address of second operand; bits 0-63 of the updated R2 + 1 have been processed, the padding operation
address replace the contents of general register R2 is performed, and then normal completion occurs.
and carries out of bit position 0 are ignored.
When the operation ends due to normal completion,
In both the 24-bit and the 31-bit addressing modes, condition code 0 is set and the resulting value in
the contents of bit positions 32-63 of general register R2 + 1 is zero. When the operation ends due to par-
R2 + 1 form a 32-bit unsigned binary integer which tial completion, condition code 3 is set and the result-
specifies the number of bytes in the second operand; ing value in R2 + 1 is nonzero.
and the updated value replaces the contents of bit
positions 32-63 of general register R2 + 1. In the When the second-operand length is initially zero, the
64-bit addressing mode, the contents of bit positions second operand is not accessed, general registers
0-63 of general register R2 + 1 form a 64-bit unsigned R2 and R2 + 1 are not changed, and condition code 0
binary integer which specifies the number of bytes in is set. For COMPUTE INTERMEDIATE MESSAGE
the second operand; and the updated value replaces DIGEST, the parameter block is not accessed. How-
the contents of general register R2 + 1. ever, for COMPUTE LAST MESSAGE DIGEST, the
empty block (L = 0) case padding operation is per-
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
formed and the result is stored into the parameter more than 4K bytes beyond the current location
block. being processed.
As observed by other CPUs and channel programs, Symbols Used in Function Descriptions
references to the parameter block and storage oper-
ands may be multiple-access references, accesses The following symbols are used in the subsequent
to these storage locations are not necessarily block- description of the COMPUTE INTERMEDIATE MES-
concurrent, and the sequence of these accesses or SAGE DIGEST and COMPUTE LAST MESSAGE
references is undefined. DIGEST functions. Further description of the secure
hash algorithm may be found in Secure Hash Stan-
Access exceptions may be reported for a larger por- dard, Federal Information Processing Standards pub-
tion of the second operand than is processed in a lication 180-2, National Institute of Standards and
single execution of the instruction; however, access Technology, Washington DC, August 1, 2002. Further
exceptions are not recognized for locations beyond description of the GCM (Galois/counter mode) multi-
the length of the second operand nor for locations plication over GF(2128) may be found in the draft of
NIST Special Publication 800-38D, dated June 2007.
Symbol Explanation
<n> Length of item in bytes
ICV Initial chaining value
M Message block
ICV <20> M <64> OCV Output chaining value
Figure 7-190. Symbol for SHA-512 Block Digest Algorithm
SHA-1
bda
X <16>
OCV <20>
Y <16> *
Symbol Explanation
<n> Length of item in bytes Z <16>
ICV Initial chaining value
M Message block Z= X* Y
OCV Output chaining value Symbol Explanation
128
Figure 7-188. Symbol for SHA-1 Block Digest Algorithm * GCM multiplication operation over GF(2 )
Figure 7-191. Symbol For GCM Multiplication Operation
128
Over GF(2 )
OCV <32> The parameter block used for the function has the fol-
lowing format:
Symbol Explanation 0
<n> Length of item in bytes Status Word
8
ICV Initial chaining value 0 63
M Message block
OCV Output chaining value Figure 7-192. Parameter Block for KIMD-Query
Figure 7-189. Symbol for SHA-256 Block Digest Algorithm
A 128-bit status word is stored in the parameter
block. Bits 0-127 of this field correspond to function
codes 0-127, respectively, of the COMPUTE INTER-
ICV <64> M <128> MEDIATE MESSAGE DIGEST instruction. When a
bit is one, the corresponding function is installed; oth-
erwise, the function is not installed.
SHA-512
bda
Condition code 0 is set when execution of the KIMD-
Query function completes; condition code 3 is not
OCV <64> applicable to this function.
0 H0 0 H0
4 H1 4 H1
8 H2 8 H2
12 H3 12 H3
16 H4 16 H4
0 31 20 H5
Figure 7-193. Parameter Block for KIMD-SHA-1 24 H6
28 H7
A 20-byte intermediate message digest is generated 0 31
OCV <20>
ICV SHA-256 SHA-256 SHA-256 ... SHA-256
bda bda bda bda
Figure 7-194. KIMD-SHA-1
The locations of the operands and addresses used Figure 7-196. KIMD-SHA-256
by the instruction are as shown in Figure 7-187 on
page 7-161.
KIMD-SHA-512 (KIMD Function Code 3)
The locations of the operands and addresses used
by the instruction are as shown in Figure 7-187 on
page 7-161.
0 H0 0
Initial Chaining Value (ICV)
8 H1 8
16 H2 16
Hash Subkey (H)
24 H3 24
32 H4 0 63
The message digest for the message (M) in operand ICV <20>
p <56> z <56>
<8>
<8>
<64>
q <64>
ICV SHA-1
<20> bda Operand 2 in Storage
M <L>
p <64-L>
OCV <20>
ICV <32>
Operand 2 in Storage
M <L>
OCV <32>
p <56-L>
Parameter <8>
Block in H0 H1 H2 H3 H4 H5 H6 H7
Storage
<64>
ICV <32>
ICV SHA-256
Op 2 in Storage <32> bda
...
M <64>
...
OCV <32>
ICV SHA-256
<32> bda Figure 7-210. KLMD-SHA-256 Partial-Block Case 1 (1 [ L
[ 55)
OCV <32>
OCV <32>
Parameter
KLMD-SHA-512 (KLMD Function Code 3) Block in H0 H1 H2 H3 H4 H5 H6 H7
Storage
The locations of the operands and addresses used
by the instruction are as shown in Figure 7-187 on ICV <64>
page 7-161.
Op 2 in Storage
...
M <128>
The parameter block used for the function has the fol- ...
lowing format:
ICV SHA-512
0 H0 <64> bda
8 H1
16 H2 OCV <64>
Parameter Parameter
Block in H0 H1 H2 H3 H4 H5 H6 H7 mbl Block in H0 H1 H2 H3 H4 H5 H6 H7 mbl
Storage Storage
p <112>
z <112>
<16> <16>
<128>
q <128>
ICV SHA-512
<64> bda Operand 2 in Storage
M <L>
p <128-L>
OCV <64>
1.-6. Exceptions with the same priority as the priority 4. The instructions COMPUTE INTERMEDIATE
of program-interruption conditions for the general MESSAGE DIGEST and COMPUTE LAST MES-
case. SAGE DIGEST are designed to be used by a
security service application programming inter-
7.A Access exceptions for second instruction
face (API). These APIs provide the program with
halfword.
means to compute the digest of messages of
7.B Operation exception. almost unlimited size, including those too large to
fit in storage all at once. This is accomplished by
8. Specification exception due to invalid function permitting the program to pass the message to
code or invalid register number.
the API in parts. The following programming
9. Specification exception due to invalid operand notes are described in terms of these APIs.
length.
5. Before processing the first part of a message,
10. Condition code 0 due to second-operand length the program must set the initial values for the
originally zero. chaining-value field. For SHA-1, the initial hexa-
decimal chaining values are listed as follows:
11. Access exceptions for an access to the
parameter block or second operand.
H0 = 6745 2301
12. Condition code 0 due to normal completion H1 = E F CD AB 8 9
(second-operand length originally nonzero, but H2 = 9 8 BA DC F E
stepped to zero). H3 = 1032 5476
H4 = C3D2 E1F0
13. Condition code 3 due to partial completion
(second-operand length still nonzero). For SHA-256, the initial hexadecimal chaining
values are listed as follows:
Figure 7-217. Priority of Execution: KIMD and KLMD
H0 = 6A0 9 E6 6 7
Programming Notes: H1 = BB 6 7 AE 8 5
H2 = 3C6E F372
1. Bit 56 of general register 0 is reserved for future H3 = A5 4F F53A
extension and should be set to zero. H4 = 510E 527F
H5 = 9B0 5 6 8 8C
2. When condition code 3 is set, the second oper- H6 = 1F83 D9 AB
and address and length in general registers R2 H7 = 5 BE 0 CD 1 9
and R2 + 1, respectively, and the chaining-value
in the parameter block are usually updated such
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
In the access-register mode, access registers 1 and number of blocks depends on the model, and may be
R2 specify the address spaces containing the param- a different number each time the instruction is exe-
eter block and second operand, respectively. cuted. The CPU-determined number of blocks is usu-
ally nonzero. In certain unusual situations, this
The result is obtained as if processing starts at the number may be zero, and condition code 3 may be
left end of the second operand and proceeds to the set with no progress. However, the CPU protects
right, block by block. The operation is ended when all against endless reoccurrence of this no-progress
source bytes in the second operand have been pro- case.
cessed (called normal completion), or when a CPU-
determined number of blocks that is less than the When the initial-chaining-value field overlaps any
length of the second operand have been processed portion of the second operand, the result in the
(called partial completion). The CPU-determined chaining-value field is unpredictable.
The parameter block used for the function has the fol- For the KMAC-Encrypted-DEA function, the contents
lowing format: of byte offsets 16-39 of the parameter block are com-
pared with the contents of the DEA wrapping-key ver-
0 ification-pattern register. If they mismatch, the
Status Word
8 operation is completed by setting condition code 1. If
0 63 they match, byte offsets 0-7 of the parameter block
contain the initial chaining value, and the contents of
Figure 7-225. Parameter Block for KMAC-Query
byte offsets 8-15 of the parameter block are deci-
phered using the DEA wrapping key to obtain the 64-
A 128-bit status word is stored in the parameter
bit cryptographic key. (See the section, “Protection of
block. Bits 0-127 of this field correspond to function
Cryptographic Key” on page 7-339, for details.)
codes 0-127, respectively, of the KMAC instruction.
both functions. value is in byte offsets 0-7 of the parameter block and
the cryptographic key is in byte offsets 8-23 of the
The message authentication code for the 8-byte parameter block.
message blocks (M1, M2, …, Mn) in operand 2 is
computed using the DEA algorithm with the 64-bit The parameter block used for the KMAC-Encrypted-
cryptographic key and the 64-bit initial chaining TDEA-128 function has the following format:
value.
0 Initial Chaining Value (ICV)
The message authentication code, also called the 8 Encrypted Cryptographic Key
output chaining value (OCV), is stored in the initial- (WKd(K))
16
chaining-value field of the parameter block. The oper-
24 DEA Wrapping-Key
ation is shown in Figure 7-228.
32 Verification Pattern
40 (WKdVP)
OCV
0 63
Parameter
Block in CV <8> K <8> Figure 7-230. Parameter Block for KMAC-Encrypted-
Storage TDEA-128
ICV K
For the KMAC-Encrypted-TDEA-128 function, the
...
contents of byte offsets 24-47 of the parameter block
Operand 2
in M1 <8> M2 <8> M3 <8> Mn <8> are compared with the contents of the DEA wrap-
Storage ...
ping-key verification-pattern register. If they mis-
match, the operation is completed by setting
ICV xor xor xor ... xor condition code 1. If they match, byte offsets 0-7 of
the parameter block contain the initial chaining value,
and the contents of byte offsets 8-23 of the parame-
K DEA K DEA K DEA K DEA ter block are deciphered using the DEA wrapping key
e e e e
to obtain the 128-bit cryptographic key, K. (See the
OCV
section, “Protection of Cryptographic Key” on
page 7-339, for details.)
Figure 7-228. MAC Computation Using 64-bit DEA Key
The description in the following paragraph applies to
KMAC-TDEA-128 (Function Code 2) both functions.
ation is shown in Figure 7-234. AES-128 function has the following format:
0
OCV Initial Chaining Value (ICV)
8
Parameter
Block in CV <8> K1 <8> K2 <8> K3 <8>
16 Encrypted Cryptographic Key
Storage (WKa(K))
24
32
ICV K1 K2 K3
40 AES Wrapping-Key
Operand 2 ... Verification Pattern
48 (WKaVP)
in M1 <8> M2 <8> M3 <8> Mn <8>
...
Storage 56
0 63
The parameter block used for the KMAC-AES-128 The message authentication code, also called the
function has the following format: output chaining value (OCV), is stored in the initial-
chaining-value field of the parameter block. The oper-
0 ation is shown in Figure 7-237.
Initial Chaining Value (ICV)
8
16 Operand 2
Cryptographic Key (K) in Storage M1 <16> M2 <16> M3 <16> Mn <16>
...
24
0 63
ICV XOR XOR XOR ... XOR
<16>
Figure 7-235. Parameter Block for KMAC-AES-128
For the KMAC-AES-128 function, the initial-chaining K AES K AES K AES K AES
<16> e <16> e <16> e <16> e
value is in byte offsets 0-15 of the parameter block
and the cryptographic key is in byte offsets 16-31of OCV
the parameter block.
Figure 7-237. KMAC-AES-128
The parameter block used for the KMAC-Encrypted- Figure 7-240. KMAC-AES-192
AES-192 function has the following format:
KMAC-AES-256 (Function Code 20)
0
Initial Chaining Value (ICV)
8 KMAC-Encrypted-AES-256 (Function
16 Code 28)
Encrypted Cryptographic Key The locations of the operands and addresses used
24
(WKa(K))
32 by the instruction are as shown in Figure 7-219 on
page 7-173.
40
48 AES Wrapping-Key
Verification Pattern The parameter block used for the KMAC-AES-256
56 (WKaVP) function has the following format:
64
0 63 0
Initial Chaining Value (ICV)
Figure 7-239. Parameter Block for KMAC-Encrypted-AES- 8
192 16
24
For the KMAC-Encrypted-AES-192 function, the con- Cryptographic Key (K)
32
tents of byte offsets 40-71 of the parameter block are
40
compared with the contents of the AES wrapping-key
0 63
verification-pattern register. If they mismatch, the
operation is completed by setting condition code 1. If Figure 7-241. Parameter Block for KMAC-AES-256
they match, byte offsets 0-15 of the parameter block
contain the initial chaining value, and the contents of For the KMAC-AES-256 function, the initial-chaining
byte offsets 16-39 of the parameter block are deci- value is in byte offsets 0-15 of the parameter block
phered using the AES wrapping key to obtain the and the cryptographic key is in byte offsets 16-47 of
192-bit cryptographic key, K. (See the section “Pro- the parameter block.
AES-256 function has the following format: ation is shown in Figure 7-243.
0 Operand 2
Initial Chaining Value (ICV) M1 <16> M2 <16> M3 <16> Mn <16>
8 in Storage ...
16
ICV XOR XOR XOR ... XOR
24 Encrypted Cryptographic Key <16>
32 (WKa(K))
40 K AES K AES K AES K AES
<32> e <32> e <32> e <32> e
48
56 AES Wrapping-Key
OCV
Verification Pattern
64 (WKaVP) Figure 7-243. KMAC-AES-256
72
0 63 Special Conditions
Figure 7-242. Parameter Block for KMAC-Encrypted-AES-
A specification exception is recognized and no other
256
action is taken if any of the following occurs:
For the KMAC-Encrypted-AES-256 function, the con-
1. Bit 56 of general register 0 is not zero.
tents of byte offsets 48-79 of the parameter block are
compared with the contents of the AES wrapping-key 2. Bits 57-63 of general register 0 specify an unas-
verification-pattern register. If they mismatch, the signed or uninstalled function code.
operation is completed by setting condition code 1. If
they match, byte offsets 0-15 of the parameter block 3. The R2 field designates an odd-numbered regis-
contain the initial chaining value, and the contents of ter or general register 0.
byte offsets 16-47 of the parameter block are deci-
4. The second-operand length is not a multiple of
phered using the AES wrapping key to obtain the
the data block size of the designated function
256-bit cryptographic key, K. (See the section “Pro-
(see Figure 7-218 on page 7-172 to determine
tection of Cryptographic Key” on page 7-339 for
the data block size for COMPUTE MESSAGE
details.)
AUTHENTICATION CODE functions).
The description in the following paragraph applies to
Resulting Condition Code:
both functions.
CONVERT TO BINARY
set to all binary zeros. To comply with ANSI X9.9,
1.-6. Exceptions with the same priority as the priority ANSI X9.19, or NIST Special Publication 800-
of program-interruption conditions for the general 38D, the initial chaining value shall be set to all
case. binary zeros.
7.A Access exceptions for second instruction 4. For the KMAC-GHASH function, the hash sub-
halfword. key, H, is the result of encrypting a 128-bit zero
using the AES encryption algorithm with a 128-
7.B Operation exception.
bit, 192-bit, or 256-bit cryptographic key.
8. Specification exception due to invalid function
code or invalid register number. 5.
ation is completed by placing the 32 rightmost bits of 'E3' R1 X2 B2 DL2 DH2 '26'
the binary result in the register, and a fixed-point-
0 8 12 16 20 32 40 47
divide exception is recognized.
For CONVERT TO BINARY (CVBG), the result of the CVDG R1,D2(X2,B2) [RXY-a]
conversion is a 64-bit signed binary integer, which is 'E3' R1 X2 B2 DL2 DH2 '2E'
placed in bit positions 0-63 of general register R1. 0 8 12 16 20 32 40 47
The maximum positive number that can be converted
and still be contained in a 64-bit register is
9,223,372,036,854,775,807; the maximum negative The first operand is changed from binary to decimal,
number (the negative number with the greatest abso- and the result is stored at the second-operand loca-
lute value) that can be converted is tion.
-9,223,372,036,854,775,808. For any decimal num-
ber outside this range, a fixed-point-divide exception For CONVERT TO DECIMAL (CVD, CVDY), the first
is recognized, and the operation is suppressed. operand is treated as a 32-bit signed binary integer,
and the result occupies eight bytes in storage. For
The displacement for CVB is treated as a 12-bit CONVERT TO DECIMAL (CVDG), the first operand
unsigned binary integer. The displacement for CVBY is treated as a 64-bit signed binary integer, and the
and CVBG is treated as a 20-bit signed binary inte- result occupies sixteen bytes in storage.
ger.
The result is in the format for signed-packed-decimal
Condition Code: The code remains unchanged. data, as described in Chapter 8, “Decimal Instruc-
tions.” The rightmost four bits of the result represent
Program Exceptions: the sign. A positive sign is encoded as 1100; a nega-
tive sign is encoded as 1101.
• Access (fetch, operand 2)
• Data The displacement for CVD is treated as a 12-bit
• Fixed-point divide unsigned binary integer. The displacement for CVDY
• Operation (CVBY, if the long-displacement facility and CVDG is treated as a 20-bit signed binary inte-
is not installed) ger.
3. The storage-operand references for CONVERT 1. An example of the use of the CONVERT TO
TO BINARY may be multiple-access references. DECIMAL instruction is given in Appendix A,
(See “Storage-Operand Consistency” on “Number Representation and Instruction-Use
page 5-95.) Examples.”
The two-byte UTF-16 (Unicode) characters of the The handling of the addresses in general registers R1
second operand are converted to UTF-32 characters and R2 is dependent on the addressing mode.
and placed at the first-operand location. The UTF-32
characters are four bytes. The operation proceeds In the 24-bit addressing mode, the contents of bit
until the end of the first or second operand is positions 40-63 of general registers R1 and R2 consti-
reached, a CPU-determined number of characters tute the address, and the contents of bit positions
have been converted, or an invalid Unicode character 0-39 are ignored. In the 31-bit addressing mode, the
is encountered, whichever occurs first. The result is contents of bit positions 33-63 of the registers consti-
indicated in the condition code. tute the address, and the contents of bit positions
0-32 are ignored. In the 64-bit addressing mode, the
The R1 and R2 fields each designate an even-odd contents of bit positions 0-63 constitute the address.
pair of general registers and must designate an even-
numbered register; otherwise, a specification excep- The contents of the registers just described are
tion is recognized. shown in Figure 7-245 on page 7-184.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
When the ETF3-enhancement facility is installed, the zero, enhanced checking is not performed. When
M3 field has the following format: the W bit is one, enhanced checking is per-
formed, as described below.
/ / / W
0 3
When the ETF3-enhancement facility is not installed,
the M3 field is ignored.
The bits of the M3 field are defined as follows: The characters of the second operand are selected
one by one for conversion, proceeding left to right.
• Unassigned: Bits 0-2 are unassigned and The characters resulting from a conversion are
should contain zeros; otherwise, the program placed at the first-operand location, proceeding left to
may not operate compatibly in the future. right. The operation proceeds until the first-operand
or second-operand location is exhausted or a CPU-
• Enhanced Well-Formedness-Checking (W):
determined number of second-operand characters
The W bit, bit 3 of the M3 field, controls whether
have been converted.
enhanced well-formedness checking of the Uni-
code characters is performed. When the W bit is
When the ETF3-enhancement facility is not installed, The amount of processing that results in the setting
or when the W bit of the M3 field is zero, the first six of condition code 3 is determined by the CPU on the
bits of the Unicode low surrogate are ignored. When basis of improving system performance, and it may
the ETF3-enhancement facility is installed, and the W be a different amount each time the instruction is
bit is one, the first six bits of the Unicode low surro- executed.
gate must contain 110111 binary; otherwise, the Uni-
code low surrogate is invalid, and condition code 2 is When the R1 register is the same register as the R2
set. register, the results are unpredictable.
The second-operand location is considered When the second operand overlaps the first operand,
exhausted when it does not contain at least two the results are unpredictable.
remaining bytes or at least four remaining bytes
when the first two bytes are a Unicode high surro-
the right of the last byte processed may or may not and are converted to UTF-8 characters and placed at
be recognized. For an operand longer than 4K bytes, the first-operand location. The UTF-8 characters are
access exceptions are not recognized for locations one, two, three, or four bytes, depending on the Uni-
more than 4K bytes beyond the last byte processed. code characters that are converted. The operation
proceeds until the end of the first or second operand
When the length of an operand is zero, no access is reached or a CPU-determined number of charac-
exceptions are recognized for that operand. Access ters have been converted, whichever occurs first.
exceptions are not recognized for an operand if the R The result is indicated in the condition code.
field associated with that operand is odd.
The R1 and R2 fields each designate an even-odd
Resulting Condition Code: pair of general registers and must designate an even-
numbered register; otherwise, a specification excep-
0 Entire second operand processed tion is recognized.
1 End of first operand reached
2 Invalid Unicode low surrogate The location of the leftmost byte of the first operand
3 CPU-determined number of characters con- and the second operand is designated by the con-
verted tents of general registers R1 and R2, respectively. In
the 24-bit or 31-bit addressing mode, the number of
Program Exceptions: bytes in the first-operand and second-operand loca-
tions is specified by the contents of bit positions
• Access (fetch, operand 2; store, operand 1) 32-63 of general registers R1 + 1 and R2 + 1, respec-
• Operation (if the extended-translation facility 3 is tively, and those contents are treated as 32-bit
not installed) unsigned binary integers. In the 64-bit addressing
• Specification mode, the number of bytes in the first-operand and
second-operand locations is specified by the entire
Programming Notes: contents of general registers R1 + 1 and R2 + 1,
respectively, and those contents are treated as 64-bit
1. When condition code 3 is set, the program can unsigned binary integers.
simply branch back to the instruction to continue
the conversion. The program need not determine The handling of the addresses in general registers R1
the number of first-operand or second-operand and R2 is dependent on the addressing mode.
bytes that were processed.
In the 24-bit addressing mode, the contents of bit
2. The storage-operand references of CONVERT positions 40-63 of general registers R1 and R2 consti-
UTF-16 TO UTF-32 may be multiple-access ref- tute the address, and the contents of bit positions
erences. (See “Storage-Operand Consistency” 0-39 are ignored. In the 31-bit addressing mode, the
on page 5-95.) contents of bit positions 33-63 of the registers consti-
3. The CONVERT UTF-16 TO UTF-32 instruction tute the address, and the contents of bit positions
supports UTF-16 and UTF-32 characters only in 0-32 are ignored. In the 64-bit addressing mode, the
the big-endian encoding. contents of bit positions 0-63 constitute the address.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
When the ETF3-enhancement facility is installed, the zero, enhanced checking is not performed. When
M3 field has the following format: the W bit is one, enhanced checking is per-
formed, as described below.
/ / / W
0 3
When the ETF3-enhancement facility is not installed,
the M3 field is ignored.
The bits of the M3 field are defined as follows: The characters of the second operand are selected
one by one for conversion, proceeding left to right.
• Unassigned: Bits 0-2 are unassigned and The bytes resulting from a conversion are placed at
should contain zeros; otherwise, the program the first-operand location, proceeding left to right.
may not operate compatibly in the future. The operation proceeds until the first-operand or sec-
ond-operand location is exhausted, a CPU-deter-
• Enhanced Well-Formedness-Checking (W):
mined number of second-operand characters have
The W bit, bit 3 of the M3 field, controls whether
been converted, or an invalid Unicode character is
enhanced well-formedness checking of the Uni-
encountered in the second operand.
code characters is performed. When the W bit is
ter to a UTF-8 character, the bits of a Unicode char- rogate in the range D800 to DBFF hex is converted to
acter are identified by letters as follows: a four-byte UTF-8 character as follows:
When the R1 register is the same register as the R2 The four-byte UTF-32 characters of the second oper-
register, the results are unpredictable. and are converted to two-byte UTF-16 characters
and placed at the first-operand location. The opera-
When the second operand overlaps the first operand, tion proceeds until the end of the first or second oper-
the results are unpredictable. and is reached, a CPU-determined number of
characters have been converted, or an invalid
Access exceptions for the portions of the operands to UTF-32 character is encountered, whichever occurs
the right of the last byte processed may or may not first. The result is indicated in the condition code.
be recognized. For an operand longer than 4K bytes,
access exceptions are not recognized for locations The R1 and R2 fields each designate an even-odd
more than 4K bytes beyond the last byte processed. pair of general registers and must designate an even-
numbered register; otherwise, a specification excep-
When the length of an operand is zero, no access tion is recognized.
exceptions are recognized for that operand. Access
exceptions are not recognized for an operand if the R The location of the leftmost byte of the first operand
field associated with that operand is odd. and the second operand is designated by the con-
tents of general registers R1 and R2, respectively. In
Resulting Condition Code: the 24-bit or 31-bit addressing mode, the number of
bytes in the first-operand and second-operand loca-
0 Entire second operand processed tions is specified by the contents of bit positions
1 End of first operand reached 32-63 of general registers R1 + 1 and R2 + 1, respec-
2 Invalid Unicode low surrogate tively, and those contents are treated as 32-bit
3 CPU-determined number of characters con- unsigned binary integers. In the 64-bit addressing
verted mode, the number of bytes in the first-operand and
second-operand locations is specified by the entire
Program Exceptions: contents of general registers R1 + 1 and R2 + 1,
respectively, and those contents are treated as 64-bit
• Access (fetch, operand 2; store, operand 1) unsigned binary integers.
• Specification
The handling of the addresses in general registers R1
Programming Notes: and R2 is dependent on the addressing mode.
1. When condition code 3 is set, the program can In the 24-bit addressing mode, the contents of bit
simply branch back to the instruction to continue positions 40-63 of general registers R1 and R2 consti-
the conversion. The program need not determine tute the address, and the contents of bit positions
contents of bit positions 33-63 of the registers consti- shown in Figure 7-247 on page 7-190.
tute the address, and the contents of bit positions
0-32 are ignored. In the 64-bit addressing mode, the
contents of bit positions 0-63 constitute the address.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
The characters of the second operand are selected 0000DC00 to 0000FFFF hex are identified by letters
one by one for conversion, proceeding left to right. as follows:
The bytes resulting from a conversion are placed at
the first-operand location, proceeding left to right. UTF-32
The operation proceeds until the first-operand or sec- Character
ond-operand location is exhausted, a CPU-deter- Bit Numbers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
mined number of second-operand characters have Identifying Bit Letters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
been converted, or an invalid UTF-32 character is
encountered in the second operand.
UTF-32
Character
To show the method of converting a UTF-32 charac- Bit Numbers 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ter to a UTF-16 character, the bits of a UTF-32 char-
Identifying Bit Letters a b c d e f g h i j k l mn o p
acter in the range 00000000 to 0000D7FF and
UTF-16 High Surrogate Bit When the contents of the next UTF-32 character is in
Numbers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 the range 0000D800 to 0000DBFF or 00110000 to
Identifying Bit Letters 1 1 0 1 1 0 a b c d e f g h i j FFFFFFFF hex, the character is invalid, and condi-
tion code 2 is set.
UTF-16 Low Surrogate Bit
Numbers 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
When the conditions for setting condition codes 1
Identifying Bit Letters 1 1 0 1 1 1 k l mn o p q r s t and 2 are both met, condition code 2 is set.
contains the address of the invalid UTF-32 character. UTF-32 TO UTF-16 may be multiple-access ref-
erences. (See “Storage-Operand Consistency”
When condition code 3 is set, the registers have on page 5-95.)
been updated so that the instruction, when reexe-
cuted, resumes at the next byte locations to be pro- 3. The CONVERT UTF-32 TO UTF-16 instruction
cessed. supports UTF-16 and UTF-32 characters only in
the big-endian encoding.
The amount of processing that results in the setting
of condition code 3 is determined by the CPU on the CONVERT UTF-32 TO UTF-8
basis of improving system performance, and it may
be a different amount each time the instruction is CU41 R1,R2 [RRE]
executed.
'B9B2' / / / / / / / / R1 R2
When the R1 register is the same register as the R2 0 16 24 28 31
When the length of an operand is zero, no access The R1 and R2 fields each designate an even-odd
exceptions are recognized for that operand. Access pair of general registers and must designate an even-
exceptions are not recognized for an operand if the R numbered register; otherwise, a specification excep-
field associated with that operand is odd. tion is recognized.
Resulting Condition Code: The location of the leftmost byte of the first operand
and the second operand is designated by the con-
0 Entire second operand processed tents of general registers R1 and R2, respectively. In
1 End of first operand reached the 24-bit or 31-bit addressing mode, the number of
2 Invalid UTF-32 character bytes in the first-operand and second-operand loca-
3 CPU-determined number of characters pro- tions is specified by the contents of bit positions
cessed 32-63 of general registers R1 + 1 and R2 + 1, respec-
tively, and those contents are treated as 32-bit
Program Exceptions: unsigned binary integers. In the 64-bit addressing
mode, the number of bytes in the first-operand and
• Access (fetch, operand 2; store, operand 1) second-operand locations is specified by the entire
• Operation (if the extended-translation facility 3 is contents of general registers R1 + 1 and R2 + 1,
not installed) respectively, and those contents are treated as 64-bit
• Specification unsigned binary integers.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
The characters of the second operand are selected 0000DC00 to 0000FFFF hex are identified by letters
one by one for conversion, proceeding left to right. as follows:
The bytes resulting from a conversion are placed at
the first-operand location, proceeding left to right. UTF-32
The operation proceeds until the first-operand or sec- Character
ond-operand location is exhausted or a CPU-deter- Bit Numbers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
mined number of second-operand characters have Identifying Bit Letters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
been converted.
UTF-32
To show the method of converting a UTF-32 charac- Character
ter to a UTF-8 character, the bits of a UTF-32 charac- Bit Numbers 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ter in the range 00000000 to 0000D7FF and
Identifying Bit Letters a b c d e f g h i j k l mn o p
00010000 to 0010FFFF hex (UTF-16 surrogate pair) contain the UTF-8 character resulting from the con-
are identified by letters as follows: version of the next second-operand character or sur-
rogate pair.
UTF-32
Character When the second-operand location is exhausted,
Bit Numbers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 condition code 0 is set. When the first-operand loca-
Identifying Bit Letters 0 0 0 0 0 0 0 0 0 0 0 u v w x y tion is exhausted, condition code 1 is set, except that
condition code 0 is set if the second-operand location
also is exhausted. When a CPU-determined number
UTF-32
Character of characters have been converted, condition code 3
Bit Numbers 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
is set.
Identifying Bit Letters e f g h i j k l mn o p q r s t
When the UTF-32 character is in the range
0000D800 and 0000DBFF or 00110000 to
Any UTF-32 character in the range 00000000 to
FFFFFFFF hex, the character is invalid, and condi-
0000007F hex is converted to a one-byte UTF-8
tion code 2 is set.
character as follows:
When the conditions for setting condition codes 1
UTF-32
Character 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 j k l mn o p
and 2 are both met, condition code 2 is set.
UTF-8 0 j k l mn o p
Character When the operation is completed, the contents of
general register R2 + 1 are decremented by the num-
Any UTF-32 character in the range 00000080 to ber of bytes converted, and the contents of general
000007FF hex is converted to a two-byte UTF-8 register R2 are incremented by the same number.
character as follows: Also, the contents of general register R1 + 1 are dec-
remented by the number of bytes placed at the first-
UTF-32
operand location, and the contents of general regis-
Character 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f g h i j k l mn o p ter R1 are incremented by the same number. When
UTF-8 1 1 0 f g h i j 1 0 k l mn o p general registers R1 and R2 are updated in the 24-bit
Character or 31-bit addressing mode, bits 32-39 of them, in the
24-bit mode, or bit 32, in the 31-bit mode, may be set
Any UTF-32 character in the range 00000800 to to zeros or may remain unchanged.
0000D7FF and 0000DC00 to 0000FFFF hex is con-
verted to a three-byte UTF-8 character as follows: In the 24-bit or 31-bit addressing mode, the contents
of bit positions 0-31 of general registers R1, R1 + 1,
UTF-32 R2, and R2 + 1, always remain unchanged.
Character 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a b c d e f g h i j k l mn o p
UTF-8 1 1 1 0 a b c d 1 0 e f g h i j 1 0 k l mn o p When condition code 2 is set, general register R2
Character contains the address of the invalid UTF-32 character.
Any UTF-32 character in the range 00010000 to When condition code 3 is set, the registers have
0010FFFF hex is converted to a four-byte UTF-8 been updated so that the instruction, when reexe-
character as follows: cuted, resumes at the next byte locations to be pro-
cessed.
UTF-32
Character 0 0 0 0 0 0 0 0 0 0 0 u v w x y e f g h i j k l mn o p q r s t The amount of processing that results in the setting
UTF-8 1 1 1 1 0 u v w1 0 x y e f g h 1 0 i j k l mn 1 0 o p q r s t of condition code 3 is determined by the CPU on the
Character basis of improving system performance, and it may
be a different amount each time the instruction is
The second-operand location is considered executed.
exhausted when it does not contain at least four
remaining bytes. The first-operand location is consid- When the R1 register is the same register as the R2
ered exhausted when it does not contain at least the register, the results are unpredictable.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
When the ETF3-enhancement facility is installed, the zero, enhanced checking is not performed. When
M3 field has the following format: the W bit is one, enhanced checking is per-
formed, as described below.
/ / / W
0 3
When the ETF3-enhancement facility is not installed,
the M3 field is ignored.
The bits of the M3 field are defined as follows: The characters of the second operand are selected
one by one for conversion, proceeding left to right.
• Unassigned: Bits 0-2 are unassigned and The bytes resulting from a conversion are placed at
should contain zeros; otherwise, the program the first-operand location, proceeding left to right.
may not operate compatibly in the future. The operation proceeds until the first-operand or sec-
ond-operand location is exhausted, a CPU-deter-
• Enhanced Well-Formedness-Checking (W):
mined number of second-operand characters have
The W bit, bit 3 of the M3 field, controls whether
been converted, or an invalid UTF-8 character is
enhanced well-formedness checking of the UTF-
encountered in the second operand.
8 characters is performed. When the W bit is
UTF-8
Conversion of a UTF-8 character to a Unicode char-
Character 1 1 1 0 a b c d 1 0 e f g h i j 1 0 k l m n o p
acter is as follows:
Unicode a b c d e f g h i j k l m n o p
Character
1. When the contents of the first byte of a UTF-8
character are in the range 00 to 7F hex, the char- When the ETF3-enhancement facility is not
acter is a one-byte character, and it is converted installed or when the W bit of the M3 field is zero,
to a two-byte Unicode character as follows: the first two bits in the second and third bytes of
the UTF-8 character are ignored.
UTF-8
Character 0 j k l m n o p When the ETF3-enhancement facility is installed
Unicode 0 0 0 0 0 0 0 0 0 j k l m n o p and the W bit of the M3 field is one, the contents
Character of the second and third bytes of the UTF-8 char-
acter must be as follows:
2. When the contents of the first byte of the UTF-8
character are in the range 80 to BF hex, the char- • When the first byte is E0 hex, the second
acter is invalid. When the ETF3-enhancement and third bytes must be in the ranges A0 to
facility is installed, the W bit of the M3 field is one, BF and 80 to BF, respectively.
and the contents of the first byte of the UTF-8
character are in the range C0 to C1 hex, the • When the first byte is in the range E1 to EC
character is also invalid. hex or EE to EF, the second and third bytes
must both be in the range 80 to BF hex.
3. When the ETF3-enhancement facility is not
installed or the W bit of the M3 field is zero, and • When the first byte is ED hex, the second
the contents of the first byte of the UTF-8 charac- and third bytes must be in the ranges 80 to
ter are in the range of C0 to DF hex; or when the 9F and 80 to BF, respectively.
ETF3-enhancement facility is installed, the W bit
Otherwise, the character is invalid.
is one, and the contents of the first byte of the
UTF-8 character are in the range of C2 to DF 5. When the ETF3-enhancement facility is not
hex; the character is a two-byte character, and it installed or the W bit of the M3 field is zero, and
the contents of the first byte of the UTF-8 charac-
ter are in the range of F0 to F7 hex; or when the
ETF3-enhancement facility is installed, the W bit
is one, and the contents of the first byte of the
the character is a four-byte character, and it is or at least four remaining bytes in the case when a
converted to two two-byte Unicode characters (a four byte UTF-8 character is to be converted.
surrogate pair) as follows:
When the second-operand location is exhausted,
UTF-8 condition code 0 is set. When the first-operand loca-
Character 1 1 1 1 0 u v w 1 0 x y e f g h 1 0 i j k l m n 1 0 o p q r s t
tion is exhausted, condition code 1 is set, except that
Unicode 1 1 0 1 1 0 a b c d e f g h i j 1 1 0 1 1 1 k l m n o p q r s t
condition code 0 is set if the second-operand location
Characters
also is exhausted. When a CPU-determined number
where zabcd = uvwxy - 1
of characters have been processed, condition code 3
When the ETF3-enhancement facility is not is set.
installed or when the W bit of the M3 field is zero,
the first two bits in the second, third, and fourth When the contents of the first byte of the next UTF-8
bytes of the UTF-8 character are ignored, and character are in the range 80 to BF hex or F8 to FF
the high order bit (z) produced by the subtract hex, the character is invalid, and condition code 2 is
operation should be zero but is ignored. set.
When the ETF3-enhancement facility is installed When the conditions for setting condition codes 1
and the W bit of the M3 field is one, the contents and 2 are both met, condition code 2 is set.
of the second, third, and fourth bytes of the UTF-
8 character must be as follows: When the operation is completed, the contents of
general register R2 + 1 are decremented by the num-
• When the first byte is F0 hex, the second,
ber of bytes converted, and the contents of general
third, and fourth bytes must be in the ranges
register R2 are incremented by the same number.
90 to BF, 80 to BF, and 80 to BF, respectively.
Also, the contents of general register R1 + 1 are dec-
• When the first byte is in the range F1 to F3, remented by the number of bytes placed at the first-
the second, third, and fourth bytes must all operand location, and the contents of general regis-
be in the range 80 to BF hex. ter R1 are incremented by the same number. When
general registers R1 and R2 are updated in the 24-bit
• When the first byte is F4 hex, the second, or 31-bit addressing mode, bits 32-39 of them, in the
third, and fourth bytes must be in the ranges 24-bit mode, or bit 32, in the 31-bit mode, may be set
80 to 8F, 80 to BF, and 80 to BF, respectively. to zeros or may remain unchanged.
Otherwise, the character is invalid.
In the 24-bit or 31-bit addressing mode, the contents
6. When the ETF3-enhancement facility is installed, of bit positions 0-31 of general registers R1, R1 + 1,
the W bit of the M3 field is one, and the contents R2, and R2 + 1, always remain unchanged.
of the first byte of the UTF-8 character are in the
range of F5 to F7 hex, the character is invalid. When condition code 2 is set, general register R2
contains the address of the invalid UTF-8 character.
7. When the contents of the first byte of the UTF-8
character are in the range of F8-FF, the character When condition code 3 is set, the registers have
is invalid. been updated so that the instruction, when reexe-
cuted, resumes at the next byte locations to be pro-
If an invalid character is encountered, condition code cessed.
2 is set, and general register R2 contains the address
of the first byte of the invalid UTF-8 character. The amount of processing that results in the setting
of condition code 3 is determined by the CPU on the
The second-operand location is considered basis of improving system performance, and it may
exhausted when it does not contain at least one be a different amount each time the instruction is
remaining byte or when it does not contain at least executed.
the two, three, or four remaining bytes required to
contain the two-, three-, or four-byte UTF-8 character When the R1 register is the same register as the R2
indicated by the contents of the first remaining byte. register, the results are unpredictable.
The first-operand location is considered exhausted
Program Exceptions: The location of the leftmost byte of the first operand
and the second operand is designated by the con-
• Access (fetch, operand 2; store, operand 1) tents of general registers R1 and R2, respectively. In
• Specification the 24-bit or 31-bit addressing mode, the number of
bytes in the first-operand and second-operand loca-
Programming Notes: tions is specified by the contents of bit positions
32-63 of general registers R1 + 1 and R2 + 1, respec-
1. When condition code 3 is set, the program can tively, and those contents are treated as 32-bit
simply branch back to the instruction to continue unsigned binary integers. In the 64-bit addressing
the conversion. The program need not determine mode, the number of bytes in the first-operand and
the number of first-operand or second-operand second-operand locations is specified by the entire
bytes that were processed. contents of general registers R1 + 1 and R2 + 1,
respectively, and those contents are treated as 64-bit
2. When the ETF3-enhancement facility is not
unsigned binary integers.
installed, or when the W bit of the M3 operand is
zero, bits 0 and 1 of the continuation bytes of
The handling of the addresses in general registers R1
multiple-byte UTF-8 characters are not checked
and R2 is dependent on the addressing mode.
in order to improve the performance of the con-
version. Therefore, invalid continuation bytes are
In the 24-bit addressing mode, the contents of bit
not detected.
positions 40-63 of general registers R1 and R2 consti-
3. The storage-operand references of CONVERT tute the address, and the contents of bit positions
UTF-8 TO UTF-16 may be multiple-access refer- 0-39 are ignored. In the 31-bit addressing mode, the
ences. (See “Storage-Operand Consistency” on contents of bit positions 33-63 of the registers consti-
page 5-95.) tute the address, and the contents of bit positions
0-32 are ignored. In the 64-bit addressing mode, the
4. The CONVERT UTF-8 TO UTF-16 (CONVERT contents of bit positions 0-63 constitute the address.
UTF-8 TO UNICODE) instruction supports UTF-
16 characters only in the big-endian encoding. The contents of the registers just described are
shown in Figure 7-250 on page 7-200.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R2 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
R2 + 1 Second-Operand Length
0 63
When the ETF3-enhancement facility is installed, the the W bit is one, enhanced checking is per-
M3 field has the following format: formed, as described below.
Conversion of a UTF-8 character to a UTF-32 char- When the ETF3-enhancement facility is not
acter is as follows: installed or when the W bit of the M3 field is zero,
the first two bits in the second and third bytes of
1. When the contents of the first byte of a UTF-8 the UTF-8 character are ignored.
character are in the range 00 to 7F hex, the char-
acter is a one-byte character, and it is converted When the ETF3-enhancement facility is installed
to a four-byte UTF-32 character as follows: and the W bit of the M3 field is one, the contents
of the second and third bytes of the UTF-8 char-
UTF-8 acter must be as follows:
Character 0 j k l m n o p
UTF-32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 j k l m n o p • When the first byte is E0 hex, the second
Character and third bytes must be in the ranges A0 to
BF and 80 to BF, respectively.
2. When the contents of the first byte of the UTF-8
character are in the range 80 to BF hex, the char- • When the first byte is in the range E1 to EC
acter is invalid. When the ETF3-enhancement hex or EE to EF, the second and third bytes
facility is installed, the W bit of the M3 field is one, must both be in the range 80 to BF hex.
and the contents of the first byte of the UTF-8
• When the first byte is ED hex, the second
character are in the range C0 to C1 hex, the
and third bytes must be in the ranges 80 to
character is also invalid.
9F and 80 to BF, respectively.
3. When the ETF3-enhancement facility is not
Otherwise, the character is invalid.
installed or the W bit of the M3 field is zero, and
the contents of the first byte of the UTF-8 charac- 5. When the ETF3-enhancement facility is not
ter are in the range of C0 to DF hex; or when the installed or the W bit of the M3 field is zero, and
ETF3-enhancement facility is installed, the W bit the contents of the first byte of the UTF-8 charac-
is one, and the contents of the first byte of the ter are in the range of F0 to F7 hex; or when the
When the ETF3-enhancement facility is not When the contents of the first byte of the next UTF-8
installed or when the W bit of the M3 field is zero, character are in the range 80 to BF hex or F8 to FF
the first two bits in the second, third, and fourth hex, the character is invalid, and condition code 2 is
bytes of the UTF-8 character are ignored. set.
When the ETF3-enhancement facility is installed When the conditions for setting condition codes 1
and the W bit of the M3 field is one, the contents and 2 are both met, condition code 2 is set.
of the second, third, and fourth bytes of the UTF-
8 character must be as follows: When the operation is completed, the contents of
general register R2 + 1 are decremented by the num-
• When the first byte is F0 hex, the second,
ber of bytes converted, and the contents of general
third, and fourth bytes must be in the ranges
register R2 are incremented by the same number.
90 to BF, 80 to BF, and 80 to BF, respectively.
Also, the contents of general register R1 + 1 are dec-
• When the first byte is in the range F1 to F3, remented by the number of bytes placed at the first-
the second, third, and fourth bytes must all operand location, and the contents of general regis-
be in the range 80 to BF hex. ter R1 are incremented by the same number. When
general registers R1 and R2 are updated in the 24-bit
• When the first byte is F4 hex, the second, or 31-bit addressing mode, bits 32-39 of them, in the
third, and fourth bytes must be in the ranges 24-bit mode, or bit 32, in the 31-bit mode, may be set
80 to 8F, 80 to BF, and 80 to BF, respectively. to zeros or may remain unchanged.
Otherwise, the character is invalid.
In the 24-bit or 31-bit addressing mode, the contents
6. When the ETF3-enhancement facility is installed, of bit positions 0-31 of general registers R1, R1 + 1,
the W bit of the M3 field is one, and the contents R2, and R2 + 1, always remain unchanged.
of the first byte of the UTF-8 character are in the
range of F5 to F7 hex, the character is invalid. When condition code 2 is set, general register R2
contains the address of the invalid UTF-8 character.
7. When the contents of the first byte of the UTF-8
character are in the range of F8-FF, the character When condition code 3 is set, the registers have
is invalid. been updated so that the instruction, when reexe-
cuted, resumes at the next byte locations to be pro-
If an invalid character is encountered, condition code cessed.
2 is set, and general register R2 contains the address
of the first byte of the invalid UTF-8 character. The amount of processing that results in the setting
of condition code 3 is determined by the CPU on the
The second-operand location is considered basis of improving system performance, and it may
exhausted when it does not contain at least one be a different amount each time the instruction is
remaining byte or when it does not contain at least executed.
the two, three, or four remaining bytes required to
contain the two-, three-, or four-byte UTF-8 character When the R1 register is the same register as the R2
indicated by the contents of the first remaining byte. register, the results are unpredictable.
The first-operand location is considered exhausted
DIVIDE
the results are unpredictable.
CPYA R1,R2 [RRE]
Access exceptions for the portions of the operands to
the right of the last byte processed may or may not 'B24D' / / / / / / / / R1 R2
be recognized. For an operand longer than 4K bytes, 0 16 24 28 31
Programming Notes:
The 64-bit first operand (the dividend) is divided by
1. When condition code 3 is set, the program can the 32-bit second operand (the divisor), and the
simply branch back to the instruction to continue 32-bit remainder and quotient are placed at the first-
the conversion. The program need not determine operand location.
the number of first-operand or second-operand
bytes that were processed. The R1 field designates an even-odd pair of general
registers and must designate an even-numbered reg-
2. When the ETF3-enhancement facility is not ister; otherwise, a specification exception is recog-
installed, or when the W bit of the M3 operand is nized.
zero, bits 0 and 1 of the continuation bytes of
multiple-byte UTF-8 characters are not checked The dividend is treated as a 64-bit signed binary inte-
in order to improve the performance of the con- ger. The leftmost 32 bits of the dividend are in bit
version. Therefore, invalid continuation bytes are positions 32-63 of general register R1, and the right-
not detected. most 32 bits are in bit positions 32-63 of general reg-
ister R1 + 1.
3. The storage-operand references of CONVERT
UTF-8 TO UTF-32 may be multiple-access refer-
The divisor, remainder, and quotient are treated as
ences. (See “Storage-Operand Consistency” on
32-bit signed binary integers. For DIVIDE (DR), the
page 5-95.)
divisor is in bit positions 32-63 of general register R2.
4. The CONVERT UTF-8 TO UTF-32 instruction The remainder is placed in bit positions 32-63 of gen-
supports UTF-32 characters only in the big- eral register R1, and the quotient is placed in bit posi-
endian encoding. tions 32-63 of general register R1 + 1. Bits 0-31 of the
registers remain unchanged.
algebra, and the remainder has the same sign as the treated as a 64-bit unsigned binary integer. The left-
dividend, except that a zero quotient or a zero most 32 bits of the dividend are in bit positions 32-63
remainder is always positive. of general register R1, and the rightmost 32 bits are
in bit positions 32-63 of general register R1 + 1.
When the divisor is zero, or when the magnitudes of
the dividend and divisor are such that the quotient The divisor, remainder, and quotient are treated as
cannot be expressed by a 32-bit signed binary inte- 32-bit unsigned binary integers. For DIVIDE LOGI-
ger, a fixed-point-divide exception is recognized. This CAL (DLR), the divisor is in bit positions 32-63 of
includes the case of division of zero by zero. general register R2. The remainder is placed in bit
positions 32-63 of general register R1, and the quo-
Condition Code: The code remains unchanged. tient is placed in bit positions 32-63 of general regis-
ter R1 + 1. Bits 0-31 of the registers remain
Program Exceptions: unchanged.
• Access (fetch, operand 2 of D only) For DIVIDE LOGICAL (DLGR, DLG), the dividend is
• Fixed-point divide treated as a 128-bit unsigned binary integer. The left-
• Specification most 64 bits of the dividend are in general register
R1, and the rightmost 64 bits are in general register
R1 + 1. The divisor, remainder, and quotient are
DIVIDE LOGICAL treated as 64-bit unsigned binary integers. The
remainder is placed in general register R1, and the
Register-and-register formats:
quotient is placed in general register R1 + 1.
DLR R1,R2 [RRE]
When the divisor is zero, or when the magnitudes of
'B997' / / / / / / / / R1 R2 the dividend and divisor are such that the quotient
0 16 24 28 31 cannot be expressed as a 32-bit unsigned binary
integer for DIVIDE LOGICAL (DLR, DL), or a 64-bit
DLGR R1,R2 [RRE] unsigned binary integer for DIVIDE LOGICAL
(DLGR, DLG), a fixed-point-divide exception is rec-
'B987' / / / / / / / / R1 R2
ognized. This includes the case of division of zero by
0 16 24 28 31
zero.
EXCLUSIVE OR
DSG R1,D2(X2,B2) [RXY-a]
Register-and-register formats:
'E3' R1 X2 B2 DL2 DH2 '0D'
0 8 12 16 20 32 40 47 XR R1,R2 [RR]
'17' R1 R2
DSGF R1,D2(X2,B2) [RXY-a] 0 8 12 15
0 Result zero
XILF R1,I2 [RIL-a]
1 Result not zero
2 -- 'C0' R1 '7' I2
3 -- 0 8 12 16 47
Program Exceptions:
The second operand is EXCLUSIVE ORed with bits
of the first operand, and the result replaces those bits
• Access (fetch, operand 2, X, XY, XG, and XC;
of the first operand. The remainder of the first oper-
fetch and store, operand 1, XI, XIY, and XC)
and remains unchanged.
• Operation (XY and XIY, if the long-displacement
facility is not installed; XGRK and XRK, if the dis-
tinct-operands facility is not installed)
The condition code is set based on the result of the The instruction address in the current PSW is
32-bit EXCLUSIVE OR operation. increased by the length of the execute-type instruc-
tion (EXECUTE or EXECUTE RELATIVE LONG).
Resulting Condition Code: This updated address and the instruction-length
code of the execute-type instruction are used, for
0 Result is zero example, as part of the link information when the tar-
1 Result is not zero get instruction is BRANCH AND LINK. When the tar-
2 -- get instruction is a successful branching instruction,
3 -- the instruction address in the current PSW is
replaced by the branch address specified by the tar-
Program Exceptions: get instruction.
• Operation, if the extended-immediate facility is When the target instruction is in turn an execute-type
not installed) instruction, an execute exception is recognized.
Programming Note: The setting of the condition The effective address of EXECUTE must be even;
code is based only on the bits that are exclusive otherwise, a specification exception is recognized.
ORed and replaced.
When the target instruction is two or three halfwords
EXECUTE in length but can be executed without fetching its sec-
ond or third halfword, it is unpredictable whether
EX R1,D2(X2,B2) [RX-a] access exceptions are recognized for the unused
halfwords. Access exceptions are not recognized for
'44' R1 X2 B2 D2 the second-operand address when the address is
0 8 12 16 20 31 odd.
Program Exceptions:
EXTRACT ACCESS
• Access (fetch, target instruction)
• Execute EAR R1,R2 [RRE]
• Operation (EXRL, when the execute-extensions 'B24F' / / / / / / / / R1 R2
facility is not installed) 0 16 24 28 31
• Specification (EX)
2. The ORing of eight bits from the general register Program Exceptions: None.
with the designated instruction permits the indi-
rect specification of the length, index, mask,
immediate-data, register, or extended-op-code
EXTRACT CACHE ATTRIBUTE
field.
ECAG R1,R3,D2(B2) [RSY-a]
3. The fetching of the target instruction is consid- 'EB' R1 R3 B2 DL2 DH2 '4C'
ered to be an instruction fetch for purposes of
0 8 12 16 20 32 40 47
program-event recording and for purposes of
reporting access exceptions.
Information regarding the specified attribute of the
4. An access or specification exception may be storage subsystem is placed into the first-operand
caused by execute-type instructions or by the tar- location. The first operand is 64 bits.
get instruction, except that EXECUTE RELATIVE
LONG cannot cause a specification exception The second-operand address is not used to address
due to a misaligned target operand. data; rather, the rightmost 24 bits of the address are
treated as a code specifying which attribute is
5. When an interruptible instruction is made the tar- returned in general register R1. The rightmost 24 bits
get of an execute-type instruction, the program of the second-operand address are defined as fol-
normally should not designate any register lows:
updated by the interruptible instruction as the R1,
X2, or B2 register for EXECUTE or R1 register for Reserved AI LI TI
EXECUTE RELATIVE LONG. Otherwise, on 40 56 60 63
resumption of execution after an interruption, or if
the instruction is refetched without an interrup-
tion, the updated values of these registers will be Attribute Indication (AI): Bit positions 56-59 of
used in the execution of the execute-type instruc- the second-operand address contain a 4-bit
tion. Similarly, the program should normally not unsigned integer indicating the cache attribute to be
let the destination field in storage of an interrupt- extracted, as follows:
ible instruction include the location of an execute-
type instruction, since the new contents of the 0 Extract topology summary
location may be interpreted when resuming exe- 1 Extract line size of the cache, in bytes
cution. 2 Extract total size of the cache, in bytes
3 Extract set-associativity level of the cache
6. Exceptions conditions that occur during the exe-
cution of EXECUTE or EXECUTE RELATIVE 4-15 Reserved
Bits 0-39 of the second-operand address are 1. Knowledge of the cache line size is useful when
ignored. Bits 40-55 of the second-operand address determining the placement of PREFETCH DATA
are reserved and should contain zeros. If a reserved and PREFETCH DATA RELATIVE LONG instruc-
bit position in the second-operand address contains tions.
one, or if a reserved attribute indication or level indi-
cation are specified, bits 0-63 of general register R1 2. The value placed in the first-operand location is
are set to ones. model dependent and may differ significantly
from one model to another. For example, the size
The contents of general register R3 are ignored, how- of the data cache on one model may be smaller
ever the R3 field should specify register 0; otherwise, or larger than the size of the data cache on
the program may not operate compatibly in the another model. To ensure compatible operation
future. across multiple models, the program should not
rely on any particular value being returned in the
When the attribute indication is zero, a summary of first-operand location.
each level of cache is returned in general register R1.
3. When the attribute indication is 0000 binary, bit
Each summary field is eight bits, where bits 0-7 of
positions 4-5 of each 8-bit field returned in gen-
the register contain the summary for the first-level
eral register R1 contain a cache-scope indication.
cache, bits 8-15 contain the summary for the second-
level cache, and so forth. The contents of an eight-bit When the cache-scope indication is 10 binary,
summary field are as follows: the cache may be shared by more than one CPU
in the configuration. The System Library publica-
tion for the model may provide further explana-
Bits Meaning
tion of cache topology.
0-3 Reserved, stored as zeros
4-5 Cache scope, as follows: 4. When the attribute indication is 0000 binary, the
summary indications are returned in contiguous
00 Cache does not exist at this level
8-bit fields in general register R1. Thus if the pro-
01 Cache is private to the CPU gram scans the resulting summary-indication
10 Cache may be shared by multiple CPUs fields from left to right and encounters an 8-bit
11 Reserved field containing all zeros, no further meaningful
fields exist.
6-7 When bit positions 4-5 contain a nonzero value, bit
positions 6-7 contain the cache type, as follows:
In the 24-bit addressing mode, the contents of bit The contents of the registers just described are
positions 40-63 of general register R3 constitute the shown in Figure 7-251.
address of the third operand, and the contents of bit
On Completion
GR0 First Operand – Current CPU Timer
0 63
R3 Third Operand
0 63
installed)
Bits 0-31 of the current PSW are placed in bit posi-
tions 32-63 of the first operand, and bits 0-31 of the
INSERT CHARACTER
32-63 of the current PSW are placed in bit positions
32-63 of the second operand, and bits 0-31 of the • Operation (if the extended-immediate facility is
operand remain unchanged. The action associated not installed)
with the second operand is not performed if the R2 • Specification
field is zero.
Programming Notes:
Bits 0-63 of the 128-bit PSW have the following for-
mat: 1. An example of the use of the FIND LEFTMOST
ONE instruction is given in Appendix A, “Number
I E Prog E Representation and Instruction-Use Examples.”
0R000T Key 0 MW P AS CC 0000000
OX Mask A
0 1 2 5 6 7 8 12 13 14 16 18 20 24 31
2. When the R1 and R2 fields designate the same
register, the original contents of general register
B R2 are replaced by the resulting bit-position
0000000000000000000000000000000
A value, or 64 if no one bit was found.
32 33 63
3. When the R2 field designates general register
R1 + 1, the leftmost one bit (if any) of general
Condition Code: The code remains unchanged. register R2 is set to zero; if no one bit is found,
the entire register is set to zero.
Program Exceptions: None.
4. When the R2 field designates neither the even
nor the odd registers designated by the R1 field,
FIND LEFTMOST ONE then general register R2 is not modified.
Program Exceptions:
ICMH R1,M3,D2(B2) [RSY-b]
• Access (fetch, operand 2)
'EB' R1 M3 B2 DL2 DH2 '80'
• Operation (ICMY, if the long-displacement facility
0 8 12 16 20 32 40 47
is not installed)
LOAD IMMEDIATE
'A5' R1 '1' I2 rent PSW are inserted into bit positions 34 and 35
and 36-39, respectively, of general register R1. Bits
0 8 12 16 31
32 and 33 of the register are set to zeros; bits 0-31
and 40-63 are left unchanged.
IILF R1,I2 [RIL-a]
'C0' R1 '9' I2 Condition Code: The code remains unchanged.
0 8 12 16 47
Program Exceptions: None.
IILH R1,I2 [RI-a]
'A5' R1 '2' I2 LOAD
0 8 12 16 31
Register-and-register formats:
The second operand is placed in bit positions of the LGR R1,R2 [RRE]
first operand. The remainder of the first operand
'B904' / / / / / / / / R1 R2
remains unchanged.
0 16 24 28 31
LOAD IMMEDIATE
LA R1,D2(X2,B2) [RX-a]
LOAD ADDRESS EXTENDED
'41' R1 X2 B2 D2
0 8 12 16 20 31 LAE R1,D2(X2,B2) [RX-a]
'51' R1 X2 B2 D2
LAY R1,D2(X2,B2) [RXY-a]
0 8 12 16 20 31
The displacement for LA is treated as a 12-bit The address computation follows the rules for
unsigned binary integer. The displacement for LAY is address arithmetic. In the 24-bit addressing mode,
treated as a 20-bit signed binary integer. the address is placed in bit positions 40-63 of general
register R1, bits 32-39 are set to zeros, and bits 0-31
No storage references for operands take place, and remain unchanged. In the 31-bit addressing mode,
the address is not inspected for access exceptions. the address is placed in bit positions 33-63, bit 32 is
set to zero, and bits 0-31 remain unchanged. In the
• Operation (LAEY; if the general-instructions- No storage references for operands take place, and
extension facility is not installed) the address is not inspected for access exceptions.
1. When DAT is on, the different values of the Program Exceptions: None.
address-space-control bits correspond to transla-
tion modes as follows: Programming Notes:
The second operand is added to the third operand, OP represents the arithmetic or logical operation
and the sum is placed at the second-operand loca- being performed by the instruction.
tion. Subsequently, the original contents of the sec-
ond operand (prior to the addition) are placed LOAD AND ADD LOGICAL
unchanged at the first-operand location.
LAAL R1,R3,D2(B2) [RSY-a]
For LAA, the operands are treated as being 32-bit
signed binary integers. For LAAG, the operands are 'EB' R1 R3 B2 DL2 DH2 'FA'
treated as being 64-bit signed binary integers. 0 8 12 16 20 32 40 47
The fetch of the second operand for purposes of LAALG R1,R3,D2(B2) [RSY-a]
loading and the store into the second-operand loca-
'EB' R1 R3 B2 DL2 DH2 'EA'
tion appear to be a block-concurrent interlocked-
0 8 12 16 20 32 40 47
update reference as observed by other CPUs. A spe-
cific-operand-serialization operation is performed.
The second operand is added to the third operand,
The displacement is treated as a 20-bit signed binary and the sum is placed at the second-operand loca-
integer. tion. Subsequently, the original contents of the sec-
ond operand (prior to the addition) are placed
The second operand of LAA must be designated on a unchanged at the first-operand location.
word boundary. The second operand of LAAG must
be designated on a doubleword boundary. Other- For LAAL, the operands are treated as being 32-bit
wise, a specification exception is recognized. unsigned binary integers. For LAALG, the operands
are treated as being 64-bit unsigned binary integers.
Resulting Condition Code:
The fetch of the second operand for purposes of
0 Result zero; no overflow loading and the store into the second-operand loca-
1 Result less than zero; no overflow tion appear to be a block-concurrent interlocked-
2 Result greater than zero; no overflow update reference as observed by other CPUs. A spe-
3 Overflow cific-operand-serialization operation is performed.
LAN R1,R3,D2(B2) [RSY-a] Programming Note: See the programming notes for
'EB' R1 R3 B2 DL2 DH2 'F4' LOAD AND ADD.
0 8 12 16 20 32 40 47
For LAN, the operands are 32 bits. For LANG, the The EXCLUSIVE OR of the second operand and
operands are 64 bits. third operand is placed at the second-operand loca-
tion. Subsequently, the original contents of the sec-
The connective AND is applied to the operands bit by ond operand (prior to the EXCLUSIVE OR operation)
bit. The contents of a bit position in the result are set are placed unchanged at the first-operand location.
to one if the corresponding bit positions in both oper-
ands contain ones; otherwise, the result bit is set to For LAX, the operands are 32 bits. For LAXG, the
zero. operands are 64 bits.
The fetch of the second operand for purposes of The connective exclusive OR is applied to the oper-
loading and the store into the second-operand loca- ands bit by bit. The contents of a bit position in the
tion appear to be a block-concurrent interlocked- result are set to one if the bits in the corresponding
The fetch of the second operand for purposes of The connective OR is applied to the operands bit by
loading and the store into the second-operand loca- bit. The contents of a bit position in the result are set
tion appear to be a block-concurrent interlocked- to one if the corresponding bit position in one or both
update reference as observed by other CPUs. A spe- operands contains a one; otherwise, the result bit is
cific-operand-serialization operation is performed. set to zero.
The displacement is treated as a 20-bit signed binary The fetch of the second operand for purposes of
integer. loading and the store into the second-operand loca-
tion appear to be a block-concurrent interlocked-
The second operand of LAX must be designated on a update reference as observed by other CPUs. A spe-
word boundary. The second operand of LAXG must cific-operand-serialization operation is performed.
be designated on a doubleword boundary. Other-
wise, a specification exception is recognized. The displacement is treated as a 20-bit signed binary
integer.
Resulting Condition Code:
The second operand of LAO must be designated on
0 Result zero a word boundary. The second operand of LAOG
1 Result not zero must be designated on a doubleword boundary. Oth-
2 -- erwise, a specification exception is recognized.
3 --
Resulting Condition Code:
Program Exceptions:
0 Result zero
• Access (fetch and store, operand 2) 1 Result not zero
• Operation (if the interlocked-access facility is not 2 --
installed) 3 --
• Specification
Program Exceptions:
Programming Note: See the programming notes for
LOAD AND ADD. • Access (fetch and store, operand 2)
• Operation (if the interlocked-access facility is not
installed)
LOAD AND OR • Specification
LAO R1,R3,D2(B2) [RSY-a] Programming Note: See the programming notes for
'EB' R1 R3 B2 DL2 DH2 'F6' LOAD AND ADD.
0 8 12 16 20 32 40 47
0 8 12 16 20 32 40 47
LTR R1,R2 [RR]
'12' R1 R2
The OR of the second operand and third operand is
0 8 12 15
placed at the second-operand location. Subse-
quently, the original contents of the second operand
(prior to the OR operation) are placed unchanged at LTGR R1,R2 [RRE]
the first-operand location. 'B902' / / / / / / / / R1 R2
0 16 24 28 31
'B912' / / / / / / / / R1 R2
0 16 24 28 31
Register-and-register formats:
LB R1,D2(X2,B2) [RXY-a]
LTGF R1,D2(X2,B2) [RXY-a]
'E3' R1 X2 B2 DL2 DH2 '76'
'E3' R1 X2 B2 DL2 DH2 '32' 0 8 12 16 20 32 40 47
0 8 12 16 20 32 40 47
Resulting Condition Code: For LOAD BYTE (LB and LBR), the first operand is
treated as a 32-bit signed binary integer. For LOAD
0 Result zero BYTE (LGB and LGBR), the first operand is treated
1 Result less than zero as a 64-bit signed binary integer.
2 Result greater than zero
3 -- The displacement for LB and LGB is treated as a
20-bit signed binary integer.
Program Exceptions:
Condition Code: The code remains unchanged.
• Access (fetch, operand 2 of LT, LTG, and LTGF
only) Program Exceptions:
• Operation (LT and LTG, if the extended-immedi-
ate facility is not installed; LTGF, if the general- • Access (fetch, operand 2 of LB and LGB)
instructions-extension facility is not installed) • Operation (LB and LGB, if the long-displacement
facility is not installed; LBR and LGBR, if the
Programming Note: For LOAD AND TEST (LTR and extended-immediate facility is not installed)
LTGR) when the R1 and R2 fields designate the same
register, the operation is equivalent to a test without
data movement.
LOAD HALFWORD
allowing any carry into the sign-bit position and ignor-
LBH R1,D2(X2,B2) [RXY-a] ing any carry out of the sign-bit position, and condi-
tion code 3 is set. If the fixed-point-overflow mask is
'E3' R1 X2 B2 DL2 DH2 'C0' one, a program interruption for fixed-point overflow
0 8 12 16 20 32 40 47 occurs.
The second operand is sign extended and placed at Resulting Condition Code:
the first-operand location. The second operand is
one byte in length and is treated as an eight-bit 0 Result zero; no overflow
signed binary integer. 1 Result less than zero; no overflow
2 Result greater than zero; no overflow
The first operand is treated as a 32-bit signed binary 3 Overflow
integer in bits 0-31 of general register R1; bits 32-63
of the register are unchanged. Program Exceptions:
The displacement is treated as a 20-bit signed binary • Fixed-point overflow (LCR and LCGR only)
integer.
Programming Note: The operation complements all
Condition Code: The code remains unchanged. numbers. Zero remains unchanged. For LCR or
LCGR, the maximum negative 32-bit number or
Program Exceptions: 64-bit number, respectively, remains unchanged, and
an overflow condition occurs when the number is
• Access (fetch, operand 2) complemented. LCGFR complements the maximum
negative 32-bit number without recognizing overflow.
• Operation (if the high-word facility is not installed)
LOAD HALFWORD
LOAD COMPLEMENT
Register-and-register formats:
LCR R1,R2 [RR]
LHR R1,R2 [RRE]
'13' R1 R2
0 8 12 15 'B927' / / / / / / / / R1 R2
0 16 24 28 31
'E3' R1 X2 B2 DL2 DH2 '15' tents of the I2 field are a signed binary integer speci-
fying the number of halfwords that is added to the
0 8 12 16 20 32 40 47
address of the instruction to generate the address of
the second operand in storage. When DAT is on, the
second operand is accessed using the same
LOAD HALFWORD IMMEDIATE addressing-space mode as that used to access the
instruction. When DAT is off, the second operand is
LHI R1,I2 [RI-a]
accessed using a real address.
'A7' R1 '8' I2
0 8 12 16 31 Condition Code: The code remains unchanged.
• Access (fetch, operand 2) The four-byte second operand is placed in bit posi-
tions 32-63 of general register R1, and zeros are
• Operation (if the high-word facility is not installed)
placed in bit positions 0-31 of general register R1.
• Operation (if the high-word facility is not installed) • Access (fetch, operand 2 of LLGF and LLGFRL
only)
LOAD LOGICAL • Operation (LLGFRL, if the general-instructions-
extension facility is not installed)
Register-and-register format: • Specification (LLGFRL only)
Register-and-storage format:
LLCR R1,R2 [RRE]
'B994' / / / / / / / / R1 R2
LLGF R1,D2(X2,B2) [RXY-a] 0 16 24 28 31
unchanged.
Register-and-storage formats:
For LOAD LOGICAL CHARACTER (LLC, LLGC), the
second operand is in storage. For LOAD LOGICAL LLH R1,D2(X2,B2) [RXY-a]
CHARACTER (LLCR, LLGCR), the second operand 'E3' R1 X2 B2 DL2 DH2 '95'
is in bits 56-63 of general register R2. 0 8 12 16 20 32 40 47
For LOAD LOGICAL HALFWORD RELATIVE LONG, Condition Code: The code remains unchanged.
the contents of the I2 field are a signed binary integer
specifying the number of halfwords that is added to Program Exceptions:
the address of the instruction to generate the
address of the second operand in storage. When • Access (fetch, operand 2)
DAT is on, the second operand is accessed using the
same addressing-space mode as that used to • Operation (if the high-word facility is not installed)
access the instruction. When DAT is off, the second
operand is accessed using a real address. LOAD LOGICAL IMMEDIATE
Condition Code: The code remains unchanged. LLIHF R1,I2 [RIL-a]
0 8 12 16 20 32 40 47
LLIHF 0-31
LMY R1,R3,D2(B2) [RSY-a]
LLIHH 0-15
LLIHL 16-31 'EB' R1 R3 B2 DL2 DH2 '98'
0 8 12 16 20 32 40 47
LLILF 32-63
LLILH 32-47
LMG R1,R3,D2(B2) [RSY-a]
LLILL 48-63
'EB' R1 R3 B2 DL2 DH2 '04'
0 8 12 16 20 32 40 47
Condition Code: The code remains unchanged.
LLGT R1,D2(X2,B2) [RXY-a] The general registers are loaded in the ascending
'E3' R1 X2 B2 DL2 DH2 '17' order of their register numbers, starting with general
0 8 12 16 20 32 40 47
register R1 and continuing up to and including gen-
eral register R3, with general register 0 following gen-
eral register 15.
For LLGTR, bits 33-63 of general register R2, with 33
zeros appended on the left, are placed in general The displacement for LM is treated as a 12-bit
register R1. For LLGT, bits 1-31 of the four bytes at unsigned binary integer. The displacement for LMY
the second-operand location, with 33 zeros and LMG is treated as a 20-bit signed binary integer.
appended on the left, are placed in general register
R1. Condition Code: The code remains unchanged.
LOAD NEGATIVE
the number specified by R3 is less than the number
specified by R1, the register numbers wrap around LMH R1,R3,D2(B2) [RSY-a]
from 15 to 0.
'EB' R1 R3 B2 DL2 DH2 '96'
0 8 12 16 20 32 40 47
LOAD MULTIPLE DISJOINT
The high-order halves, bit positions 0-31, of the set of
LMD R1,R3,D2(B2),D4(B4) [SS-e]
general registers starting with general register R1
'EF' R1 R3 B2 D2 B4 D4 and ending with general register R3 are loaded from
0 8 12 16 20 32 36 47 storage beginning at the location designated by the
second-operand address and continuing through as
many locations as needed, that is, bit positions 0-31
Bit positions 0-31 of the set of general registers start-
are loaded from successive four-byte fields beginning
ing with general register R1 and ending with general
at the second-operand address. Bits 32-63 of the
register R3 are loaded from storage beginning at the
registers remain unchanged.
location designated by the second-operand address
and continuing through as many locations as
The general registers are loaded in the ascending
needed. Bit positions 32-63 of the same registers are
order of their register numbers, starting with general
similarly loaded from storage beginning at the loca-
register R1 and continuing up to and including gen-
tion designated by the fourth-operand address.
eral register R3, with general register 0 following gen-
eral register 15.
The general registers are loaded in the ascending
order of their register numbers, starting with general
Condition Code: The code remains unchanged.
register R1 and continuing up to and including gen-
eral register R3, with general register 0 following gen-
Program Exceptions:
eral register 15.
• Access (fetch, operand 2)
Condition Code: The code remains unchanged.
Programming Note: All combinations of register
Program Exceptions:
numbers specified by R1 and R3 are valid. When the
register numbers are equal, only four bytes are trans-
• Access (fetch, operands 2 and 4)
mitted. When the number specified by R3 is less than
the number specified by R1, the register numbers
Programming Notes:
wrap around from 15 to 0.
1. All combinations of register numbers specified by
R1 and R3 are valid. When the register numbers LOAD NEGATIVE
are equal, only eight bytes are transmitted. When
the number specified by R3 is less than the num- LNR R1,R2 [RR]
ber specified by R1, the register numbers wrap
around from 15 to 0. '11' R1 R2
0 8 12 15
2. The second-operand and fourth-operand
addresses are computed before the contents of LNGR R1,R2 [RRE]
any register are changed.
'B901' / / / / / / / / R1 R2
3. The combination of a LOAD MULTIPLE instruc- 0 16 24 28 31
tion and a LOAD MULTIPLE HIGH instruction
provides equal or better performance than a
LNGFR R1,R2 [RRE]
LOAD MULTIPLE DISJOINT instruction for the
same register range. LOAD MULTIPLE DIS- 'B911' / / / / / / / / R1 R2
JOINT is for use when the second or fourth oper- 0 16 24 28 31
second operand is placed at the first-operand loca- are 32 bits, and for LOCG and LOCGR, the first and
tion. For LOAD NEGATIVE (LNR), the second oper- second operands are 64 bits.
and and result are treated as 32-bit signed binary
integers, and, for LOAD NEGATIVE (LNGR), they are The M3 field is used as a four-bit mask. The four con-
treated as 64-bit signed binary integers. For LOAD dition codes (0, 1, 2, and 3) correspond, left to right,
NEGATIVE (LNGFR), the second operand is treated with the four bits of the mask, as follows:
as a 32-bit signed binary integer, and the result is
treated as a 64-bit signed binary integer. Mask
Condition Position
Resulting Condition Code: Code Value
0 8
0 Result zero 1 4
1 Result less than zero 2 2
2 -- 3 1
3 --
The current condition code is used to select the cor-
Program Exceptions: None. responding mask bit. If the mask bit selected by the
condition code is one, the load is performed. If the
Programming Note: The operation complements mask bit selected is zero, the load is not performed.
positive numbers; negative numbers remain
unchanged. The number zero remains unchanged. The displacement for LOC and LOCG is treated as a
20-bit signed binary integer.
LOAD ON CONDITION
For LOC and LOCG, when the condition specified by
Register-and-register formats: the M3 field is not met (that is, the load operation is
not performed), it is model dependent whether an
LOCR R1,R2,M3 [RRF-c] access exception, or PER zero-address detection is
recognized for the second operand.
'B9F2' M3 / / / / R1 R2
0 16 20 24 28 31
Condition Code: The code remains unchanged.
'EB' R1 M3 B2 DL2 DH2 'F2' 1. When the M3 field contain all zeros and no
0 8 12 16 20 32 40 47 exception condition exists, the instruction acts as
a NOP. When the M3 field contains all ones and
LOCG R1,D2(B2),M3 [RSY-b] no exception condition exists, the load operation
is always performed. However, these are not the
'EB' R1 M3 B2 DL2 DH2 'E2'
preferred means of implementing a NOP or
0 8 12 16 20 32 40 47
unconditional load, respectively.
The second operand is placed unchanged at the first- 2. For LOC and LOCG, when the condition speci-
operand location if the condition code has one of the fied by the M3 field is not met, it is model depen-
values specified by M3; otherwise, the first operand dent whether the second operand is brought into
remains unchanged. the cache.
On models that implement predictive branching, The first and second operands of LPD must be desig-
the combination of the BRANCH ON CONDI- nated on a word boundary. The first and second
TION and LOAD instructions may perform some- operands of LPDG must be designated on a double-
what better than the LOAD ON CONDITION word boundary. General register R3 must designate
instruction when the CPU is able to successfully the even numbered register. Otherwise, a specifica-
predict the branch condition. However, on mod- tion exception is recognized.
els where the CPU is not able to successfully
predict the branch condition, such as when the Resulting Condition Code:
condition is more random, the LOAD ON CONDI-
TION instruction may provide significant perfor- 0 Register pair loaded by means of interlocked
mance improvement. fetch
1 --
2 --
LOAD PAIR DISJOINT 3 Register pair not loaded by means of interlocked
fetch
LPD R3,D1(B1),D2(B2) [SSF]
'C8' R3 '4' B1 D1 B2 D2 Program Exceptions:
0 8 12 16 20 32 36 47
• Access (fetch, operands 1 and 2)
LPDG R3,D1(B1),D2(B2) [SSF] • Operation (if the interlocked-access facility is not
installed)
'C8' R3 '5' B1 D1 B2 D2 • Specification
0 8 12 16 20 32 36 47
Programming Notes:
General register R3 designates the even numbered
register of an even/odd register pair. 1. The setting of the condition code is dependent
upon storage accesses by other CPUs in the
The first operand is placed unchanged into the even- configuration.
numbered register of the third operand, and the sec-
2. When the resulting condition code is 3, the pro-
ond operand is placed unchanged into odd-num-
gram may branch back to reexecute the LOAD
bered register of the third operand. The condition
PAIR DISJOINT instruction. However, after
code indicates whether the first and second oper-
repeated unsuccessful attempts to attain an
ands appear to be fetched by means of block-concur-
interlocked fetch, the program should use an
rent interlocked fetch.
alternate means of serializing access to the stor-
age operands. It is recommended that the pro-
For LPD, the first and second operands are words in
gram reexecute the LOAD PAIR DISJOINT no
storage, and the third operand is in bits 32-63 of gen-
more than 10 times before branching to the alter-
eral registers R3 and R3 + 1; bits 0-31 of the registers
nate path.
are unchanged. For LPDG, the first and second oper-
ands are doublewords in storage, and the third oper- 3. The program should be able to accommodate a
and is in bits 0-63 of general registers R3 and R3 + 1. situation where condition code 0 is never set.
'B910' / / / / / / / / R1 R2
LPQ R1,D2(X2,B2) [RXY-a] 0 16 24 28 31
The R1 field designates an even-odd pair of general When there is an overflow, the result is obtained by
registers and must designate an even-numbered reg- allowing any carry into the sign-bit position and ignor-
ister. The second operand must be designated on a ing any carry out of the sign-bit position, and condi-
quadword boundary. Otherwise, a specification tion code 3 is set. If the fixed-point-overflow mask is
exception is recognized. one, a program interruption for fixed-point overflow
occurs.
Condition Code: The code remains unchanged.
Resulting Condition Code:
Program Exceptions:
0 Result zero; no overflow
• Access (fetch, operand 2) 1 --
• Specification 2 Result greater than zero; no overflow
3 Overflow
Programming Notes:
Program Exceptions:
1. The LOAD MULTIPLE (LM or LMG) instruction
does not necessarily provide quadword-concur- • Fixed-point overflow (LPR and LPGR only)
rent access.
Programming Note: The operation complements
2. The performance of LOAD PAIR FROM QUAD- negative numbers; positive numbers and zero remain
WORD on some models may be significantly unchanged. For LPR or LPGR, an overflow condition
slower than that of LOAD MULTIPLE (LMG). occurs when the maximum negative 32-bit number or
Unless quadword consistency is required, LMG 64-bit number, respectively, is complemented; the
should be used instead of LPQ. number remains unchanged. LPGFR complements
the maximum negative 32-bit number without recog-
nizing overflow.
LOAD POSITIVE
LPR R1,R2 [RR] LOAD REVERSED
'10' R1 R2
Register-and-register formats:
0 8 12 15
0 16 24 28 31
MONITOR CALL
'B90F' / / / / / / / / R1 R2 least significant. In the little-endian format, the
bytes are in the order least significant to most
0 16 24 28 31
significant. For example, the bytes ABCD in the
big-endian format are DCBA in the little-endian
Register-and-storage formats:
format.
LRVH R1,D2(X2,B2) [RXY-a] 2. LOAD REVERSED (LRVR) can be used with a
'E3' R1 X2 B2 DL2 DH2 '1F' two-byte value already in a register as shown in
0 8 12 16 20 32 40 47 the following example. In the example, the two
bytes of interest are in bit positions 48-63 of the
R1 register.
LRV R1,D2(X2,B2) [RXY-a]
'E3' R1 X2 B2 DL2 DH2 '1E' LRVR R1,R1
0 8 12 16 20 32 40 47 SRA R1,16
When the enhanced-monitor facility is installed, the 1. The monitor-event program interruption provides
enhanced-monitor-mask bits are in bit positions the capability for passing control to a monitoring
16-31 of control register 8, which correspond to mon- program when selected points are reached in the
itor classes 0-15 respectively. When a monitor event monitored program. This is accomplished by
occurs and either (a) the enhanced-monitor facility is implanting MONITOR CALL instructions at the
not installed, or (b) the facility is installed but the desired points in the monitored program. This
enhanced-monitor-mask bit corresponding to the function may be useful in performing various
monitor class is zero, then a monitor-event program measurement functions; specifically, tracing
interruption occurs, as described below. When a information can be generated indicating which
monitor event occurs and the enhanced-monitor- programs were executed, counting information
mask bit corresponding to the monitor class is one, a can be generated indicating how often particular
monitor-event counting operation is performed. programs were used, and timing information can
be generated indicating the amount of time a
The first-operand address is not used to address particular program required for execution.
data; instead, the address specified by the B1 and D1
fields forms the monitor code. Address computation 2. The monitor masks provide a means of disallow-
follows the rules of address arithmetic; in the 24-bit ing all monitor events or allowing monitor events
addressing mode, bits 0-39 are set to zeros; in the for all or selected classes.
31-bit addressing mode, bits 0-32 are set to zeros. 3. When used to generate a monitor-event program
interruption, the monitor code provides a means
Monitor-Event Program Interruption of associating descriptive information, in addition
When a monitor-event program interruption occurs: to the class number, with each MONITOR CALL.
• The monitor code formed by the first-operand Without the use of a base register, up to 4,096
address is placed in the doubleword at real loca- distinct monitor codes can be associated with a
tion 176. monitor event. With the base register designated
by a nonzero value in the B1 field, each monitor-
• The contents of the I2 field are stored at real loca- ing interruption can be identified by a 24-bit,
tion 149, with zeros stored at real location 148. 31-bit, or 64-bit code, depending on the address-
• Bit 9 of the program-interruption code is set to ing mode.
one.
MOVE
Monitor-Event Counting Operation
The monitor-event counting operation is described in Storage-and-storage format:
“Monitor-Event Counting” on page 5-102.
MVC D1(L,B1),D2(B2) [SS-a]
Special Conditions 'D2' L B1 D1 B2 D2
0 8 16 20 32 36 47
Bit positions 8-11 of the instruction must contain
zeros; otherwise, a specification exception is recog- Storage-and-immediate formats:
nized.
MVHHI D1(B1),I2 [SIL]
Condition Code: The code remains unchanged.
'E544' B1 D1 I2
0 16 20 32 47
MOVE INVERSE
'E54C' B1 D1 I2 installed)
0 16 20 32 47
Programming Notes:
MVGHI D1(B1),I2 [SIL] 1. Examples of the use of the MOVE instruction are
'E548' B1 D1 I2 given in Appendix A, “Number Representation
0 16 20 32 47 and Instruction-Use Examples.”
location.
The second operand is placed at the first-operand
For MOVE (MVC), each operand is processed left to location with the left-to-right sequence of the bytes
right. When the operands overlap, the result is inverted.
obtained as if the operands were processed one byte
at a time and each result byte were stored immedi- The first-operand address designates the leftmost
ately after fetching the necessary operand byte. byte of the first operand. The second-operand
address designates the rightmost byte of the second
For MOVE (MVI, MVIY), the first operand is one byte operand. Both operands have the same length.
in length, and only one byte is stored.
The result is obtained as if the second operand were
For MOVE (MVGHI, MVHHI, and MVHI,), the second processed from right to left and the first operand from
operand is treated as a 16-bit signed integer, sign- left to right. The second operand may wrap around
extended as necessary, and placed in the first-oper- from location 0 to location 224 - 1 in the 24-bit
and location. The first operand is two, four, or eight addressing mode, to location 231 - 1 in the 31-bit
bytes for MVHHI, MVHI, and MVGHI, respectively. addressing mode, or to location 264 - 1 in the 64-bit
addressing mode. The first operand may wrap
The displacements for MVGHI, MVHHI, MVHI, MVI around from location 224 - 1 to location 0 in the 24-bit
and both operands of MVC are treated as 12-bit addressing mode, from location 231 - 1 to location 0
unsigned binary integers. The displacement for MVIY in the 31-bit addressing mode, or from location 264 - 1
is treated as a 20-bit signed binary integer. to location 0 in the 64-bit addressing mode.
Condition Code: The code remains unchanged. When the operands overlap by more than one byte,
the contents of the overlapped portion of the result
Program Exceptions: field are unpredictable.
• Access (fetch, operand 2 of MVC; store, operand Condition Code: The code remains unchanged.
1, MVC, MVGHI, MVHHI, MVHI, MVI, and MVIY)
• Operation (MVIY, if the long-displacement facility Program Exceptions:
is not installed; MVGHI, MVHHI, and MVHI, if the
• Access (fetch, operand 2; store, operand 1)
MVCL R1,R2 [RR] As part of the execution of the instruction, the values
'0E' R1 R2 of the two length fields are compared for the setting
0 8 12 15 of the condition code, and a check is made for
destructive overlap of the operands. Operands are
said to overlap destructively when the first-operand
The second operand is placed at the first-operand location is used as a source after data has been
location, provided overlapping of operand locations moved into it, assuming the inspection for overlap is
would not affect the final contents of the first-operand performed by the use of logical operand addresses.
location. The remaining rightmost byte positions, if When the operands overlap destructively, no move-
any, of the first-operand location are filled with pad- ment takes place, and condition code 3 is set.
ding bytes.
Operands do not overlap destructively, and move-
The R1 and R2 fields each designate an even-odd ment is performed, if the leftmost byte of the first
pair of general registers and must designate an even- operand does not coincide with any of the second-
numbered register; otherwise, a specification excep- operand bytes participating in the operation other
tion is recognized. than the leftmost byte of the second operand. When
an operand wraps around from location 224 - 1 (or
The location of the leftmost byte of the first operand
231 - 1 or 264 - 1) to location 0, operand bytes in loca-
and second operand is designated by the contents of
tions up to and including 224 - 1 (or 231 - 1 or 264 - 1)
general registers R1 and R2, respectively. The num-
are considered to be to the left of bytes in locations
ber of bytes in the first-operand and second-operand from 0 up.
locations is specified by unsigned binary integers in
bit positions 40-63 of general registers R1 + 1 and In the 24-bit addressing mode, wraparound is from
R2 + 1, respectively. Bit positions 32-39 of general location 224 - 1 to location 0; in the 31-bit addressing
register R2 + 1 contain the padding byte. The con-
mode, wraparound is from location 231 - 1 to location
tents of bit positions 0-39 of general register R1 + 1
0; in the 64-bit addressing mode, wraparound is from
and of bit positions 0-31 of general register R2 + 1 location 264 - 1 to location 0.
are ignored.
In the access-register mode, the contents of access
The handling of the addresses in general registers R1
register R1 and access register R2 are compared. If
and R2 is dependent on the addressing mode. the R1 or R2 field is zero, 32 zeros are used rather
than the contents of access register 0. If all 32 bits of
the compared values are equal, then the destructive
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 40 63
R2 Second-Operand Address
0 63
overlap test is made. If all 32 bits of the compared mode, the leftmost bits which are not part of the
values are not equal, destructive overlap is declared address in bit positions 32-63 of general registers R1
not to exist. If, for this case, the operands actually and R2 are set to zeros, and the contents of bit posi-
overlap in real storage, it is unpredictable whether tions 0-31 remain unchanged. In any addressing
the result reflects the overlap condition. mode, the contents of bit positions 0-39 of general
registers R1 + 1 and R2 + 1 remain unchanged; and
When the length specified by bits 40-63 of general the condition code is unpredictable. If the operation is
register R1 + 1 is zero, no movement takes place, interrupted during padding, the length field in general
and condition code 0 or 1 is set to indicate the rela- register R2 + 1 is 0, the address in general register R2
tive values of the lengths. is incremented by the original length in general regis-
ter R2 + 1, and general registers R1 and R1 + 1 reflect
The execution of the instruction is interruptible. When the extent of the padding operation.
an interruption occurs, other than one that follows ter-
mination, the lengths in general registers R1 + 1 and When the first-operand location includes the location
R2 + 1 are decremented by the number of bytes of the instruction or of an execute-type instruction,
moved, and the addresses in general registers R1 the instruction may be refetched from storage and
and R2 are incremented by the same number, so that reinterpreted even in the absence of an interruption
the instruction, when reexecuted, resumes at the during execution. The exact point in the execution at
point of interruption. In the 24-bit or 31-bit addressing which such a refetch occurs is unpredictable.
used during the nonpadding part of the operation by ated with operand access are recognized. When the
some models, in certain cases, as an indication of length of an operand is zero, no access exceptions
whether the movement should be performed bypass- for that operand are recognized. Similarly, when the
ing the cache or using the cache, respectively. Thus, second operand is longer than the first operand,
a padding byte of B0 hex indicates no intention to ref- access exceptions are not recognized for the part of
erence the destination area after the move, and a the second-operand field that is in excess of the first-
padding byte of B8 hex indicates an intention to refer- operand field. For operands longer than 2K bytes,
ence the destination area. access exceptions are not recognized for locations
more than 2K bytes beyond the current location
For the nonpadding part of the operation when the being processed. Access exceptions are not recog-
padding byte is not B1 hex, accesses to the oper- nized for an operand if the R field associated with
ands for MOVE LONG may be multiple-access refer- that operand is odd. Also, when the R1 field is odd,
ences, and these accesses do not necessarily PER storage-alteration events are not recognized,
appear to occur in a left-to-right direction as and no change bits are set.
observed by other CPUs and by the channel sub-
system. When the padding byte is B1 hex, accesses Resulting Condition Code:
to the operands are single-access references, and
these accesses appear to occur in a left-to-right 0 Operand lengths equal; no destructive overlap
direction as observed by other CPUs and by the 1 First-operand length low; no destructive overlap
channel subsystem. During the nonpadding part of 2 First-operand length high; no destructive overlap
the operation, operands appear to be accessed dou- 3 No movement performed because of destructive
bleword concurrent as observed by other CPUs, pro- overlap
vided that both operands start on doubleword
boundaries, are an integral number of doublewords in Program Exceptions:
length, and do not overlap.
• Access (fetch, operand 2; store, operand 1)
As observed by other CPUs and by the channel sub- • Specification
system, that portion of the first operand which is filled
with the padding byte is not necessarily stored into in Programming Notes:
a left-to-right direction and may appear to be stored
into more than once. During the padding operation, 1. An example of the use of the MOVE LONG
stores by other CPUs or by the channel subsystem instruction is given in Appendix A, “Number Rep-
into that portion of the first operand which is filled resentation and Instruction-Use Examples.”
with the padding byte may cause unpredictable
results. 2. MOVE LONG may be used for clearing storage
by setting the padding byte to zero and the sec-
At the completion of the operation, the length in gen- ond-operand length to zero. On most models,
eral register R1 + 1 is decremented by the number of this is the fastest instruction for clearing storage
bytes stored at the first-operand location, and the areas in excess of 256 bytes. However, the
address in general register R1 is incremented by the stores associated with this clearing may be multi-
same amount. The length in general register R2 + 1 ple-access stores and should not be used to
is decremented by the number of bytes moved out of clear an area if the possibility exists that another
the second-operand location, and the address in CPU or a channel program will attempt to access
general register R2 is incremented by the same and use the area as soon as it appears to be
amount. In the 24-bit or 31-bit addressing mode, the zero. For more details, see “Storage-Operand
leftmost bits which are not part of the address in bit Consistency” on page 5-95.
positions 32-63 of general registers R1 and R2 are set 3. The program should avoid specification of a
to zeros, even when one or both of the original length length for either operand which would result in an
values are zeros or when condition code 3 is set. The addressing exception. Addressing (and also pro-
contents of bit positions 0-31 of the registers remain tection) exceptions may result in termination of
unchanged. In any addressing mode, the contents of the entire operation, not just the current unit of
bit positions 0-39 of general registers R1 + 1 and operation. The termination may be such that the
R2 + 1 remain unchanged.
MOVE LONG
the case of MOVE LONG, this includes the con- wraps around from location 224 - 1 (or 231 - 1 or
dition code and the two even-odd general-regis- 264 - 1, depending on the addressing mode) to
ter pairs, as well as the first-operand location in location 0, movement takes place in the following
main storage. The following are situations that cases:
have actually occurred on one or more models:
a. When the second operand does not wrap
a. When a protection exception occurs on a 4K- around, movement is performed if the left-
byte block of a first operand which is several most byte of the first operand coincides with
blocks in length, stores to the protected block or is to the left of the leftmost byte of the sec-
are suppressed. However, the move contin- ond operand, or if the leftmost byte of the
ues into the subsequent blocks of the first first operand is to the right of the rightmost
operand, which are not protected. Similarly, second-operand byte participating in the
an addressing exception on a block does not operation.
necessarily suppress processing of subse-
quent blocks which are available. b. When the second operand wraps around,
movement is performed if the leftmost byte of
b. Some models may update the general regis- the first operand coincides with or is to the
ters only when an external, I/O, repressible left of the leftmost byte of the second oper-
machine-check, or restart interruption and, and if the leftmost byte of the first oper-
occurs, or when a program interruption and is to the right of the rightmost second-
occurs for which it is required to nullify or operand byte participating in the operation.
suppress a unit of operation. Thus, if, after a
move into several blocks of the first operand, The rightmost second-operand byte is deter-
an addressing or protection exception mined by using the smaller of the first-operand
occurs, the general registers may remain and second-operand lengths.
unchanged. When the second-operand length is one or zero,
4. When the first-operand length is zero, the opera- destructive overlap cannot exist.
tion consists in setting the condition code and, in 7. Special precautions should be taken if MOVE
the 24-bit or 31-bit addressing mode, of setting LONG is made the target of an execute-type
the leftmost bits in bit positions 32-63 of general instruction. See the programming note concern-
registers R1 and R2 to zero. ing interruptible instructions under EXECUTE.
5. When the contents of the R1 and R2 fields are the 8. Since the execution of MOVE LONG is interrupt-
same, the contents of the designated registers ible, the instruction cannot be used for situations
are incremented or decremented only by the where the program must rely on uninterrupted
number of bytes moved, not by twice the number execution of the instruction. Similarly, the pro-
of bytes moved. Condition code 0 is set. gram should normally not let the first operand of
6. The following is a detailed description of those MOVE LONG include the location of the instruc-
cases in which movement takes place, that is, tion or of an execute-type instruction because the
where destructive overlap does not exist. new contents of the location may be interpreted
for a resumption after an interruption, or the
In the access-register mode, the contents of the instruction may be refetched without an interrup-
access registers used are called the effective tion.
space designations. When the effective space
designations are not equal, destructive overlap is 9. Further programming notes concerning interrupt-
declared not to exist and movement occurs. ible instructions are included in “Interruptible
When the effective space designations are the Instructions” in Chapter 5, “Program Execution.”
same or when not in the access-register mode, 10. In the access-register mode, access register 0
then the following cases apply. designates the primary address space regard-
less of the contents of access register 0.
The second-operand address is not used to address When the length specified in general register R1 + 1
data; instead, the rightmost eight bits of the second- is zero, no movement takes place, and condition
operand address, bits 56-63, are the padding byte. code 0 or 1 is set to indicate the relative values of the
Bits 0-55 of the second-operand address are lengths.
ignored.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 40 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 33 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R3 Third-Operand Address
0 63
R3 + 1 Third-Operand Length
0 63
Figure 7-253. Register Contents and Second-Operand Address for MOVE LONG EXTENDED
Padding byte values of B0 hex and B8 hex may be observed by other CPUs and by the channel sub-
used during the nonpadding part of the operation by system. When the padding byte is B1 hex, accesses
some models, in certain cases, as an indication of to the operands are single-access references, and
whether the movement should be performed bypass- these accesses appear to occur in a left-to-right
ing the cache or using the cache, respectively. Thus, direction as observed by other CPUs and by the
a padding byte of B0 hex indicates no intention to ref- channel subsystem. During the nonpadding part of
erence the destination area after the move, and a the operation, operands appear to be accessed dou-
padding byte of B8 hex indicates an intention to refer- bleword concurrent as observed by other CPUs, pro-
ence the destination area. vided that both operands start on doubleword
boundaries, are an integral number of doublewords in
For the nonpadding part of the operation when the length, and do not overlap.
padding byte is not B1 hex, accesses to the oper-
ands for MOVE LONG EXTENDED may be multiple- As observed by other CPUs and by the channel sub-
access references, and these accesses do not nec- system, that portion of the first operand which is filled
essarily appear to occur in a left-to-right direction as with the padding byte is not necessarily stored into in
into more than once. During the padding operation, when one or both of the original length values are
stores by other CPUs or by the channel subsystem zeros.
into that portion of the first operand which is filled
with the padding byte may cause unpredictable When the length of an operand is zero, no access
results. exceptions for that operand are recognized. Similarly,
when the third operand is longer than the first oper-
At the completion of the operation, the length in gen- and, access exceptions are not recognized for the
eral register R1 + 1 is decremented by the number of part of the third-operand field that is in excess of the
bytes stored at the first-operand location, and the first-operand field. For operands longer than 4K
address in general register R1 is incremented by the bytes, access exceptions are not recognized for loca-
same amount. The length in general register R3 + 1 tions more than 4K bytes beyond the current location
is decremented by the number of bytes moved out of being processed. Access exceptions are not recog-
the third-operand location, and the address in gen- nized for an operand if the R field associated with
eral register R3 is incremented by the same amount. that operand is odd. Also, when the R1 field is odd,
PER storage-alteration events are not recognized,
If the operation is completed because a CPU-deter- and no change bits are set.
mined number of bytes have been moved without
reaching the end of the first operand, the lengths in Resulting Condition Code:
general registers R1 + 1 and R3 + 1 are decremented
by the number of bytes moved, and the addresses in 0 All bytes moved, operand lengths equal
general registers R1 and R3 are incremented by the 1 All bytes moved, first-operand length low
same number, so that the instruction, when reexe- 2 All bytes moved, first-operand length high
cuted, resumes at the next byte to be moved. If the 3 CPU-determined number of bytes moved without
operation is completed during padding, the length reaching end of first operand
field in general register R3 + 1 is zero, the address in
general register R3 is incremented by the original Program Exceptions:
length in general register R3 + 1, and general regis-
ters R1 and R1 + 1 reflect the extent of the padding • Access (fetch, operand 3; store, operand 1)
operation. • Specification
5. When the contents of the R1 and R3 fields are the The handling of the addresses in general registers R1
same, the contents of the designated registers and R3 is dependent on the addressing mode.
are incremented or decremented only by the
number of bytes moved, not by twice the number In the 24-bit addressing mode, the contents of bit
of bytes moved. The condition code is finally set positions 40-63 of general registers R1 and R3 consti-
to 0 after possible settings to 3. tute the address, and the contents of bit positions
6. In the access-register mode, access register 0 0-39 are ignored. In the 31-bit addressing mode, the
designates the primary address space regard- contents of bit positions 33-63 of the registers consti-
less of the contents of access register 0. tute the address, and the contents of bit positions
0-32 are ignored. In the 64-bit addressing mode, the
contents of bit positions 0-63 of the registers consti-
MOVE LONG UNICODE tute the address.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 40 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Address
0 33 63
R3 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Third-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
R3 Third-Operand Address
0 63
R3 + 1 Third-Operand Length
0 63
Figure 7-254. Register Contents and Second-Operand Address for MOVE LONG UNICODE
When the operation is completed because a CPU- the third-operand bytes participating in the operation
determined number of bytes have been moved with- other than the leftmost byte of the third operand.
24
out reaching the end of the first operand, condition When an operand wraps around from location 2 - 1
31 64
code 3 is set. (or 2 - 1 or 2 - 1) to location 0, operand bytes in
24 31
locations up to and including 2 - 1 (or 2 - 1 or
64
No test is made for destructive overlap, and the 2 - 1) are considered to be to the left of bytes in
results in the first-operand location are unpredictable locations from 0 up.
when destructive overlap exists. Operands are said
to overlap destructively when the first-operand loca- In the 24-bit addressing mode, wraparound is from
24
tion is used as a source after data has been moved location 2 - 1 to location 0; in the 31-bit addressing
31
into it. mode, wraparound is from location 2 - 1 to location
0; and, in the 64-bit addressing mode, wraparound is
64
Operands do not overlap destructively if the leftmost from location 2 - 1 to location 0.
byte of the first operand does not coincide with any of
MOVE STRING
“Multiprogramming and Multiprocessing Exam- moved, condition code 1 is set. When a CPU-deter-
ples” in Appendix A, “Number Representation mined number of second-operand bytes not including
and Instruction-Use Examples.” an ending character have been moved, condition
code 3 is set. Destructive overlap is not recognized. If
the second operand is used as a source after it has
MOVE STRING been used as a destination, the results are unpredict-
able.
MVST R1,R2 [RRE]
'B255' / / / / / / / / R1 R2 When condition code 1 is set, the address of the end-
0 16 24 28 31 ing character in the first operand is placed in general
register R1, and the contents of general register R2
remain unchanged. When condition code 3 is set, the
All or part of the second operand is placed in the first- address of the next byte to be processed in the first
operand location. The operation proceeds until the and second operands is placed in general registers
end of the second operand is reached or a CPU- R1 and R2, respectively. Whenever an address is
determined number of bytes have been moved,
placed in a general register, bits 32-39 of the register,
whichever occurs first. The CPU-determined number
in the 24-bit addressing mode, or bit 32, in the 31-bit
is at least one. The result is indicated in the condition
addressing mode, are set to zeros. Bits 0-31 of the
code.
R1 and R2 registers always remain unchanged in the
24-bit or 31-bit mode.
The location of the leftmost byte of the first operand
and second operand is designated by the contents of
The amount of processing that results in the setting
general registers R1 and R2, respectively.
of condition code 3 is determined by the CPU on the
basis of improving system performance, and it may
The handling of the addresses in general registers R1 be a different amount each time the instruction is
and R2 is dependent on the addressing mode. In the executed.
24-bit addressing mode, the contents of bit positions
40-63 of general registers R1 and R2 constitute the Access exceptions for the first and second operands
address, and the contents of bit positions 0-39 are are recognized only for that portion of the operand
ignored. In the 31-bit addressing mode, the contents that is necessarily used in the operation.
of bit positions 33-63 of the registers constitute the
address, and the contents of bit positions 0-32 are The storage-operand-consistency rules are the same
ignored. In the 64-bit addressing mode, the contents as for the MOVE (MVC) instruction, except that
of bit positions 0-63 constitute the address. destructive overlap is not recognized.
The end of the second operand is indicated by an Resulting Condition Code:
ending character in the last byte position of the oper-
and. The ending character to be used to determine 0 --
the end of the second operand is specified in bit posi- 1 Entire second operand moved; general register
tions 56-63 of general register 0. Bit positions 32-55 R1 updated with address of ending character in
of general register 0 are reserved for possible future
first operand; general register R2 unchanged
extensions and must contain all zeros; otherwise, a
2 --
specification exception is recognized.
3 CPU-determined number of bytes moved; gen-
eral registers R1 and R2 updated with addresses
The operation proceeds left to right and ends as
of next bytes
soon as the second-operand ending character has
been moved or a CPU-determined number of sec-
Program Exceptions:
ond-operand bytes have been moved, whichever
occurs first. The CPU-determined number is at least
• Access (fetch, operand 2; store, operand 1)
one. When the ending character is in the first byte
• Specification
position of the second operand, only the ending char-
refetched.
1. An example of the use of the MOVE STRING
instruction is given in Appendix A, “Number Rep- Condition Code: The code remains unchanged.
resentation and Instruction-Use Examples.”
Program Exceptions:
2. When condition code 3 is set, the program can
simply branch back to the instruction to continue • Access (fetch, operand 2; fetch and store, oper-
the data movement. The program need not and 1)
determine the number of bytes that were moved.
The result is obtained as if the operands were pro- 4. The storage-operand references for MOVE WITH
cessed right to left. When necessary, the second OFFSET may be multiple-access references.
operand is considered to be extended on the left with (See “Storage-Operand Consistency” on
zeros. If the first operand is too short to contain all of page 5-95.)
the second operand, the remaining leftmost portion
of the second operand is ignored. Access exceptions MOVE ZONES
for the unused portion of the second operand may or
may not be indicated.
MVZ D1(L,B1),D2(B2) [SS-a]
MULTIPLY
rightmost four bits of each byte in the first operand
remain unchanged. M R1,D2(X2,B2) [RX-a]
'5C' R1 X2 B2 D2
Each operand is processed left to right. When the 0 8 12 16 20 31
operands overlap, the result is obtained as if the
operands were processed one byte at a time and
MFY R1,D2(X2,B2) [RXY-a]
each result byte were stored immediately after the
necessary operand byte is fetched. 'E3' R1 X2 B2 DL2 DH2 '5C'
0 8 12 16 20 32 40 47
MULTIPLY SINGLE
ignored. The product is a 128-bit unsigned binary
Register-and-register formats: integer. Bits 0-63 of the product replace the contents
of general register R1, and bits 64-127 of the product
MLR R1,R2 [RRE] replace the contents of general register R1 + 1. An
'B996' / / / / / / / / R1 R2 overflow cannot occur.
0 16 24 28 31
Condition Code: The code remains unchanged.
ML R1,D2(X2,B2) [RXY-a]
MULTIPLY SINGLE
'E3' R1 X2 B2 DL2 DH2 '96' Register-and-register formats:
0 8 12 16 20 32 40 47
MSR R1,R2 [RRE]
MLG R1,D2(X2,B2) [RXY-a] 'B252' / / / / / / / / R1 R2
0 16 24 28 31
'E3' R1 X2 B2 DL2 DH2 '86'
0 8 12 16 20 32 40 47
MSGR R1,R2 [RRE]
MS R1,D2(X2,B2) [RX-a]
For MULTIPLY LOGICAL (MLR, ML), both the multi-
plicand and the multiplier are treated as 32-bit '71' R1 X2 B2 D2
unsigned binary integers. The multiplicand is in bit 0 8 12 16 20 31
positions 32-63 of general register R1 + 1. For MUL-
TIPLY LOGICAL (MLR), the multiplier is in bit posi- MSY R1,D2(X2,B2) [RXY-a]
tions 32-63 of general register R2. The contents of
general register R1 and of bit positions 0-31 of gen- 'E3' R1 X2 B2 DL2 DH2 '51'
eral register R1 + 1 and, for MLR, of general register 0 8 12 16 20 32 40 47
integer.
MSFI R1,I2 [RIL-a]
Condition Code: The code remains unchanged.
'C2' R1 '1' I2
0 8 12 16 47 Program Exceptions:
OR IMMEDIATE
OI D1(B1),I2 [SI] • Access (fetch, operand 2, O, OY, OG, and OC;
'96' I2 B1 D1 fetch and store, operand 1, OI, OIY, and OC)
0 8 16 20 31 • Operation (OY and OIY, if the long-displacement
facility is not installed; OGRK and ORK, if the
distinct-operands facility is not installed)
OIY D1(B1),I2 [SIY]
'EB' I2 B1 DL1 DH1 '56' Programming Notes:
0 8 16 20 32 40 47
'A5' R1 'A' I2
0 8 12 16 31 PACK D1(L1,B1),D2(L2,B2) [SS-b]
'F2' L1 L2 B1 D1 B2 D2
OILL R1,I2 [RI-a] 0 8 12 16 20 32 36 47
'A5' R1 'B' I2
0 8 12 16 31 The format of the second operand is changed from
zoned to signed-packed-decimal, and the result is
placed at the first-operand location. The zoned and
The second operand is ORed with bits of the first
signed-packed-decimal formats are described in
operand, and the result replaces those bits of the first
Chapter 8, “Decimal Instructions.”
operand. The remainder of the first operand remains
unchanged.
The second operand is treated as having the zoned
format. The numeric bits of each byte are treated as
For each instruction, the bits of the first operand that
a digit. The zone bits are ignored, except the zone
are ORed with the second operand and then
bits in the rightmost byte, which are treated as a sign.
replaced are as follows:
The sign and digits are moved unchanged to the first
Bits ORed
Instruction and Replaced operand and are not checked for valid codes. The
sign is placed in the rightmost four bit positions of the
OIHF 0-31
rightmost byte of the result field, and the digits are
OIHH 0-15 placed adjacent to the sign and to each other in the
OIHL 16-31 remainder of the result field.
OILF 32-63
The result is obtained as if the operands were pro-
OILH 32-47
cessed right to left. When necessary, the second
OILL 48-63 operand is considered to be extended on the left with
zeros. If the first operand is too short to contain all
The connective OR is applied to the operands bit by digits of the second operand, the remaining leftmost
bit. The contents of a bit position in the result are set portion of the second operand is ignored. Access
to one if the corresponding bit position in one or both exceptions for the unused portion of the second
operands contains a one; otherwise, the result bit is operand may or may not be indicated.
set to zero.
When the operands overlap, the result is obtained as
Resulting Condition Code: if each result byte were stored immediately after
fetching the necessary operand bytes. Two second-
0 Result is zero operand bytes are needed for each result byte,
1 Result is not zero except for the rightmost byte of the result field, which
2 -- requires only the rightmost second-operand byte.
3 --
Condition Code: The code remains unchanged.
Program Exceptions:
Program Exceptions:
• Operation (OIHF and OILF, if the extended-
immediate facility is not installed) • Access (fetch, operand 2; store, operand 1)
PACK ASCII
decimal digits in one byte by specifying a zero in the contents of the L2 field. The second-operand
the L1 and L2 fields and the same address for length must not exceed 32 bytes (L2 must be less
both operands. than or equal to 31); otherwise, a specification excep-
tion is recognized.
3. To remove the zone bits of all bytes of a field,
including the rightmost byte, both operands When the length of the second operand is 32 bytes,
should be extended on the right with a dummy the leftmost byte is ignored.
byte, which subsequently should be ignored in
the result field. The results are unpredictable if the first and second
4. The storage-operand references for PACK may operands overlap in any way.
be multiple-access references. (See “Storage-
Operand Consistency” on page 5-95.) As observed by other CPUs and by channel pro-
grams, the first-operand location is not necessarily
stored into in any particular order.
PACK ASCII
Condition Code: The code remains unchanged.
PKA D1(B1),D2(L2,B2) [SS-f]
Program Exceptions:
'E9' L2 B1 D1 B2 D2
0 8 16 20 32 36 47
• Access (fetch, operand 2; store, operand 1)
• Operation (if the extended-translation facility 2 is
The format of the second operand is changed from not installed)
ASCII to signed-packed-decimal, and the result is • Specification
placed at the first-operand location. The signed-
packed-decimal format is described in Chapter 8, Programming Notes:
“Decimal Instructions.”
1. Although PACK ASCII is primarily intended to
The second-operand bytes are treated as containing change the format of ASCII decimal digits, its use
decimal digits, having the binary encoding is not restricted to ASCII since the leftmost four
0000-1001 for 0-9, in their rightmost four bit posi- bits of each byte are ignored.
tions. The leftmost four bit positions of a byte are
ignored. The second operand is considered to be 2. The following example illustrates the use of the
positive. instruction to pack ASCII digits:
The implied positive sign (1100 binary) and the ASDIGITS DS 0CL31
source digits are placed at the first-operand location. DC X'3132333435'
DC X'3637383930'
The source digits are moved unchanged and are not
DC X'3132333435'
checked for valid codes. The sign is placed in the
DC X'3637383930'
rightmost four bit positions of the rightmost byte of DC X'3132333435'
the result field, and the digits are placed adjacent to DC X'3637383930'
the sign and to each other in the remainder of the DC X'31'
result field. PKDIGITS DS PL16
§
The result is obtained as if the operands were pro- PKA PKDIGITS,ASDIGITS(31)
cessed right to left. When necessary, the second
operand is considered to be extended on the left with 3. The instruction can also be used to pack
zeros. EBCDIC digits, which is especially useful when
The format of the second operand is changed from • Access (fetch, operand 2; store, operand 1)
Unicode to signed-packed-decimal, and the result is • Operation (if the extended-translation facility 2 is
placed at the first-operand location. The signed- not installed)
packed-decimal format is described in Chapter 8, • Specification
“Decimal Instructions.”
Programming Notes:
The two-byte second-operand characters are treated
as Unicode Basic Latin characters containing deci- 1. The following example illustrates the use of
mal digits, having the binary encoding 0000-1001 for PACK UNICODE to pack European numbers:
0-9, in their rightmost four bit positions. The leftmost
12 bit positions of a character are ignored. The sec- UNDIGITS DS 0CL62
ond operand is considered to be positive. DC X'00310032003300340035'
DC X'00360037003800390030'
The implied positive sign (1100 binary) and the DC X'00310032003300340035'
source digits are placed at the first-operand location. DC X'00360037003800390030'
The source digits are moved unchanged and are not DC X'00310032003300340035'
checked for valid codes. The sign is placed in the DC X'00360037003800390030'
rightmost four bit positions of the rightmost byte of DC X'0031'
PKDIGITS DS PL16
the result field, and the digits are placed adjacent to
§
the sign and to each other in the remainder of the
PKU PKDIGITS,UNDIGITS(62)
result field.
2. Because the leftmost 12 bits of each character
The result is obtained as if the operands were pro-
are ignored, those Unicode decimal digits where
cessed right to left. When necessary, the second
the digit zero has four rightmost zero bits can
Symbols Used in Function Descriptions Figure 7-257. Symbol For Bit-Wise Exclusive OR
2j <16>
C <16> P <16>
Symbol Explanation
Symbol for AES-192 Symbol for AES-192
** XTS power operation over GF(2128)
Encryption Decryption
Figure 7-259. Symbol For XTS Power Operation Over
128
GF(2 ) Symbol Explanation
<n> Length of item in bytes
C Ciphertext
K <8> P <8> K <8> C <8> K Key value
P Plaintext
DEA DEA
e d Figure 7-262. Symbols for AES-192 Encryption and
Decryption
C <8> P <8>
K <32> P <16> K <32> C <16>
Symbol for DEA Symbol for DEA
Encryption Decryption
AES AES
e d
Symbol Explanation
<n> Length of item in bytes
C Ciphertext C <16> P <16>
K Key value Symbol for AES-256 Symbol for AES-256
P Plaintext Encryption Decryption
Figure 7-260. Symbols for DEA Encryption and Decryption
Symbol Explanation
<n> Length of item in bytes
K <16> P <16> K <16> C <16> C Ciphertext
K Key value
AES AES P Plaintext
e d
Figure 7-263. Symbols for AES-256 Encryption and
Decryption
C <16> P <16>
Symbol for AES-128 Symbol for AES-128 PCC-Query (Function Code 0)
Encryption Decryption The locations of the operands and addresses used
by the instruction are as shown in Figure 7-256 on
Symbol Explanation page 7-256.
<n> Length of item in bytes
C Ciphertext The parameter block used for the function has the fol-
K Key value lowing format:
P Plaintext
When a bit is one, the corresponding function is offsets 16-23 of the parameter block contain the ini-
installed; otherwise, the function is not installed. tial chaining value, and the contents of byte offsets
24-31 of the parameter block are deciphered using
PCC-Compute-Last-Block-CMAC-Using- the DEA wrapping key to obtain the 64-bit crypto-
graphic key, K. (See the section “Protection of Cryp-
DEA (Function Code 1)
tographic Key” on page 7-339 for details.)
When the ML field specifies the value of 64, the 64- Figure 7-268. Parameter Block for PCC-Compute-Last-
bit message block is exclusive-ORed with the subkey Block-CMAC-Using-TDEA-128
Kx. The result of the exclusive-OR operation is then
exclusive-ORed with initial-chaining value. The result For the PCC-Compute-Last-Block-CMAC-Using-
of the second exclusive-OR operation is then enci- TDEA-128 function, the initial-chaining value is in
phered using the 64-bit cryptographic key, K, and the byte offsets 16-23 of the parameter block and the
DEA encryption algorithm. The result of the encryp- cryptographic key is in byte offsets 24-39 of the
tion operation is the CMAC and is placed in byte off- parameter block.
sets 16-23 of the parameter block.
The parameter block used for the PCC-Compute-
When the ML field specifies a value in the range Last-Block-CMAC-Using-Encrypted-TDEA-128 func-
between 0 and 63, inclusively, the 64-bit message tion has the following format:
block is exclusive-ORed with the subkey Ky. The
result of the exclusive-OR operation is then exclu- 0 ML Reserved
sive-ORed with initial-chaining value. The result of
8 Message
the second exclusive-OR operation is then enci-
phered using the 64-bit cryptographic key, K, and the 16 Initial Chaining Value (ICV)
DEA encryption algorithm. The result of the encryp- 24 Encrypted Cryptographic Key
tion operation is the CMAC and is placed in byte off- 32 (WKd(K))
sets 16-23 of the parameter block. 40 DEA Wrapping-Key
48 Verification Pattern
PCC-Compute-Last-Block-CMAC-Using- 56 (WKdVP)
TDEA-128 (Function Code 2) 0 63
the parameter block is specified by an 8-bit unsigned bit message block is exclusive-ORed with the subkey
binary integer in the message-length (ML) field at Kx. The result of the exclusive-OR operation is then
byte offset 0. When the ML field contains a value exclusive-ORed with initial-chaining value. The result
greater than 64, the operation is completed by setting of the second exclusive-OR operation is then enci-
condition code 2. Otherwise, the ML field specifies phered using the 128-bit cryptographic key, K, and
the number of leftmost bits in byte offsets 8-15 that the TDEA-128 encryption algorithm. The result of the
constitute the message. All other bits in byte offsets encryption operation is the CMAC and is placed in
8-15 are ignored. byte offsets 16-23 of the parameter block.
When the ML field specifies a value of 0, a 64-bit When the ML field specifies a value in the range
message block is formed by setting the leftmost bit to between 0 and 63, inclusively, the 64-bit message
one and all other bits to zero; when the ML field block is exclusive-ORed with the subkey Ky. The
specifies a value of 64, the contents of byte offsets 8- result of the exclusive-OR operation is then exclu-
15 form the 64-bit message block; when the ML field sive-ORed with initial-chaining value. The result of
specifies a value of 63, the leftmost 63 bits in byte the second exclusive-OR operation is then enci-
offsets 8-15 padded with a bit of one on the right form phered using the 128-bit cryptographic key, K, and
the 64-bit message block; when the ML field speci- the TDEA-128 encryption algorithm. The result of the
fies a value in the range between 1 and 62, inclu- encryption operation is the CMAC and is placed in
sively, the specified number of leftmost bits in byte byte offsets 16-23 of the parameter block.
offsets 8-15 padded on the right with a bit of one fol-
lowed by the necessary number of bits of zero form a PCC-Compute-Last-Block-CMAC-Using-
64-bit message block.
TDEA-192 (Function Code 3)
When the ML field specifies the value of 64, a 64-bit
subkey, Kx, is derived using the 128-bit cryptographic PCC-Compute-Last-Block-CMAC-Using-
key, K. When the ML field specifies a value in the Encrypted-TDEA-192 (Function Code 11)
range between 0 and 63, inclusively, a different sub- The locations of the operands and addresses used
key, Ky, is derived using the 128-bit cryptographic key, by the instruction are as shown in Figure 7-256 on
K. The subkey generation algorithm is shown in the page 7-256.
following figure.
The parameter block used for the PCC-Compute-
Steps: Last-Block-CMAC-Using-TDEA-192 function has the
following format:
1. L = CIPHK(0)
PCC-Compute-Last-Block-CMAC-Using-
Figure 7-278. Parameter Block for PCC-Compute-Last-
AES-192 (Function Code 19) Block-CMAC-Using-Encrypted-AES-192
Explanation:
phered using the AES wrapping key to obtain the
192-bit cryptographic key, K. (See the section “Pro- CIPHK(0) Encryption of the value zero using a 192-bit key and
tection of Cryptographic Key” on page 7-339 for the AES-192 encryption algorithm.
details.) MSB(A) Most significant (leftmost) bit of A
B<<1 The bit string that results from discarding the leftmost
The description in the following paragraphs applies to bit of B and appending a '0' bit on the right.
both functions. XOR Bit-wise exclusive OR.
R64 A 128-bit value of 135.
The bit length of the message in byte offsets 8-23 of Figure 7-279. Subkey Generation Algorithm (Continued)
the parameter block is specified by an 8-bit unsigned
binary integer in the message-length (ML) field at When the ML field specifies the value of 128, the
byte offset 0. When the ML field contains a value 128-bit message block is exclusive-ORed with the
greater than 128, the operation is completed by set- subkey Kx. The result of the exclusive-OR operation
ting condition code 2. Otherwise, the ML field speci- is then exclusive-ORed with initial-chaining value.
fies the number of leftmost bits in byte offsets 8-23 The result of the second exclusive-OR operation is
that constitute the message. All other bits in byte off- then enciphered using the 192-bit cryptographic key,
sets 8-23 are ignored. K, and the AES-192 encryption algorithm. The result
of the encryption operation is the CMAC and is
When the ML field specifies a value of 0, a 128-bit placed in byte offsets 24-39 of the parameter block.
message block is formed by setting the leftmost bit to
one and all other bits to zero; when the ML field When the ML field specifies a value in the range
specifies a value of 128, the contents of byte offsets between 0 and 127, inclusively, the 128-bit message
8-23 form the 128-bit message block; when the ML block is exclusive-ORed with the subkey Ky. The
field specifies a value of 127, the leftmost 127 bits in result of the exclusive-OR operation is then exclu-
byte offsets 8-23 padded with a bit of one on the right sive-ORed with initial-chaining value. The result of
form the 128-bit message block; when the ML field the second exclusive-OR operation is then enci-
specifies a value in the range between 1 and 126, phered using the 192-bit cryptographic key, K, and
inclusively, the specified number of leftmost bits in the AES-192 encryption algorithm. The result of the
byte offsets 8-23 padded on the right with a bit of one encryption operation is the CMAC and is placed in
followed by the necessary number of bits of zero form byte offsets 24-39 of the parameter block.
a 128-bit message block.
PCC-Compute-Last-Block-CMAC-Using-
When the ML field specifies the value of 128, a 128- AES-256 (Function Code 20)
bit subkey, Kx, is derived using the 192-bit crypto-
graphic key, K. When the ML field specifies a value in
the range between 0 and 127, inclusively, a different
PCC-Compute-Last-Block-CMAC-Using-
subkey, Ky, is derived using the 192-bit cryptographic Encrypted-AES-256(Function Code 28)
key, K. The subkey generation algorithm is shown in The locations of the operands and addresses used
the following figure. by the instruction are as shown in Figure 7-256 on
page 7-256.
Steps:
1. L = CIPHK(0)
Explanation:
XTS-Parameter-Using-AES-128 function has the fol-
CIPHK(0) Encryption of the value zero using a 256-bit key and lowing format:
the AES-256 encryption algorithm.
MSB(A) Most significant (leftmost) bit of A 0
B<<1 The bit string that results from discarding the leftmost Cryptographic Key (K)
8
bit of B and appending a '0' bit on the right.
XOR Bit-wise exclusive OR. 16
Tweak Value (i)
R64 A 128-bit value of 135. 24
Figure 7-282. Subkey Generation Algorithm (Continued) 32
Block Sequential Number (j)
40
When the ML field specifies the value of 128, the 48
128-bit message block is exclusive-ORed with the Intermediate Bit Index (t)
56
subkey Kx. The result of the exclusive-OR operation
is then exclusive-ORed with initial-chaining value. 64
XTS Parameter
The result of the second exclusive-OR operation is 72
then enciphered using the 256-bit cryptographic key, 0 63
Figure 7-284. Parameter Block for PCC-Compute-XTS- Figure 7-285. Compute XTS Parameter Using AES 128
Parameter-Using-Encrypted-AES-128
The value of 2 raised to the power of j is computed as
For the PCC-Compute-XTS-Parameter-Using- follows: For each bit in j, the value of 2 raised to the
Encrypted-AES-128 function, the contents of byte power of an exponent, that is a 128-bit unsigned
offsets 16-47 of the parameter block are compared binary integer with an one in that bit and zeros in all
with the contents of the AES wrapping-key verifica- other bits, is pre-computed. To obtain the value of 2
tion-pattern register. If they mismatch, the operation raised to the power of j, the pre-computed values that
is completed by setting condition code 1. If they correspond to a bit of one in j are multiplied together.
match, the contents of byte offsets 0-15 of the The power and multiplication operations are per-
parameter block are deciphered using the AES wrap- formed over GF(2128).
ping key to obtain the 128-bit cryptographic key, K.
(See the section “Protection of Cryptographic Key”
For a nonzero j, bits in j are processed from left to
on page 7-339 for details.) The 128-bit tweak value
right, with an index of 0 for the leftmost bit and an
(i) and the 128-bit block sequential number (j) are in
index of 127 for the right most bit. The operation is
byte offsets 48-63 and 64-79, respectively, of the
ended when all bits in j have been processed (called
parameter block. When the block sequential number
normal completion) or when a CPU-determined num-
is zero, the contents of byte offsets 80-111 of the
ber of bits that is less than the total number of bits in j
parameter block are ignored, the encrypted tweak
have been processed (called partial completion). The
value is placed in byte offsets 96-111 of the parame-
CPU-determined number of bits depends on the
ter block, and the operation is completed by setting
model, and may be a different number each time the
condition code 0. When the block sequential number
instruction is executed. The CPU-determined number
is nonzero, byte offsets 80-95 of the parameter block
of bits is usually nonzero. In certain unusual situa-
contain the index of the next bit in j to be processed.
tions, this number may be zero, and condition code 3
In this case, if the contents of byte offsets 80-95 are
may be set with no progress. However, the CPU pro-
zero, then it is the initial execution of the computa-
tects against endless reoccurrence of this no-
tion, and the contents of byte offsets 96-111 of the
progress case.
parameter block are ignored; if the contents of byte
offsets 80-95 are in the range between 1 and 127,
When the operation ends due to normal completion,
inclusively, then byte offsets 96-111 contain the par-
condition code 0 is set and the intermediate bit index
tial XTS parameter computed by a previous iteration;
field (t) in the parameter block is set to 128. When the
if byte offsets 80-95 of the parameter block contain a
operation ends due to partial completion, condition
the parameter block is set to the index of the next bit nonzero, byte offsets 64-79 of the parameter block
in j to be processed. For the Compute-XTS-Parame- contain the index of the next bit in j to be processed.
ter-Using-AES-128 function, the computed XTS In this case, if the contents of byte offsets 64-79 are
parameter or partial XTS parameter is placed in byte zero, then it is the initial execution of the computa-
offsets 64-79 of the parameter block. For the Com- tion, and the contents of byte offsets 80-95 of the
pute-XTS-Parameter-Using-Encrypted-AES-128 parameter block are ignored; if the contents of byte
function, the computed XTS parameter or partial XTS offsets 64-79 are in the range between 1 and 127,
parameter is placed in byte offsets 96-111 of the inclusively, then byte offsets 80-95 contain the partial
parameter block. XTS parameter computed by a previous iteration; if
byte offsets 64-79 of the parameter block contain a
PCC-Compute-XTS-Parameter-Using- value greater than 127, the operation is completed by
setting condition code 2.
AES-256 (Function Code 52)
The parameter block used for the PCC-Compute-
PCC-Compute-XTS-Parameter-Using- XTS-Parameter-Using-Encrypted-AES-256 function
Encrypted-AES-256 (Function Code 60) has the following format:
The locations of the operands and addresses used
by the instruction are as shown in Figure 7-256 on 0 Encrypted
page 7-256. 8 Cryptographic
16 Key
The parameter block used for the PCC-Compute- (WKa(K))
24
XTS-Parameter-Using-AES-256 function has the fol-
lowing format: 32
40 AES Wrapping-Key
Verification Pattern
0 48 (WKaVP)
8 56
Cryptographic Key (K)
16 64
Tweak Value (i)
24 72
32 80
Tweak Value (i) Block Sequential Number (j)
40 88
48 96
Block Sequential Number (j) Intermediate Bit Index (t)
56 104
64 112
Intermediate Bit Index (t) XTS Parameter
72 120
80 0 63
XTS Parameter
88 Figure 7-287. Parameter Block for PCC-Compute-XTS-
0 63 Parameter-Using-Encrypted-AES-256
Figure 7-286. Parameter Block for PCC-Compute-XTS-
Parameter-Using-AES-256 For the PCC-Compute-XTS-Parameter-Using-
Encrypted-AES-256 function, the contents of byte
For the PCC-Compute-XTS-Parameter-Using-AES- offsets 32-63 of the parameter block are compared
256 function, the cryptographic key is in byte offsets with the contents of the AES wrapping-key verifica-
0-31 of the parameter block; the 128-bit tweak value tion-pattern register. If they mismatch, the operation
(i) and the 128-bit block sequential number (j) are in is completed by setting condition code 1. If they
byte offsets 32-47 and 48-63, respectively, of the match, the contents of byte offsets 0-31 of the
parameter block. When the block sequential number parameter block are deciphered using the AES wrap-
is zero, the contents of byte offsets 64-95 of the ping key to obtain the 256-bit cryptographic key, K.
parameter block are ignored, the encrypted tweak (See the section “Protection of Cryptographic Key”
value is placed in byte offsets 80-95 of the parameter on page 7-339 for details.) The 128-bit tweak value
block, and the operation is completed by setting con- (i) and the 128-bit block sequential number (j) are in
byte offsets 64-79 and 80-95, respectively, of the
9. Specification exception due to invalid operand A test bit in general register 0 specifies, when one,
length. that a lock is not to be obtained and none of the six
operations is to be performed but, instead, the valid-
10. Condition code 0 due to second-operand length ity of the function code is to be tested. This will be
originally zero.
useful if additional function codes for additional oper-
11. Access exceptions for an access to the ations are assigned in the future. This definition is
parameter block or second operand. written as if the test bit is zero except when stated
otherwise.
12.A Condition code 1 due to verification pattern
mismatch.
If compare and load is specified, the first-operand
12.B Condition code 2 due to invalid bit index or comparison value and the second operand are com-
message length pared. If they are equal, the fourth operand is placed
in the third-operand location. If the comparison indi-
13. Condition code 0 due to normal completion cates inequality, the second operand is placed in the
(second-operand length originally nonzero, but
first-operand-comparison-value location as a new
stepped to zero).
first-operand comparison value.
14. Condition code 3 due to partial completion
(second-operand length still nonzero). If compare and swap is specified, the first-operand
comparison value and the second operand are com-
Figure 7-289. Priority of Execution: PCC pared. If they are equal, the first-operand replace-
ment value is stored at the second-operand location.
Programming Note: e For the initial execution of a If the comparison indicates inequality, the second
PCC Compute-XTS-Parameter function, the contents operand is placed in the first-operand-comparison-
of the intermediate-bit-index (t) field in the parameter value location as a new first-operand comparison
block shall be set to zeros. value.
PERFORM LOCKED OPERATION If double compare and swap is specified, the first-
operand comparison value and the second operand
PLO R1,D2(B2),R3,D4(B4) [SS-e] are compared. If they are equal, the third-operand
comparison value and the fourth operand are com-
'EE' R1 R3 B2 D2 B4 D4 pared. If both comparisons indicate equality, the first-
0 8 12 16 20 32 36 47 operand and third-operand replacement values are
stored at the second-operand location and fourth-
After the lock specified in general register 1 has been operand location, respectively. If the first comparison
obtained, the operation specified by the function indicates inequality, the second operand is placed in
code in general register 0 is performed, and then the the first-operand-comparison-value location as a new
lock is released. However, as observed by other first-operand comparison value. If the first compari-
CPUs: (1) storage operands, including fields in a son indicates equality but the second does not, the
parameter list that may be used, may be fetched, and fourth operand is placed in the third-operand-com-
may be tested for store-type access exceptions if a parison-value location as a new third-operand com-
store at a tested location is possible, before the lock parison value.
For the even-numbered function codes, including 0, For function codes 1, 3, 5, 7, 9, 11, 13, 15, and
the first-operand comparison value is in general reg- 16-23, the B4 and D4 fields of the instruction specify
ister R1. For the even-numbered function codes the address of a parameter list that is used by the
beginning with 4, the first-operand replacement value instruction, and this address is not called the fourth-
is in general register R1 + 1, and R1 designates an operand address. The parameter list contains odd-
even-odd pair of registers and must designate an numbered operands, including comparison and
even-numbered register; otherwise, a specification replacement values, and addresses of even-num-
exception is recognized. For function codes 0 and 2, bered operands other than the second operand. In
R1 can be even or odd. the access-register mode, the parameter list also
contains access-list-entry tokens (ALETs) associated
For function codes 0, 2, 12, and 14, the third operand with the even-numbered-operand addresses.
is in general register R3, and R3 can be even or odd.
In the access-register mode, for function codes that
For function codes 8 and 10, the third-operand com- cause use of a parameter list containing an ALET, R3
parison value is in general register R3, the third-oper- must not be zero; otherwise, a specification excep-
and replacement value is in general register R3 + 1, tion is recognized.
and R3 designates an even-odd pair of registers and
must designate an even-numbered register; other- The rules about R1 and R3, and the use of the
wise, a specification exception is recognized. address specified by B4 and D4, are summarized in
Figure 7-292 on page 7-273.
For all function codes, the B2 and D2 fields of the
instruction specify the second-operand address. Figure 7-293 on page 7-274 shows the locations of
the operands (including operand comparison and
For function codes 0, 2, 8, 10, 12, and 14, the B4 and replacement values), operand addresses, and
D4 fields of the instruction specify the fourth-operand parameter-list address used by the instruction.
address.
Figure 7-293. Operand and Address Locations for PERFORM LOCKED OPERATION
Parameter List for Function Code 1 Function Codes 4-7 (Compare and Swap)
0 The locations of the operands and addresses used
8 Operand-1 Comparison Value by the instruction are as shown in Figure 7-293 on
page 7-274.
16
24 The parameter list used for function code 5 has the
32 following format:
40 Operand 3
Parameter List for Function Code 5
48
0
56
8 Operand-1 Comparison Value
64 Operand-4 ALET
16
72 Operand-4 Address
24 Operand-1 Replacement Value
The parameter list used for function code 3 has the
following format: The parameter list used for function code 7 has the
following format:
Parameter List for Function Code 3
Parameter List for Function Code 7
0 Operand-1 Comparison Value
0 Operand-1 Comparison Value
8 Operand-1 Comparison Value (continued)
8 Operand-1 Comparison Value (continued)
16
16 Operand-1 Replacement Value
24
24 Operand-1 Replacement Value (continued)
32 Operand 3
40 Operand 3 (continued)
The first-operand comparison value is compared to
48 the second operand. When the first-operand compar-
56 ison value is equal to the second operand, the first-
64 Operand-4 ALET operand replacement value is stored at the second-
operand location, and condition code 0 is set.
72 Operand-4 Address
When the first-operand comparison value is not Parameter List for Function Code 17
equal to the second operand, the first-operand com- 0
parison value is replaced by the second operand,
8 Operand-1 Comparison Value
and condition code 1 is set.
16
Parameter List for Function Code 21 Parameter List for Function Code 22
0 0
8 Operand-1 Comparison Value 8
16 16
24 Operand-1 Replacement Value 24
32 32
40 40
48 48
56 Operand 3 56 Operand 3
64 Operand-4 ALET 64 Operand-4 ALET
72 Operand-4 Address 72 Operand-4 Address
80 80
88 Operand 5 88 Operand 5
96 Operand-6 ALET 96 Operand-6 ALET
104 Operand-6 Address 104 Operand-6 Address
112 112
120 Operand 7 120 Operand 7
128 Operand-8 ALET 128 Operand-8 ALET
136 Operand-8 Address 136 Operand-8 Address
When the first-operand comparison value is not A nonrecoverable failure of a CPU while holding a
equal to the second operand, the first-operand com- lock may result in a machine check, entry into the
parison value is replaced by the second operand, check-stop state, or system check stop. The machine
and condition code 1 is set. check is processing backup if all operands are
undamaged or processing damage if register oper-
Locking ands are damaged. If a machine check or the check-
stop state is the result, either no storage operands
A lock is obtained at the beginning of the operation have been changed or else all storage operands that
and released at the end of the operation. The lock were due to be changed have been correctly
obtained is represented by a program lock token changed, and, in either case, the lock has been
(PLT) whose logical address is specified in general released. If the storage operands are not in either
register 1 as already described. their correct original state or their correct final state,
the result is system check stop.
A PLT is a value produced by a model-dependent
transformation of the PLT logical address. Depending Storage-Operand References
on the model, the PLT may be derived directly from
As observed by other CPUs, in all operations except Access exceptions may be recognized for parameter-
the compare-and-swap operation (which does not list locations even when the locations are not
have a fourth operand), the fourth operand is required in the operation. The locations are those
accessed while the lock is held only if a comparison beginning at offset 0 and extending up through the
of the first-operand comparison value to the second last location defined for the function code used.
operand while the lock is held has indicated equality.
In these operations, the fourth operand is accessed For the compare-and-load and compare-and-swap
before the lock is held only if a comparison of the operations, the operation is suppressed on all
first-operand comparison value to the second oper- addressing and protection exceptions.
and has indicated equality and only if, when DAT is
on, an INVALIDATE PAGE TABLE ENTRY instruction When a nonrecoverable failure of a CPU while hold-
executed by another CPU after the fetch of the sec- ing a lock results in a machine check or entry into the
ond operand will not be the cause of a page-transla- check-stop state, either no storage operands have
tion exception recognized for the fourth operand, been changed or else all storage operands that were
which it will if it sets to one the page-invalid bit in the due to be changed have been correctly changed.
page-table entry for the fourth operand when this The latter may be accomplished by repeating stores
CPU does not have a TLB entry corresponding to that were performed successfully before the failure.
that page-table entry. In the compare-and-swap-and- Therefore, there may be two single-access store ref-
double-store and compare-and-swap-and-triple-store erences (possibly the store part of an update refer-
operations, the sixth operand, and also the eighth ence and then a store reference) to the store-type
operand in the triple-store operation, are treated the operands, with the first value stored equal to the sec-
same as the fourth operand described above. The ond value stored.
reason for this specification about INVALIDATE
PAGE TABLE ENTRY is given in programming note Resulting Condition Code:
6.
When test bit is zero:
Provided that accessing of an operand is not prohib-
ited as described in the preceding paragraph, store- 0 All comparisons equal; replacement value or val-
type access exceptions may be recognized for the ues stored or loaded
operand even when a store does not occur because 1 First-operand comparison not equal; first-oper-
of the results of a comparison. A storage-alteration and comparison value replaced
PER event is recognized, and a change bit is set, 2 -- (all operations except double compare and
only if a store occurs. swap)
2 First-operand comparison equal but third-oper-
When a comparison is made between an operand and comparison not equal; third-operand com-
comparison value and an operand before the lock is parison value replaced (double compare and
obtained and indicates inequality, the lock still is swap)
obtained. The condition code is set only as a result of 3 --
a comparison made while the lock is held. When con-
dition code 1 or 2 is set, the first-operand comparison When test bit is one:
c. CPU 1 attempts to fetch operand 4. CPU 1 If CPU 1 had had a TLB entry for the page, its
does not have a TLB entry for the operand-4 PLO instruction would not have been interrupted,
page. CPU 1 signals CPU 2 that the CPU 2 and the comparison of the first-operand compari-
IPTE instruction may proceed. son value to the second operand while the lock
was held would indicate that CPU 2 had changed
d. CPU 2 completes its IPTE instruction. The the second operand. The PLO instruction would
program on CPU 2 sets a software bit in the set condition code 1. If CPU 1 did not have a TLB
page-table entry to one to indicate that the entry but IPTE could not set the page-invalid bit
page has been freemained and that, there- to one while CPU 1 was executing an instruction,
fore, a reference to the page should result in CPU 1 could successfully translate the oper-
presentation by the control program of an and-4 address and, again, discover while the
addressing exception to the program making lock was held that operand 2 had changed. The
the reference. case when operand 2 points to element X but the
e. CPU 1 attempts to do DAT for operand 4 and freemained bit for the element-X page is one is a
sees that the page-invalid bit is one. CPU 1 programming error.
performs a program interruption indicating a 7. “Summary of PERFORM LOCKED OPERATION
page-translation exception. The exception Results” on page 7-284 summarizes the results
handler sees that the software bit indicating of the operation.
freemained is one, and it presents an
Cond
Op1c=Op2 Op3c=Op4 Code Action
Function Codes 0-3 (Compare and Load)
No - 1 Op2 J Op1c
Yes - 0 Op4 J Op3
Function Codes 4-7 (Compare and Swap)
No - 1 Op2 J Op1c
Yes - 0 Op1r J Op2
Function Codes 8-11 (Double Compare and Swap)
No - 1 Op2 J Op1c
Yes No 2 Op4 J Op3c
Yes Yes 0 Op1r J Op2 Op3r J Op4
Function Codes 12-15 (Compare and Swap and Store)
No - 1 Op2 J Op1c
Yes - 0 Op1r J Op2 Op3 J Op4
Function Codes 16-19 (Compare and Swap and Double Store)
No - 1 Op2 J Op1c
Yes - 0 Op1r J Op2 Op3 J Op4
Op5 J Op6
Function Codes 20-23 (Compare and Swap and Triple Store)
No - 1 Op2 J Op1c
Yes - 0 Op1r J Op2 Op3 J Op4
Op5 J Op6
Op7 J Op8
Explanation:
- Not applicable.
OpNc Operand-N comparison value.
OpNr Operand-N replacement value.
Figure 7-294. Summary of PERFORM LOCKED OPERATION Results
A count of the number of one bits in each of the eight 1. The condition code is set based on all 64 bits of
bytes of general register R2 is placed into the corre- general register R1.
sponding byte of general register R1. Each byte of
2. The total number of one bits in a general register
general register R1 is an 8-bit binary integer in the
can be computed as shown below. In this exam-
range of 0-8.
ple, general register 15 contains the bits to be
counted; the result containing the total number of
Resulting Condition Code:
one bits in general register 15 is placed in gen-
eral register 8. (General register 9 is used as a
0 Result zero
work register and contains residual values on
1 Result not zero
completion.)
2 --
3 -- POPCNT 8,15
AHHLR 8,8,8
Program Exceptions:
For RLL, the first and third operands are in bit posi- Bits 2-7 of the I3 field (bits 18-23 of the instruction)
tions 32-63 of general registers R1 and R3, respec- contain an unsigned binary integer specifying the
tively. For RLLG, the operands are in bit positions starting bit position of the selected range of bits in the
0-63 of the registers. first operand and in the second operand after rota-
tion. Bits 2-7 of the I4 field (bits 26-31 of the instruc-
All 32 or 64 bits of the third operand participate in a tion) contain an unsigned binary integer specifying
left shift. Each bit shifted out of the leftmost bit posi- the ending bit position (inclusive) of the selected
tion of the operand reenters in the rightmost bit posi- range of bits. When the ending bit position is less
tion of the operand. than the starting bit position, the range of bits wraps
around from bit 63 to bit 0.
Condition Code: The code remains unchanged.
Bits 2-7 of the I5 field (bits 34-39 of the instruction)
Program Exceptions: None. contain an unsigned binary integer specifying the
number of bits that the second operand is rotated to
the left.
ROTATE THEN AND SELECTED
BITS Bit 0 of the I3 field (bit 16 of the instruction) contains
the test-results control (T). When the T bit is zero, the
RNSBG R1,R2,I3,I4[,I5] [RIE-f] results of the logical operation replace the selected
bits of the first operand, and the remaining bits of the
'EC' R1 R2 I3 I4 I5 '54'
first operand are unchanged. When the T bit is one,
0 8 12 16 24 32 40 47
the entire first operand is unchanged.
RNSBG R5,R7,X'80'+40,43,0
Programming Notes:
The X‘80’ represents the test-results control
1. Although the bits 2-7 of the I5 field are defined to which is added to the starting-bit position to form
contain an unsigned binary integer specifying the the I3 field.
number of bits that the second operand is rotated
to the left, a negative value may be coded which The high-level assembler (HLASM) provides
effectively specifies a rotate-right amount. alternative mnemonics for the test versions of
these instructions, as shown below:
2. The first operand is always used in its unrotated
form. When the R1 and R2 fields designate the RNSBGT R5,R7,40,43,0
same register, the contents of the register are The “T” suffix to the mnemonic indicates that the
first rotated, and then the selected bits of the specified I3 field is ORed with a value of X’80’
rotated value logically operate upon the corre- when generating the object code. The T mne-
sponding bits of the unrotated register contents. monic suffix also applies to ROSBG and
3. Examples of the use of ROTATE THEN EXCLU- RXSBG.
SIVE OR SELECTED BITS, and ROTATE THEN 6. The High Level Assembler implements various
OR SELECTED BITS are given in “Number Rep- high-word logical operations by providing
resentation and Instruction-Use Examples” on extended-mnemonics for the RNSBG, ROSBG,
page A-1. and RXSBG instructions, as shown in
4. In the assembler syntax, the I5 operand contain- Figure 7-295.
ing the rotate amount is considered to be
ROTATE THEN INSERT SELECTED The second operand is rotated left by the number of
bits specified in the fifth operand. Each bit shifted out
BITS of the leftmost bit position of the operand reenters in
the rightmost bit position of the operand. The
RISBG R1,R2,I3,I4[,I5] [RIE-f] selected bits of the rotated second operand replace
'EC' R1 R2 I3 I4 I5 '55' the contents of the corresponding bit positions of the
0 8 12 16 24 32 40 47
RISBG R5,R7,40,X'80'+43,0
Resulting Condition Code:
The X‘80’ represents the zero-remaining-bits
0 Result is zero control which is added to the ending-bit position
1 Result is less than zero to form the I4 field.
2 Result is greater than zero
alternative mnemonic for the zero-remaining-bits rotation. When the ending bit position is less than the
version of the instruction, as shown below: starting bit position, the range of selected bits wraps
around from bit 31 to bit 0. Thus, the starting and
RISBGZ R5,R7,40,43,0 ending bit positions of the selected range of bits are
The “Z” suffix to the mnemonic indicates that the always between 0 and 31.
specified I4 field is ORed with a value of X’80’
when generating the object code. For ROTATE THEN INSERT SELECTED BITS LOW,
bits 3-7 of the I3 and I4 fields, with a binary one
appended on the left of each, form six-bit unsigned
ROTATE THEN INSERT SELECTED binary integers specifying the starting and ending bit
BITS HIGH positions (inclusive) of the selected range of bits in
the first operand and in the second operand after
rotation. When the ending bit position is less than the
RISBHG R1,R2,I3,I4[,I5] [RIE-f]
starting bit position, the range of selected bits wraps
'EC' R1 R2 I3 I4 I5 '5D' around from bit 63 to bit 32. Thus, the starting and
0 8 12 16 24 32 40 47 ending bit positions of the selected range of bits are
always between 32 and 63.
ROTATE THEN INSERT SELECTED Bits 2-7 of the I5 field (bits 34-39 of the instruction)
BITS LOW contain an unsigned binary integer specifying the
number of bits that the second operand is rotated to
the left.
RISBLG R1,R2,I3,I4[,I5] [RIE-f]
'EC' R1 R2 I3 I4 I5 '51' Bit 0 of the I4 field (bit 24 of the instruction) contains
0 8 12 16 24 32 40 47 the zero-remaining-bits control (Z). The Z bit controls
how the remaining bits of the first operand are set
The 64-bit second operand is rotated left by the num- (that is, those bits, if any, that are outside of the spec-
ber of bits specified in the fifth operand. Each bit ified range). When the Z bit is zero, the remaining bits
shifted out of the leftmost bit position of the operand of the first operand are unchanged. When the Z bit is
reenters in the rightmost bit position of the operand. one, the remaining bits of the first operand are set to
The selected bits of the rotated second operand zeros.
replace the contents of the corresponding bit posi-
tions of the first operand. The immediate fields just described are as follows:
For ROTATE THEN INSERT SELECTED BITS HIGH, I3 Field I4 Field I5 Field
the first operand is in bits 0-31 of general register R1, / / /
Starting Bit
Z / /
Ending Bit
Rotate Amount
and bits 32-63 of the register are unchanged. For Position Position
ROTATE THEN INSERT SELECTED BITS LOW, the 0 3 7 0 1 3 7 0 2 7
SEARCH STRING
control which is added to the ending-bit position
1. Although the bits 2-7 of the I5 field are defined to to form the I4 field.
contain an unsigned binary integer specifying the
number of bits that the second operand is rotated The high-level assembler (HLASM) provides
to the left, a negative value may be coded which alternative mnemonics for the zero-remaining-
effectively specifies a rotate-right amount. bits versions of RISBHG and RISBLG in the form
of RISBHGZ and RISBLHZ, respectively. The “Z”
2. The first operand is always used in its unrotated suffix to the mnemonic indicates that the speci-
form. When the R1 and R2 fields designate the fied I4 field is ORed with a value of X’80’ when
same register, the value contained in the register generating the object code.
is first rotated, and then the selected bits of the
rotated value are inserted into the corresponding An equivalent to the example shown above using
bits of the unrotated register contents. the Z-suffixed mnemonic is as follows:
and R2 is dependent on the addressing mode. In the registers always remain unchanged in the 24-bit or
24-bit addressing mode, the contents of bit positions 31-bit mode.
40-63 of general registers R1 and R2 constitute the
address, and the contents of bit positions 0-39 are When the address in general register R1 equals the
ignored. In the 31-bit addressing mode, the contents address in general register R2, condition code 2 is set
of bit positions 33-63 of the registers constitute the immediately, and access exceptions are not recog-
address, and the contents of bit positions 0-32 are nized. When the address in general register R1 is
ignored. In the 64-bit addressing mode, the contents less than the address in general register R2, condi-
of bit positions 0-63 constitute the address. tion code 2 can be set only if the operand wraps
around from the top of storage to location 0.
In the access-register mode, the address space con-
taining the second operand is specified only by The amount of processing that results in the setting
means of access register R2. The contents of access of condition code 3 is determined by the CPU on the
register R1 are ignored. basis of improving system performance, and it may
be a different amount each time the instruction is
The character for which the search occurs is speci- executed.
fied in bit positions 56-63 of general register 0. Bit
positions 32-55 of general register 0 are reserved for Access exceptions for the second operand are rec-
possible future extensions and must contain all ognized only for that portion of the operand that is
zeros; otherwise, a specification exception is recog- necessarily examined.
nized.
The storage-operand-consistency rules aredescribed
The operation proceeds left to right and ends as in the section “Storage-Operand Consistency” on
soon as the specified character has been found in page 5-95.
the second operand, the address of the next second-
operand byte to be examined equals the address in Resulting Condition Code:
general register R1, or a CPU-determined number of
second-operand bytes have been examined, which- 0 --
ever occurs first. The CPU-determined number is at 1 Specified character found; general register R1
least 256. When the specified character is found, updated with address of character; general regis-
condition code 1 is set. When the address of the next ter R2 unchanged
second-operand byte to be examined equals the 2 Specified character not found in entire second
address in general register R1, condition code 2 is operand; general registers R1 and R2 unchanged
set. When a CPU-determined number of second- 3 CPU-determined number of bytes searched;
operand bytes have been examined, condition code general register R1 unchanged; general register
3 is set. When the CPU-determined number of sec- R2 updated with address of next byte
ond-operand bytes have been examined and the
address of the next second-operand byte is in gen- Program Exceptions:
eral register R1, it is unpredictable whether condition
code 2 or 3 is set. • Access (fetch, operand 2)
• Specification
When condition code 1 is set, the address of the
specified character found in the second operand is Programming Notes:
placed in general register R1, and the contents of
general register R2 remain unchanged. When condi- 1. Examples of the use of the SEARCH STRING
tion code 3 is set, the address of the next byte to be instruction are given in Appendix A, “Number
processed in the second operand is placed in gen- Representation and Instruction-Use Examples.”
eral register R2, and the contents of general register
R1 remain unchanged. When condition code 2 is set, 2. When condition code 3 is set, the program can
the contents of general registers R1 and R2 remain simply branch back to the instruction to continue
unchanged. Whenever an address is placed in a gen- the search. The program need not determine the
eral register, bits 32-39 of the register, in the 24-bit number of bytes that were searched.
addressing mode, or bit 32, in the 31-bit addressing
However, if the program branches back to the The location of the first two-byte character of the sec-
SEARCH STRING instruction following condi- ond operand is designated by the contents of general
tion code 3, specifying R2 as register 0 is imprac- register R2. When the contents of bit position 63 of
tical. This is because bits 32-55 of the register general registers R1 and R2 are identical (that is,
will have been altered to a nonzero value, thus when both addresses are even or both addresses are
resulting in a specification exception on the sub- odd), the location of the first two-byte character after
sequent execution. The search character in bit the second operand is designated by the contents of
positions 56-63 of the register also may have general register R1. When the contents of bit position
been altered. 63 of general registers R1 and R2 differ (that is, when
4. When it is desired to search a string of unknown one address is even and the other is odd), the loca-
length for its ending character, and assuming tion of the first two-byte character after the second
that the specified character in general register 0 operand is one more than the contents of general
need not be preserved, then the R1 field can des- register R1.
ignate general register 0 in order to have
SEARCH STRING use only two general registers The handling of the addresses in general registers R1
instead of three. In this case, the rightmost por- and R2 is dependent on the addressing mode. In the
tion of general register 0 containing the required 24-bit addressing mode, the contents of bit positions
zeros and the 8-bit search character is also used 40-63 of general registers R1 and R2 constitute the
to form the address of the first byte after the sec- address, and the contents of bit positions 0-39 are
ond operand. ignored. In the 31-bit addressing mode, the contents
of bit positions 33-63 of the registers constitute the
5. If the program branches back to the SEARCH address, and the contents of bit positions 0-32 are
STRING instruction when condition code 3 is set, ignored. In the 64-bit addressing mode, the contents
and a subsequent execution results in condition of bit positions 0-63 constitute the address.
code 1 or 2, general register R2 will have
changed from its initial value, even though the In the access-register mode, the address space con-
definition states that the register is unchanged taining the second operand is specified only by
when the character is found. means of access register R2. The contents of access
register R1 are ignored.
6. If the length of the string (as determined by the
difference between the addresses in general reg- The two-byte character for which the search occurs is
isters R1 and R2) is 255 characters or less, condi- specified in bit positions 48-63 of general register 0.
tion code 3 will never be set, and branching on Bit positions 32-47 of general register 0 are reserved
that condition is not necessary. However, if the for possible future extensions and must contain all
length of the string is 256 or more characters, zeros; otherwise, a specification exception is recog-
condition code 3 may be set – even if condition nized.
code 2 also applies.
Except for the case when the address in general reg-
SEARCH STRING UNICODE ister R1 equals the address in general register R2, the
operation proceeds from left to right in steps of two
SRSTU R1,R2 [RRE] bytes and ends as soon as the specified two-byte
character has been found in the second operand, the
'B9BE' / / / / / / / / R1 R2 address of the next second-operand two-byte char-
0 16 24 28 31 acter to be examined (excluding the first two-byte
character) is equal to the address of the first two-byte
The second operand is searched until a specified character after the second operand (as designated
two-byte character is found, the end of the second by general register R1), or a CPU-determined num-
operand is reached, or a CPU-determined number of ber of second-operand two-byte characters have
been examined, whichever occurs first. The CPU-
4. If the program branches back to the SEARCH PSW PSW Resulting Addressing
STRING UNICODE instruction when condition Instruction Bit 31 Bit 32 Mode
code 3 is set, and a subsequent execution
SAM24 0 0 24-bit
results in condition code 1 or 2, general register
R2 will have changed from its initial value, even SAM31 0 1 31-bit
though the definition states that the register is SAM64 1 1 64-bit
unchanged when the two-byte character is found.
The instruction address in the PSW is updated under
5. If the length of the string (as determined by the
the control of the new addressing mode, as follows.
difference between the addresses in general reg-
The value 2 (the instruction length) is added to the
isters R1 and R2) is 256 two-byte characters or
contents of bit positions 64-127 of the PSW, or the
less, condition code 3 will never be set, and
value 4 is added if the instruction is the target of
branching on that condition is not necessary.
EXECUTE, or the value 6 is added if the instruction is
However, if the length of the string is 257 or more
the target of EXECUTE RELATIVE LONG. In any
two-byte characters, condition code 3 may be
case, a carry out of bit position 0 is ignored. Then bits
set.
64-103 of the PSW are set to zeros if the new
addressing mode is the 24-bit mode, or bits 64-96
SET ACCESS are set to zeros if the new addressing mode is the
31-bit mode.
SAR R1,R2 [RRE]
The instruction is completed only if the new address-
'B24E' / / / / / / / / R1 R2
ing mode and the unupdated instruction address in
0 16 24 28 31
the PSW are a valid combination. When the new
addressing mode is to be the 24-bit mode, bits
The contents of bit positions 32-63 of general register 64-103 of the unupdated PSW must be all zeros, or,
R2 are placed in access register R1. when the new addressing mode is to be the 31-bit
mode, bits 64-96 of the unupdated PSW must be all
Condition Code: The code remains unchanged. zeros; otherwise, a specification exception is recog-
nized.
Program Exceptions: None.
Condition Code: The code remains unchanged.
SET ADDRESSING MODE Program Exceptions:
• Fixed-point overflow
• Specification
4. The base register participating in the generation 'EB' R1 R3 B2 DL2 DH2 'DD'
of the second-operand address permits indirect 0 8 12 16 20 32 40 47
SHIFT LEFT DOUBLE LOGICAL For SLA, the 31-bit numeric part of the signed first
operand is shifted left the number of bits specified by
SLDL R1,D2(B2) [RS-a]
the second-operand address, and the result is placed
'8D' R1 / / / / B2 D2 at the first-operand location. Bits 0-31 of general reg-
0 8 12 16 20 31 ister R1 remain unchanged.
data; its rightmost six bits indicate the number of bit numbers with a value greater than or equal to
positions to be shifted. The remainder of the address -230 and less than 230, a left shift of one bit posi-
is ignored. tion is equivalent to multiplying the number by 2.
For SHIFT LEFT SINGLE (SLAG), the compara-
For SLA, the first operand is treated as a 32-bit ble values are -262 and 262.
signed binary integer in bit positions 32-63 of general
register R1. The sign of the first operand remains 3. For SHIFT LEFT SINGLE (SLA and SLAK), shift
unchanged. All 31 numeric bits of the operand partic- amounts from 31 to 63 cause the entire numeric
ipate in the left shift. part to be shifted out of the register, leaving a
result of the maximum negative number or zero,
For SLAK, the first and third operands are treated as depending on whether or not the initial contents
32-bit signed binary integers in bit positions 32-63 of were negative. For SHIFT LEFT SINGLE
general registers R1 and R3, respectively. The sign of (SLAG), a shift amount of 63 causes the same
the first operand is set equal to the sign of the third effect.
operand. All 31 numeric bits of the third operand par-
ticipate in the left shift. SHIFT LEFT SINGLE LOGICAL
For SLAG, the first and third operands are treated as SLL R1,D2(B2) [RS-a]
64-bit signed binary integers in bit positions 0-63 of
general registers R1 and R3, respectively. The sign of '89' R1 / / / / B2 D2
the first operand is set equal to the sign of the third 0 8 12 16 20 31
If one or more bits unlike the sign bit are shifted out SLLG R1,R3,D2(B2) [RSY-a]
of bit position 33, for SLA or SLAK, or 1, for SLAG, an 'EB' R1 R3 B2 DL2 DH2 '0D'
overflow occurs, and condition code 3 is set. If the 0 8 12 16 20 32 40 47
fixed-point-overflow mask bit is one, a program inter-
ruption for fixed-point overflow occurs.
For SLL, the 32-bit first operand is shifted left the
Resulting Condition Code: number of bits specified by the second-operand
address, and the result is placed at the first-operand
0 Result zero; no overflow location. Bits 0-31 of general register R1 remain
1 Result less than zero; no overflow unchanged.
2 Result greater than zero; no overflow
3 Overflow For SLLK, the 32-bit third operand is shifted left the
number of bits specified by the second-operand
Program Exceptions: address, and the result is placed at the first-operand
location. Bits 0-31 of general register R1 remain
• Fixed-point overflow unchanged. Except for when the R1 and R3 fields
• Operation (SLAK, if the distinct-operands facility designate the same register, the third operand
is not installed) remains unchanged in general register R3.
Programming Notes: For SLLG, the 64-bit third operand is shifted left the
number of bits specified by the second-operand
1. An example of the use of the SHIFT LEFT SIN- address, and the result is placed at the first-operand
GLE instruction is given in Appendix A, “Number location. Except for when the R1 and R3 fields desig-
Representation and Instruction-Use Examples.” nate the same register, the third operand remains
unchanged in general register R3.
For SLLG, the first and third operands are in bit posi- 0 Result zero
tions 0-63 of general registers R1 and R3, respec- 1 Result less than zero
tively. All 64 bits of the third operand participate in the 2 Result greater than zero
left shift. 3 --
For SLL, SLLG, or SLLK, zeros are supplied to the Program Exceptions:
vacated bit positions on the right.
• Specification
Condition Code: The code remains unchanged.
For SHIFT RIGHT SINGLE (SRAG), the 63-bit 1. A right shift of one bit position is equivalent to
numeric part of the signed third operand is shifted division by 2 with rounding downward. When an
right the number of bits specified by the second-oper- even number is shifted right one position, the
and address, and the result, with the sign bit of the result is equivalent to dividing the number by 2.
third operand appended on its left, is placed at the When an odd number is shifted right one posi-
first-operand location. Except for when the R1 and R3 tion, the result is equivalent to dividing the next
fields designate the same register, the third operand lower number by 2. For example, +5 shifted right
remains unchanged in general register R3. by one bit position yields +2, whereas -5 yields
-3.
The second-operand address is not used to address
2. For SRA and SRAK, shift amounts from 31 to 63
data; its rightmost six bits indicate the number of bit
cause the entire numeric part to be shifted out of
positions to be shifted. The remainder of the address
the register, leaving a result of -1 or zero,
is ignored.
depending on whether or not the initial contents
were negative. For SHIFT RIGHT SINGLE
ST R1,D2(X2,B2) [RX-a]
For SRL, the 32-bit first operand is shifted right the '50' R1 X2 B2 D2
number of bits specified by the second-operand 0 8 12 16 20 31
address, and the result is placed at the first-operand
location. Bits 0-31 of general register R1 remain STY R1,D2(X2,B2) [RXY-a]
unchanged.
'E3' R1 X2 B2 DL2 DH2 '50'
For SRLK, the 32-bit third operand is shifted right the 0 8 12 16 20 32 40 47
For SRLG, the 64-bit third operand is shifted right the STORE RELATIVE LONG
number of bits specified by the second-operand
address, and the result is placed at the first-operand STRL R1,RI2 [RIL-b]
location. Except for when the R1 and R3 fields desig- 'C4' R1 'F' RI2
nate the same register, the third operand remains 0 8 12 16 47
unchanged in general register R3.
STGRL R1,RI2 [RIL-b]
The second-operand address is not used to address
data; its rightmost six bits indicate the number of bit 'C4' R1 'B' RI2
positions to be shifted. The remainder of the address 0 8 12 16 47
is ignored.
The first operand is placed unchanged at the second-
For SRL, the first operand is in bit positions 32-63 of operand location.
general register R1. All 32 bits of the operand partici-
pate in the right shift. For STORE (ST, STY) and STORE RELATIVE LONG
(STRL), the operands are 32 bits, and, for STORE
For SRLK, the first and third operands are in bit posi- (STG) and STORE RELATIVE LONG (STGRL), the
tions 32-63 of general registers R1 and R3, respec- operands are 64 bits.
tively. All 32 bits of the third operand participate in the
right shift.
unsigned binary integer. The displacement for STY 'EB' R1 R3 B2 DL2 DH2 '9B'
and STG is treated as a 20-bit signed binary integer.
0 8 12 16 20 32 40 47
Condition Code: The code remains unchanged. The contents of the M3 field are used as a mask.
These four bits, left to right, correspond one for one
Program Exceptions: with four bytes, left to right, of general register R1. For
STORE CHARACTERS UNDER MASK (STCM,
• Access (store, operand 2) STCMY), the four bytes to which the mask bits corre-
• Operation (STCY, if the long-displacement facility spond are in bit positions 32-63 of general register
is not installed) R1. For STORE CHARACTERS UNDER MASK
(STCMH), the four bytes are in the high-order half, bit
positions 0-31, of the register. The bytes correspond-
STORE CHARACTER HIGH ing to ones in the mask are placed in the same order
at successive and contiguous storage locations
STCH R1,D2(X2,B2) [RXY-a] beginning at the second-operand address. When the
'E3' R1 X2 B2 DL2 DH2 'C3' mask is not zero, the length of the second operand is
0 8 12 16 20 32 40 47 equal to the number of ones in the mask. The con-
tents of the general register remain unchanged.
Bits 24-31 of general register R1 are placed When the mask is not zero, exceptions associated
unchanged at the second-operand location. The sec- with storage-operand accesses are recognized only
ond operand is one byte in length. for the number of bytes specified by the mask.
The displacement is treated as a 20-bit signed binary When the mask is zero, the single byte designated by
integer. the second-operand address remains unchanged;
however, on some models, the contents may be
Condition Code: The code remains unchanged. fetched and subsequently stored back unchanged at
the same storage location. This update appears to be
Program Exceptions: an interlocked-update reference as observed by
other CPUs.
• Access (store, operand 2)
• Operation (if the high-word facility is not installed) The displacement for STCM is treated as a 12-bit
unsigned binary integer. The displacement for
STORE CHARACTERS UNDER STCMY and STCMH is treated as a 20-bit signed
binary integer.
MASK
Condition Code: The code remains unchanged.
STCM R1,M3,D2(B2) [RS-b]
'BE' R1 M3 B2 D2 Program Exceptions:
0 8 12 16 20 31
• Access (store, operand 2)
• Operation (STCMY, if the long-displacement
STCMY R1,M3,D2(B2) [RSY-b]
facility is not installed)
'EB' R1 M3 B2 DL2 DH2 '2D'
0 8 12 16 20 32 40 47 Programming Notes:
in modifying the address in a format-0 CCW. clock is in the error state or the not-operational state.
3. STORE CHARACTERS UNDER MASK (STCM, The quality of the clock value stored by the instruc-
STCMY) with a mask of 1111, 0011, or 0001 tion is indicated by the resultant condition-code set-
binary performs the same function as STORE ting.
(ST), STORE HALFWORD, or STORE CHARAC-
TER, respectively. For STORE CLOCK, a serialization function is per-
4. Using STORE CHARACTERS UNDER MASK formed before the value of the clock is fetched and
with a zero mask may cause any of the following again after the value is placed in storage.
to occur for the byte designated by the second-
operand address: a PER storage-alteration event Resulting Condition Code:
may be recognized; access exceptions may be
recognized; and, provided no access exceptions 0 Clock in set state
exist, the change bit may be set to one. Because 1 Clock in not-set state
the contents of storage remain unchanged, the 2 Clock in error state
change bit may or may not be one when a PER 3 Clock in stopped state or not-operational state
storage-alteration event is recognized.
Program Exceptions:
5. On certain models, STORE CHARACTERS
UNDER MASK with mask field that specifies dis- • Access (store, operand 2)
contiguous bytes may perform slower than when • Operation (STCKF, if the store-clock-fast facility
the mask specifies contiguous bytes. is not installed)
Programming Notes:
STORE CLOCK
1. Bit position 31 of the clock is incremented every
STCK D2(B2) [S] 1.048576 seconds; hence, for timing applications
'B205' B2 D2 involving human responses, the leftmost clock
0 16 20 31 word may provide sufficient resolution.
5. Two executions of STORE CLOCK FAST, or an The quality of the clock value stored by the instruc-
execution of STORE CLOCK FAST and STORE tion is indicated by the resultant condition-code set-
CLOCK, either on the same or different CPUs, ting.
do not necessarily return different values of the
clock if the clock is running. Thus, the values A serialization function is performed before the value
returned by STORE CLOCK FAST do not neces- of the clock is fetched and again after the value is
sarily indicate the correct sequence of execution placed in storage.
of the instruction by one or more CPUs.
Program Exceptions:
STORE CLOCK EXTENDED
• Access (store, operand 2)
STCKE D2(B2) [S]
1. Condition code 0 normally indicates that the
'B278' B2 D2 clock has been set by the control program.
0 16 20 31 Accordingly, the value may be used in elapsed-
time measurements and as a valid time-of-day
The current value of bits 0-103 of the TOD clock is and calendar indication. Condition code 1 indi-
stored in byte positions 1-13 of the sixteen-byte field cates that the clock value is the elapsed time
designated by the second-operand address, pro- since the power for the clock was turned on. In
vided the clock is in the set, stopped, or not-set state. this case, the value may be used in elapsed-time
Zeros are stored in byte position 0. The TOD pro- measurements but is not a valid time-of-day indi-
grammable field, bits 16-31 of the TOD programma- cation. Condition codes 2 and 3 mean that the
ble register, is stored in byte positions 14 and 15. value provided by STORE CLOCK EXTENDED
cannot be used for time measurement or indica-
The operand just described has the following format: tion.
When the size of the second operand is large enough 2. When condition code 0 is set, bits 56-63 of gen-
to contain all of the facility bits assigned for a model, eral register 0 are updated to contain a value that
then the complete facility list is stored in the second is one less than the number of doublewords
operand location, bits 56-63 of general register 0 are stored. If the program chooses to ignore the
updated to contain one less than the number of dou- results in general register 0, then it should
blewords needed to contain all of the facility bits ensure that the entire second operand in storage
assigned for the model, and condition code 0 is set. is set to zero prior to executing STORE FACILITY
LIST EXTENDED.
When the size of the second operand is not large
enough to contain all of the facility bits assigned for a STORE HALFWORD
model, then only the number of doublewords speci-
fied by the second-operand size are stored, bits 56- STH R1,D2(X2,B2) [RX-a]
63 of general register 0 are updated to contain one
less than the number of doublewords needed to con- '40' R1 X2 B2 D2
tain all of the facility bits assigned for the model, and 0 8 12 16 20 31
Special Conditions
Program Exceptions:
The first operand is placed unchanged at the second-
Access (store, operand 2) operand location. The first operand is in bits 0-31 of
general register R1, and the second operand is 32
Operation (STHY if the long-displacement facility is bits in storage.
not installed; STHRL, if the general-instructions-
extension facility is not installed.) The displacement is treated as a 20-bit signed binary
integer.
Programming Notes:
Condition Code: The code remains unchanged.
1. For STORE HALFWORD RELATIVE LONG, the
second operand is necessarily aligned on an Program Exceptions:
integral boundary corresponding to the operand’s
size. • Access (store, operand 2)
• Operation (if the high-word facility is not installed)
2. When STORE HALFWORD RELATIVE LONG is
the target of an execute-type instruction, the sec-
ond-operand address is relative to the target
STORE MULTIPLE
address.
STM R1,R3,D2(B2) [RS-a]
3. Significant delay may be incurred if the program '90' R1 R3 B2 D2
stores into the same cache line as that contain-
0 8 12 16 20 31
ing the storing instruction. The EXTRACT
CACHE ATTRIBUTE instruction may be used to
determine the cache-line size. STMY R1,R3,D2(B2) [RSY-a]
'EB' R1 R3 B2 DL2 DH2 '90'
Bits 16-31 of general register R1 are placed The contents of bit positions of the set of general reg-
unchanged at the second-operand location. The sec- isters starting with general register R1 and ending
ond operand is two bytes in length. with general register R3 are placed in the storage
area beginning at the location designated by the sec-
The displacement is treated as a 20-bit signed binary ond-operand address and continuing through as
integer. many locations as needed.
Condition Code: The code remains unchanged. For STORE MULTIPLE (STM, STMY), the contents
of bit positions 32-63 of the general registers are
STORE ON CONDITION
second-operand address. For STORE MULTIPLE
(STMG), the contents of bit positions 0-63 of the gen- Program Exceptions:
eral registers are stored in successive eight-byte
fields beginning at the second-operand address. • Access (store, operand 2)
The general registers are stored in the ascending Programming Note: All combinations of register
order of their register numbers, starting with general numbers specified by R1 and R3 are valid. When the
register R1 and continuing up to and including gen- register numbers are equal, only four bytes are trans-
eral register R3, with general register 0 following gen- mitted. When the number specified by R3 is less than
eral register 15. the number specified by R1, the register numbers
wrap around from 15 to 0.
The displacement for STM is treated as a 12-bit
unsigned binary integer. The displacement for STMY
and STMG is treated as a 20-bit signed binary inte- STORE ON CONDITION
ger.
STOC R1,D2(B2),M3 [RSY-b]
Condition Code: The code remains unchanged. 'EB' R1 M3 B2 DL2 DH2 'F3'
0 8 12 16 20 32 40 47
Program Exceptions:
STOCG R1,D2(B2),M3 [RSY-b]
• Access (store, operand 2)
• Operation (STMY, if the long-displacement facil- 'EB' R1 M3 B2 DL2 DH2 'E3'
ity is not installed) 0 8 12 16 20 32 40 47
Programming Note: An example of the use of the The first operand is placed unchanged at the second-
STORE MULTIPLE instruction is given in operand location if the condition code has one of the
Appendix A, “Number Representation and Instruc- values specified by M3; otherwise, the second oper-
tion-Use Examples.” and remains unchanged.
STORE MULTIPLE HIGH For STOC, the first and second operands are 32 bits,
and for STOCG, the first and second operands are
STMH R1,R3,D2(B2) [RSY-a] 64 bits.
'EB' R1 R3 B2 DL2 DH2 '26' The M3 field is used as a four-bit mask. The four con-
0 8 12 16 20 32 40 47 dition codes (0, 1, 2, and 3) correspond, left to right,
with the four bits of the mask, as follows:
The contents of the high-order halves, bit positions
0-31, of the set of general registers starting with gen- Mask
eral register R1 and ending with general register R3 Condition Position
Code Value
are placed in the storage area beginning at the loca-
tion designated by the second-operand address and 0 8
continuing through as many locations as needed, 1 4
that is, the contents of bit positions 0-31 are stored in 2 2
successive four-byte fields beginning at the second- 3 1
operand address. Bits 32-63 of the registers are
ignored.
The current condition code is used to select the cor-
responding mask bit. If the mask bit selected by the
The general registers are stored in the ascending
condition code is one, the store is performed. If the
order of their register numbers, starting with general
mask bit selected is zero, the store is not performed.
register R1 and continuing up to and including gen-
eral register R3, with general register 0 following gen- The displacement is treated as a 20-bit signed binary
eral register 15. integer.
3. STORE ON CONDITION provides a function 1. The STORE MULTIPLE (STM or STMG) instruc-
similar to that of a separate BRANCH ON CON- tion does not necessarily provide quadword-con-
DITION instruction followed by a STORE instruc- current access.
tion, except that STORE ON CONDITION does
2. The performance of STORE PAIR TO QUAD-
not provide an index register. For example, the
WORD on some models may be significantly
following two instruction sequences are equiva-
slower than that of STORE MULTIPLE (STMG).
lent.
Unless quadword consistency is required, STMG
should be used instead of STPQ.
STOCG 15,256(7),8 BC 7,SKIP
STG 15,256(0,7)
SKIP DS 0H STORE REVERSED
On models that implement predictive branching, STRVH R1,D2(X2,B2) [RXY-a]
the combination of the BRANCH ON CONDI-
TION and STORE instructions may perform 'E3' R1 X2 B2 DL2 DH2 '3F'
somewhat better than the STORE ON CONDI- 0 8 12 16 20 32 40 47
SUBTRACT
'E3' R1 X2 B2 DL2 DH2 '2F' 'B919' / / / / / / / / R1 R2
0 8 12 16 20 32 40 47 0 16 24 28 31
format.
For S, SG, SGF, SGFR, SGR, SR, and SY, the sec-
2. The storage-operand references of STORE
ond operand is subtracted from the first operand, and
REVERSED may be multiple-access references.
the difference is placed at the first-operand location.
(See “Storage-Operand Consistency” on
For SGRK and SRK, the third operand is subtracted
page 5-95.)
from the second operand, and the difference is
placed at the first-operand location.
SUBTRACT
For S, SR, SRK, and SY, the operands and the differ-
Register-and-register formats: ence are treated as 32-bit signed binary integers. For
SG, SGR, and SGRK, they are treated as 64-bit
SR R1,R2 [RR] signed binary integers. For SGFR and SGF, the sec-
'1B' R1 R2 ond operand is treated as a 32-bit signed binary inte-
0 8 12 15
ger, and the first operand and the difference are
treated as 64-bit signed binary integers.
SGR R1,R2 [RRE]
When there is an overflow, the result is obtained by
'B909' / / / / / / / / R1 R2 allowing any carry into the sign-bit position and ignor-
0 16 24 28 31 ing any carry out of the sign-bit position, and condi-
tion code 3 is set. If the fixed-point-overflow mask is
SH R1,D2(X2,B2) [RX-a]
'4B' R1 X2 B2 D2 SHHLR R1,R2,R3 [RRF-a]
0 8 12 16 20 31 'B9D9' R3 / / / / R1 R2
0 16 20 24 28 31
3. A zero difference is always accompanied by a • Operation (if the high-word facility is not installed)
carry out of bit position 0 for 64-bit results or bit
position 32 for 32-bit results, and, therefore, no SUBTRACT LOGICAL WITH
borrow.
BORROW
4. The condition-code setting for SUBTRACT LOG-
ICAL can also be interpreted as indicating the Register-and-register formats:
presence or absence of a carry, as follows:
SLBR R1,R2 [RRE]
1 Result not zero; no carry 'B999' / / / / / / / / R1 R2
2 Result zero; carry 0 16 24 28 31
The second operand and the borrow are subtracted SUPERVISOR CALL
from the first operand, and the difference is placed at
the first-operand location. For SUBTRACT LOGICAL SVC I [I]
WITH BORROW (SLBR, SLB), the operands, the
'0A' I
borrow, and the difference are treated as 32-bit
0 8 15
unsigned binary integers. For SUBTRACT LOGICAL
WITH BORROW (SLBGR, SLBG), they are treated
as 64-bit unsigned binary integers. The instruction causes a supervisor-call interruption,
with the I field of the instruction providing the right-
Resulting Condition Code: most byte of the interruption code.
0 Result zero; borrow Bits 8-15 of the instruction, with eight zeros
1 Result not zero; borrow appended on the left, are placed in the supervisor-
2 Result zero; no borrow call interruption code that is stored in the course of
3 Result not zero; no borrow the interruption. See “Supervisor-Call Interruption”
on page 6-50.
Program Exceptions:
A serialization and checkpoint-synchronization func-
• Access (fetch, operand 2 of SLB and SLBG only) tion is performed.
The byte in storage is set to all ones as it is fetched TMHH R1,I2 [RI-a]
for the testing of bit 0. This update appears to be an
'A7' R1 '2' I2
interlocked-update reference as observed by other
0 8 12 16 31
CPUs.
1. TEST AND SET may be used for controlled shar- A mask is used to select bits of the first operand, and
ing of a common storage area by programs oper- the result is indicated in the condition code.
ating on different CPUs. This instruction is
TRANSLATE
and TMLL are new mnemonics for, the ESA/390
instructions TEST UNDER MASK HIGH (TMH) and 0 Selected bits all zeros; or mask bits all zeros
TEST UNDER MASK LOW (TML), respectively. 1 Selected bits mixed zeros and ones (TM and
TMY only)
In TEST UNDER MASK (TM, TMY), the byte of 1 Selected bits mixed zeros and ones, and leftmost
immediate data, I2, is used as an eight-bit mask. The is zero (TMHH, TMHL, TMLH, TMLL)
bits of the mask are made to correspond one for one 2 -- (TM and TMY only)
with the bits of the byte in storage designated by the 2 Selected bits mixed zeros and ones, and leftmost
first-operand address. is one (TMHH, TMHL, TMLH, TMLL)
3 Selected bits all ones
A mask bit of one indicates that the storage bit is to
be tested. When the mask bit is zero, the storage bit Program Exceptions:
is ignored. When all storage bits thus selected are
zero, condition code 0 is set. Condition code 0 is also • Access (fetch, operand 1, TM and TMY only)
set when the mask is all zeros. When the selected • Operation (TMY, if the long-displacement facility
bits are all ones, condition code 3 is set; otherwise, is not installed)
condition code 1 is set.
Programming Notes:
Access exceptions associated with the storage oper-
and are recognized for one byte even when the mask 1. An example of the use of the TEST UNDER
is all zeros. MASK (TM) instruction is given in Appendix A,
“Number Representation and Instruction-Use
In TEST UNDER MASK (TMHH, TMHL, TMLH, Examples.”
TMLL), The contents of the I2 field are used as a
16-bit mask. For each instruction, the bits of the 2. When the mask for TMHH, TMHL, TMLH, or
mask are made to correspond one for one with 16 TMLL selects exactly two bits, the two selected
bits of the first operand as follows: bits effectively are loaded into the condition code.
A mask bit of one indicates that the first-operand bit The bytes of the first operand are used as eight-bit
is to be tested. When the mask bit is zero, the first- arguments to reference a list designated by the sec-
operand bit is ignored. When all first-operand bits ond-operand address. Each function byte selected
thus selected are zero, condition code 0 is set. Con- from the list replaces the corresponding argument in
dition code 0 is also set when the mask is all zeros. the first operand.
When the selected bits are mixed zeros and ones,
condition code 1 is set if the leftmost selected bit is The L field specifies the length of only the first oper-
zero, or condition code 2 is set if the leftmost and.
selected bit is one. When the selected bits are all
ones, condition code 3 is set. The bytes of the first operand are selected one by
one for translation, proceeding left to right. Each
The displacement for TM is treated as a 12-bit argument byte is added to the initial second-operand
unsigned binary integer. The displacement for TMY address. The addition is performed following the
is treated as a 20-bit signed binary integer. rules for address arithmetic, with the argument byte
treated as an eight-bit unsigned binary integer and
extended with zeros on the left. The sum is used as
The operation proceeds until the first-operand field is 6. The fetch and subsequent store accesses to a
exhausted. The list is not altered unless an overlap particular byte in the first-operand field do not
occurs. necessarily occur one immediately after the
other. Thus, this instruction cannot be safely
When the operands overlap, the result is obtained as used to update a location in storage if the possi-
if each result byte were stored immediately after bility exists that another CPU or a channel pro-
fetching the corresponding function byte. gram may also be updating the location. An
example of this effect is shown for OR (OI) in
Access exceptions are recognized only for those “Multiprogramming and Multiprocessing Exam-
bytes in the second operand which are actually ples” in Appendix A, “Number Representation
required. and Instruction-Use Examples.”
• Access (fetch, operand 2; fetch and store, oper- TRANSLATE AND TEST
and 1)
TRT D1(L,B1),D2(B2) [SS-a]
Programming Notes:
'DD' L B1 D1 B2 D2
0 8 16 20 32 36 47
1. An example of the use of the TRANSLATE
instruction is given in Appendix A, “Number Rep-
resentation and Instruction-Use Examples.” The bytes of the first operand are used as eight-bit
arguments to select function bytes from a list desig-
2. TRANSLATE may be used to convert data from nated by the second-operand address. The first non-
one code to another code. zero function byte is inserted in general register 2,
and the related argument address in general register
3. The instruction may also be used to rearrange
1.
data. This may be accomplished by placing a
pattern in the destination area, by designating
The L field specifies the length of only the first oper-
the pattern as the first operand of TRANSLATE,
and.
and by designating the data that is to be rear-
ranged as the second operand. Each byte of the
pattern contains an eight-bit number specifying The bytes of the first operand are selected one by
the byte destined for this position. Thus, when one for translation, proceeding left to right. The first
the instruction is executed, the pattern selects operand remains unchanged in storage. Calculation
the bytes of the second operand in the desired of the address of the function byte is performed as in
order. the TRANSLATE instruction. The function byte
retrieved from the list is inspected for a value of zero.
4. Because each eight-bit argument byte is added
to the initial second-operand address to obtain When the function byte is zero, the operation pro-
the address of a function byte, the list may con- ceeds with the next byte of the first operand. When
tain 256 bytes. In cases where it is known that the first-operand field is exhausted before a nonzero
not all eight-bit argument values will occur, it is function byte is encountered, the operation is com-
possible to reduce the size of the list. pleted by setting condition code 0. The contents of
general registers 1 and 2 remain unchanged.
5. Significant performance degradation is possible
when the second-operand address of TRANS- When the function byte is nonzero, the operation is
LATE designates a location that is less than 256 completed by inserting the function byte in general
bytes to the left of a 4K-byte boundary. This is register 2 and the related argument address in gen-
because the machine may perform a trial execu- eral register 1. This address points to the argument
1. An example of the use of the TRANSLATE AND General register R1 + 1 contains the length of the first
TEST instruction is given in Appendix A, “Num- operand in bytes.
ber Representation and Instruction-Use Exam-
ples.” Operation of the instruction is subject to controls
specified in the M3 field, bits 16-19 of the instruction.
2. TRANSLATE AND TEST may be used to scan The M3 field has the following format:
the first operand for characters with special
meaning. The second operand, or list, is set up A F L /
with all-zero function bytes for those characters 0 1 2 3
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R1 + 1 First-Operand Length
0 63
Explanation:
The argument characters of the first operand are with a binary 0, is added to the function-code-table
selected one by one for processing, proceeding in a address in general register 1 to form the address of
left-to-right direction for TRANSLATE AND TEST the selected 16-bit function code. These additions
EXTENDED, or in a right-to-left direction for TRANS- follow the rules for address arithmetic.
LATE AND TEST REVERSE EXTENDED. Depend-
ing on the A bit of the M3 field, the argument When both the A and L bits are one, and the value of
characters are treated as either eight-bit or sixteen- the argument character is greater than 255, then the
bit unsigned binary integers, extended with zeros on function-code table is not accessed. The function
the left. code is assumed to contain zero in this case.
When the F bit of the M3 field is zero, the argument When the selected function code contains zero, or
character is added to the function-code-table when the function code is assumed to contain zero,
address in general register 1 to form the address of processing continues with the next argument charac-
the selected 8-bit function code. When the F bit is ter in the first operand. The operation proceeds until
one, the argument character, extended on the right a nonzero function code is selected, the first-operand
of first-operand bytes have been processed. the same register as register R1+1, the updated first-
operand length is placed in the register.
When the first-operand location is exhausted without
having selected a nonzero function code, general When general register R1 is updated in the 24-bit or
register R1 is either incremented or decremented by 31-bit addressing mode, bits 32-39, in the 24-bit
the first operand length in general register R1 + 1; mode, or bit 32, in the 31-bit mode, may be set to
general register R1 + 1 is set to zero; general register zeros or may remain unchanged from their original
R2 is set as though a function code of zero was values.
selected; and condition code 0 is set. For TRANS-
LATE AND TEST EXTENDED, general register R1 is In the 24-bit or 31-bit addressing mode, the contents
incremented by the first operand length; for TRANS- of bit positions 0-31 of general registers R1, R1 + 1,
LATE AND TEST REVERSE EXTENDED, general and R2 always remain unchanged.
register R1 is decremented by the first operand
length. In the 24-bit or 31-bit addressing mode, bits The amount of processing that results in the setting
0-31 of general register R2 are unchanged, and bits of condition code 3 is determined by the CPU on the
32-63 of the register are set to zeros; in the 64-bit basis of improving system performance, and it may
addressing mode, bits 0-63 of general register R2 are be a different amount each time the instruction is
set to zeros. executed.
When a nonzero function code is selected, the func- Access exceptions for the portion of the first operand
tion code replaces bits 56-63 or bits 48-63 of general beyond the last byte processed may or may not be
register R2, depending on whether the F bit is zero or recognized. For an operand longer than 4K bytes,
one, respectively; depending on the addressing access exceptions are not recognized for locations
mode, the remaining bits in general register R2 are more than 4K bytes beyond the last byte processed.
set to zeros; the address of the argument character When the length of the first operand is zero, no
used to select the nonzero function code is placed in access exceptions for the first operand are recog-
general register R1; general register R1 + 1 is decre- nized.
mented by the number of first-operand bytes pro-
cessed prior to selecting the nonzero function byte; Access exceptions for any byte of the function-code
and condition code 1 is set. In the 24-bit or 31-bit table specified by general register 1 may be recog-
addressing mode, bits 0-31 of general register R2 are nized, even if not all bytes are used.
unchanged, and bits 32-55 (F=0) or 32-47 (F=1) are
set to zero; in the 64-bit addressing mode, bits 0-55 Special Conditions
(F=0) or 0-47 (F=1) are set to zeros.
A specification exception is recognized for any of the
When a CPU-determined number of bytes have been following conditions:
processed, general register R1 is either incremented
or decremented by the number of bytes in the first 1. The R1 field designates an odd-numbered regis-
operand that were processed, general register R1 + 1 ter.
is decremented by this number, and condition code 3
is set. For TRANSLATE AND TEST EXTENDED, 2. The A bit of the M3 field is one and the first oper-
general register R1 is incremented by the number of and length in general register R1 + 1 is odd.
bytes processed; for TRANSLATE AND TEST
REVERSE EXTENDED, general register R1 is decre- Resulting Condition Code:
mented by the number of bytes processed. Condition
code 3 may be set even when the first-operand loca- 0 Entire first operand processed without selecting
tion is exhausted or when the next argument charac- a nonzero function code
ter to be processed selects a nonzero function byte. 1 Nonzero function code selected
In these cases, condition code 0 or 1 will be set when 2 --
the instruction is executed again. 3 CPU-determined number of bytes processed
The bytes of the first operand are selected one by • Access (fetch, operands 1 and 2)
one for translation, proceeding from right to left. The • Operation (if the extended-translation facility 3 is
first operand remains unchanged in storage. Calcula- not installed)
tion of the address of the function byte is performed
as in the TRANSLATE instruction. The function byte Programming Note:
retrieved from the list is inspected for a value of zero.
TRANSLATE AND TEST REVERSE may be used to
When the function byte is zero, the operation pro- scan the first operand for characters with special
ceeds with the preceding byte of the first operand. meaning. The second operand, or list, is set up with
When the first-operand field is exhausted before a all-zero function bytes for those characters to be
nonzero function byte is encountered, the operation skipped over and with nonzero function bytes for the
is completed by setting condition code 0. The con- characters to be detected.
tents of general registers 1 and 2 remain unchanged.
Access exceptions can be recognized for any byte in The location of the leftmost byte of the first operand
either the first or in the second operand. and second operand is designated by the contents of
general registers R1 and R2, respectively. In the
24-bit or 31-bit addressing mode, the number of
TRANSLATE EXTENDED
contents of bit positions 32-63 of general register 0-39 are ignored. In the 31-bit addressing mode, the
R1 + 1, and those contents are treated as a 32-bit contents of bit positions 33-63 of the registers consti-
unsigned binary integer. In the 64-bit addressing tute the address, and the contents of bit positions
mode, the number of bytes in the first-operand loca- 0-32 are ignored. In the 64-bit addressing mode, the
tion is specified by the entire contents of general reg- contents of bit positions 0-63 constitute the address.
ister R1 + 1, and those contents are treated as a
64-bit unsigned binary integer. The test byte is in bit positions 56-63 of general reg-
ister 0, and the contents of bit positions 0-55 of this
The handling of the addresses in general registers R1 register are ignored.
and R2 is dependent on the addressing mode.
The contents of the registers just described are
In the 24-bit addressing mode, the contents of bit shown in Figure 7-299.
positions 40-63 of general registers R1 and R2 consti-
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R1 + 1 First-Operand Length
0 63
R2 Second-Operand Address
0 63
The bytes of the first operand are selected one by addition is performed following the rules for address
one for translation, proceeding left to right. Each arithmetic, with the argument byte treated as an
argument byte is first compared to the test byte in eight-bit unsigned binary integer and extended with
general register 0. If the result is an equal compari- zeros on the left. The sum is used as the address of
son, the operation is completed. If the argument byte the function byte, which then replaces the original
is not equal to the test byte, the argument byte is argument byte. The second operand is not altered
added to the initial second-operand address. The unless an overlap occurs.
When the first-operand location is exhausted without Access exceptions for the portion of the first operand
finding a byte equal to the test byte, condition code 0 to the right of the last byte processed may or may not
is set. When a first-operand byte equal to the test be recognized. For an operand longer than 4K bytes,
byte is encountered, condition code 1 is set. When a access exceptions are not recognized for locations
CPU-determined number of bytes have been pro- more than 4K bytes beyond the last byte processed.
cessed, condition code 3 is set. Condition code 3
may be set even when the first-operand location is Access exceptions for all 256 bytes of the second
exhausted or when the next byte to be processed is operand may be recognized, even if not all bytes are
equal to the test byte. In these cases, condition code used.
0 or 1, respectively, will be set when the instruction is
executed again. Access exceptions are not recognized if the R1 field
is odd. When the length of the first operand is zero,
If the operation is completed with condition code 0, no access exceptions for the first operand are recog-
the contents of general register R1 are incremented nized.
by the contents of general register R1 + 1, and then
the contents of general register R1 + 1 are set to Resulting Condition Code:
zero. If the operation is completed with condition
code 1, the contents of general register R1 + 1 are 0 Entire first operand processed without finding a
decremented by the number of bytes processed byte equal to the test byte
before the first-operand byte equal to the test byte 1 First-operand byte is equal to the test byte
was encountered, and the contents of general regis- 2 --
ter R1 are incremented by the same number, so that 3 CPU-determined number of bytes processed
general register R1 contains the address of the equal
byte. If the operation is completed with condition Program Exceptions:
code 3, the contents of general register R1 + 1 are
decremented by the number of bytes processed, and • Access (fetch, operand 2; store, operand 1)
the contents of general register R1 are incremented • Specification
by the same number, so that the instruction, when
reexecuted, resumes at the next byte to be pro- Programming Notes:
cessed. When general register R1 is updated in the
24-bit or 31-bit addressing mode, bits 32-39 of it, in 1. When condition code 3 is set, the program can
the 24-bit mode, or bit 32, in the 31-bit mode, may be simply branch back to the instruction to continue
set to zeros or may remain unchanged from their the translation. The program need not determine
original values. the number of bytes that were translated.
In the 24-bit or 31-bit addressing mode, the contents 2. The instruction can improve performance by
of bit positions 0-31 of general registers R1 and being used in place of a TRANSLATE AND TEST
R1 + 1 always remain unchanged. instruction that locates an escape character, fol-
lowed by a TRANSLATE instruction that trans-
The amount of processing that results in the setting lates the bytes preceding the escape character.
of condition code 3 is determined by the CPU on the 3. The storage-operand references of TRANSLATE
basis of improving system performance, and it may EXTENDED may be multiple-access references.
be a different amount each time the instruction is (See “Storage-Operand Consistency” on
executed. page 5-95.)
The characters of the second operand are used as • For TRANSLATE ONE TO ONE, the second-
arguments to select function characters from a trans- operand, first-operand, and test characters are
lation table designated by the address in general reg- single bytes.
ister 1. • For TRANSLATE ONE TO TWO, the second-
operand characters are single bytes, and the
When the ETF2-enhancement facility is not installed, first-operand and test characters are double
or when the test-character-comparison control is bytes.
zero, each function character selected from the trans-
lation table is compared to a test character in general • For TRANSLATE TWO TO ONE, the second-
register 0, and, unless an equal comparison occurs, operand characters are double bytes, and the
is placed at the first-operand location. The operation first-operand and test characters are single
proceeds until a selected function character equal to bytes.
the test character is encountered, the end of the sec-
ond operand is reached, or a CPU-determined num- • For TRANSLATE TWO TO TWO, the second-
ber of characters have been processed, whichever operand, first-operand, and test characters are
occurs first. double bytes.
When the ETF2-enhancement facility is installed and For TRANSLATE ONE TO ONE and TRANSLATE
the test-character-comparison control is one, test- TWO TO ONE, the test character is in bit positions
character comparison is not performed. Each func- 56-63 of general register 0. For TRANSLATE ONE
tion character selected from the translation table is TO TWO and TRANSLATE TWO TO TWO, the test
placed at the first operation location. The operation character is in bit positions 48-63 of general register
proceeds until the end of the second operand is 0.
registers and must designate an even-numbered reg- 31-bit addressing mode, the contents of bit positions
ister; otherwise, a specification exception is recog- 33-63 of registers R1 and R2 and 33-60 or 33-51 of 1
nized. constitute the address, and the contents of bit posi-
tions 0-32 are ignored. In the 64-bit addressing
The location of the leftmost byte of the first operand mode, the contents of bit positions 0-63 of registers
and second operand is designated by the contents of R1 and R2 and 0-60 or 0-51 of 1 constitute the
general registers R1 and R2, respectively. In the address.
24-bit or 31-bit addressing mode, the number of
bytes in the second-operand location is specified by The contents of the registers just described are
the contents of bit positions 32-63 of general register shown in Figure 7-300 on page 7-329.
R1 + 1, and those contents are treated as a 32-bit
unsigned binary integer. In the 64-bit addressing In the access-register mode, the contents of access
mode, the number of bytes in the second-operand registers R1, R2, and 1 are used for accessing the
location is specified by the contents of bit positions first operand, second operand, and translation table,
0-63 of general register R1 + 1, and those contents respectively.
are treated as a 64-bit unsigned binary integer. The
length of the first-operand location is considered to The length of the translation table designated by the
be the same as that of the second operand for address contained in general register 1 is as follows:
TRANSLATE ONE TO ONE and TRANSLATE TWO
TO TWO, twice that for TRANSLATE ONE TO TWO, • For TRANSLATE ONE TO ONE, the translation-
and one half that for TRANSLATE TWO TO ONE. table length is 256 bytes; each of the 256 func-
tion characters is a single byte.
For TRANSLATE TWO TO ONE and TRANSLATE
TWO TO TWO, the length in general register R1 + 1 • For TRANSLATE ONE TO TWO, the translation-
must be an even number of bytes; otherwise, a spec- table length is 512 bytes; each of the 256 func-
ification exception is recognized. tion characters is a double byte.
The rightmost bits of the register that are not used to • For TRANSLATE ONE TO ONE, the argument
form the address, which are bits 61-63 in the double- character is treated as an eight-bit unsigned
word case and bits 52-63 in the 4K-byte case, are binary integer extended on the left with 56 zeros.
ignored but should contain zeros; otherwise, the pro-
gram may not operate compatibly in the future. • For TRANSLATE ONE TO TWO, the argument
character is treated as an eight-bit unsigned
The handling of the addresses in general registers binary integer extended on the right with a zero
R1, R2, and 1 is dependent on the addressing mode. and on the left with 55 zeros.
In the 24-bit addressing mode, the contents of bit • For TRANSLATE TWO TO ONE, the argument
positions 40-63 of general registers R1 and R2 and character is treated as a 16-bit unsigned binary
40-60 or 40-51 of 1 constitute the address, and the integer extended on the left with 48 zeros.
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 40 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Length
0 32 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address
0 33 63
R1 + 1 Second-Operand Length
0 63
R2 Second-Operand Address
0 63
Explanation:
1
When the ETF2-enhancement facility is not installed, or when the C bit, bit 3 of the M3 field, is zero, test-character comparison is
performed. When the ETF2-enhancement facility is installed and the C bit is one, test-character comparison is not performed, and general
register 0 is ignored.
N
When the ETF2-enhancement facility is not installed, N is 61 for TRANSLATE ONE TO ONE and TRANSLATE ONE TO TWO, and N is 52
for TRANSLATE TWO TO ONE and TRANSLATE TWO TO TWO. When the ETF2-enhancement facility is installed, N is 61.
Figure 7-300. Register Contents for TRANSLATE ONE TO ONE, TRANSLATE ONE TO TWO, TRANSLATE TWO TO ONE,
and TRANSLATE TWO TO TWO
• For TRANSLATE TWO TO TWO, the argument The rightmost bits of the translation-table address
character is treated as a 16-bit unsigned binary that are ignored (61-63 or 52-63) are treated as zeros
integer extended on the right with a zero and on during this addition.
the left with 47 zeros.
When the ETF2-enhancement facility is installed and If the operation is completed with condition code 3,
the test-character-comparison control is one, pro- the contents of general register R1 + 1 are decre-
cessing is as described above, except that no test- mented by the number of second-operand bytes pro-
character comparison is performed. cessed, and the contents of general register R2 are
incremented by the same number, so that the instruc-
When a selected function character equal to the test tion, when reexecuted, contains the address of the
character is encountered, condition code 1 is set. next character to be processed. The contents of gen-
When the second-operand location is exhausted eral register R1 are incremented by the same, twice,
without finding a selected function character equal to or one half the number, as described above for condi-
the test character, condition code 0 is set. When a tion code 0.
CPU-determined number of characters have been
processed, condition code 3 is set. Condition code 3 When general registers R1 and R2 are updated in the
may be set even when the next character to be pro- 24-bit or 31-bit addressing mode, the bits in bit posi-
cessed results in a function character equal to the tions 32-39 of them that are not part of the address
test character or when the second-operand location may be set to zeros or may remain unchanged from
is exhausted. In these cases, condition code 1 or 0, their original values. In the 24-bit or 31-bit addressing
respectively, will be set when the instruction is exe- mode, the contents of bit positions 0-31 of general
cuted again. When the ETF2-enhancement facility is registers R1, R1 + 1, and R2 always remain
installed and the test-character-comparison control is unchanged.
one, condition code 1 does not apply.
The contents of general registers 0 and 1 remain
If the operation is completed with condition code 0, unchanged.
the contents of general register R2 are incremented
by the contents of general register R1 + 1, and the The amount of processing that results in the setting
contents of general register R1 are incremented as of condition code 3 is determined by the CPU on the
follows: basis of improving system performance, and it may
be a different amount each time the instruction is
executed.
UNPACK
condition code 3 being set with possibly incorrect is performed)
data having been stored in the first operand location 2 --
at or to the right of the location designated by the 3 CPU-determined number of characters pro-
final address in general register R1. The amount of cessed
data stored depends on the operation and the point
in time at which CPU retry occurred. In all cases, the Program Exceptions:
storing will occur again, with correct data stored,
when the instruction is executed again to continue • Access (fetch, operand 2 and translation table;
processing the same operands. store, operand 1)
• Operation (if the extended-translation facility 2 is
When any of the following conditions are true, the not installed)
results are unpredictable: • Specification
packed-decimal format. Its digits and sign are placed may be multiple-access references. (See “Stor-
unchanged in the first-operand location, using the age-Operand Consistency” on page 5-95.)
zoned format. Zone bits with coding of 1111 are sup-
plied for all bytes except the rightmost byte, the zone
of which receives the sign of the second operand. UNPACK ASCII
The sign and digits are not checked for valid codes.
UNPKA D1(L1,B1),D2(B2) [SS-a]
The result is obtained as if the operands were pro- 'EA' L1 B1 D1 B2 D2
cessed right to left. When necessary, the second 0 8 16 20 32 36 47
operand is considered to be extended on the left with
zeros. If the first-operand field is too short to contain
all digits of the second operand, the remaining left- The format of the second operand is changed from
most portion of the second operand is ignored. signed-packed-decimal to ASCII, and the result is
Access exceptions for the unused portion of the sec- placed at the first-operand location. The signed-
ond operand may or may not be indicated. packed-decimal format is described in Chapter 8,
“Decimal Instructions.”
When the operands overlap, the result is obtained as
if the operands were processed one byte at a time The second operand is treated as having the signed-
and as if the first result byte were stored immediately packed-decimal format. Its digits are converted to
after fetching the first operand byte. The entire right- ASCII characters by extending them on the left with
most second-operand byte is used in forming the first 0011 binary, and the ASCII characters are then
result byte. For the remainder of the field, information placed at the first operand location. The digits are not
for two result bytes is obtained from a single second- checked for valid codes.
operand byte, and execution proceeds as if the left-
most four bits of the byte were to remain available for The sign of the second operand is not transferred to
the next result byte and need not be refetched. Thus, the first operand but is checked for validity and deter-
the result is as if two result bytes were to be stored mines the condition code. If the sign is 1010, 1100,
immediately after fetching a single operand byte. 1110 or 1111 binary (plus), condition code 0 is set. If
the sign is 1011 or 1101 binary (minus), condition
Condition Code: The code remains unchanged. code 1 is set. If the sign is not one of the codes for
plus or minus, condition code 3 is set.
Program Exceptions:
The converted last digit is placed in the rightmost
• Access (fetch, operand 2; store, operand 1) byte position of the result field, and the other con-
verted digits are placed adjacent to the last and to
Programming Notes: each other in the remainder of the result field.
1. An example of the use of the UNPACK instruc- The result is obtained as if the operands were pro-
tion is given in Appendix A, “Number Represen- cessed right to left.
tation and Instruction-Use Examples.”
The length of the second operand is 16 bytes. The
2. A field that is to be unpacked can be destroyed second operand consists of 31 digits and a sign.
by improper overlapping. To save storage space
for unpacking by overlapping the operands, the The length of the first operand is designated by the
rightmost byte of the first operand must be to the contents of the L1 field. The first-operand length must
right of the rightmost byte of the second operand not exceed 32 bytes (L1 must be less than or equal to
by the number of bytes in the second operand 31); otherwise, a specification exception is recog-
minus 2. If only one or two bytes are to be nized.
unpacked, the rightmost bytes of the two oper-
ands may coincide. If the first operand is too short to contain all digits of
the second operand, the remaining leftmost portion
of the second operand is ignored. Access exceptions
UNPACK UNICODE
may not be indicated.
UNPKU D1(L1,B1),D2(B2) [SS-a]
When the length of the first operand is 32 bytes, the
leftmost byte is set to ASCII zero, 30 hex. 'E2' L1 B1 D1 B2 D2
0 8 16 20 32 36 47
Resulting Condition Code: The second operand is treated as having the signed-
packed-decimal format. Its digits are converted to
0 Sign is plus two-byte Unicode characters by extending them on
1 Sign is minus the left with 000000000011 binary (003 hex), and the
2 -- Unicode characters are then placed at the first oper-
3 Sign is invalid and location. The digits are not checked for valid
codes. The sign of the second operand is not trans-
Program Exceptions: ferred to the first operand but is checked for validity
and determines the condition code. If the sign is
• Access (fetch, operand 2; store, operand 1) 1010, 1100, 1110 or 1111 binary (plus), condition
• Operation (if the extended-translation facility 2 is code 0 is set. If the sign is 1011 or 1101 binary
not installed) (minus), condition code 1 is set. If the sign is not one
• Specification of the codes for plus or minus, condition code 3 is
set.
Programming Note:
The converted last digit is placed in the rightmost
1. The following example illustrates the use of the character position of the result field, and the other
instruction to unpack to ASCII digits: converted digits are placed adjacent to the last and
to each other in the remainder of the result field.
ASDIGITS DS CL31
PKDIGITS DS 0PL16 The result is obtained as if the operands were pro-
DC X'1234567890' cessed right to left.
DC X'1234567890'
DC X'1234567890'
The length of the second operand is 16 bytes; the
DC X'1C'
§ second operand consists of 31 digits and a sign.
UNPKA ASDIGITS(31),PKDIGITS
The length of the first operand is designated by the
2. The storage-operand references of UNPACK contents of the L1 field. The first-operand length must
ASCII may be multiple-access references. (See not exceed 32 characters or 64 bytes (L1 must be
“Storage-Operand Consistency” on page 5-95.) less than or equal to 63 and must be odd); otherwise
a specification exception is recognized.
3. The UNPACK ASCII and UNPACK UNICODE
instructions set condition code 0 to indicate a If the first operand is too short to contain all digits of
positive sign, and these instructions provide no the second operand, the remaining leftmost portion
indication of a zero result. In all other instructions of the second operand is ignored. Access exceptions
that indicate a signed result, condition code 0 for the unused portion of the second operand may or
indicates a result of zero, and condition code 2 may not be indicated.
indicates a positive result.
When the length of the first operand is 32 characters,
the leftmost character is set to Unicode Basic Latin
zero, 0030 hex.
operands overlap in any way. sively on a path toward the base of the tree, and con-
tents of general register 0, conceptually followed on
As observed by other CPUs and by channel pro- the right by contents of general register 1, are condi-
grams, the first operand is not necessarily stored into tionally interchanged with the contents of the nodes
in any particular order. so as to give a unique maximum logical value in gen-
eral register 0. The first half of a node and general
Resulting Condition Code: register 0 contain a codeword, which is for use in
sort/merge algorithms.
0 Sign is plus
1 Sign is minus If the codeword in general register 0 equals the code-
2 -- word in a node, the contents of the node are placed
3 Sign is invalid in general registers 2 and 3.
3. The UNPACK ASCII and UNPACK UNICODE In the 24-bit or 31-bit addressing mode, the double-
instructions set condition code 0 to indicate a word nodes of a tree in storage are examined suc-
positive sign, and these instructions provide no cessively on a path toward the base of the tree, and
indication of a zero result. In all other instructions the contents of bit positions 32-63 of general register
that indicate a signed result, condition code 0 0, conceptually followed on the right by the contents
indicates a result of zero, and condition code 2 of bit positions 32-63 of general register 1, are condi-
indicates a positive result. tionally interchanged with the contents of the nodes
so as to give a unique maximum logical value in bit
positions 32-63 of general register 0.
UPDATE TREE
Bit positions 32-63 of general register 4 contain the
UPT [E] base address of the tree, and bit positions 32-63 of
'0102' general register 5 contain the index of a node whose
0 15
parent node will be examined first. The base address
is eight less than the address of the root node of the
tree. The initial contents of bit positions 32-63 of gen-
UPDATE TREE
wise, a specification exception is recognized. tree, and general register 5 contain the index of a
node whose parent node will be examined first. The
A unit of operation begins by shifting the contents of base address is 16 less than the address of the root
bit positions 32-63 of general register 5 right logically node of the tree. The initial contents of general regis-
one position and then setting bit 61 to zero. However, ters 4 and 5 must be a multiple of 16; otherwise, a
bits 32-63 of general register 5 remain unchanged if specification exception is recognized.
the execution of a unit of operation is nullified or sup-
pressed. If after shifting and setting bit 61 to zero, bits A unit of operation begins by shifting the contents of
32-63 of general register 5 are all zeros, the instruc- general register 5 right logically one position and
tion is completed, and condition code 1 is set; other- then setting bit 60 to zero. However, general register
wise, the unit of operation continues. 5 remains unchanged if the execution of a unit of
operation is nullified or suppressed. If after shifting
Bit 32 of general register 0 is tested. If bit 32 of gen- and setting bit 60 to zero, the contents of general reg-
eral register 0 is one, the instruction is completed, ister 5 are zero, the instruction is completed, and
and condition code 3 is set. condition code 1 is set; otherwise, the unit of opera-
tion continues.
If bit 32 of general register 0 is zero, the sum of bits
32-63 of general registers 4 and 5 is used as the Bit 0 of general register 0 is tested. If bit 0 of general
intermediate value for normal operand address gen- register 0 is one, the instruction is completed, and
eration. The generated address is the address of a condition code 3 is set.
node in storage.
If bit 0 of general register 0 is zero, the sum of the
Bits 32-63 of general register 0 are logically com- contents of general registers 4 and 5 is used as the
pared with the contents of the first word of the cur- intermediate value for normal operand address gen-
rently addressed node. If the register operand is low, eration. The generated address is the address of a
the contents of bit positions 32-63 of general regis- node in storage.
ters 0 and 1 are interchanged with those of the node,
and a unit of operation is completed. If the register The contents of general register 0 are logically com-
operand is high, no additional action is taken, and the pared with the contents of the first doubleword of the
unit of operation is completed. If the compare values currently addressed node. If the register operand is
are equal, bit positions 32-63 of general register 2, low, the contents of general registers 0 and 1 are
conceptually followed on the right by bit positions interchanged with those of the node, and a unit of
32-63 of general register 3, are loaded from the cur- operation is completed. If the register operand is
rently addressed node, the instruction is completed, high, no additional action is taken, and the unit of
and condition code 0 is set. operation is completed. If the compare values are
equal, general registers 2 and 3 are loaded from the
In those cases when the value in the first word of the currently addressed node, the instruction is com-
node is less than or equal to the value in bit positions pleted, and condition code 0 is set.
32-63 of the register, the contents of the node remain
unchanged. However, in some models, these con- In those cases when the value in the first doubleword
tents may be fetched and subsequently stored back. of the node is less than or equal to the value in the
register, the contents of the node remain unchanged.
Operation in the 64-Bit Addressing Mode However, in some models, these contents may be
fetched and subsequently stored back.
In the 64-bit addressing mode, the quadword nodes
of a tree in storage are examined successively on a Specifications Independent of Addressing Mode
path toward the base of the tree, and the contents of
general register 0, conceptually followed on the right Access exceptions are recognized only for one node
by the contents of general register 1, are condition- at a time. Access exceptions, change-bit action, and
ally interchanged with the contents of the nodes so PER storage alteration do not occur for subsequent
as to give a unique maximum logical value in general nodes until the previous node has been successfully
register 0. compared and updated, and they also do not occur if
a specification-exception condition exists.
3. The program should avoid placing a nonzero 9. The storage-operand references for UPDATE
value in bit positions 32-38 of general register 5 TREE may be multiple-access references. (See
when in the 24-bit addressing mode. If any bit in “Storage-Operand Consistency” on page 5-95.)
bit positions 32-38 is a one, the nodes of the tree
will not be examined successively. 10. Figure 7-301 on page 7-337 is a summary of the
operation of UPDATE TREE in the 24-bit or
4. When bits 32-63 of general register 0 are nega- 31-bit addressing mode, and Figure 7-302 on
tive in the 24-bit or 31-bit addressing mode, or page 7-338 is a summary of the operation in the
when bits 0-63 are negative in the 64-bit mode, 64-bit addressing mode.
and provided that the tree has been updated
Unit-of- Yes
operation
boundary
TEMPWORD1 I GR5 shifted right *
one position
Bit 29 of TEMPWORD1 I 0
Yes
TEMPWORD1 = 0? GR5 I 0 *
Condition code I 1
No
Yes
Bit 32 of GR0 one? GR5 I TEMPWORD1 *
Condition code I 3
No
GR5 I TEMPWORD1 *
Compare *
GR0 high GR0 equal
GR0 and GR2 I TEMPWORD2 *
TEMPWORD2 *
GR3 I TEMPWORD3
GR0 low
Condition code I 0
Store contents of GR0 and GR1 in *
doubleword designated by TEMPADDRESS
End operation
*
GR0 I TEMPWORD2 * Only bits 32-63 of a GR
GR1 I TEMPWORD3 * participate when no bits
are mentioned.
Figure 7-301. Execution of UPDATE TREE in the 24-Bit or 31-Bit Addressing Mode
Unit-of- Yes
operation
boundary
TEMPDWRD1 I GR5 shifted right *
one position
Bit 60 of TEMPDWRD1 I 0
Yes
TEMPDWRD1 = 0? GR5 I 0 *
Condition code I 1
No
Yes
Bit 0 of GR0 one? GR5 I TEMPDWRD1 *
Condition code I 3
No
GR5 I TEMPDWRD1 *
Compare *
GR0 high GR0 equal
GR0 and GR2 I TEMPDWRD2 *
TEMPDWRD2 *
GR3 I TEMPDWRD3
GR0 low
Condition code I 0
Store contents of GR0 and GR1 in *
quadword designated by TEMPADDRESS
End operation
*
GR0 I TEMPDWRD2 * Bits 0-63 of a GR
GR1 I TEMPDWRD3 * participate when no
bits are mentioned.
The following symbols are used in the subsequent <n> Length of item in bytes
C Ciphertext
description. For data-encryption-algorithm (DEA)
K Key value
functions, the DEA-key-parity bit in each byte of the
P Plaintext
DEA key is ignored, and the operation proceeds nor-
mally, regardless of the DEA-key parity of the key. Figure 7-305. Symbols for DEA Encryption and Decryption
AES AES
e d
...
C <16> P <16> K K1 <8> K2 <8> Kn <8>
...
Symbol for AES-256 Symbol for AES-256
Encryption Decryption
xor ... xor
Explanation:
WK1d WK1d WK1d
DEA DEA DEA
<n> Length of item in bytes e e e
C Ciphertext
K Key value WK2d WK2d WK2d
P Plaintext DEA DEA DEA
d d d
Figure 7-306. Symbols for AES-256 Encryption and
Decryption WK3d WK3d WK3d
DEA DEA DEA
e e e
Protection of DES Keys
...
WKd(K) C1 <8> C2 <8> Cn <8>
When the message-security-assist-extension-3 facil- ...
ity is installed, user DEA or TDEA keys may be pro- Explanation:
tected under the 192-bit DEA wrapping key.
K = K1 || K2 || ... || Kn; a user DEA key or TDEA key.
Figure 7-307 on page 7-340 describes encryption of WKd = WK1d || WK2d || WK3d
a 64-bit DEA key, a 128-bit TDEA key, and a 192-bit WKd(K) = C1 || C2 || ... || Cn; K is encrypted under WKd.
TDEA key using the 192-bit DEA wrapping key. n=1, when K is a 64-bit DEA key; n=2, when K is a 128-bit TDEA key; n=3,
when K is a 192-bit TDEA key.
WKa(K) <16>
K K1 <8> K2 <8> Kn <8>
Explanation:
Explanation:
K A user 128-bit AES key.
K = K1 || K2 || ... || Kn; a user DEA key or TDEA key. WKa(K) K is encrypted under WKa using AES-256 encryption.
WKd = WK1d || WK2d || WK3d
WKd(K) = C1 || C2 || ... || Cn; K is encrypted under WKd.
Figure 7-309. Encryption of 128-Bit AES Key Using WKa
n=1, when K is a 64-bit DEA key; n=2, when K is a 128-bit TDEA key; n=3,
when K is a 192-bit TDEA key.
WKa(K) WKa(K)
C1 <8> C2 <16> C1 <16> C2 <16>
<24> <32>
Explanation: Explanation:
K = K1 || K2; a user 192-bit AES key. K = K1 || K2; a user 256-bit AES key.
WKa(K) = C1 || C2; K is encrypted under WKa using AES-256 encryption. WKa(K) = C1 || C2; K is encrypted under WKa using AES-256 encryption.
Pad is a 64-bit value of zero. Figure 7-313. Encryption of 256-Bit AES Key Using WKa
WKa (K)
C1 <16> C2 <16>
<32>
AES AES
WKa <32> WKa <32>
d d xor
K K
K1 <16> <32> K1 <16> K2 <16>
<24>
Explanation:
<8> <8>
xor
K = K1 || K2; a user 256-bit AES key.
WKa(K) = C1 || C2; K is encrypted under WKa using AES-256 encryption.
Explanation:
The decimal instructions of this chapter perform of a code representing a decimal digit. The leftmost
arithmetic and editing operations on decimal data. four bits of a byte are called the zone bits (Z), except
Additional operations on decimal data are provided for the rightmost byte of a decimal operand, where
by several of the instructions in Chapter 7, “General these bits may be treated either as a zone or as a
Instructions.” Also, several instructions in Chapter 20, sign (S).
“Decimal-Floating-Point Instructions” operate on dec-
imal numbers in the packed-decimal format. Except Decimal digits in the zoned format may be part of a
for decimal-floating-point instructions, decimal oper- larger character set, which includes also alphabetic
ands always reside in storage, and most decimal and special characters. The zoned format is, there-
instructions use the SS instruction format. Decimal fore, suitable for input, editing, and output of numeric
operands occupy storage fields that can start on any data in human-readable form. There are no decimal-
byte boundary. For decimal-floating-point instruc- arithmetic instructions which operate directly on deci-
tions, the packed-decimal operands are fixed length mal numbers in the zoned format; such numbers
and occupy a general register, or general register must first be converted to the signed-packed-decimal
pair. format.
Code Recognized As A decimal zero normally has a plus sign, but multipli-
(Binary) Digit Sign cation, division, and overflow may produce a zero
0000 0 Invalid value with a minus sign. Such a negative zero is a
0001 1 Invalid valid operand and is treated as equal to a positive
0010 2 Invalid zero by COMPARE DECIMAL.
0011 3 Invalid
0100 4 Invalid The lengths of the two operands specified in the
0101 5 Invalid instruction need not be the same. If necessary, the
0110 6 Invalid shorter operand is considered to be extended with
0111 7 Invalid zeros on the left. Results, however, cannot exceed
1000 8 Invalid the first-operand length as specified in the instruc-
1001 9 Invalid tion.
1010 Invalid Plus
1011 Invalid Minus When a carry or leftmost nonzero digits of the result
1100 Invalid Plus (preferred) are lost because the first-operand field is too short,
1101 Invalid Minus (preferred) the result is obtained by ignoring the overflow digits,
1110 Invalid Plus condition code 3 is set, and, if the decimal-overflow
1111 Invalid Plus (zone) mask bit is one, a program interruption for decimal
Figure 8-1. Summary of Digit and Sign Codes overflow occurs. The operand lengths alone are not
an indication of overflow; nonzero digits must have
Programming Note: Since 1111 is both the zone been lost during the operation.
code and an alternate code for plus, unsigned (posi-
tive) decimal numbers may be represented in the The operands of decimal-arithmetic instructions
zoned format with 1111 zone codes in all byte posi- should not overlap at all or should have coincident
tions. The result of the PACK instruction converting rightmost bytes. In ZERO AND ADD, the operands
such a number to the signed-packed-decimal format may also overlap in such a manner that the rightmost
may be used directly as an operand for decimal byte of the first operand (which becomes the result)
instructions. is to the right of the rightmost byte of the second
operand. For these cases of proper overlap, the
result is obtained as if operands were processed
right to left. Because the codes for digits and signs
Decimal Operations are verified during the performance of the arithmetic,
improperly overlapping operands are recognized as
The decimal instructions in this chapter consist of two data exceptions. However, in ZERO AND ADD when
classes, the decimal-arithmetic instructions and the the rightmost byte of the first operand is to the left of
editing instructions. the rightmost byte of the second operand, the entire
second operand may be fetched, depending on the
model, before any storing occurs, which will cause a
Decimal-Arithmetic Instructions data exception not to be recognized. See “Interlocks
within a Single Instruction” on page 5-87 for how
The decimal-arithmetic instructions perform addition, overlap is detected in the access-register mode.
subtraction, multiplication, division, comparison, and
shifting. Programming Note: A signed-packed-decimal num-
ber in storage may be designated as both the first
Operands of the decimal-arithmetic instructions are and second operand of ADD DECIMAL, COMPARE
in the signed-packed-decimal format and are treated DECIMAL, DIVIDE DECIMAL, MULTIPLY DECIMAL,
as signed decimal integers. A decimal integer is rep- SUBTRACT DECIMAL, or ZERO AND ADD. Thus, a
resented in true form as an absolute value with a decimal number may be added to itself, compared
separate plus or minus sign. It contains an odd num- with itself, and so forth; SUBTRACT DECIMAL may
ber of decimal digits, from one to 31, and the sign; be used to set a decimal field in storage to zero; and,
for MULTIPLY DECIMAL, a decimal number may be
Overlapping operands for the editing instructions CONVERT TO UNSIGNED PACKED and CONVERT
yield unpredictable results. FROM UNSIGNED PACKED (described in Chapter
20) provide conversion between decimal floating
point (DFP) formats and the unsigned-packed-deci-
Execution of Decimal Instructions mal format. Unsigned-packed-decimal operands of
up to 16 bytes in length (32 digits) can be processed.
During the execution of a decimal instruction, all
bytes of the operands are not necessarily accessed MOVE WITH OFFSET (described in Chapter 7) oper-
concurrently, and the fetch and store accesses to a ates on data in the packed format. (The first operand
single location do not necessarily occur one immedi- is treated as signed-packed decimal and the second
ately after the other. Furthermore, for decimal operand as unsigned-packed decimal.) Operands
instructions, data in source fields may be accessed are not checked for valid codes. Signed-packed-deci-
more than once, and intermediate values may be mal operands of up to 16 bytes in length (31 digits
placed in the result field that may differ from the origi- and a sign) can be processed.
nal operand and final result values. (See “Storage-
Operand Consistency” on page 5-95.) Thus, in a PACK, UNPACK, PACK ASCII, UNPACK ASCII,
multiprocessing configuration, an instruction such as PACK UNICODE, and UNPACK UNICODE provide
ADD DECIMAL cannot be safely used to update a conversion between zoned or character data and
shared storage location when the possibility exists signed-packed-decimal data. Operands are not
that another CPU may also be updating that location. checked for valid codes. Signed-packed-decimal
operands of up to 16 bytes in length (31 digits and a
Other Instructions for Decimal sign) can be processed.
2. The operand fields in ADD DECIMAL, COM- The decimal instructions and their mnemonics, for-
PARE DECIMAL, DIVIDE DECIMAL, MULTIPLY mats, and operation codes are listed in Figure 8-2 on
DECIMAL, and SUBTRACT DECIMAL overlap in page 8-5. The figure also indicates when the condi-
a way other than with coincident rightmost bytes; tion code is set, the instruction fields that designate
or operand fields in ZERO AND ADD overlap, access registers, and the exceptional conditions in
and the rightmost byte of the second operand is operand designations, data, or results that cause a
to the right of the rightmost byte of the first oper- program interruption.
and. On some models, the improper overlap of
operands for ZERO AND ADD is not recognized Note: In the detailed descriptions of the individual
as a decimal-operand data exception; instead, instructions, the mnemonic and the symbolic oper-
the operation is performed as if the entire second and designation for the assembler language are
operand were fetched before any byte of the shown with each instruction. For ADD DECIMAL, for
result is stored. example, AP is the mnemonic and
D1(L1,B1),D2(L2,B2) the operand designation.
3. The multiplicand in MULTIPLY DECIMAL has an
insufficient number of leftmost zeros. Programming Note: The decimal instruction TEST
DECIMAL is available when the extended-translation
A decimal-operand data exception causes the opera- facility 2 is installed.
tion to be suppressed, except that, for EDIT and
EDIT AND MARK, and COMPRESSION CALL, the
operation may be suppressed or terminated. In the
case of EDIT and EDIT AND MARK, and COM-
PRESSION CALL, an invalid sign code cannot occur.
Mne- Op
Name monic Characteristics Code Page
ADD DECIMAL AP SS-b C A Dd DF ST B1 B2 FA 8-6
COMPARE DECIMAL CP SS-b C A Dd B1 B2 F9 8-6
DIVIDE DECIMAL DP SS-b A SP Dd DK ST B1 B2 FD 8-7
EDIT ED SS-a C A Dd ST B1 B2 DE 8-7
EDIT AND MARK EDMK SS-a C A Dd G1 ST B1 B2 DF 8-10
MULTIPLY DECIMAL MP SS-b A SP Dd ST B1 B2 FC 8-11
SHIFT AND ROUND DECIMAL SRP SS-c C A Dd DF ST B1 B2 F0 8-12
SUBTRACT DECIMAL SP SS-b C A Dd DF ST B1 B2 FB 8-13
TEST DECIMAL TP RSL C E2 A B1 B2 EBC0 8-13
ZERO AND ADD ZAP SS-b C A Dd DF ST B1 B2 F8 8-13
Explanation:
The second operand is added to the first operand, The first operand is compared with the second oper-
and the resulting sum is placed at the first-operand and, and the result is indicated in the condition code.
location. The operands and result are in the signed- The operands are in the signed-packed-decimal for-
packed-decimal format. mat.
Addition is algebraic, taking into account the signs Comparison is algebraic and follows the procedure
and all digits of both operands. All sign and digit for decimal subtraction, except that both operands
codes are checked for validity. remain unchanged. When the difference is zero, the
operands are equal. When a nonzero difference is
If the first operand is too short to contain all leftmost positive or negative, the first operand is high or low,
nonzero digits of the sum, decimal overflow occurs. respectively.
The operation is completed. The result is obtained
by ignoring the overflow digits, and condition code 3 Overflow cannot occur because the difference is dis-
is set. If the decimal-overflow mask is one, a pro- carded.
gram interruption for decimal overflow occurs.
All sign and digit codes are checked for validity.
The sign of the sum is determined by the rules of
algebra. In the absence of overflow, the sign of a Resulting Condition Code:
zero result is made positive. If overflow occurs, a
zero result is given either a positive or negative sign, 0 Operands equal
as determined by what the sign of the correct sum 1 First operand low
would have been. 2 First operand high
3 --
Resulting Condition Code:
Program Exceptions:
0 Result zero; no overflow
1 Result less than zero; no overflow • Access (fetch, operands 1 and 2)
2 Result greater than zero; no overflow • Data
3 Overflow
Programming Notes:
Program Exceptions:
1. An example of the use of the COMPARE DECI-
• Access (fetch, operand 2; fetch and store, oper- MAL instruction is given in Appendix A, “Number
and 1) Representation and Instruction-Use Examples.”
• Data
• Decimal overflow 2. The preferred and alternate sign codes for a par-
ticular sign are treated as equivalent for compari-
Programming Note: An example of the use of the son purposes.
ADD DECIMAL instruction is given in Appendix A, 3. A negative zero and a positive zero compare
“Number Representation and Instruction-Use Exam- equal.
ples.”
EDIT
and 1)
DP D1(L1,B1),D2(L2,B2) [SS-b] • Data
• Decimal divide
'FD' L1 L2 B1 D1 B2 D2 • Specification
0 8 12 16 20 32 36 47
Programming Notes:
The first operand (the dividend) is divided by the sec-
ond operand (the divisor). The resulting quotient and 1. An example of the use of the DIVIDE DECIMAL
remainder are placed at the first-operand location. instruction is given in Appendix A, “Number Rep-
The operands and results are in the signed-packed- resentation and Instruction-Use Examples.”
decimal format.
2. The dividend cannot exceed 31 digits and sign.
Since the remainder cannot be shorter than one
The quotient is placed leftmost in the first-operand
digit and sign, the quotient cannot exceed 29 dig-
location. The number of bytes in the quotient field is
its and sign.
equal to the difference between the dividend and
divisor lengths (L1 - L2). The remainder is placed 3. The condition for a decimal-divide exception can
rightmost in the first-operand location and has a be determined by a trial comparison. The left-
length equal to the divisor length. Together, the quo- most digit of the divisor is aligned one digit to the
tient and remainder fields occupy the entire first oper- right of the leftmost dividend digit, with rightmost
and; therefore, the address of the quotient is the zeros appended up to the length of the dividend.
address of the first operand. When the divisor, so aligned, is less than or
equal to the dividend, ignoring signs, a divide
The divisor length cannot exceed 15 digits and sign exception is indicated.
(L2 not greater than seven) and must be less than the
dividend length (L2 less than L1); otherwise, a specifi- 4. If a data exception does not exist, a decimal-
cation exception is recognized. divide exception occurs when the leftmost divi-
dend digit is not zero.
The dividend, divisor, quotient, and remainder are
each signed decimal integers in the signed-packed-
decimal format and are right-aligned in their fields. All
EDIT
sign and digit codes of the dividend and divisor are
ED D1(L,B1),D2(B2) [SS-a]
checked for validity.
'DE' L B1 D1 B2 D2
The sign of the quotient is determined by the rules of 0 8 16 20 32 36 47
algebra from the dividend and divisor signs. The sign
of the remainder has the same value as the dividend
The second operand (the source), which normally
sign. These rules hold even when the quotient or
contains one or more decimal numbers in the signed-
remainder is zero.
packed-decimal or unsigned-packed-decimal format,
is changed to the zoned format and modified under
Overflow cannot occur. If the divisor is zero or the
the control of the first operand (the pattern). The
quotient is too large to be represented by the number
edited result replaces the first operand.
of digits specified, a decimal-divide exception is rec-
ognized. This includes the case of division of zero by
The length field specifies the length of the first oper-
zero. The decimal-divide exception is indicated only
and, which may contain bytes of any value.
if the sign codes of both the dividend and divisor are
valid, and only if the digit or digits used in establish-
The length of the source is determined by the opera-
ing the exception are valid.
tion according to the contents of the pattern. The
source normally consists of one or more decimal
Condition Code: The code remains unchanged.
numbers, each in the signed-packed-decimal or
unsigned-packed-decimal format. The leftmost four
Program Exceptions:
bits of each source byte must specify a decimal-digit
code (0000-1001); a sign code (1010-1111) is recog-
may specify either a sign code or a decimal-digit the fill byte or remain unchanged in the result,
code. Access and data exceptions are recognized depending on the state of the significance indicator.
only for those bytes in the second operand which are They may thus be used for padding, punctuation, or
actually required. text in the significant portion of a field or for the inser-
tion of sign-dependent symbols.
The result is obtained as if both operands were pro-
cessed left to right one byte at a time. Overlapping Fill Byte: The first byte of the pattern is used as the
pattern and source fields give unpredictable results. fill byte. The fill byte can have any code and may
concurrently specify a control function. If this byte is
During the editing process, each byte of the pattern a digit selector or significance starter, the indicated
is affected in one of three ways: editing action is taken after the code has been
assigned to the fill byte.
1. It is left unchanged.
Source Digits: Each time a digit selector or signifi-
2. It is replaced by a source digit expanded to the cance starter is encountered in the pattern, a new
zoned format. source digit is examined for placement in the pattern
3. It is replaced by the first byte in the pattern, field. Either the source digit is disregarded, or it is
called the fill byte. expanded to the zoned format, by appending the
zone code 1111 on the left, and stored in place of the
Which of the three actions takes place is determined pattern byte.
by one or more of the following: the type of the pat-
tern byte, the state of the significance indicator, and Execution is as if the source digits were selected one
whether the source digit examined is zero. byte at a time. The leftmost four bits of each byte are
examined first, and the rightmost four bits, when they
Pattern Bytes: There are four types of pattern represent a decimal-digit code, remain available for
bytes: digit selector, significance starter, field sepa- the next pattern byte that calls for a digit examination.
rator, and message byte. Their coding is as follows: When the leftmost four bits contain an invalid digit
code, a data exception is recognized, and the opera-
Code tion is either suppressed or terminated.
Name (Binary) (Hex)
At the time the left digit of a source byte is examined,
Digit Selector 0010 0000 20 the rightmost four bits are checked for the existence
Significance starter 0010 0001 21 of a sign code. When a sign code is encountered in
Field separator 0010 0010 22 the rightmost four bit positions, these bits are not
Message byte Any other Any other treated as a decimal-digit code, and a new source
byte is fetched from storage when the next pattern
The detection of either a digit selector or a signifi- byte calls for a source-digit examination.
cance starter in the pattern causes an examination to
be made of the significance indicator and of a source When the pattern contains no digit selector or signifi-
digit. As a result, either the expanded source digit or cance starter, no source bytes are fetched and exam-
the fill byte, as appropriate, is selected to replace the ined.
pattern byte. Additionally, encountering a digit selec-
tor or a significance starter may cause the signifi- Significance Indicator: The significance indicator
cance indicator to be changed. is turned on or off to indicate the significance or non-
significance, respectively, of subsequent source dig-
The field separator identifies individual fields in a its or message bytes. Significant source digits
multiple-field editing operation. It is always replaced replace their corresponding digit selectors or signifi-
in the result by the fill byte, and the significance indi- cance starters in the result. Significant message
cator is always off after the field separator is encoun- bytes remain unchanged in the result.
tered.
The significance indicator, by its on or off state, indi-
cates also the negative or positive value, respec-
EDIT
factor in the setting of the condition code. considered to be of zero length.
The significance indicator is set to off at the start of Condition code 0 is set when the last field edited is
the editing operation, after a field separator is zero or of zero length.
encountered, or after a source byte is examined that
has a plus code in the rightmost four bit positions. Condition code 1 is set when the last field edited is
nonzero and the significance indicator is on. (This
The significance indicator is set to on when a signifi- indicates a result less than zero if the last source
cance starter is encountered whose source digit is a byte examined contained a sign code in the rightmost
valid decimal digit, or when a digit selector is encoun- four bits.)
tered whose source digit is a nonzero decimal digit,
provided that in both instances the source byte does Condition code 2 is set when the last field edited is
not have a plus code in the rightmost four bit posi- nonzero and the significance indicator is off. (This
tions. indicates a result greater than zero if the last source
byte examined contained a sign code in the rightmost
In all other situations, the significance indicator is not four bits.)
changed. A minus sign code has no effect on the
significance indicator. For the purposes of setting condition codes 2 or 3,
the significance indicator is examined after the pro-
Result Bytes: The result of an editing operation cessing of the last source digit.
replaces and is equal in length to the pattern. It is
composed of pattern bytes, fill bytes, and zoned Figure 8-3 on page 8-10 summarizes the functions of
source digits. the EDIT and EDIT AND MARK operations. The left-
most four columns list all the significant combinations
If the pattern byte is a message byte and the signifi- of the four conditions that can be encountered in the
cance indicator is on, the message byte remains execution of an editing operation. The rightmost two
unchanged in the result. If the pattern byte is a field columns list the action taken for each case — the
separator or if the significance indicator is off when a type of byte placed in the result field and the new set-
message byte is encountered in the pattern, the fill ting of the significance indicator.
byte replaces the pattern byte in the result.
Resulting Condition Code:
If the digit selector or significance starter is encoun-
tered in the pattern with the significance indicator off 0 Last field zero or zero length
and the source digit zero, the source digit is consid- 1 Last field less than zero
ered nonsignificant, and the fill byte replaces the pat- 2 Last field greater than zero
tern byte. If the digit selector or significance starter is 3 --
encountered either with the significance indicator on
or with a nonzero decimal source digit, then the Program Exceptions:
source digit (a) is considered significant, (b) is
changed to the zoned format, and (c) replaces the • Access (fetch, operand 2; fetch and store, oper-
pattern byte in the result. Examination of the signifi- and 1)
cance indicator occurs prior to the processing of the • Data
source digit (which might change the significance
indicator). Programming Notes:
Condition Code: The sign and magnitude of the 1. Examples of the use of the EDIT instruction are
last field edited are used to set the condition code. given in Appendix A, “Number Representation
The term “last field” refers to those source digits, if and Instruction-Use Examples.”
any, in the second operand selected by digit selec-
tors or significance starters after the last field separa- 2. Editing includes sign and punctuation control,
tor; if the pattern contains no field separator, there is and the suppression of leading zeros by replac-
only one field, which is considered to be the last field. ing them with blanks, or the protection of leading
zeros from malicious alteration by replacing them
Conditions Results
Previous State of State of Significance
Significance Right Four Source Indicator at End of
Pattern Byte Indicator Source Digit Bits Are Plus Code Result Byte Digit Examination
0 * Fill byte Off
Off No Source digit# On
1-9
Digit selector Yes Source digit# Off
No Source digit On
On 0-9
Yes Source digit Off
No Fill byte On
0
Yes Fill byte Off
Off
No Source digit# On
Significance starter 1-9
Yes Source digit# Off
No Source digit On
On 0-9
Yes Source digit Off
Field separator * ** ** Fill byte Off
Off ** ** Fill byte Off
Message byte
On ** ** Message byte On
Explanation:
with asterisks or other characters. It also facili- code reflects the sign and value only of the field
tates programmed blanking of all-zero fields. following the last field separator.
Several fields may be edited in one operation,
and numeric information may be combined with 7. Significant performance degradation is possible
text. when the second-operand address of an EDIT
instruction designates a location that is closer to
3. In most cases, the source is shorter than the pat- the left of an access boundary than the length of
tern because each four-bit source digit produces the first operand of that instruction (for the pur-
an eight-bit byte in the result. poses of this discussion, an access boundary is
4 K-bytes, except when fetch-protection override
4. The total number of digit selectors and signifi- applies in which case it is 2 K-bytes). This is
cance starters in the pattern always equals the because the machine may perform a trial execu-
number of source digits edited. tion of the instruction to determine if the second
5. If the fill byte is a blank, if no significance starter operand actually crosses the boundary. The sec-
exists in the pattern, and if the source digit exam- ond operand of EDIT, while normally shorter than
ined for each digit selector is zero, the editing the first operand, can in the extreme case have
operation blanks the result field. the same length as the first.
MULTIPLY DECIMAL
contains one or more decimal numbers in the signed- inserted in general register 1 is one greater than
packed-decimal or unsigned-packed-decimal format, the address where a floating currency-sign would
is changed to the zoned format and modified under be inserted.
the control of the first operand (the pattern). The
address of the first significant result byte of the right- 3. No address is inserted in general register 1 when
most (or only) field is inserted in general register 1. the significance indicator is turned on as a result
The edited result replaces the pattern. of encountering a significance starter with the
corresponding source digit zero. To ensure that
EDIT AND MARK is identical to EDIT, except for the general register 1 contains a proper address
additional function of inserting the address of the when this occurs, the address of the pattern byte
result byte in general register 1 if the result byte is a that immediately follows the appropriate signifi-
zoned source digit and the significance indicator was cance starter could be placed in the register
off before the examination of the source bytes. If no beforehand.
result byte meets the criteria, general register 1 4. When multiple fields are edited with one execu-
remains unchanged; if more than one result byte tion of the EDIT AND MARK instruction, the
meets the criteria, the address of the rightmost such address, if any, inserted in general register 1
result byte is inserted. applies to the rightmost field edited for which the
criteria were met.
In the 24-bit addressing mode, the address replaces
bits 40-63 of general register 1, and bits 0-39 of the 5. See also the programming note under EDIT
register are not changed. In the 31-bit addressing regarding performance degradation due to a pos-
mode, the address replaces bits 33-63 of general sible trial execution.
register 1, bit 32 of the register is set to zero, and bits
0-31 of the register remain unchanged. In the 64-bit
addressing mode, the address replaces bits 0-63 of MULTIPLY DECIMAL
general register 1.
MP D1(L1,B1),D2(L2,B2) [SS-b]
The contents of access register 1 remain unchanged. 'FC' L1 L2 B1 D1 B2 D2
0 8 12 16 20 32 36 47
See Figure 8-3 on page 8-10 for a summary of the
EDIT and EDIT AND MARK operations.
The product of the first operand (the multiplicand)
Resulting Condition Code: and the second operand (the multiplier) is placed at
the first-operand location. The operands and result
0 Last field zero or zero length are in the signed-packed-decimal format.
1 Last field less than zero
2 Last field greater than zero The multiplier length cannot exceed 15 digits and
3 -- sign (L2 not greater than seven) and must be less
than the multiplicand length (L2 less than L1); other-
Program Exceptions: wise, a specification exception is recognized.
• Access (fetch, operand 2; fetch and store, oper- The multiplicand must have at least as many bytes of
and 1) leftmost zeros as the number of bytes in the multi-
• Data plier; otherwise, a data exception is recognized. This
restriction ensures that no product overflow occurs.
Programming Notes:
The multiplicand, multiplier, and product are each
1. Examples of the use of the EDIT AND MARK signed decimal integers in the signed-packed-deci-
instruction are given Appendix A, “Number Rep- mal format and are right-aligned in their fields. All
resentation and Instruction-Use Examples.” sign and digit codes of the multiplicand and multiplier
are checked for validity. The sign of the product is
2. EDIT AND MARK facilitates the programming of determined by the rules of algebra from the multiplier
floating currency-symbol insertion. Using appro-
The first operand is considered to be in the signed- A data exception is recognized when the first oper-
packed-decimal format. Only its digit portion is and does not have valid sign and digit codes or when
shifted; the sign position does not participate in the the rounding digit is not a valid digit code. The valid-
shifting. Zeros are supplied for the vacated digit ity of the first-operand codes is checked even when
positions. The result replaces the first operand. no shift is specified, and the validity of the rounding
Nothing is stored outside of the specified first-oper- digit is checked even when no addition for rounding
and location. takes place.
4. When the B2 field is zero, the six-bit shift value is Program Exceptions:
obtained directly from bits 42-47 of the instruc-
tion. • Access (fetch, operand 1)
• Operation (if the extended-translation facility 2 is
not installed)
SUBTRACT DECIMAL
SP D1(L1,B1),D2(L2,B2) [SS-b] ZERO AND ADD
'FB' L1 L2 B1 D1 B2 D2
0 8 12 16 20 32 36 47
ZAP D1(L1,B1),D2(L2,B2) [SS-b]
'F8' L1 L2 B1 D1 B2 D2
The second operand is subtracted from the first oper- 0 8 12 16 20 32 36 47
• Access (fetch, operand 2; fetch and store, oper- In the absence of overflow, the sign of a zero result is
and 1) made positive. If overflow occurs, a zero result is
• Data given the sign of the second operand but with the
• Decimal overflow preferred sign code.
Floating-point instructions are used to perform calcu- significand. By choosing the appropriate bias, any
lations on operands having a wide range of magni- finite floating-point number can be considered in any
tude and to obtain results scaled to preserve of these views, or even in another view. For the first
precision. three of these views, the bias is called the fraction-
view bias, left-units-view bias, and right-units-view
Floating-point operands have formats based on three bias, respectively. Except where otherwise indicated,
radixes: 2, 10, or 16. These radix values lead to the HFP is defined in terms of the fraction view, BFP
terminology “binary,” “decimal,” and “hexadecimal” terms of the left-units view, and DFP in terms of the
floating point (BFP, DFP, and HFP), respectively. The right-units view.
formats are also based on three operand lengths:
short (32 bits), long (64 bits), and extended (128 For HFP, the significand is considered to be a fraction
bits). Short operands require less storage than long with the implied radix point on the left. In this view,
or extended operands. On the other hand, long and the significand is referred to as the fraction. For BFP,
extended operands permit greater precision in com- the significand consists of an implicit unit digit to the
putation. left of an implied radix point and an explicit fraction
field to the right. For DFP, the significand is consid-
Sign Bit ered to be an integer with the implied radix point on
All floating-point data have a sign bit. The sign bit is the right.
zero for plus and one for minus.
Infinities
Finite Floating-Point Numbers BFP and DFP data include an infinite numeric datum,
A finite floating-point number has three components: called infinity. Infinities can participate in most arith-
a sign bit, an exponent, and a significand. The mag- metic operations and give a consistent result, usually
nitude (an unsigned value) of the number is the prod- infinity. An infinity has a sign bit. In comparisons,
uct of the significand and the radix raised to the infinities of the same sign compare equal, +∞ com-
power of the exponent. The number is positive or pares greater than any finite number, and -∞ com-
negative depending on whether the sign bit is zero or pares less than any finite number.
one, respectively.
Not-A-Number (NaN)
The significand consists of a string of digits, where
each digit is an integral value from zero to one less
BFP and DFP data types include a nonnumeric
than the radix (2, 10, or 16). (Thus, a BFP digit is one
datum, called not-a-number (or NaN). A NaN is pro-
bit, an HFP digit is four bits, and a DFP digit is a
duced in place of a numeric result after an invalid
value from zero to nine.) The number of digit posi-
operation when there is no IEEE trap action. NaNs
tions in the significand is called the precision of the
may also be used by the program to flag special
floating-point number. The significand has an implied
operands, such as the contents of an uninitialized
radix point, which, depending on the view, may be
storage area. A NaN has a sign bit, a NaN-type bit,
considered to be on the left, to the right of the left-
and a payload.
most digit, on the right, or elsewhere.
B BFP.
BE or C Biased exponent of BFP number, combination field of DFP number, or characteristic of HFP number.
D DFP.
H HFP.
S Sign.
Figure 9-2. Examples of Floating-Point Numbers in Short Format
B BFP.
BE or C Biased exponent of BFP number, combination field of DFP number, or characteristic of HFP number.
D DFP.
H HFP.
S Sign.
Figure 9-3. Examples of Floating-Point Numbers in Long Format
I I I I I I SSSSSS y
A datum in the extended (128-bit) format occupies a MMMMMM 0 0 F F F F F F 0 0 i z o u x / 0 DRM 0 BRM
register pair. Register pairs are formed by coupling i z o u x q i z o u x q q
the 16 registers as follows: 0 and 2, 4 and 6, 8 and I Byte 0 J I Byte 1 J I Byte 2 J I Byte 3 J
10, 12 and 14, 1 and 3, 5 and 7, 9 and 11, and 13
Figure 9-5. FPC Register Overview
and 15.
Byte Bit(s) Name Abbr.
Each of the eight pairs is referred to by the number of
the lower-numbered register of the pair. 0 0 IEEE-invalid-operation mask IMi
0 1 IEEE-division-by-zero mask IMz
Additional Floating-Point (AFP) 0 2 IEEE-overflow mask IMo
Registers 0 3 IEEE-underflow mask IMu
Floating-point registers 0, 2, 4, and 6 are ones that 0 4 IEEE-inexact mask IMx
were originally available on ESA/390 models. The 0 5 Quantum-exception mask IMq
remaining 12 floating-point registers (1, 3, 5, and 7- 0 6-7 (Unassigned) 0
15) were added to ESA/390 and are referred to as
1 0 IEEE-invalid-operation flag SFi
the additional floating-point (AFP) registers. The AFP
1 1 IEEE-division-by-zero flag SFz
registers can be used only if bit 45 of control register
0, the AFP-register-control bit, is one. Attempting to 1 2 IEEE-overflow flag SFo
use an AFP register when the AFP-register-control 1 3 IEEE-underflow flag SFu
bit is zero results in an AFP-register data exception 1 4 IEEE-inexact flag SFx
(DXC 1). 1 5 Quantum-exception flag SFq
1 6-7 (Unassigned) 0
Valid Floating-Point-Register 2 0-7 Data-exception code DXC
Designations 3 0 (Unassigned) 0
Any installed register may be designated by an
3 1-3 DFP rounding mode DRM
instruction to specify the register location of a short
3 4 (Unassigned) 0
or long floating-point operand.
3 5-7 BFP rounding mode BRM
An instruction specifying a floating-point operand in Figure 9-6. FPC-Register Bit Assignments
the extended format must designate register 0, 1, 4,
5, 8, 9, 12, or 13; otherwise, a specification exception
is recognized.
Floating-Point-Control (FPC)
Register
The floating-point-control (FPC) register is a 32-bit
register that contains mask bits, flag bits, a data-
exception code, and two rounding-mode fields. An
overview of the FPC register is shown in Figure 9-5.
Bit 45 of control register 0 is the AFP-register-control Handling of the case when more than one source
bit. The AFP registers, the BFP instructions, the DFP operand is a NaN is covered in the individual instruc-
instructions, and PFPO can be used successfully tion descriptions.
only when the AFP-register-control bit is one.
Attempting to use one of the 12 additional floating- In the absence of a NaN, if an operand is an infinity,
point registers or executing PFPO when the AFP- special “infinity arithmetic” rules are followed to pro-
register-control bit is zero results in an AFP-register duce the result.
data exception (DXC 1). Attempting to execute any
BFP instruction when the AFP-register-control bit is Programming Note: PERFORM FLOATING-POINT
zero results in a BFP-instruction data exception OPERATION is an IEEE computational operation.
(DXC 2). Attempting to execute any DFP instruction
when the AFP-register-control bit is zero results in a
DFP-instruction data exception (DXC 3).
Intermediate Values
DXC 2 and 3 are mutually exclusive and are of higher In the normal case (when all source operands are
priority than any other DXC. Thus, for example, DXC finite numbers), first, a precise intermediate value is
2 (BFP instruction) takes precedence over any IEEE produced, then a rounded intermediate value. In the
exception; and DXC 3 (DFP instruction) takes prece- absence of trapped overflow and trapped underflow,
dence over any IEEE exception. As another example, the rounded intermediate value is used as the deliv-
if the conditions for both DXC 3 (DFP instruction) and ered value. For trapped overflow and trapped under-
DXC 1 (AFP register) exist, DXC 3 is reported. flow, the rounded intermediate value is divided by a
scale factor to produce a scaled value, which is used
If the conditions for both a data exception and a as the delivered value. Finally, the delivered value is
specification exception exist, it is unpredictable which placed in the target location. For DFP, since the
exception is reported. cohort for the delivered value may have multiple
members, one member from the cohort must be
The initial value of the AFP-register-control bit is selected. Selection is performed by choosing the
zero. member having a quantum closest to the preferred
Scaled Value Where b is the radix (2, 10, and 16) for BFP, DFP and
For both overflow and underflow when the associated HFP, respectively. Thus, for overflow, the signed scal-
trap is enabled, the precision-rounded value is scaled ing exponent (Ω) is a positive value, and for under-
to bring it into the representable exponent range of flow it is a negative value.
the target. This is called the scaled value and is
derived as explained in the next section.
1
Decimal Binary
Common- Common-
Left-Units Right-Units Rounding- Left-Units Right-Units Rounding-
Participant View View Point View View View Point View
Input Value 2.95%101 295%10-1 29.5%100 1.11011%24 111011%2-1 11101.1%20
Candidate TZ 2.9%101 29%100 29.0%100 1.1101%24 11101%20 11101.0%20
1 1 0 4 1
Candidate AZ 3.0%10 3%10 30.0%10 1.111%2 1111%2 11110.0%20
Explanation:
1
Significand is shown in binary, exponent in decimal.
Figure 9-10. LOAD FP INTEGER - Decimal and Binary
IEEE Exceptions
This section defines handling of IEEE exceptions for
most IEEE computational operations. For some
instructions the action may differ from the general
The action taken for each IEEE exception is con- IEEE Invalid Operation
trolled by a mask bit in the FPC register. When an An IEEE-invalid-operation exception is recognized
IEEE exception is recognized, one of two actions is when, in the execution of an IEEE computational
taken: operation, any of the following occurs:
• If the corresponding mask bit in the FPC register 1. An SNaN is encountered in an IEEE computa-
is zero, a default action, called IEEE nontrap tional operation.
action, is taken, as specified for each condition,
and the corresponding flag bit in the FPC register 2. A QNaN is encountered in an unordered-signal-
is set to one. Program execution then continues ing comparison (COMPARE AND SIGNAL with a
normally. QNaN operand).
• If the corresponding mask bit in the FPC register 3. An IEEE difference is undefined (addition of infin-
is one, an action, called IEEE trap action, is ities of opposite sign, or subtraction of infinities of
taken for that exception, a program interruption like sign).
for a data exception occurs, and the operation is 4. An IEEE product is undefined (zero times infin-
suppressed or completed, depending on the ity).
exception, and the data-exception code (DXC)
assigned for that exception is provided. For 5. An IEEE quotient is undefined (DIVIDE instruc-
PFPO, a control bit in GR0 can select alternate tion with both operands zero or both operands
exception handling, where overflow or underflow infinity).
can be reflected by completion with a distin-
guished condition code, avoiding the interruption. 6. A BFP remainder is undefined (DIVIDE TO INTE-
GER with a dividend of infinity or a divisor of
zero).
Concurrent IEEE Exceptions
IEEE-overflow or IEEE-underflow exception, IEEE- 7. A BFP square root is undefined (negative non-
inexact exception, and quantum exception can coin- zero operand).
cide concurrently.
8. Any other IEEE computational operation whose
When the action for IEEE overflow (or underflow) is a result is either undefined or not representable in
nontrap action, the IEEE-overflow (or IEEE-under- the target format.
flow) flag bit in the FPC register is set to one and
then the action for IEEE inexact (which could be a Even though an invalid-operation condition exists, the
nontrap or trap action) occurs. exception is not recognized if recognition of the
exception is suppressed by means of an IEEE-
When the action for IEEE overflow (or underflow) is a invalid-operation-exception control (XiC).
trap action, the inexact exception is not recognized
and not reported directly; instead, the DXC is set to IEEE-Invalid-Operation Nontrap Action: IEEE-
indicate whether the result is exact, inexact and trun- invalid-operation nontrap action occurs when the
cated, or inexact and incremented. IEEE-invalid-operation exception is recognized and
the IEEE-invalid-operation mask bit in the FPC regis-
When the action for all concurrent IEEE exceptions, ter is zero. The operation is completed and the IEEE-
except the quantum exception, is a nontrap action, invalid-operation flag bit in the FPC register is set to
the flag bits in the FPC register corresponding to one. The result of the operation depends on the type
these nontrap concurrent exceptions are set to one, of operation and the operands.
and then the action for the quantum exception (which
could be a nontrap or trap action) occurs. If the instruction performs a comparison, the compar-
ison result is unordered.
IEEE Division-By-Zero 4. For round toward -∞, the result is the largest pos-
An IEEE-division-by-zero exception is recognized itive finite number if the sign is plus or -∞. if the
when in IEEE division the divisor is zero and the divi- sign is minus.
dend is a nonzero finite number.
IEEE-Overflow Trap Action: IEEE-overflow trap
IEEE-Division-By-Zero Nontrap Action: IEEE- action occurs when the IEEE-overflow exception is
division-by-zero nontrap action occurs when the recognized and the IEEE-overflow mask bit in the
IEEE-division-by-zero exception is recognized and FPC register is one.
the IEEE-division-by-zero mask bit in the FPC regis-
ter is zero. The operation is completed and the IEEE- The operation is completed by setting the result to
division-by-zero flag bit in the FPC register is set to the scaled value and the exception is reported as a
one. The result is set to an infinity with a sign that is program interruption for a data exception with DXC
the exclusive or of the dividend and divisor signs. 20, 28, or 2C hex, depending on whether the deliv-
ered value is exact, inexact and truncated, or inexact
IEEE-Division-By-Zero Trap Action: IEEE-divi- and incremented, respectively.
sion-by-zero trap action occurs when the IEEE-divi-
sion-by-zero exception is recognized and the IEEE- The result of the operation is derived from the preci-
division-by-zero mask bit in the FPC register is one. sion-rounded value, the scale factor, and, for DFP, on
The operation is suppressed, and the exception is the scaled preferred quantum. The value of the scale
reported as a program interruption for a data excep- factor depends on the type of operation and operand
tion with DXC 40 hex. format. The scaled preferred quantum for a particular
operation is equal to the preferred quantum for that
operation divided by the scale factor for that opera-
IEEE Overflow tion.
An IEEE-overflow exception is recognized for an
IEEE target when the precision-rounded value of an The delivered value is equal to the precision-rounded
IEEE computational operation is greater in magni- value divided by the scale factor. For DFP targets,
tude than the largest finite number (Nmax) represent- the cohort member with the quantum nearest to the
able in the target format. scaled preferred quantum is selected.
The tininess condition exists when the precise inter- An inexact condition exists when the rounded inter-
mediate value of an IEEE computational operation is mediate value differs from the precise intermediate
nonzero and smaller in magnitude than the smallest value. The condition also exists when IEEE-overflow
normal number (Nmin) representable in the target nontrap action occurs. When the inexact condition
format. exists, the delivered value and the result are said to
be inexact.
The denormalized value is inexact if it is not equal to
the precise intermediate value. Even though an inexact condition exists, the IEEE-
inexact exception is not recognized if recognition of
IEEE-Underflow Nontrap Action: IEEE-under- the exception is suppressed by means of an IEEE-
flow nontrap action occurs when the IEEE-underflow inexact-exception control (XxC) or if IEEE overflow or
exception is recognized and the IEEE-underflow IEEE underflow trap action occurs. When an inexact
mask bit in the FPC register is zero. condition exists and the conditions for an IEEE-over-
flow trap action or IEEE-underflow trap action also
The operation is completed and the IEEE-underflow apply, the trap action takes precedence and the inex-
flag bit in the FPC register is set to one. The result is act condition is reported in the DXC.
set to the denormalized value. For DFP targets, the
cohort member with the smallest quantum is IEEE-Inexact Nontrap Action: IEEE-inexact non-
selected. trap action occurs when the IEEE-inexact exception
is recognized and the IEEE-inexact mask bit in the
IEEE-Underflow Trap Action: IEEE-underflow FPC register is zero.
trap action occurs when the IEEE-underflow excep-
tion is recognized and the IEEE-underflow mask bit In the absence of another IEEE nontrap action, the
in the FPC register is one. operation is completed using the rounded intermedi-
ate value and the IEEE-inexact flag bit in the FPC
The operation is completed by setting the result to register is set to one. For DFP targets, except for
the scaled value and the exception is reported as a QUANTIZE and REROUND, the cohort member with
program interruption for a data exception with DXC the smallest quantum is selected.
10, 18, or 1C hex, depending on whether the deliv-
ered value is exact, inexact and truncated, or inexact When an IEEE-inexact nontrap action and another
and incremented, respectively. IEEE nontrap action coincide, the operation is com-
pleted using the result specified for the other excep-
The result of the operation is derived from the preci- tion and the flag bits for both exceptions are set to
sion-rounded value, the scale factor and, for DFP, on one.
the scaled preferred quantum. The value of the scale
factor depends on the type of operation and operand IEEE-Inexact Trap Action: IEEE-inexact trap
format. The scaled preferred quantum for a particular action occurs when the IEEE-inexact exception is
operation is equal to the preferred quantum for that recognized and the IEEE-inexact mask bit in the FPC
operation divided by the scale factor for that opera- register is one. The operation is completed and the
tion. exception is reported as a program interruption for a
data exception with DXC 08 or 0C hex, depending on
The result is set to the precision-rounded value whether the result is inexact and truncated or inexact
divided by the scale factor. For DFP targets, the and incremented, respectively.
cohort member with the quantum nearest to the
scaled preferred quantum is selected. In the absence of a coincident IEEE nontrap action,
the delivered value is set to the rounded intermediate
IEEE Inexact value. For DFP targets, the cohort member with the
An IEEE-inexact exception is recognized when, for smallest quantum is selected.
an IEEE computational operation, an inexact condi-
tion exists, recognition of the exception is not sup- When the IEEE-inexact trap action coincides with an
IEEE nontrap action, the operation is completed
For LOAD FP INTEGER, QUANTIZE, and In the absence of a coincident IEEE nontrap action,
REROUND, a quantum-exception condition exists the delivered value is set to the rounded intermediate
when the delivered DFP result is a finite number, but value, and the delivered result, if it is a finite number,
the delivered quantum is different from the quantum is the cohort member with the quantum closest to the
of the source operand (the second operand for LOAD preferred quantum.
FP INTEGER, and the third operand for QUANTIZE
and REROUND). When the quantum-exception trap action coincides
with other IEEE nontrap actions, the operation is
For PERFORM FLOATING-POINT OPERATION, a completed using the result specified for the other
quantum-exception condition exists when the deliv- IEEE nontrap actions, the flag bits for the other IEEE
ered quantum exceeds the preferred quantum of 1. nontrap exceptions are set to one, and the quantum-
exception trap action takes place.
When floating-point extension facility is not installed,
no quantum exception is recognized by executing Programming Notes:
any instruction.
1. IEEE traps are reported by means of a program
interruption for a data exception with a data-
exception code.1 The use of data exception pro-
Items a and d are supplied as part of the inter- c. The difference between detection of loss of
ruption action. Items b, c, and e can be obtained accuracy as a denormalization loss or as an
starting with the instruction address in the old inexact result can best be understood by
PSW and from this finding the instruction (which considering three intermediate values:
indicates the operation and format) and then the (1) the precise intermediate value, which has
operands. unbounded precision and unbounded expo-
nent range, (2) the precision-rounded
3. The description of underflow is one of the most value, which is obtained by rounding the pre-
difficult parts of the standard to understand. This cise intermediate value to the precision of
is because: the target format but with unbounded expo-
nent range, and (3) the denormalized value,
a. The condition is described as two “correlated which is obtained by rounding the precise
events” — “tininess” and “loss of accuracy”. intermediate value to the precision and expo-
b. For tininess, ANSI/IEEE Standard 754-1985 nent range of the target format. An inexact
provides two options for detection: “after condition is said to exist when the denormal-
rounding” or “before rounding”. ized value (3) differs from the precise inter-
mediate value (1). A denormalization loss is
c. For loss of accuracy, ANSI/IEEE Standard said to exist when the denormalized value
754-1985 provides two options for detection: (3) differs from the precision-rounded value
“denormalization loss” or “inexact result”. (2). The two options differ in the case when
the denormalized value (3) is equal to the
d. Implementation of the trap is optional. precision-rounded value (2) but these are not
e. The conditions to signal underflow are differ- equal to the precise intermediate value (1).
ent depending on whether or not the trap is Although ANSI/IEEE Standard 754-1985
taken. uses the term “denormalization loss”, this
1. PFPO provides an option for trap action without the program interruption.
Mne- Op
Name monic Characteristics Code Page
CONVERT BFP TO HFP (long) THDR RRE C Da B359 9-27
CONVERT BFP TO HFP (short to long) THDER RRE C Da B358 9-27
CONVERT HFP TO BFP (long) TBDR RRF-e C SP Da B351 9-28
CONVERT HFP TO BFP (long to short) TBEDR RRF-e C SP Da B350 9-28
COPY SIGN (long) CPSDR RRF-b FS Da B372 9-29
EXTRACT FPC EFPC RRE Db B38C 9-30
LOAD (extended) LXR RRE SP Da B365 9-30
Figure 9-17. Summary of Floating-Point-Support Instructions
CONVERT HFP TO BFP See Figure 9-20 on page 9-29 for a detailed descrip-
tion of the results of this instruction.
Mnemonic R1,M3,R2 [RRF-e]
If the M3 field designates any of the following invalid
Op Code M3 / / / / R1 R2 modifier values: 2 and 8-15, then a specification
0 16 20 24 28 31 exception is recognized. When the floating-point
extension facility is not installed, if the M3 field desig-
Mnemonic Op Code Operands
TBEDR 'B350' Long HFP operand, short BFP result nates the invalid value 3, it is undefined whether a
TBDR 'B351' Long HFP operand, long BFP result specification exception is recognized or an unpredict-
able rounding method is performed.
The second operand (the source operand) is con-
verted from the hexadecimal-floating-point (HFP) for- Resulting Condition Code:
mat to the binary-floating-point (BFP) format, and the
result rounded according to the rounding method 0 Source was zero
specified by the M3 field is placed at the first-operand 1 Source was less than zero
location. The sign and magnitude of the source oper- 2 Source was greater than zero
and are tested to determine the setting of the condi- 3 Special case
tion code.
Program Exceptions:
The M3 field contains a modifier specifying a round-
ing method, as follows: • Data with DXC 1, AFP register
• Specification
M3 Effective Rounding Method
0 Round toward 0 Programming Notes:
1 Round to nearest with ties away from 0
3 Round to prepare for shorter precision 1. The HFP-to-BFP conversion instructions are
4 Round to nearest with ties to even summarized in Figure 9-19 on page 9-28.
5 Round toward 0 2. Conversion to short BFP data requires HFP
6 Round toward +∞ operands in the long format; a short HFP oper-
7 Round toward -∞ and should be extended to long by ensuring that
the right half of the register is cleared. Thus, the
A modifier other than 0, 1, or 3-7 is invalid. If the float- entire register should be cleared before loading a
ing-point extension facility is not installed, an M3 mod- short HFP operand into it for conversion to BFP.
ifier of 3 is also invalid. This avoids unrepeatable rounding errors in the
BFP result due to data left over from previous
The sign of the result is the sign of the second oper- use.
and. If the second operand has a sign bit of one and
all other operand bits are zeros, the result also is a
one followed by all zeros.
Programming Notes:
The second operand is placed at the first-operand
location with the sign bit set to the sign of the third 1. COPY SIGN is radix independent and can be
operand. The first, second, and third operands are used to operate on HFP, BFP, or DFP operands
each in a 64-bit floating-point register. The sign bit of or even to copy the sign between operands hav-
the second operand and bits 1-63 of the third oper- ing different radixes.
and are ignored.
2. Since the sign is in the same bit position (the left-
most bit) in all widths for all radixes, the third
Condition Code: The code remains unchanged.
Condition Code: The code remains unchanged. The displacement for LE and LD is treated as a 12-bit
unsigned binary integer. The displacement for LEY
IEEE Exceptions: None. and LDY is treated as a 20-bit signed binary integer.
0 16 24 28 31
2. LOAD COMPLEMENT (LCDFR) can be used in 2. When the floating-point extension facility is
conjunction with LOAD (LDR) to set the sign of installed, bits 29-31 of the second operand must
an operand in the extended format. specify a valid BFP rounding mode and bits 6-7,
14-15, 24, and 28 must be zero; otherwise, a
specification exception is recognized.
LOAD FPC
3. When the floating-point extension facility is not
LFPC D2(B2) [S] installed, bits 5-7, 13-15, 24, and 28-29 are
unassigned and must be zero; otherwise, a spec-
'B29D' B2 D2
ification exception is recognized.
0 16 20 31
The four-byte second operand in storage is loaded LOAD FPC AND SIGNAL
into the FPC (floating-point-control) register.
LFAS D2(B2) [S]
Bits corresponding to unsupported bit positions in the 'B2BD' B2 D2
FPC register must be zero; otherwise, a specification 0 16 20 31
exception is recognized. For purposes of this check-
ing, a bit position is considered to be unsupported
only if it is either unassigned or assigned to a facility First, flags of byte 1 of the floating-point-control
which is not installed in any architectural mode of the (FPC) register at the beginning of the operation are
configuration. preserved to be used as signaling flags. Next, the
contents of the source operand are placed in the
When the floating-point extension facility is installed, FPC register; then the flags in the FPC register are
the bits corresponding to the BFP rounding mode set to the logical OR of the signaling flags and the
must specify a valid rounding mode; otherwise, a source flags. Finally, the conditions for simulated-
specification exception is recognized. IEEE-exception trap action are examined.
Condition Code: The code remains unchanged. The source operand is the second operand in stor-
age.
IEEE Exceptions: None.
If any signaling flag is one and the corresponding
Program Exceptions: source mask is also one, simulated-IEEE-exception
trap action occurs. The data-exception code (DXC) in
• Access (fetch, operand 2) the FPC register is updated to indicate the specific
• Data with DXC 2, BFP instruction cause of the interruption and a data-exception pro-
• Specification gram interruption occurs at completion of the instruc-
tion execution. The DXC for the interruption is shown
Programming Notes: in Figure 9-21.
1. When the architectural mode of a CPU is If no signaling flag is enabled, the DXC in the FPC
changed without resetting the FPC register (by register remains as loaded from the source and
means of the set architecture signal-processor instruction execution completes with no trap action.
order, for example) the entire contents of the
FPC register are preserved. This is true even See Figure 9-22 for a detailed description of the
when some of these bits are associated with a result of this instruction.
facility which is not available in both architectural
modes. Checking for unsupported bit positions of Bits in the source operand that correspond to unsup-
ported bit positions in the FPC register must be zero;
LOAD NEGATIVE
DXC indicate the type of IEEE exception. Addi- installed)
tional information required by the trap handler
can be determined by the contents of a trap-
information block, located by convention, at a LOAD GR FROM FPR
fixed offset from the location where the instruc-
tion causing the trap resides. LGDR R1,R2 [RRE]
'B3CD' / / / / / / / / R1 R2
The following shows an example of this scheme.
0 16 24 28 31
The block and the code below are inserted at an
appropriate place where a trap can occur. In this
example, the LOAD FPC AND SIGNAL instruc- The second operand is placed at the first-operand
tion is used, and the caller's FPC register con- location. The second operand is in a floating-point
tents are at the location, SAVEDFPC. register, and the first operand is in a general register.
Program Exceptions:
The operation specified by the function code in gen-
• Data with DXC 1, AFP register eral register 0 is performed and the condition code is
• Operation (if the floating-point-support-sign-han- set to indicate the result. When there are no excep-
dling facility is not installed) tional conditions, condition code 0 is set. When an
IEEE nontrap exception is recognized, condition
Programming Notes: code 1 is set. When an IEEE trap exception with
alternate action is recognized, condition code 2 is
1. LOAD POSITIVE (LPDFR) is radix independent set. A 32-bit return code is placed in bits 32-63 of
and can be used to operate on HFP, BFP, or DFP general register 1; bits 0-31 of general register 1
operands. remain unchanged.
2. LOAD POSITIVE (LPDFR) can be used in con- The PERFORM FLOATING-POINT OPERATION
junction with LOAD (LDR) to set the sign of an (PFPO) instruction is subject to the AFP-register-
operand in the extended format. control bit, bit 45 of control register 0. For PFPO to be
executed successfully, the AFP-register-control bit
must be one; otherwise, an AFP-register data excep-
LOAD ZERO tion, DXC 1, is recognized.
Mnemonic R1 [RRE]
Bit 32 of general register 0 is the test bit. When bit 32
Op Code / / / / / / / / R1 / / / / is zero, the function specified by bits 33-63 of general
0 16 24 28 31 register 0 is performed; each field in bits 33-63 must
be valid and the combination must be a valid and
Mnemonic Op Code Operands installed function; otherwise a specification exception
LZER 'B374' Short
is recognized. When bit 32 is one, the function speci-
LZDR 'B375' Long
fied by bits 33-63 is not performed but, instead, the
LZXR 'B376' Extended
condition code is set to indicate whether these bits
specify a valid and installed function; the condition
All bits of the first operand are set to zeros.
code is set to 0 if the function is valid and installed, or
to 3 if the function is invalid or not installed. This will
For LZXR, The R1 field must designate a valid float-
be useful if additional functions are assigned in the
ing-point-register pair; otherwise, a specification
future. This definition is written as if the test bit is zero
exception is recognized.
except when stated otherwise.
Condition Code: The code remains unchanged.
Bits 33-39 of GR0 specify the operation type. Only
one operation type is currently defined: 01, hex, is
Program Exceptions:
PFPO Convert Floating-Point Radix.
• Data with DXC 1, AFP register
For the PFPO-convert-floating-point-radix operation,
• Specification (LZXR only)
other fields in general register 0 include first-operand
When converting between DFP and BFP, the sign of Unnormalized HFP values are accepted on input, but
the NaN is always preserved, and the value of the all HFP results are normalized. If an HFP result
payload is preserved, when possible. If the value of would be less than the smallest (in magnitude) repre-
the source payload exceeds the maximum value of sentable normalized number, an HFP underflow con-
the target payload, the target is set to the default dition exists.
QNaN, but with the same sign as the source.
HFP Zero Result
When traps are disabled, an SNaN is converted to For PFPO-convert-BFP-to-HFP or PFPO-convert-
the corresponding QNaN, and the payload is pre- DFP-to-HFP functions, if the source operand is zero,
served, when possible; that is, SNaN(x) is converted the result has the same sign as that of the source
to QNaN(x), where x is the value of the payload. For operand, and has all zeros in fraction and character-
DFP, both QNaN(0) and SNaN(0) can be repre- istic.
sented; but in BFP, there is a representation for
QNaN(0), but not for SNaN(0).
HFP Overflow and Underflow for PFPO
For an HFP target of a PFPO-convert-floating-point-
Scaled Value and Signed Scaling radix operation, the handling of overflow and under-
Exponent (Ω) for PFPO flow conditions is controlled by the HFP-overflow
When, for the PFPO-convert-floating-point-radix control and the HFP-underflow control, respectively.
operation, IEEE-overflow trap action or IEEE-under-
flow trap action occurs, the scaled value is computed HFP Overflow: An HFP-overflow condition exists
using the following steps: when an HFP target precision's largest number
(Hmax) is exceeded in magnitude by the precision-
Ψ = bΩ rounded value. That is, when the characteristic of a
z=g+Ψ normalized HFP result would exceed 127 and the
fraction is not zero.
Where Ω is the signed scaling exponent, b is the tar-
get radix (2, 10, or 16), Ψ is the scale factor, g is the When the HFP-overflow control is zero, HFP-overflow
precision-rounded value, and z is the scaled value. is reported as an IEEE-invalid-operation exception
and is subject to the IEEE-invalid-operation mask in
The signed scaling exponent (Ω) is selected to make the FPC register. This is called an HFP-overflow-as-
the magnitude of the value of the scaled result (z) lie IEEE-invalid-operation condition.
in the range:
When the HFP-overflow control is one, HFP overflow
1 [ |z| < b. is reported as an IEEE-overflow exception and is
subject to the IEEE-overflow mask in the FPC regis-
The value of the signed scaling exponent (Ω), treated ter. This is called an HFP-overflow-as-IEEE-overflow
as a 32-bit signed binary integer, is placed in bits 32- condition.
63 of general register 1; bits 0-31 of general register
1 remain unchanged. HFP Underflow: An HFP-underflow condition
exists when the precision-rounded value is nonzero
The scaled value is used as the delivered value and and less in magnitude than the HFP target preci-
is placed in the result location. For DFP targets, the sion's smallest normalized number, Hmin. That is,
cohort member with the quantum nearest to the when the characteristic of a normalized HFP result
scaled preferred quantum is selected. (But it should would be less than zero and the fraction is not zero.
be noted that for all currently supported conversions, The result is set to a true zero with the same sign as
the result is always inexact, so the cohort member the source. Reporting of the HFP-underflow condition
with the smallest quantum is selected.) For BFP tar- is subject to the HFP-underflow control. The result in
gets, there are no redundant representations, there is this case, however, is inexact and is subject to the
only one member in a cohort. For HFP targets, the controls for that condition.
result is normalized.
When the HFP-underflow control is zero, the HFP-
underflow condition is not reported.
• When the target is HFP and the source is an Additional action depends on whether there is also
IEEE infinity, the result is Hmax with the same an IEEE-inexact exception or a quantum exception.
sign as the source.
together with an IEEE-inexact nontrap action, or with underflow exception is recognized when the tininess
a quantum-exception nontrap action, or with nontrap condition exists and either: (1) the IEEE-underflow
actions for both IEEE-inexact and quantum-excep- mask bit in the FPC register is zero and the denor-
tion, the IEEE flag bits in the FPC register for all the malized value is inexact, or (2) the IEEE-underflow
recognized exceptions are set to ones and condition mask bit in the FPC register is one.
code 1 is set.
The tininess condition exists when the precise inter-
When IEEE-overflow nontrap action and IEEE-inex- mediate value of an IEEE computational operation is
act trap action occur, the condition code is not set, nonzero and smaller in magnitude than the smallest
the IEEE-overflow flag bit in the FPC register is set to normal number (Nmin) representable in the target
one, and the IEEE-inexact exception is reported as a format.
program interruption for a data exception with DXC
08 or 0C hex, depending on whether the result is The denormalized value is inexact if it is not equal to
inexact and truncated or inexact and incremented, the precise intermediate value.
respectively.
For HFP targets, an IEEE-underflow exception is rec-
When IEEE-overflow nontrap action and quantum- ognized when the HFP-underflow condition exists
exception trap action occur, the condition code is not and the HFP-underflow control is one.
set, the IEEE-overflow flag bit in the FPC register is
set to one, and the quantum exception is reported as IEEE-Underflow Nontrap Action
a program interruption for a data exception with DXC IEEE-underflow nontrap action occurs when the
04 hex. When in addition an IEEE-inexact nontrap IEEE-underflow exception is recognized and the
action occurs, the IEEE-inexact flag bit in the FPC IEEE-underflow mask bit in the FPC register is zero.
register is set to one.
The operation is completed and the IEEE-underflow
IEEE-Overflow Trap Action flag bit in the FPC register is set to one.
IEEE-overflow trap action occurs when the IEEE-
overflow exception is recognized and the IEEE-over- For IEEE targets, the result is set to the denormal-
flow mask bit in the FPC register is one. ized value. For DFP targets, the cohort member with
the smallest quantum is selected.
The operation is completed by setting the result to
the scaled value; placing the value of the signed scal- For HFP targets, the result is set to a true zero with
ing exponent (Ω), treated as a 32-bit signed binary the same sign as the source.
integer in bits 32-63 of general register 1; and setting
DXC 20, 28, or 2C hex, depending on whether the Additional action depends on whether there is also
delivered value is exact, inexact and truncated, or an IEEE-inexact exception or a quantum exception.
inexact and incremented, respectively.
When IEEE-underflow nontrap action occurs, and
For DFP targets, the delivered value is always inex- neither IEEE-inexact exception nor quantum excep-
act and the cohort member with the smallest quan- tion has been recognized, the IEEE-underflow flag bit
tum is selected. in the FPC register is set to one and condition code 1
is set.
Additional action depends on the value of the alter-
nate-exception-action control. When an IEEE-underflow nontrap action occurs
together with an IEEE-inexact nontrap action, or with
When the alternate-exception-action control is zero, a quantum-exception nontrap action, or with nontrap
the condition code is not set and the exception is actions for both IEEE-inexact and quantum-excep-
reported as a program interruption for a data excep- tion, the IEEE flag bits in the FPC register for all the
tion. recognized exceptions are set to ones and condition
code 1 is set.
When the alternate-exception-action control is one,
condition code 2 is set and no program interruption When IEEE-underflow nontrap action and IEEE-inex-
occurs. act trap action occur, the condition code is not set,
Additional action depends on the value of the alter- IEEE-Inexact Trap Action
nate-exception-action control. IEEE-inexact trap action occurs when the IEEE-inex-
act exception is recognized and the IEEE-inexact
When the alternate-exception-action control is zero, mask bit in the FPC register is one. The operation is
the condition code is not set and the exception is completed, the condition code is not set, and the
reported as a program interruption for a data excep- exception is reported as a program interruption for a
tion. data exception with DXC 08 or 0C hex, depending on
whether the result is inexact and truncated or inexact
When the alternate-exception-action control is one, and incremented, respectively.
condition code 2 is set and no program interruption
occurs. In the absence of a coincident IEEE nontrap action,
the delivered value is set to the rounded intermediate
IEEE Inexact: An IEEE-inexact exception is recog- value. For DFP targets, the cohort member with the
nized when, for a PFPO-convert-floating-point-radix smallest quantum is selected.
operation, an inexact condition exists, recognition of
the exception is not suppressed, and neither IEEE- When the IEEE-inexact trap action coincides with an
overflow trap action nor IEEE-underflow trap action IEEE nontrap action, the operation is completed
occurs. using the result specified for the IEEE nontrap action,
the flag bit for the nontrap exception is set to one,
An inexact condition exists when the rounded inter- and the IEEE-inexact trap action takes place.
mediate value differs from the precise intermediate
ognized when the floating-point extension facility is the delivered value is set to the rounded intermediate
installed, and when a quantum-exception condition value.
exists, recognition of the exception is not suppressed
(DQPC = 1), and none of IEEE-overflow trap action, When the quantum-exception trap action coincides
IEEE-underflow trap action, and IEEE-inexact trap with other IEEE nontrap actions, the operation is
action occurs. completed using the result specified for the other
IEEE nontrap actions, the flag bits for the nontrap
For a PFPO-convert-floating-point-radix operation exceptions are set to one, and the quantum-excep-
with DFP result, a quantum-exception condition tion trap action takes place.
exists when the delivered DFP result is inexact, or
when the delivered DFP result is exact and finite , but Resulting Condition Code (when test bit is zero):
the delivered quantum exceeds the preferred quan-
tum of 1. 0 Normal result
1 Nontrap exception
When the floating-point extension facility is not 2 Trap exception with alternate action
installed, no quantum exception is recognized. 3 --
Even though a quantum-exception condition exists, Resulting Condition Code (when test bit is one):
the quantum exception is not recognized if recogni-
tion of the exception is suppressed (DQPC = 0), or if 0 Function is valid
IEEE-overflow, IEEE-underflow, or IEEE-inexact trap 1 --
action occurs. When a quantum-exception condition 2 --
exists, and the conditions for an IEEE-overflow, 3 Function is invalid
IEEE-underflow, or IEEE-inexact trap action also
apply, the trap action takes precedence and the IEEE Exceptions:
quantum exception is not reported in status flag or
DXC. • Invalid operation
• Overflow
Quantum-Exception Nontrap Action • Underflow
Quantum-exception nontrap action occurs when the • Inexact
quantum exception is recognized and the quantum-
exception mask bit in the FPC register is zero. Program Exceptions:
In the absence of another IEEE nontrap action, the • Data with DXC 1, AFP register
operation is completed using the rounded intermedi- • Data with DXC for IEEE exception
ate value, condition code 1 is set, and the quantum- • Operation (if the PFPO facility is not installed)
exception flag bit in the FPC register is set to one. • Specification
• Quantum (if the floating-point extension facility is
When a quantum-exception nontrap action and installed)
another one or two IEEE nontrap actions coincide,
the operation is completed using the result specified Programming Notes:
for the other exceptions and the flag bits for all two or
three exceptions are set to one, and condition code 1 1. The PFPO-convert-floating-point-radix operation
is set. performs “correct rounding”; that is, the result is
accurately obtained from the precise intermedi-
Quantum-Exception Trap Action ate value using the effective rounding method.
Quantum-exception trap action occurs when the This is in contrast to some radix conversion pro-
quantum exception is recognized and the quantum- grams, which may produce results with larger
exception mask bit in the FPC register is one. The rounding errors.
operation is completed, the condition code is not set,
and the exception is reported as a program interrup- 2. Note that a value of zero in the rounding method
tion for a data exception with DXC 04 hex. field (GR0 bits 60-63) specifies rounding accord-
ing to the current DFP rounding mode (FPC 3.1-
Condi
Symbol Meaning -tion IMu Rx Csx IMx Rq DQPC IMq Caa Action
Caa Alternate-exception-action control Xu 0 N - - N - - - complete, cc=0
Xu 0 N - - Y 1 0 - complete, cc=1, SFq=1
Cho HFP-overflow control
Xu 0 N - - Y 0 - - complete, cc=0
Chu HFP-underflow control Xu 0 N - - Y 1 1 - complete, PI, DXC=00000100
Csx Inexact-suppression control Xu 0 Y 1 - Y’ 0 - - complete, cc=1, SFu=1
DQPC DFP quantum-permission control Xu 0 Y 0 0 Y’ 0 - - complete, cc=1, SFu=1, SFx=1
Hmax The largest (in magnitude) representable number in this Xu 0 Y 1 - Y’ 1 0 - complete, cc=1, SFu=1, SFq=1
Xu 0 Y 0 0 Y’ 1 0 - complete, cc=1, SFu=1, SFx=1,
HFP format with the same sign as the source. SFq=1
Ho HFP-overflow condition Xu 0 Y 0 0 Y’ 1 1 - complete, PI, SFu=1, SFx=1,
Hu HFP-underflow condition DXC=00000100
Xu 0 Y 1 - Y’ 1 1 - complete, PI, SFu=1,
IMi IEEE-invalid-operation mask DXC=00000100
IMo IEEE-overflow mask Xu 0 Y 0 1 N’ - - - complete, PI, SFu=1,
IMq Quantum-exception mask DXC=00001y00
Xu 1 N - - N’ - - 0 Scaled, PI, DXC=00010000
IMu IEEE-underflow mask
Xu 1 Y - - N’ - - 0 scaled, PI, DXC=0001xy00
IMx IEEE-inexact mask Xu 1 N - - N’ - - 1 Scaled, cc=2, DXC=0001000
N No Xu 1 Y - - N’ - - 1 scaled, cc=2, DXC=0001xy00
N' No (true by virtue of conditions to the left of this column)
Figure 9-32. Action for PFPO IEEE Targets (Underflow)
PI Program interruption
Rq Quantum-exception condition
Rx Inexact-result condition Condi-
SFi IEEE-invalid-operation flag tion IMo Rx Csx IMx Rq DQPC IMq Caa Action
SFo IEEE-overflow flag Xo 0 Y' 1 - Y' 0 - - complete, cc=1, SFo=1
Xo 0 Y' 0 0 Y' 0 - - complete, cc=1, SFo=1, SFx=1
SFq Quantum-exception flag
Xo 0 Y' 1 - Y' 1 0 - complete, cc=1, SFo=1, SFq=1
SFu IEEE-underflow flag Xo 0 Y' 0 0 Y' 1 0 - complete, cc=1, SFo=1, SFx=1,
SFx IEEE-inexact flag SFq=1
Xi IEEE-invalid-operation exception Xo 0 Y' 0 0 Y 1 1 - complete, PI, SFo=1, SFx=1,
DXC=00000100
Xo IEEE-overflow exception Xo 0 Y' 1 - Y' 1 1 - complete, PI, SFo=1,
Xu IEEE-underflow exception DXC=00000100
Y Yes Xo 0 Y' 0 1 N’ - - - complete, PI, SF0=1,
DXC=00001y00
Y' Yes (true by virtue of conditions to the left of this column) Xo 1 N - - N’ - - 0 scaled, PI, DXC=00100000
+Hmax Hmax with a plus sign Xo 1 Y - - N’ - - 0 scaled, PI, DXC=0010xy00
Tz True zero with the same sign as the source. Xo 1 N - - N’ - - 1 scaled, cc=2, DXC=00100000
Xo 1 Y - - N’ - - 1 scaled, cc=2, DXC=0010xy00
Figure 9-30. Symbols Used in PFPO Action Figures
Figure 9-33. Action for PFPO IEEE Targets (Overflow)
Condi-
tion Rx Csx IMx Rq DQPC IMq Action Condition IMi Rx Action
Normal N - - N - - complete, cc=0 Inf - N' canonical infinity, cc=0
Normal N - - Y 1 0 complete, cc=1, SFq=1 QNaN - N' converted QNaN, cc=0
Normal N - - Y 1 1 complete, PI, DXC=00000100 SNaN 0 N' converted QNaN, cc=1, SFi=1
Normal N - - Y 0 - complete, cc=0 SNaN 1 N' suppress, PI, DXC=10000000
Normal Y 0 0 Y’ 1 0 complete, cc=1, SFx=1, SFq=1
Figure 9-34. Action for PFPO IEEE Targets (Infinity or NaN
Normal Y 0 0 Y’ 0 - complete, cc=1, SFx=1
Normal Y 1 - Y’ 1 0 complete, cc=1, SFq=1
source)
Normal Y 1 - Y’ 0 - compete, cc=0
Normal Y 0 0 Y’ 1 1 complete, PI, SFx=1, DXC=00000100
Normal Y 1 - Y’ 1 1 complete, PI, DXC=00000100 Rx Csx IMx Action
Normal Y 0 1 N’ - - complete, PI, DXC=00001y00 N - - complete, cc=0
Figure 9-31. Action for PFPO IEEE Targets (Normal) Y 1 - complete, cc=0
Y 0 0 complete, cc=1, SFx=1
Y 0 1 complete, PI, DXC=00001y00
Figure 9-35. Action for PFPO HFP Targets (Normal)
Mnemonic Op Code Operands Bits other than 61-63 of the second-operand address
SRNM 'B299' 2-bit BFP rounding mode are ignored.
SRNMB 'B2B8' 3-bit BFP rounding mode
Condition Code: The code remains unchanged.
The BFP rounding-mode bits in the FPC register are
set from the second-operand address. IEEE Exceptions: None.
The contents of bit positions 32-63 of of the general First, bits 0-4 of byte 1 of the floating-point-control
register designated by R1 are placed in the FPC (FPC) register at the beginning of the operation are
(floating-point-control) register. preserved to be used as signaling flags. Next, the
contents of the source operand are placed in the
All of bits 32-63 corresponding to unsupported bit FPC register; then the flags in the FPC register are
positions in the FPC register must be zero; other- set to the logical OR of the signaling flags and the
wise, a specification exception is recognized. For source flags. Finally, the conditions for simulated-
purposes of this checking, a bit position is considered IEEE-exception trap action are examined.
to be unsupported only if it is either unassigned or
assigned to a facility which is not installed in any The source operand is in bits 32-63 of the general
architectural mode of the configuration. Bits 0-31 of register designated by R1; bits 0-31 of the general
the general register are ignored. register are ignored.
When the floating-point extension facility is installed, If any signaling flag is one and the corresponding
the bits corresponding to the BFP rounding mode source mask is also one, simulated-IEEE-exception
must specify a valid rounding mode; otherwise, a trap action occurs. The data-exception code (DXC) in
specification exception is recognized. the FPC register is updated to indicate the specific
cause of the interruption and a data-exception pro-
Condition Code: The code remains unchanged. gram interruption occurs at completion of the instruc-
tion execution. The DXC for the interruption is shown
IEEE Exceptions: None. in Figure 9-21 on page 9-32.
1. When the architectural mode of a CPU is Bits in the source operand that correspond to unsup-
changed without resetting the FPC register (by ported bit positions in the FPC register must be zero;
means of the set architecture signal-processor otherwise, a specification exception is recognized.
order, for example) the entire contents of the For purposes of this checking, a bit position is con-
FPC register are preserved. This is true even sidered to be unsupported only if it is either unas-
when some of these bits are associated with a signed or assigned to a facility which is not installed
facility which is not available in both architectural in any architectural mode of the configuration.
modes. Checking for unsupported bit positions of
the FPC register is performed independently of When the floating-point extension facility is installed,
the current architectural mode of the CPU; thus, the bits corresponding to the BFP rounding mode
it is always safe to restore the FPC register from must specify a valid rounding mode; otherwise, a
a value previously saved on this CPU, even after specification exception is recognized.
the architectural mode has changed.
Condition Code: The code remains unchanged.
Source Result
GR Size FPS HFP BFP DFP
Instruction Name (bits) Long Short Long Ext. Short Long Ext. Long Ext.
CONVERT FROM FIXED 32 CEFR CDFR CXFR CEFBR(A) CDFBR(A) CXFBR(A) CDFTR CXFTR
CONVERT FROM FIXED 64 CEGR CDGR CXGR CEGBR(A) CDGBR(A) CXGBR(A) CDGTR(A) CXGTR(A)
CONVERT FROM LOGICAL 32 CELFBR CDLFBR CXLFBR CDLFTR CXLFTR
CONVERT FROM LOGICAL 64 CELGBR CDLGBR CXLGBR CDLGTR CXLGTR
CONVERT FROM SIGNED PACKED 64 CDSTR
CONVERT FROM SIGNED PACKED 128 CXSTR
CONVERT FROM UNSIGNED 64 CDUTR
PACKED
CONVERT FROM UNSIGNED 128 CXUTR
PACKED
INSERT BIASED EXPONENT 64 IEDTR IEXTR
LOAD FPR FROM GR 64 LDGR
Figure 9-43. Floating-Point Instructions: General Register Source
Result
HFP BFP
Instruction Name Source Long Short Long
CONVERT BFP TO HFP BFP Short THDER
CONVERT BFP TO HFP BFP Long THDR
CONVERT HFP TO BFP HFP Long TBEDR TBDR
Figure 9-45. Floating-Point Instructions (other than PFPO): Radix Conversion
The following summarizes the different behavior of When the floating-point extension facility is installed
affected ESA/390 instructions caused by those two in the z/Architectural architecture mode, it causes the
facilities in the z/Architecture architectural mode. following deviations from the ESA/390 architecture.
3. For BFP CONVERT TO FIXED (CFEBR, 6. For BFP LOAD FP INTEGER (FIEBR, FIDBR,
CFDBR, CFXBR), if the M3 field designates the FIXBR), if the M3 field designates the value 3, it is
value 3, it is unpredictable whether a specifica- unpredictable whether a specification exception
tion exception is recognized or an undefined is recognized or an undefined rounding method
rounding method is performed. In addition, if bits is performed. In addition, if bits 20-23 of the
20-23 of the instruction contain a nonzero value, instruction contain a nonzero value, it is unpre-
it is unpredictable whether recognition of IEEE- dictable whether recognition of IEEE-inexact
inexact exception is suppressed. exception is suppressed.
4. For BFP CONVERT FROM FIXED (CEFBR, 7. For BFP LOAD ROUNDED (LEDBR, LDXBR,
CDFBR, CXFBR), if bits 16-19 of the instruction LEXBR), if bits 16-19 of the instruction contain a
contain a nonzero value, it is unpredictable nonzero value, it is unpredictable whether a
whether a specification exception is recognized specification exception is recognized or an unde-
or an undefined rounding method is performed. fined rounding method is performed. In addition,
In addition, if bits 20-23 of the instruction contain if bits 20-23 of the instruction contain a nonzero
a nonzero value, it is unpredictable whether rec- value, it is unpredictable whether recognition of
ognition of IEEE-inexact exception is sup- IEEE-inexact exception is suppressed.
pressed.
This chapter includes all privileged and semiprivi- (suppression, nullification, or completion) only for
leged instructions described in this publication, those exceptions for which the ending may vary.
except the input/output instructions, which are
described in “I/O Instructions” on page 14-1. Note: In the detailed descriptions of the individual
instructions, the mnemonic and the symbolic oper-
Privileged instructions may be executed only when and designation for the assembler language are
the CPU is in the supervisor state. An attempt to exe- shown with each instruction. For LOAD PSW, for
cute a privileged instruction in the problem state gen- example, LPSW is the mnemonic and D2(B2) the
erates a privileged-operation exception. operand designation.
For those control instructions which have special 3. The following additional control instructions are
rules regarding the handling of exceptional situa- available when the ASN-and-LX-reuse facility is
tions, a section called “Special Conditions” is installed:
included. This section indicates the type of ending
• EXTRACT PRIMARY ASN AND INSTANCE
5. The PERFORM TIMING FACILITY FUNCTION 9. The RESET REFERENCE BITS MULTIPLE con-
control instruction is available when the TOD- trol instruction is available when the reset-refer-
clock-steering facility is installed. ence-bits-multiple facility is installed.
Mne- Op-
Name monic Characteristics code Page
1
BRANCH AND SET AUTHORITY BSA RRE Q A SO T B B25A 10-6
1 5
BRANCH AND STACK BAKR RRE A Z T B ST B240 10-10
1
BRANCH IN SUBSPACE GROUP BSG RRE A SO T B R2 B258 10-13
COMPARE AND SWAP AND PURGE CSP RRE C P A1 SP $ ST R2 B250 10-17
COMPARE AND SWAP AND PURGE CSPG RRE C DE P A1 SP $ ST R2 B98A 10-17
DIAGNOSE DM P DM MD 83 10-19
EXTRACT AND SET EXTENDED AUTHORITY ESEA RRE N P B99D 10-20
EXTRACT PRIMARY ASN EPAR RRE Q SO B226 10-20
EXTRACT PRIMARY ASN AND INSTANCE EPAIR RRE RA Q SO B99A 10-20
EXTRACT SECONDARY ASN ESAR RRE Q SO B227 10-21
EXTRACT SECONDARY ASN AND INSTANCE ESAIR RRE RA Q SO B99B 10-21
EXTRACT STACKED REGISTERS (32) EREG RRE A1 SE U1 U2 B249 10-21
EXTRACT STACKED REGISTERS (64) EREGG RRE N A1 SE U1 U2 B90E 10-21
EXTRACT STACKED STATE ESTA RRE C A1 SP SE B24A 10-23
INSERT ADDRESS SPACE CONTROL IAC RRE C Q SO B224 10-25
INSERT PSW KEY IPK S Q G2 B20B 10-26
INSERT STORAGE KEY EXTENDED ISKE RRE P A1 B229 10-26
INSERT VIRTUAL STORAGE KEY IVSK RRE Q A1 SO R2 B223 10-27
INVALIDATE DAT TABLE ENTRY IDTE RRF-b DE P A1 SP $ B98E 10-28
INVALIDATE PAGE TABLE ENTRY IPTE RRF-a P A1 SP $ B221 10-32
LOAD ADDRESS SPACE PARAMETERS LASP SSE C P A1 SP SO B1 E500 10-34
LOAD CONTROL (32) LCTL RS-a P A SP B2 B7 10-44
LOAD CONTROL (64) LCTLG RSY-a N P A SP B2 EB2F 10-44
LOAD PAGE TABLE ENTRY ADDRESS LPTEA RRF-b C D2 P A1 SP SO R2 B9AA 10-44
LOAD PSW LPSW S L P A SP ¢ B2 82 10-47
LOAD PSW EXTENDED LPSWE S L N P A SP ¢ B2 B2B2 10-48
LOAD REAL ADDRESS (32) LRA RX-a C P A1 SO BP B1 10-49
LOAD REAL ADDRESS (32) LRAY RXY-a C LD P A1 SO BP E313 10-49
LOAD REAL ADDRESS (64) LRAG RXY-a C N P A1 BP E303 10-49
LOAD USING REAL ADDRESS (32) LURA RRE P A1 SP B24B 10-53
LOAD USING REAL ADDRESS (64) LURAG RRE N P A1 SP B905 10-53
MODIFY STACKED STATE MSTA RRE A1 SP SE ST B247 10-53
MOVE PAGE MVPG RRE C Q A SP G0 ST R1 R2 B254 10-54
MOVE TO PRIMARY MVCP SS-d C Q A SO ¢ ST DA 10-56
MOVE TO SECONDARY MVCS SS-d C Q A SO ¢ ST DB 10-56
Figure 10-1. Summary of Control Instructions (Part 1 of 4)
Mne- Op-
Name monic Characteristics code Page
RA Reusable-ASN-and-LX facility.
RB Reset-reference-bits-multiple facility.
RRE RRE instruction format.
RS RS instruction format.
RSY RSY instruction format.
RX RX instruction format.
RXY RXY instruction format.
S S instruction format.
SE Special-operation, stack-empty, stack-specification, and stack-type exceptions.
SF Special-operation, stack-full, and stack-specification exceptions.
SI SI instruction format.
SO Special-operation exception.
SP Specification exception.
SS SS instruction format.
SSE SSE instruction format.
SSF SSF instruction format.
ST PER storage-alteration event.
SU PER store-using-real-address event.
SW Special-operation exception and space-switch event.
T Trace exceptions (which include trace table, addressing, and low-address protection).
TS TOD-clock-steering facility.
U1 R1 field designates an access register unconditionally.
U2 R2 field designates an access register unconditionally.
WE Space-switch event.
1
Z Additional exceptions and events for PROGRAM CALL (which include ASX-translation, EX-translation, LFX-translation, LSTE-sequence, LSX-translation,
LX-translation, PC-translation-specification, special-operation, stack-full, stack-specification and subspace-replacement exceptions and space-switch
event).
Z2 Additional exceptions and events for PROGRAM TRANSFER (which include AFX-translation, ASX-translation, primary-authority, special-operation, and
subspace-replacement exceptions and space-switch event).
Z3 Additional exceptions for SET SECONDARY ASN (which include AFX translation, ASX translation, secondary authority, special operation and subspace
replacement).
Z4 Additional exceptions and events for PROGRAM RETURN (which include AFX-translation, ASTE-instance, ASX-translation, secondary-authority, special-
operation, stack-empty, stack-operation, stack-specification, stack-type, and subspace-replacement exceptions and space-switch event).
Z5 Additional exceptions for BRANCH AND STACK (which include special operation, stack full, and stack specification)
6
Z Additional exceptions and events for PROGRAM TRANSFER WITH INSTANCE (which include AFX-translation, ASTE-instance, ASX-translation, primary-
authority, special-operation, and subspace-replacement exceptions and space-switch event).
7
Z Additional exceptions for SET SECONDARY ASN WITH INSTANCE (which include AFX translation, ASTE instance, ASX translation, secondary authority,
special operation, and subspace replacement).
Figure 10-1. Summary of Control Instructions (Part 4 of 4)
BRANCH AND SET AUTHORITY If the dispatchable unit is in the base-authority state
and the 24-bit or 31-bit addressing mode: bits 32 and
BSA R1,R2 [RRE] 97-127 of the current PSW, the basic-addressing-
mode bit and bits 33-63 of the updated instruction
'B25A' / / / / / / / / R1 R2 address, are saved in the dispatchable-unit control
0 16 24 28 31 table (DUCT); the PSW-key mask (PKM), PSW key,
and problem-state bit also are saved in the DUCT;
stored in word 8 when saving occurs in the base- mode, PSW bits 64-127 are saved in words 8 and 9
authority state. In any addressing mode, all zeros are of the DUCT. In any addressing mode, the PKM, the
stored in bit positions 16-23, 29, and 30 of word 5 PSW key, and the problem-state bit are saved in
when saving occurs in the base-authority state. word 5 of the DUCT, the RA bit in word 5 is set to
one, and bits 16-23, 29, and 30 of word 5 are set to
All other fields in words 5, 8, and 9 remain zeros.
unchanged when bit 28 of word 5 is set to zero in the
reduced-authority state. Bits 56-59 of general register R1 are placed in bit
positions 8-11 of the PSW as the new PSW key. In
The fetch, store, and update references to the DUCT the problem state, the new PSW key must be autho-
are single-access references and appear to be word rized by the PKM; otherwise, if the new PSW key is
concurrent as observed by other CPUs. The words of not authorized, a privileged-operation exception is
the DUCT are accessed in no particular order. recognized.
Base-Authority Operation After the new PSW key has been placed in the PSW,
bits 32-47 of general register R1 are ANDed with the
When BRANCH AND SET AUTHORITY is executed PKM in control register 3, and the result replaces the
in the base-authority state, as indicated by the PKM in control register 3.
reduced-authority bit (RA) in the DUCT being zero,
R2 must be nonzero; otherwise, a special-operation The problem-state bit in the PSW is set to one.
exception is recognized. R1 may be zero or nonzero.
In the 24-bit or 31-bit addressing mode, bit 32 of gen-
The contents of bit positions 32-63 of general register eral register R2 is placed in bit position 32 of the PSW
R1 and of general register R2 when the execution of as the new basic-addressing-mode bit. A branch
the instruction begins in the base-authority state are address is generated from bits 33-63 of general reg-
as follows: ister R2 under the control of the new basic address-
ing mode, and the result is placed in bit positions
R1 Key Mask Key 64-127 of the PSW as the new instruction address.
32 48 56 60 63
In the 64-bit addressing mode, a branch address is
generated from bits 0-63 of general register R2 and is
In the 24-Bit or 31-Bit Addressing Mode
placed in bit positions 64-127 of the PSW as the new
R2 Ignored instruction address. Bit 32 of the PSW remains
0 31 unchanged.
B
Bits 33-63 of Branch Address Bits 48-55 and 60-63 of general register R1 may be
A
used for future extensions and should be zeros; oth-
32 33 63
erwise, the program may not operate compatibly in
the future.
In the 64-Bit Addressing Mode
In the problem state, the execution of the instruction • Addressing (dispatchable-unit control table)
in the base-authority state is subject to control by the • Privileged operation (selected PSW-key-mask bit
PSW-key mask in control register 3. When the bit in is zero in the problem state, base-authority oper-
the PSW-key mask corresponding to the PSW-key ation only)
value to be set is one, the instruction is executed suc- • Protection (low-address; dispatchable-unit con-
cessfully. When the selected bit in the PSW-key trol table)
mask is zero, a privileged-operation exception is rec- • Special operation
ognized. In the supervisor state, any value for the • Specification
PSW key is valid.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
8.B Protection exception (low-address protection) for access to dispatchable-unit control table.
8.C.2 Special-operation exception due to R2 being zero in the base-authority state or R2 being nonzero in the
reduced-authority state.
8.C.3 Privileged-operation exception due to selected PSW-key-mask bit being zero (base-authority operation
only).
9. Specification exception due to bit 32 of the newly loaded PSW zero when bits 97-103 are not all zeros
(reduced-authority operation only).
When R1 is nonzero and bit 63 of general register R1 The CPU must be in the primary-space mode or
is one, the return address is generated from the con- access-register mode; otherwise, a special-operation
tents of the register under the control of the 64-bit exception is recognized.
addressing mode. Bits 0-62 of the return address,
with a zero appended on the right, are substituted for A stack-full or stack-specification exception may be
the updated instruction address in the current PSW recognized during the stacking process.
when the contents of that PSW are placed in the
state entry. Bits 31 and 32 are set to one in the PSW The operation is suppressed on all addressing and
that is placed in the state entry. The contents of the protection exceptions.
current PSW are not changed.
The priority of recognition of program exceptions for
When the R1 field is zero, the current PSW is placed the instruction is shown in Figure 10-3 on
in the state entry without any change except for an page 10-12.
unpredictable PER mask.
Condition Code: The code remains unchanged.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B Special-operation exception due to DAT being off or the CPU being in secondary-space mode or home-
space mode.
8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry.
Note: Exceptions 8.B.2-8.B.7 can occur only if there is not enough remaining free space in the current
linkage-stack section.
8.B.2 Stack-specification exception due to remaining-free-space value in current linkage-stack entry not being a
multiple of 8.
8.B.3 Access exceptions (fetch) for second word of the trailer entry of the current section. The entry is presumed to
be a trailer entry; its entry-type field is not examined.
8.B.4 Stack-full exception due to forward-section validity bit in the trailer entry being zero.
8.B.5 Access exceptions (fetch) for entry descriptor of the header entry of the next section. This entry is presumed
to be a header entry; its entry-type field is not examined.
8.B.6 Stack-specification exception due to not enough remaining free space in the next section.
8.B.7 Access exceptions (store) for second word of the header entry of the next section. If there is no exception,
the header is now called the current entry.
8.B.8 Access exceptions (store) for entry descriptor of the current entry and for the new state entry.
if the ALE is outside the effective access list mode, bits 32 and 97-127 of the current PSW, the
or bit 0 of the ALE is one. basic-addressing-mode bit and bits 33-63 of the
updated instruction address, are placed in bit posi-
• An ASTE-validity exception is recognized if tions 32 and 33-63, respectively, of general register
bit 0 of the DASTE is one. R1, and bits 0-31 of the register remain unchanged. If
• An ASTE-sequence exception is recognized R1 is nonzero in the 64-bit addressing mode, bits
if the ASTE sequence number (ASTESN) in 64-127 of the current PSW, the updated instruction
the DASTE does not equal the ASTESN in address, are placed in bit positions 0-63 of general
the ALE. register R1. If R1 is zero, general register 0 remains
unchanged.
The operation differs from ordinary ART in that
the ALE sequence number (ALESN) in the ALE Whether R2 is nonzero or zero, in the 24-bit or 31-bit
is not compared to the ALESN in the ALET, and addressing mode, bits 32-63 of general register R2
the private bit in the ALE is treated as zero. Thus, specify the new basic addressing mode and desig-
ALE-sequence and extended-authority excep- nate the branch address. Bit 32 of the register speci-
tions cannot occur. fies the new basic addressing mode and replaces bit
32 of the current PSW, and the branch address is
The fetch-only bit in the ALE is ignored. generated from the contents of bit positions 33-63 of
the register under the control of the new basic
When the ALET is other than ALET 0 and ALET 1, addressing mode.
the special ART may be performed by using the ART-
lookaside buffer (ALB). When R2 is nonzero or zero in the 64-bit addressing
mode, the contents of general register R2 designate
The DASTE located due to an ALET other than ALET the branch address. The branch address is gener-
0 and ALET 1 may be the ASTE for the base space ated from the contents of the register under the con-
of the subspace group associated with the dispatch- trol of the 64-bit addressing mode. Bit 32 of the PSW
able unit. The DASTE is the base-space ASTE if the remains unchanged.
DASTE origin (DASTEO) obtained from an ALE by
ART equals the BASTEO in the DUCT. For determin- Regardless of the addressing mode, the new value
ing whether the DASTEO equals the BASTEO, either for the PSW is computed before general register R1
the DASTEO may be compared to the BASTEO, or is changed.
the DASTEO with one leftmost and six rightmost
zeros appended may be compared to the entire con- The secondary ASCE (SASCE) in control register 7
tents of word 0 of the DUCT. If the DASTE is not the is set equal to the new PASCE in control register 1.
base-space ASTE, the DASTE is treated as the The secondary ASN (SASN), bits 48-63 of control
ASTE for a subspace of the dispatchable unit’s sub- register 3, is set equal to the primary ASN (PASN),
space group provided that (1) the subspace-group bits 48-63 of control register 4. If the ASN-and-LX-
bit, bit 54, in the ASCE in the DASTE is one, and reuse facility is installed and is enabled by a one
(2) the DASTE does not specify the base space of value of the ASN-and-LX-reuse control, bit 44 of con-
another subspace group. The DASTE specifies the trol register 0, the secondary ASTEIN (SASTEIN),
base space of another subspace group if the base- bits 0-31 of control register 3, is set equal to the pri-
space bit, bit 31 of word 0 of the DASTE, is one. A mary ASTEIN (PASTEIN), bits 0-31 of control regis-
special-operation exception is recognized if either of ter 4.
those two provisions is not met.
If the DASTE specifies the base space, the sub-
If the DASTE specifies the base space of the sub- space-active bit, bit 0 of word 1 of the DUCT, is set to
space group, the PASCE in control register 1 is zero, and bits 1-31 of word 1 remain unchanged. If
replaced by the ASCE in the DASTE. If the DASTE the DASTE specifies a subspace by means of ALET
specifies a subspace, bits 0-55 and 58-63 of the 1, then (1) the subspace-active bit is set to one,
PASCE are replaced by the same bits of the ASCE in (2) the SSASTEO in bit positions 1-25 of word 1
the DASTE, and bits 56 and 57 of the PASCE, the remains unchanged, and (3) bits 26-31 of word 1
storage-alteration-event bit and space-switch-event- either are set to zeros or remain unchanged. If the
control bit, remain unchanged. DASTE specifies a subspace by means of an ALET
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
8.B Protection exception (low-address protection) for access to dispatchable-unit control table.
8.C.2 Special-operation exception due to current primary address space not being in a subspace group associated
with the current dispatchable unit (primary-ASTE origin in control register 5 not equal to base-ASTE origin in
dispatchable-unit control table).
Note: Exception 8.C.3.A can occur only if the access-list-entry token (ALET) in access register R2 is ALET 0.
8.C.3.A Addressing exception for access to base ASTE (ASTE designated by base-ASTE origin in dispatchable-unit
control table).
Note: Exceptions 8.C.3.B.1-8.C.3.B.4 can occur only if the access-list-entry token (ALET) in access register
R2 is ALET 1.
8.C.3.B.1 Special-operation exception due to subspace-ASTE origin in dispatchable-unit control table being zero.
8.C.3.B.4 ASTE-sequence exception due to ASTE sequence number in subspace ASTE not being equal to subspace-
ASTE sequence number in dispatchable-unit control table.
Note: Exceptions 8.C.3.C.1-8.C.3.C.9 can occur only if the access-list-entry token (ALET) in access register
R2 is other than ALET 0 and ALET 1.
8.C.3.C.1 ALET-specification exception due to bits 0-6 of ALET not being all zeros.
8.C.3.C.3 ALEN-translation exception due to access-list entry being outside the list.
8.C.3.C.8 ASTE-sequence exception due to ASTE sequence number (ASTESN) in access-list entry not being equal to
ASTESN in destination ASTE.
8.C.3.C.9 Special-operation exception due to destination-ASTE origin not equal to base-ASTE origin in dispatchable-
unit control table and (1) subspace-group bit, bit 54 in address-space-control element in destination ASTE
being zero or (2) base-space bit 31, in destination ASTE being one.
PROGRAM CALL, PROGRAM RETURN, PRO- mary ASCE or in control register 7 as the sec-
GRAM TRANSFER, PROGRAM TRANSFER ondary ASCE, and if (1) the ASCE has the
WITH INSTANCE, SET SECONDARY ASN, or subspace-group bit on in it, (2) the dispatchable
SET SECONDARY ASN WITH INSTANCE unit is subspace active, and (3) the ASCE was
places an ASCE in control register 1 as the pri- obtained from the ASN-second-table entry
6. BRANCH IN SUBSPACE GROUP does not per- For both CSP and CSPG, the location of the leftmost
form the serialization or checkpoint-synchroniza- byte of the second operand is designated by contents
tion functions, but it does cause all copies of of general register R2.
prefetched instructions to be discarded except
when in the home-space mode. The purging operation applies to ART-lookaside buff-
ers (ALBs) and translation-lookaside buffers (TLBs)
7. Unlike the RR-format branch instructions, a value in all CPUs in the configuration. Either ALBs or TLBs,
of zero in the R2 field for BRANCH IN SUB- or both ALBs and TLBs, may be selected for purging.
SPACE GROUP designates general register 0, All entries are cleared from the selected buffers.
and branching occurs.
The purging operation is specified by means of bits
8. When the R2 field designates access register 0, 62 and 63 of general register R2. When bit 62 is one,
the access register is treated as containing ALET entries are cleared from ALBs. When bit 63 is one,
entries are cleared from TLBs. When bits 62 and 63
TLBs. When bits 62 and 63 both are zeros, no entries 61 are ignored. In the 31-bit addressing mode, the
are cleared. contents of bit positions 33-60 of the register, with
three zeros appended on the right, constitute the
The handling of the address in general register R2 is address, and the contents of bit positions 0-32 and
dependent on the addressing mode. For CSP in the 61 are ignored. In the 64-bit addressing mode, the
24-bit addressing mode, the contents of bit positions contents of bit positions 0-60 of the register, with
40-61 of general register R2, with two zeros three zeros appended on the right, constitute the
appended on the right, constitute the address, and address, and the contents of bit position 61 are
the contents of bit positions 0-39 are ignored. In the ignored.
31-bit addressing mode, the contents of bit positions
33-61 of the register, with two zeros appended on the The contents of the registers just described are
right, constitute the address, and the contents of bit shown in Figure 10-5 on page 10-18 and Figure 10-6
positions 0-32 are ignored. In the 64-bit addressing on page 10-19. When an equal comparison occurs,
mode, the contents of bit positions 0-61 of the regis- the contents of bit positions 32-63 of general register
ter, with two zeros appended on the right, constitute R1 + 1 for CSP, or of bit positions 0-63 for CSPG, are
the address. stored at the second-operand location. The fetch of
the second operand for purposes of comparison and
For CSPG in the 24-bit addressing mode, the con- the store into the second-operand location appear to
tents of bit positions 40-60 of general register R2, be a block-concurrent interlocked-update reference
with three zeros appended on the right, constitute the as observed by other CPUs.
R1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / First Operand
0 32 63
R1 + 1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Swap Value
0 32 63
Figure 10-5. Register Contents for COMPARE AND SWAP AND PURGE (CSP)
When the result of the comparison is unequal, the A serialization function is performed before the oper-
second-operand is loaded at the first-operand loca- and is fetched and again after the operation is com-
tion, bits 0-31 of general register R1 remain pleted.
unchanged for CSP only, and the second-operand
location remains unchanged. However, on some When an equal comparison occurs, this CPU clears
models, the second operand may be fetched and entries from its ALB and TLB, as specified by bits 62
subsequently stored back unchanged at the second- and 63 of general register R2, and signals all CPUs in
operand location. This update appears to be a block- the configuration to clear the same specified entries
concurrent interlocked-update reference as observed from their ALBs and TLBs. The ALB entries that are
by other CPUs. cleared are all ALB access-list designations, access-
list entries, ASN-second-table entries, and authority-
table entries. The TLB entries that are cleared are all
R1 + 1 Swap Value
0 63
Figure 10-6. Register Contents for COMPARE AND SWAP AND PURGE (CSPG)
combined region-and-segment-table entries, page- Programming Note: COMPARE AND SWAP AND
table entries, and real-space entries. PURGE provides a broadcast form of the PURGE
ALB and PURGE TLB instructions, thus making it
The execution of COMPARE AND SWAP AND possible to avoid uses of SIGNAL PROCESSOR.
PURGE is not completed on the CPU which executes
it until (1) all specified entries have been cleared
from the ALB and TLB of this CPU and (2) all other DIAGNOSE
CPUs in the configuration have completed any stor-
age accesses, including the updating of the change '83'
and reference bits, by using the specified ALB and 0 8 31
TLB entries.
The CPU performs built-in diagnostic functions, or
Special Conditions other model-dependent functions. The purpose of
the diagnostic functions is to verify proper functioning
The R1 field must designate an even register; other- of equipment and to locate faulty components. Other
wise, a specification exception is recognized. model-dependent functions may include disabling of
failing buffers, reconfiguration of CPUs, storage, and
Resulting Condition Code: channel paths, and modification of control storage.
0 First and second operands equal, second oper- Bits 8-31 may be used as in the SI or RS formats, or
and replaced by contents of general register in some other way, to specify the particular diagnostic
R1 + 1 function. The use depends on the model.
1 First and second operands unequal, first operand
replaced by second operand The execution of the instruction may affect the state
2 -- of the CPU and the contents of a register or storage
3 -- location, as well as the progress of an I/O operation.
Some diagnostic functions may cause the test indica-
Program Exceptions: tor to be turned on.
• Access (fetch and store, operand 2) Resulting Condition Code: The code is unpredict-
• Operation (if DAT-enhancement facility is not able.
installed, CSPG only)
• Privileged operation Program Exceptions:
• Specification
• Privileged operation
be recognized.
EPAR R1 [RRE]
Programming Notes:
'B226' / / / / / / / / R1 / / / /
1. Since the instruction is not intended for problem- 0 16 24 28 31
8. Privileged-operation exception due to extraction- • Operation (if the ASN-and-LX-reuse facility is not
authority control, bit 36 of control register 0, installed, ESAIR only)
being zero in problem state. • Privileged operation (extraction-authority control
is zero in the problem state)
Figure 10-7. Priority of Execution: EXTRACT PRIMARY
• Special operation
ASN
EXTRACT SECONDARY ASN AND 7.B.2 Special-operation exception due to DAT being
off.
INSTANCE
8. Privileged-operation exception due to extraction-
ESAIR R1 [RRE] authority control, bit 36 of control register 0,
being zero in problem state.
'B99B' / / / / / / / / R1 / / / /
0 16 24 28 31 Figure 10-8. Priority of Execution: EXTRACT
SECONDARY ASN
The instruction must be executed with DAT on; other- Contents of a set of general registers and a set of
wise, a special-operation exception is recognized. access registers that were saved in the last state
entry in the linkage stack are restored to the regis-
In the problem state, the extraction-authority control, ters. Each set of registers begins with register R1 and
bit 36 of control register 0, must be one; otherwise, a ends with register R2.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B Special-operation exception due to DAT being off or the CPU being in secondary-space mode.
8. Access exceptions (fetch) for entry descriptor of the current linkage-stack entry.
9. Stack-type exception due to current entry not being a state entry or header entry.
Note: Exceptions 10-14 can occur only if the current entry is a header entry.
10. Access exceptions (fetch) for second word of the header entry.
11. Stack-empty exception due to backward stack-entry validity bit in the header entry being zero.
12. Access exceptions (fetch) for entry descriptor of preceding entry, which is the entry designated by the
backward stack-entry address in the current (header) entry.
14. Stack-type exception due to preceding entry not being a state entry.
15. Access exceptions (fetch) for the selected contents of the state entry.
When the entry-type code in the entry descriptor of Resulting Condition Code:
the state entry is 0001100 binary, indicating a branch
state entry, the condition code is set to 0. When the 0 Branch state entry
entry-type code is 0001101 binary, indicating a pro- 1 Program-call state entry
gram-call state entry, the condition code is set to 1. 2 --
3 --
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B Special-operation exception due to DAT being off or the CPU being in secondary-space mode.
8.A Specification exception due to R1 being odd or bits 56-63 of general register R2 having a value greater than 4
when the ASN-and-LX-reuse facility is not installed or greater than 5 when the facility is installed.
8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry.
8.B.2 Stack-type exception due to current entry not being a state entry or header entry.
Note: Exceptions 8.B.3-8.B.7 can occur only if the current entry is a header entry.
8.B.3 Access exceptions (fetch) for second word of the header entry.
8.B.4 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero.
8.B.5 Access exceptions (fetch) for entry descriptor of preceding entry, which is the entry designated by the
backward stack-entry address in the current (header) entry.
8.B.7 Stack-type exception due to preceding entry not being a state entry.
8.B.8 Access exceptions (fetch) for the selected contents of the state entry.
Programming Note: The results for a code of 1 in bit tions 54 and 55 of general register R1; that is, bit 16 is
positions 56-63 of general register R2 are intended to placed in bit position 55, and bit 17 is placed in bit
provide compatibility with ESA/390. (It may be that position 54. Bits 48-53 of the register are set to
only values of bits in bit positions 0-31 of the PSW zeros, and bits 0-47 and 56-63 of the register remain
are required.) Bit 63 of general register R1 + 1 is set unchanged. The address-space-control bits are also
to one if the instruction address in the PSW in the used to set the condition code.
state entry is larger than a 31-bit address.
Special Conditions
INSERT ADDRESS SPACE The instruction must be executed with DAT on; other-
CONTROL wise, a special-operation exception is recognized.
Program Exceptions:
1.-6. Exceptions with the same priority as the priority
of program-interruption conditions for the general • Privileged operation (extraction-authority control
case. is zero in the problem state)
7.A Access exceptions for second instruction
halfword. INSERT STORAGE KEY
7.B Special-operation exception due to DAT being EXTENDED
off.
1. Bits 48-53 of general register R1 are reserved for In the 24-bit addressing mode, bits 40-51 of general
expansion for use with possible future facilities. register R2 designate a 4K-byte block in real storage,
The program should not depend on these bits and bits 0-39 and 52-63 of the register are ignored. In
being set to zeros. the 31-bit addressing mode, bits 33-51 of general
register R2 designate a 4K-byte block in real storage,
2. INSERT ADDRESS SPACE CONTROL and SET
and bits 0-32 and 52-63 of the register are ignored. In
ADDRESS SPACE CONTROL are defined to
the 64-bit addressing mode, bits 0-51 of general reg-
operate on the seventh byte of a general register
ister R2 designate a 4K-byte block in real storage,
so that the address-space-control bits can be
and bits 52-63 of the register are ignored.
saved in the same general register as the PSW
key, which is placed in the eighth byte of general
The address designating the storage block, being a
register 2 by INSERT PSW KEY.
real address, is not subject to dynamic address
translation. The reference to the storage key is not
subject to a protection exception.
The address is a virtual address and is subject to the The priority of recognition of program exceptions for
address-space-control bits, bits 16 and 17 of the cur- the instruction is shown in Figure 10-12 on
rent PSW. The address is treated as a primary virtual page 10-28.
address in the primary-space mode, as a secondary
virtual address in the secondary-space mode, as an Condition Code: The code remains unchanged.
AR-specified virtual address in the access-register
mode, or as a home virtual address in the home- Program Exceptions:
space mode. The reference to the storage key is not
subject to a protection exception. • Access (except for protection, address specified
by general register R2)
Bits 0-4 of the storage key, which are the access-con- • Privileged operation (extraction-authority control
trol bits and the fetch-protection bit, are placed in bit is zero in the problem state)
positions 56-60 of general register R1, with bits 61-63 • Special operation
set to zeros. The contents of bit positions 0-55 of the
9. Access exceptions (except for protection) for The two operations are described separately below,
address specified by general register R2. before the section “Common Operation.”
Figure 10-12. Priority of Execution: INSERT VIRTUAL
Invalidation-and-Clearing Operation
STORAGE KEY
When bit 52 of general register R2, the clearing-by-
Programming Notes:
ASCE-option bit, is zero, the invalidation-and-clear-
ing operation is specified.
1. Since all bytes in a 4K-byte block are associated
with the same page and the same storage key,
The contents of general register R1 have the format
bits 52-63 of general register R2 essentially are
of an address-space-control element with only the
ignored. Similarly, since all bytes in a 1M-byte
table origin, bits 0-51, and designation-type control
block are associated with the same segment, bits
(DT), bits 60 and 61, used. The table origin desig-
44-63 of general register R2 may be ignored
nates the DAT table in which one or more entries are
when enhanced DAT applies and the STE-format
to be invalidated, and DT specifies the type of that
and ACCF-validity controls are both one.
table.
2. In the access-register mode, access register 0
designates the primary address space regard- Bits 52-59, 62, and 63 of general register R1 are
less of the contents of access register 0. ignored.
R2 Region-First Index Region-Second Index Region-Third Index Segment Index 000000000 Additional Entries
0 11 22 33 44 52 53 63
Figure 10-13. Register Contents for INVALIDATE DAT TABLE ENTRY Invalidation-and-Clearing Operation (Bit 52 of GR R2
Is Zero)
The table origin in general register R1 and effective The entire table entry is fetched concurrently from
invalidation index in general register R2 designate a storage. Subsequently, the byte containing the invalid
table entry in accordance with the rules in “Lookup in bit is stored. The fetch access to the entry is subject
a Table Designated by an Address-Space-Control to key-controlled protection, and the store access is
Element” on page 3-48, except that a carry from bit subject to key-controlled protection and low-address
position 0 of the resulting address is always ignored, protection.
and the index is not checked against a table-length
field. The table origin is treated as a 64-bit address, If bits 53-63 of general register R2 are not all zeros,
and the addition is performed by using the rules for the setting of the invalid bit to one in a region-table or
64-bit address arithmetic, regardless of the current segment-table entry is repeated by adding one to the
addressing mode specified by bits 31 and 32 of the previously used value of the effective invalidation
current PSW. The address formed from these two index, and this is done as many times as are speci-
components is a real or absolute address. The invalid fied by bits 53-63. A carry out of the leftmost bit posi-
bit, bit 58, of this region-table or segment-table entry tion of the effective invalidation index is ignored, and
is set to one. During this procedure, the entry is not wraparound in the table occurs in this case. The con-
checked for a format error or for whether the origin, in tents of general register R2 remain unchanged.
the entry, of the next-lower-level table would cause
an addressing exception. The table-type field in the A serialization function is performed before the oper-
entry is ignored. If the entry is a segment-table entry, ation begins and again after the operation is com-
the common-segment bit in the entry is ignored. pleted. As is the case for all serialization operations,
CPUs are not necessarily serialized. on page 3-53 for the meaning of the terminology
used here.
After it has set an invalid bit to one, this CPU clears
selected entries from its TLB and signals all other • If the entry invalidated in storage is a segment-
CPUs in the configuration to clear selected entries table entry, the page-table-origin field in the inval-
from their TLBs. Each TLB is cleared of at least those idated entry matches the page-table-origin field
combined region-and-segment-table entries in the TLB PTE.
(CRSTEs) for which all of the following conditions are
met: Storing in the region- or segment-table entry and the
clearing of TLB entries may or may not occur if the
• The effective invalidation index and all bits to the invalid bit is already one in the region- or segment-
left of it in general register R2 match the same table entry.
part of the region-and-segment-index field in the
CRSTE. Note that when multiple table entries When multiple entries are invalidated, clearing of
are invalidated due to bits 53-63 of general regis- TLB entries may be delayed until all entries have
ter R2, then the effective invalidation index is been invalidated.
incremented, a carry out of the leftmost bit posi-
tion of the index is lost, and CRSTEs are cleared Clearing-by-ASCE Operation
for each value of the index so obtained.
When bit 52 of general register R2, the clearing-by-
• Either R3 is zero or the table-origin and designa- ASCE-option bit, is one, the clearing-by-ASCE oper-
tion-type fields in general register R3 match the ation is specified.
table-origin and designation-type fields in the
address-space-control element (ASCE) used to The contents of general register R3 have the format
form the CRSTE. This ASCE is the one that of an address-space-control element with only the
attached the translation path from which the table origin, bits 0-51, and designation-type control
CRSTE was formed. See “Formation of TLB (DT), bits 60 and 61, used. These contents are used
Entries” on page 3-53 for the meaning of the ter- to select TLB entries to be cleared. Bits 52-59, 62,
minology used here. and 63 of general register R3 are ignored. R3 may be
zero or nonzero, that is, any general register, includ-
• If the entry invalidated in storage is a segment- ing register 0, may be designated.
table entry, the page-table-origin field in the inval-
idated entry matches the page-table-origin field Bits 44-51 of general register R2 must be zeros; oth-
in the CRSTE. erwise, a specification exception is recognized.
Each TLB is also cleared of at least those page-table The contents of general register R1 and of bit posi-
entries (PTEs) for which all of the following conditions tions 0-43 and 53-63 of general register R2 are
are met: ignored.
• The TLB PTE was formed through use of an The contents of the general registers just described
entry invalidated in storage or through use of a are shown in Figure 10-14 on page 10-31.
CRSTE formed through use of an entry invali-
dated in storage. The TLBs of all CPUs in the configuration are cleared
• Either R3 is zero or the table-origin and designa- of at least those combined region-and-segment-table
tion-type fields in general register R3 match the entries (CRSTEs) for which the table-origin and des-
table-origin and designation-type fields in the ignation-type fields in general register R3 match the
address-space-control element (ASCE) used to table-origin and designation-type fields in the
form the TLB PTE. This ASCE may be one that address-space-control element (ASCE) used to form
attached a translation path containing a seg- the CRSTE. This ASCE is the one that attached the
ment-table entry that attached the PTE in stor- translation path from which the CRSTE was formed.
age from which the TLB PTE was formed, or it See “Formation of TLB Entries” on page 3-53 for the
may be one that made usable a CRSTE that meaning of the terminology used here.
attached the PTE in storage from which the TLB
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 000000001 / / / / / / / / / / /
0 44 52 53 63
Figure 10-14. Register Contents for INVALIDATE DAT TABLE ENTRY Clearing-by-ASCE Operation (Bit 52 of GR R2 Is
One)
The operation is suppressed on all addressing and 2. When using the clearing-by-ASCE operation to
protection exceptions (invalidation-and-clearing oper- clear TLB entries associated with common seg-
ation only). ments, note that these entries may have been
formed through use of address-space-control
Resulting Condition Code: The code is unpredict- elements containing many different table origins.
able.
R1 Page-Table Origin / / / / / / / / / / /
0 53 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Page Index / / / / / / / / / / / /
0 44 52 63
R3 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Additional Entries
0 56 63
When the IPTE-range facility is not installed, the R3 addition is performed by using the rules for 64-bit
field is ignored but should contain zeros; otherwise, address arithmetic, regardless of the current
the program may not operate compatibly in the addressing mode, which is specified by bits 31 and
future. 32 of the current PSW. A carry out of bit position 0 as
a result of the addition of the page index and page-
The page-table origin and the page index designate table origin cannot occur. The address formed from
a page-table entry, following the dynamic-address- these two components is a real or absolute address.
translation rules for page-table lookup. The page- The page-invalid bit of this page-table entry is set to
table origin is treated as a 64-bit address, and the one. During this procedure, the page-table entry is
case, if bit 62 is zero, then the AX-old is left SASTEIN in control register 3.
unchanged in the control register and becomes the
AX-new, or, if bit 62 is one, AX-new is set equal to SASN translation is performed only when, but not
AX-d. necessarily when, SASN-d is not equal to PASN-d.
When SASN-d is equal to PASN-d, SASCE-new and
The PASN translation follows the normal rules for SASTEIN-new are set equal to PASCE-new and
ASN translation, except that the invalid bits, bit 0 in PASTEIN-new, respectively. In this case, there is not
the ASN-first-table entry and bit 0 in the ASTE, when a test of whether SASTEIN-d is equal to PASTEIN-d;
ones, do not result in an ASN-translation exception. SASTEIN-d is ignored. When SASN-d is not equal to
When either of the invalid bits is one, condition code PASN-d and is equal to SASN-old, bit 61 (force ASN
1 is set. Condition code 1 is also set if PASN transla- translation) is zero, and bit 63 (skip SASN authoriza-
tion occurs, the ASN-and-LX-reuse facility is tion) is one, SASN translation is not performed, and
enabled, and PASTEIN-d is not equal to the ASTEIN SASCE-old and SASTEIN-old become SASCE-new
in the ASTE. When a reason for setting condition and SASTEIN-new, respectively. In this case, there is
code 1 does not exist and either the current primary not a test of whether SASTEIN-d is equal to SAS-
space-switch-event-control bit in control register 1 is TEIN-old; SASTEIN-d is ignored.
one or the space-switch-event-control bit in the ASTE
is one, a space-switch event does not occur; instead, SASN translation is performed in each of the follow-
condition code 3 is set. When condition code 1 or 3 is ing cases:
set, the control registers remain unchanged.
• SASN-d is not equal to PASN-d or SASN-old.
The contents of the AX, ASCE, and ASTEIN fields in
the ASTE which is accessed as a result of the PASN • SASN-d is not equal to PASN-d but is equal to
translation are referred to as AX-p, ASCE-p, and SASN-old, and either bit 61 (force ASN transla-
ASTEIN-p, respectively. The origin of the ASTE is tion) of the second-operand address is one or bit
referred to as PASTEO-p. 63 (skip secondary authority test) of that address
is zero. (The translation must be performed when
The description in this paragraph applies to use of bit 63 is zero in order to obtain the ATO and ATL
the subspace-group facility. After ASCE-p has been from the SASTE.)
obtained, if (1) the subspace-group-control bit, bit 54
in ASCE-p, is one, (2) the dispatchable unit is sub- The SASN translation follows the normal rules for
space active, and (3) PASTEO-p designates the ASN translation, except that the invalid bits, bit 0 in
ASTE for the base space of the dispatchable unit, the ASN-first-table entry and bit 0 in the ASTE, when
then a copy of ASCE-p, called ASCE-rp, is made, ones, do not result in an ASN-translation exception.
and bits 0-55 and 58-63 of ASCE-rp are replaced by When either of the invalid bits is one, condition code
the same bits of the ASCE in the ASTE for the sub- 2 is Condition code 2 is also set if SASN translation
space in which the dispatchable unit last had control. occurs, the ASN-and-LX-reuse facility is enabled,
Further details are in “Subspace-Replacement Oper- and SASTEIN-d is not equal to the ASTEIN in the
ations” on page 5-65. If bit 0 in the subspace ASTE is ASTE. When condition code 2 is set, the control reg-
one, or if the ASTE sequence number (ASTESN) in isters remain unchanged.
the subspace ASTE does not equal the subspace
ASTESN in the dispatchable-unit control table, an The contents of the ASCE, ATO, ATL and ASTEIN
exception is not recognized; instead, condition code fields in the ASTE which is accessed as a result of
1 is set, and the control registers remain unchanged. the SASN translation are referred to as ASCE-s,
ATO-s, ATL-s, and ASTEIN-s, respectively. The origin
SASN Translation and Related Processing of the ASTE is referred to as SASTEO-s.
In the SASN-translation process, the SASN-d is The description in this paragraph applies to use of
translated by means of the ASN first table and the the subspace-group facility. After ASCE-s has been
ASN second table. The ASCE field obtained from the obtained, if (1) the subspace-group-control bit, bit 54
ASTE subsequently replaces the secondary ASCE in ASCE-s, is one, (2) the dispatchable unit is sub-
(SASCE) in control register 7. When ASN-and-LX space active, and (3) SASTEO-s designates the
reuse is enabled, SASTEIN-d is compared to the ASTE for the base space of the dispatchable unit,
control register 5, and zeros are placed in bit number in the subspace ASTE during a subspace-
positions 32 and 58-63. Bits 0-31 of the register replacement operation on the ASCE-s, or (3) SASN
remain unchanged. authorization is called for and the SASN is not autho-
rized, or condition code 2 is set, and the control reg-
• When PASN translation is not performed, the isters are not changed.
contents of control registers 1 and 5 remain
unchanged. Special Conditions
The secondary address-space-control element The instruction can be executed only when the ASN-
(SASCE) in control register 7 is replaced as follows: translation control, bit 44 of control register 14, is
one. If the ASN-translation-control bit is zero, a spe-
• When SASN-d equals PASN-d, by the new con- cial-operation exception is recognized.
tents of control register 1, the PASCE. The new
contents may be PASCE-old, ASCE-p, or The first operand must be designated on a double-
ASCE-rp. word boundary; otherwise, a specification exception
• When SASN translation is performed, by is recognized.
ASCE-s, or by ASCE-rs if a subspace-replace-
ment operation was performed on ASCE-s. The operation is suppressed on all addressing and
protection exceptions.
When SASN-d does not equal PASN-d and SASN
translation is not performed, the SASCE remains Figure 10-18 on page 10-42 and Figure 10-16 on
unchanged. page 10-40 summarize the functions of the instruc-
tion and the priority of recognition of exceptions and
Other Condition-Code Settings condition codes.
When PASN translation is called for and cannot be Resulting Condition Code:
completed because bit 0 is one in either the ASN-
first-table entry or the ASTE, or if it can be completed 0 Translation and authorization complete; parame-
but (1) ASN-and-LX reuse is enabled and PASTEIN- ters loaded
d does not equal the ASTEIN in the ASTE or (2) a 1 Primary ASN or subspace not available; parame-
subspace-replacement-exception condition exists ters not loaded
due to bit 0 or the ASTE sequence number in the 2 Secondary ASN not available or not authorized,
subspace ASTE during a subspace-replacement or secondary subspace not available; parame-
operation on the ASCE-p, condition code 1 is set, ters not loaded
and the control registers are not changed. 3 Space-switch event specified; parameters not
loaded
When PASN translation is called for and completed
and any required PASTEIN-d comparison and sub- Program Exceptions:
space-replacement operations on the ASCE-p are
also completed, and then either (1) the current pri- • Access (fetch, operand 1)
mary space-switch-event-control bit, bit 57 of control • Addressing (ASN-first-table entry, ASN-second-
register 1, is one or (2) the space-switch-event-con- table entry, authority-table entry, dispatchable-
trol bit in the ASTE designated by PASTEO-p is one, unit control table)
condition code 3 is set, and the control registers are • Privileged operation
not changed. • Special operation
• Specification
When SASN translation is called for and the transla-
tion cannot be completed because bit 0 is one in Programming Notes:
either the ASN-first-table entry or the ASTE, or if it
can be completed but (1) ASN-and-LX reuse is 1. Bits 61 and 63 in the second-operand address
enabled and SASTEIN-d does not equal the ASTEIN are intended primarily to provide improved per-
in the ASTE, (2) a subspace-replacement-exception formance for those cases where the associated
action is unnecessary.
Bit 63, when one, eliminates the SASN-authori- 3. The storage-operand references for LOAD
zation test. The program may be able to deter- ADDRESS SPACE PARAMETERS may be multi-
mine in certain cases that the SASN is ple-access references. (See “Storage-Operand
authorized, either because of prior use or Consistency” on page 5-95.)
because the AX being loaded is authorized to
access all address spaces. 4. See Figure 10-17 on page 10-41 for a listing of
abbreviations used in this instruction description.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B.2 Special-operation exception due to the ASN-translation control, bit 44 of control register 14, being zero.
8. Specification exception.
10.2 Condition code 1 due to I bit (bit 0) in ASN-first-table entry being one.
10.4 Condition code 1 due to (1) I bit (bit 0) in ASN-second-table entry (ASTE) being one or (2) ASN-and-LX
reuse enabled and primary ASTE instance number (PASTEIN) in first operand not being equal to ASTEIN in
ASTE.
10.7 Condition code 1 due to I bit (bit 0) in subspace ASN-second-table entry being one.
10.8 Condition code 1 due to subspace ASN-second-table-entry sequence number (SSASTESN) in dispatchable-
unit control table not being equal to ASTESN in subspace ASN-second-table entry.
10.9 Condition code 3 due to either the old or new space-switch-event-control bit being one.
11.2 Condition code 2 due to I bit (bit 0) in ASN-first-table entry being one.
11.4 Condition code 2 due to (1) I bit (bit 0) in ASN-second-table entry (ASTE) being one or (2) ASN-and-LX
reuse enabled and secondary ASTE instance number (SASTEIN) in first operand not being equal to ASTEIN
in ASTE.
12.B.3 Condition code 2 due to I bit (bit 0) in subspace ASN-second-table entry being one.
12.B.4 Condition code 2 due to subspace ASN-second-table-entry sequence number (SSASTESN) in dispatchable-
unit control table not being equal to ASTESN in subspace ASN-second-table entry.
First-Operand Bit
Positions when ASN-and-
LX Reuse Enabled Abbreviation
0-31 SASTEIN-d
32-47 PKM-d
48-63 SASN-d
64-95 PASTEIN-d
96-111 AX-d
112-127 PASN-d
Second-
Operand-
PASN
PASN-d Address
1 Translation
Equals Bits Result Field
Performed
PASN- PASCE- AX- PASTEO- PKM- SASN- PASN- PASTEIN-
old 61 62 new new new new new new new
Yes 0 0 No PASCE-old AX-old PASTEO-old PKM-d SASN-d PASN-d PASTEIN-old
Yes 0 1 No PASCE-old AX-d PASTEO-old PKM-d SASN-d PASN-d PASTEIN-old
Yes 1 0 Yes ASCE-p2 AX-p PASTEO-p PKM-d SASN-d PASN-d PASTEIN-d
Yes 1 1 Yes ASCE-p2 AX-d PASTEO-p PKM-d SASN-d PASN-d PASTEIN-d
No - 0 Yes ASCE-p2 AX-p PASTEO-p PKM-d SASN-d PASN-d PASTEIN-d
No - 1 Yes ASCE-p2 AX-d PASTEO-p PKM-d SASN-d PASN-d PASTEIN-d
Figure 10-18. Summary of Actions: LOAD ADDRESS SPACE PARAMETERS (Part 1 of 2).
Second-Operand-
1
SASN-d SASN-d Address Bits SASN SASN Result Field
Equals Equals Translation Authorization SASTEIN-
3
PASN-d SASN-old 61 63 Performed Performed SASCE-new new
Yes - - - No No PASCE-new PASTEIN-new
No Yes 0 1 No No SASCE-old SASTEIN-old
No Yes 1 1 Yes No ASCE-s4 SASTEIN-d
No Yes - 0 Yes Yes ASCE-s4 SASTEIN-d
No No - 1 Yes No ASCE-s4 SASTEIN-d
No No - 0 Yes Yes ASCE-s4 SASTEIN-d
Explanation:
- Action in this case is the same regardless of the outcome of this comparison or of the setting of this bit.
1
Second-operand-address bits:
61 Force ASN translation.
62 Use AX from first operand.
63 Skip secondary authority test.
2
PASCE-new is ASCE-rp (a copy of ASCE-p except with bits 0-55 and 58-63 replaced from the ASCE in the
subspace ASTE), if subspace replacement is performed.
3
SASN authorization is performed using ATO-s, ATL-s, and AX-new.
4
SASCE-new is ASCE-rs (a copy of ASCE-s except with bits 0-55 and 58-63 replaced from the ASCE in the
subspace ASTE), if subspace replacement is performed.
Figure 10-18. Summary of Actions: LOAD ADDRESS SPACE PARAMETERS (Part 2 of 2).
PASCE-tmp I ASCE-p *
PASTEO-tmp I PASTEO-p
AX-tmp I AX-p
PASTEIN-tmp I PASTEIN-d
SASN Translation
SASN-d =
PASN-d ?
No SASN-d = SASN-old ASN available &
SASTEIN-d = ASTEIN-s &
Yes
& Op-2-addr. bit 61 = 0 Cond Code I 2
& Op-2-addr. bit 63 = 1 No subspace available No
? (if required)
Yes Yes
SASCE-tmp I PASCE-tmp SASCE-tmp I SASCE-old SASCE-tmp I ASCE-s **
SASTEIN-tmp I PASTEIN-tmp SASTEIN-tmp I SASTEIN-old SASTEIN-tmp I SASTEIN-d
Op-2-addr.
Yes bit 63 = 1 ?
Op-2-addr.
bit 62 = 1 No No
Exception Code
code 2 . Name Cause (hex)
ASCE type ASCE is a region-second-table 0038
Exception Code Expected designation, and bits 0-10 of virtual
Name Cause (hex) TT Bits address not all zeros; ASCE is a
Region first Invalid bit is one in the 0039 11 region-third-table designation, and
translation region-first-table entry bits 0-21 of virtual address not all
selected by the RFX zeros; or ASCE is a segment-table
portion of the virtual designation, and bits 0-32 of virtual
address. address not all zeros.
Region Invalid bit is one in the 003A 10 Region first Region-first-table entry selected by 0039
second region-second-table entry translation RFX portion of virtual address
translation selected by the RSX outside table.
portion of the virtual Region Region-second-table entry selected 003A
address. second by RSX portion of virtual address
Region third Invalid bit is one in the 003B 01 translation outside table.
translation region-third-table entry Region third Region-third-table entry selected by 003B
selected by the RTX translation RTX portion of virtual address
portion of the virtual outside table.
address.
Segment Segment-table entry selected by SX 0010
Segment Invalid bit is one in the 0010 00 translation portion of virtual address outside
translation segment-table entry table.
selected by the SX
portion of the virtual Figure 10-21. LPTEA Exception Conditions Causing CC3
address.
Special Conditions
Figure 10-20. LPTEA Exception Conditions Causing CC2
If the M4 field contains any value other than
When a condition exists that would normally cause 0000-0100 binary, a specification exception is recog-
one of the exceptions shown in Figure 10-21, (1) the nized.
interruption code assigned to the exception is placed
in bit positions 48-63 of general register R1, and bits The address-space-control element used in the
0-47 of the register are set to zeros; and (2) the translation must not be a real-space designation; oth-
instruction is completed by setting condition code 3. erwise, a special-operation exception is recognized.
The exception due to the address-space-control ele-
Exception Code ment has priority 9 in Figure 6-6 on page 6-45.
Name Cause (hex)
ALET ALET bits 0-6 not all zeros. 0028 An addressing exception is recognized when the
specification address used by ART to fetch the effective access-
ALEN ALE outside list or I bit is one. 0029 list designation, the access-list entry, the address-
translation space-second-table entry, or the authority-table entry
ALE ALESN in ALET not equal to ALESN 002A designates a location which is not available in the
sequence in ALE. configuration. An addressing exception is also recog-
ASTE ASTE I bit is one. 002B nized when the address used by DAT to fetch a
validity region-table entry or the segment-table entry desig-
nates a location which is not available in the configu-
ASTE ASTESN in ALE not equal to 002C
ration.
sequence ASTESN in ASTE.
Extended ALE P bit not zero, ALEAX not equal 002D A carry out of bit position 0 as a result of the addition
authority to EAX, and secondary bit selected
done to compute the address of a region-table entry
by EAX either outside authority table
or the segment-table entry may be ignored or may
or zero.
result in an addressing exception.
Figure 10-21. LPTEA Exception Conditions Causing CC3
LOAD PSW
an accessed region-table entry or the segment-table the table entry designated by general regis-
entry has a zero I bit and a format error. ter R1 must contain 00 binary (designating a
segment-table entry).
The operation is suppressed on all addressing
exceptions. The following program fragment illustrates this
determination. If no branch is taken, then the
Resulting Condition Code: address in general register 1 is that of a seg-
ment-table entry in which the STE-format control
0 PTE address returned; STE P bit is 0 is one:
1 PTE address returned; STE P bit is 1
2 Invalid bit is one in the region- or segment-table LPTEA 1,0,2,4
BRC 8,PTE_WITH_NEITHER_STE_NOR_RTE_PROT
entry, or enhanced DAT applies, a valid STE was
BRC 4,PTE_WITH_PROTECTED_STE_OR_RTE
located, and STE FC is 1
BRC 1,EXCEPTION_EXISTS
3 Exception condition exists TMLL 1,X'0003'
BRNZ NOT_STE
Program Exceptions: NILL 1,X'FFF8'
LURAG 10,1
• Addressing (effective access-list designation, TMLL 10,X'002C'
access-list entry, ASN-second-table entry, BRNZ INVALID_OR_MALFORMED_STE
authority-table entry, region-table entry, or seg-
ment-table entry) 3. When condition code 2 is set as a result of locat-
• Operation (DAT-enhancement facility 2 not ing a valid segment-table entry in which the STE-
installed) format control is one, bit 61 of general register R1
• Privileged operation indicates whether DAT protection applies to the
• Special operation segment.
• Specification
• Translation specification
LOAD PSW
Programming Notes:
LPSW D2(B2) [S]
1. An addressing exception is not recognized if the '82' / / / / / / / / B2 D2
page-table-entry address returned in general 0 16 20 31
register R1 is not available in the configuration.
2. When enhanced DAT applies, the STE-format The current PSW is replaced by a 16-byte PSW
control is one, and no other exception conditions formed from the contents of the doubleword at the
apply, the address of the segment-table entry is location designated by the second-operand address.
placed in general register R1, and condition code
2 is set. This effectively performs a load-seg- Bit 12 of the doubleword must be one; otherwise, a
ment-table-entry-address function, although no specification exception may be recognized, depend-
such instruction is defined. ing on the model.
However, because condition code 2 is also used Bits 0-32 of the doubleword, except with bit 12
to indicate an invalid region-table entry or seg- inverted, are placed in bit positions 0-32 of the cur-
ment-table entry, all of the following conditions rent PSW. Bits 33-63 of the doubleword are placed in
must exist in order to assume that the located bit positions 97-127 of the current PSW. Bits 33-96 of
table entry is a valid STE: the current PSW are set to zeros.
a. Bit positions 62-63 of general register R1 (the
A serialization and checkpoint-synchronization func-
expected table-type) must contain 00 binary.
tion is performed before or after the operand is
b. Bit position 58 of the table entry designated fetched and again after the operation is completed.
by general register R1 must contain zero
(indicating a valid table entry).
the model.
The current PSW is replaced by the contents of the
The PSW fields which are to be loaded by the 16-byte second operand.
instruction are not checked for validity before they are
loaded, except for the optional checking of bit 12. A serialization and checkpoint-synchronization func-
However, immediately after loading, a specification tion is performed before or after the operand is
exception is recognized, and a program interruption fetched and again after the operation is completed.
occurs, when any of the following is true for the newly
loaded PSW: Special Conditions
• Any of bits 0, 2-4, 12, or 24-30 is a one. The operand must be designated on a doubleword
boundary; otherwise, a specification exception is rec-
• Bits 31 and 32 are both zero, and bits 97-103 are
ognized.
not all zeros.
• Bits 31 and 32 are one and zero, respectively. The value which is to be loaded by the instruction is
not checked for validity before it is loaded. However,
In these cases, the operation is completed, and the immediately after loading, a specification exception is
resulting instruction-length code is 0. recognized, and a program interruption occurs, when
any of the following is true for the newly loaded PSW:
The test for a specification exception after the PSW
is loaded is described in “Early Exception Recogni- • Any of the unassigned bits (0, 2-4, 24-30, or
tion” on page 6-8. It may be considered as occurring 33-63) is a one.
early in the process of preparing to execute the sub-
• Bit 12 is a one.
sequent instruction.
• Bits 31 and 32 are zero and one, respectively,
The operation is suppressed on all addressing and and bits 64-96 are not all zeros.
protection exceptions.
• Bits 31 and 32 are both zero, and bits 64-103 are
Resulting Condition Code: The code is set as not all zeros.
specified in the new PSW loaded.
• Bits 31 and 32 are one and zero, respectively.
Program Exceptions:
In these cases, the operation is completed, and the
resulting instruction-length code is zero.
• Access (fetch, operand 2)
• Privileged operation
The test for a specification exception after the PSW
• Specification
is loaded is described in “Early Exception Recogni-
tion” on page 6-8. It may be considered as occurring
Programming Note: The second operand should
early in the process of preparing to execute the sub-
have the format of an ESA/390 PSW. A specification
sequent instruction.
exception will be recognized during or after the exe-
cution of LOAD PSW if bit 12 of the operand is zero.
The operation is suppressed on all addressing and
protection exceptions.
(2) the instruction is completed by setting condition except that LRA or LRAY is in the 24-bit or 31-bit
code 3. addressing mode, if bits 0-32 of the address of the
page-table entry are all zeros, the result is the same
Exception Code except that bits 0-31 of general register R1 remain
Name Cause (Hex) unchanged. If bits 0-32 of the address are not all
ALET Access-list-entry-token (ALET) bits 0028 zeros, the result is as shown in the next table below.
specification 0-6 not all zeros
ALEN Access-list entry (ALE) outside list 0029 A segment-table-entry or page-table-entry address
translation or invalid (bit 0 is one) placed in general register R1 is real or absolute in
accordance with the type of address that was used
ALE ALE sequence number (ALESN) in 002A
during the attempted translation.
sequence ALET not equal to ALESN in ALE
ASTE ASN-second-table entry (ASTE) 002B If a condition exists that would normally cause one of
validity invalid (bit 0 is one)
the exceptions shown in the following table, (1) the
ASTE ASTE sequence number (ASTESN) 002C interruption code assigned to the exception is placed
sequence in ALE not equal to ASTESN in in bit positions 48-63 of general register R1, bit 32 of
ASTE this register is set to one, bits 33-47 are set to zeros,
Extended ALE private bit not zero, ALE 002D and bits 0-31 remain unchanged, and (2) the instruc-
authority authorization index (ALEAX) not tion is completed by setting condition code 3.
equal to extended authorization
index (EAX), and secondary bit
selected by EAX either outside Exception Code
authority table or zero Name Cause (Hex)
ASCE type Address-space-control element 0038
When ART is completed normally, the operation is (ASCE) being used is a region-
continued through the performance of DAT. second-table designation, and bits
0-10 of virtual address not all zeros;
When the segment-table entry is outside the table ASCE is a region-third-table
and bits 0-32 of the real or absolute address of the designation, and bits 0-21 of virtual
entry are all zeros, condition code 3 is set, bits 32-63 address not all zeros; or ASCE is a
of the entry address are placed in bit positions 32-63 segment-table designation, and bits
of general register R1, and bits 0-31 of the register 0-32 of virtual address not all zeros.
remain unchanged. If bits 0-32 of the address are not Region first Region-first-table entry selected by 0039
all zeros, the result is as shown in the next table translation region-first-index portion of virtual
below. address outside table or invalid.
Region Region-second-table entry selected 003A
For LRA or LRAY in the 64-bit addressing mode or second by region-second-index portion of
LRAG in any addressing mode, when the I bit in the translation virtual address outside table or
segment-table entry is one, condition code 1 is set, invalid.
and the 64-bit real or absolute address of the seg- Region third Region-third-table entry selected by 003B
ment-table entry is placed in general register R1. In translation region-third-index portion of virtual
this case except that LRA or LRAY is in the 24-bit or address outside table or invalid.
31-bit addressing mode, if bits 0-32 of the address of Segment Segment-table entry selected by 0010
the segment-table entry are all zeros, the result is the translation segment-index portion of virtual
same except that bits 0-31 of general register R1 address outside table (only when
remain unchanged. If bits 0-32 of the address are not bits 0-32 of entry address not all
all zeros, the result is as shown in the next table zeros); or segment-table entry
below. invalid (LRA and LRAY only, and
only in 24-bit or 31-bit addressing
mode when bits 0-32 of entry
For LRA or LRAY in the 64-bit addressing mode or
address not all zeros).
LRAG in any addressing mode, when the I bit in the
page-table entry is one, condition code 2 is set, and
the 64-bit real or absolute address of the page-table
LURAG R1,R2 [RRE] The contents of bit positions 32-63 of the pair of gen-
'B905' / / / / / / / / R1 R2 eral registers designated by the R1 field are placed in
0 16 24 28 31
the modifiable area, byte positions 152-159, of the
last state entry in the linkage stack.
For LOAD USING REAL ADDRESS (LURA), the The R1 field designates the even-numbered register
word at the real-storage location addressed by the of an even-odd pair of general registers.
contents of general register R2 is placed in bit posi-
tions 32-63 of general register R1, and the contents The last state entry is located as described in
of bit positions 0-31 remain unchanged. For LOAD “Unstacking Process” on page 5-82. The state entry
USING REAL ADDRESS (LURAG), the doubleword remains in the linkage stack, and the linkage-stack-
at that real-storage location is placed in bit positions entry address in control register 15 remains
0-63 of general register R1. unchanged.
In the 24-bit addressing mode, bits 40-63 of general Key-controlled protection does not apply to the refer-
register R2 designate the real-storage location, and ences to the linkage stack, but low-address and DAT
bits 0-39 of the register are ignored. In the 31-bit protection do apply.
addressing mode, bits 33-63 of general register R2
designate the real-storage location, and bits 0-32 of Special Conditions
the register are ignored. In the 64-bit addressing
mode, bits 0-63 of general register R2 designate the A specification exception is recognized when R1 is
real-storage location. odd.
Because it is a real address, the address designating The CPU must be in the primary-space mode,
the storage word or doubleword is not subject to access-register mode, or home-space mode; other-
dynamic address translation. wise, a special-operation exception is recognized.
Condition Code: The code remains unchanged. The priority of recognition of program exceptions for
the instruction is shown in Figure 10-23 on
Program Exceptions: page 10-54.
• Addressing (address specified by general regis- Condition Code: The code remains unchanged.
ter R2)
• Privileged operation Program Exceptions:
• Protection (fetch, operand 2, key-controlled pro-
tection) • Access (fetch and store, except for key-controlled
• Specification protection, linkage-stack entry)
• Special operation
• Specification
• Stack empty
• Stack type
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B Special-operation exception due to DAT being off or the CPU being in secondary-space mode.
8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry.
8.B.2 Stack-type exception due to current entry not being a state entry or header entry.
Note: Exceptions 8.B.3-8.B.7 can occur only if the current entry is a header entry.
8.B.3 Access exceptions (fetch) for second word of the header entry.
8.B.4 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero.
8.B.5 Access exceptions (fetch) for entry descriptor of preceding entry, which is the entry designated by the
backward stack-entry address in the current (header) entry.
8.B.7 Stack-type exception due to preceding entry not being a state entry.
8.B.8 Access exceptions (store) for the modifiable area of the state entry.
MOVE PAGE appended, are the address, and bits 0-39 and 52-63
in the register are ignored. In the 31-bit addressing
MVPG R1,R2 [RRE] mode, the contents of bit positions 33-51 of a general
register, with 12 rightmost zeros appended, are the
'B254' / / / / / / / / R1 R2 address, and bits 0-32 and 52-63 in the register are
0 16 24 28 31 ignored. In the 64-bit addressing mode, the contents
of bit positions 0-51 of a general register, with 12
The first operand is replaced by the second operand. rightmost zeros appended, are the address, and bits
The first and second operands both are 4K bytes on 52-63 in the register are ignored.
4K-byte boundaries. The results are indicated in the
condition code. The accesses to the first-operand Bits 56-59 of general register 0 are used as the spec-
location or the second-operand location, but not to ified access key. Bit 52 of general register 0, when
both locations, may be performed by using the key one, specifies that the specified access key is to be
specified in general register 0; otherwise, the used for accessing the first operand, and bit 53 spec-
accesses to an operand location are performed by ifies the same for the second operand. A specifica-
using the PSW key. tion exception is recognized if bits 52 and 53 are both
ones. Bit 54 of general register 0 is a destination-ref-
The location of the leftmost byte of the first operand erence-intention bit, and bit 55 is a condition-code-
and second operand is designated by the contents of option bit. Bits 48-51 of general register 0 must be
general registers R1 and R2, respectively. zeros; otherwise, a specification exception is recog-
nized. Bits 0-47 and 60-63 of general register 0 are
The handling of the addresses in general registers R1 ignored.
and R2 depends on the addressing mode. In the
24-bit addressing mode, the contents of bit positions The contents of the registers just described are
40-51 of a general register, with 12 rightmost zeros shown in Figure 10-24 on page 10-55.
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address / / / / / / / / / / / /
0 40 52 63
R2 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Second-Operand Address / / / / / / / / / / / /
0 33 52 63
R2 Second-Operand Address / / / / / / / / / / / /
0 52 63
Explanation:
When bit 52 of general register 0 is one, the fetch condition code 1 or 2 is set. Condition code 1 is set if
accesses to the second-operand location are per- a page-translation-exception condition exists for the
formed by using the PSW key, and the store first operand and not for the second operand. Condi-
accesses to the first-operand location are performed tion code 2 is set if a page-translation-exception con-
by using the key specified in general register 0. When dition exists for the second operand, regardless of
bit 53 of general register 0 is one, the fetch accesses whether the condition exists for the first operand.
to the second-operand location are performed by
using the key specified in general register 0, and the When an access exception can be recognized for
store accesses to the first-operand location are per- both operands, it is unpredictable for which operand
formed by using the PSW key. When bits 52 and 53 an exception is recognized. If one of the exceptions is
are both zeros, the PSW key is used for accessing a page-translation exception that would cause condi-
both operands. tion code 1 or 2 to be set, it is unpredictable whether
the access exception for the other operand is recog-
When 4K bytes have been moved, condition code 0 nized or condition code 1 or 2 is set.
is set.
The references to main storage are not necessarily
When a page-translation-exception condition exists, single-access references and are not necessarily
the exception is not recognized if the condition-code- performed in a left-to-right direction, as observed by
option bit, bit 55 in general register 0, is one; instead, other CPUs and by channel programs.
more efficiently.
In the problem state, when either bit 52 or bit 53 in
general register 0 is one, the operation is performed 3. The condition-code-option bit provides compati-
only if the access key specified in general register 0 bility with the MOVE PAGE instruction of the
is valid, that is, if the corresponding PSW-key-mask ESA/390 move-page facility 1. The bit is for use
bit in control register 3 is one. Otherwise, a privi- by the MVS/ESA HSPSERV macro expansion.
leged-operation exception is recognized. In the 4. The condition code set by the instruction nor-
supervisor state, any value for the specified access mally need not be examined if the condition-
key is valid. When bits 52 and 53 are both zeros, the code-option bit is zero or if DAT is off.
access key in general register 0 is not tested for
validity. 5. See the definitions of real locations 162 and
168-175 under “Assigned Storage Locations” in
In the problem state, when bits 52 and 53 in general Chapter 3, “Storage” for a description of informa-
register 0 are both ones and the access key in gen- tion stored during a program interruption due to a
eral register 0 is not permitted by the PSW-key mask, DAT-related translation exception recognized by
it is unpredictable whether a specification exception MOVE PAGE.
or a privileged-operation exception is recognized.
MOVE TO SECONDARY
address is translated by using the secondary ger called the true length. In the 24-bit or 31-bit
address-space-control element. addressing mode, the true length is in bit positions
32-63 of the register, and the contents of bit positions
For MOVE TO SECONDARY, movement is to the 0-31 of the register are ignored. In the 64-bit
secondary space from the primary space. The first- addressing mode, the true length is in bit positions
operand address is translated by using the second- 0-63 of the register.
ary address-space-control element, and the second-
operand address is translated by using the primary The contents of the general registers just described
address-space-control element. are shown in Figure 10-25 on page 10-57.
The first and second operands are the same length, zation function is performed before the operation
called the effective length. The effective length is begins and again after the operation is completed.
equal to the true length or 256, whichever is less.
Access exceptions for the first and second operands Special Conditions
are recognized only for that portion of the operand
within the effective length. When the effective length Since the secondary space is accessed, the opera-
is zero, no access exceptions are recognized for the tion is performed only when the secondary-space
first and second operands, and no movement takes control, bit 37 of control register 0, is one and DAT is
place. on. When either the secondary-space control is zero
or DAT is off, a special-operation exception is recog-
Each storage operand is processed left to right. The nized. A special-operation exception is also recog-
storage-operand-consistency rules are the same as nized when the address-space-control bits in the
for MOVE (MVC), except that when the operands current PSW specify the access-register or home-
overlap in real storage, the use of the common real- space mode.
storage locations is not necessarily recognized.
In the problem state, the operation is performed only
As part of the execution of the instruction, the value if the secondary-space access key is valid, that is, if
of the true length is used to set the condition code. If the corresponding PSW-key-mask bit in control regis-
the true length is 256 or less, including zero, the true ter 3 is one. Otherwise, a privileged-operation excep-
length and effective length are equal, and condition tion is recognized. In the supervisor state, any value
code 0 is set. If the true length is greater than 256, for the secondary-space access key is valid.
the effective length is 256, and condition code 3 is
set. The priority of the recognition of exceptions and con-
dition codes is shown in Figure 10-26 on page 10-58.
For both MOVE TO PRIMARY and MOVE TO SEC-
ONDARY, a serialization and checkpoint-synchroni- Resulting Condition Code:
7.B Special-operation exception due to the The first operand is replaced by the second operand.
secondary-space control, bit 37 of control The accesses to the destination-operand location are
register 0, being zero, to DAT being off, or to the performed by using the key specified in general reg-
CPU being in the access-register or home-space
ister 1, and the accesses to the source-operand loca-
mode.
tion are performed by using the PSW key.
8. Privileged-operation exception due to selected
PSW-key-mask bit being zero in the problem The first and second operands are of the same
state. length, which is specified by bits 56-63 of general
register 0. Bits 0-55 of general register 0 are ignored.
9. Completion due to length zero.
10. Access exceptions for operands. Bits 56-59 of general register 1 are used as the spec-
ified access key. Bits 0-55 and 60-63 of general reg-
Figure 10-26. Priority of Execution: MOVE TO PRIMARY ister 1 are ignored.
and MOVE TO SECONDARY
The contents of general registers 0 and 1 are shown
Programming Notes: in Figure 10-27 on page 10-58.
GR0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / L
0 56 63
GR1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Key / / / /
0 56 60 63
L specifies the number of bytes to the right of the first The fetch accesses to the second-operand location
byte of each operand. Therefore, the length in bytes are performed by using the PSW key, and the store
of each operand is 1-256, corresponding to a length accesses to the first-operand location are performed
code in L of 0-255. by using the key specified in general register 1.
(MVC) instruction.
The first operand is replaced by the second operand.
Special Conditions The fetch accesses to the second-operand location
are performed by using the key specified in the third
In the problem state, the operation is performed only operand, and the store accesses to the first-operand
if the access key specified in general register 1 is location are performed by using the PSW key.
valid, that is, if the corresponding PSW-key-mask bit
in control register 3 is one. Otherwise, a privileged- Bit positions 56-59 of general register R3 are used as
operation exception is recognized. In the supervisor the source access key. Bit positions 0-55 and 60-63
state, any value for the specified access key is valid. of the register are ignored.
Condition Code: The code remains unchanged. General register R1 contains an unsigned binary inte-
ger called the true length. In the 24-bit or 31-bit
Program Exceptions: addressing mode, the true length is in bit positions
32-63 of the register, and the contents of bit positions
• Access (fetch, operand 2; store, operand 1) 0-31 of the register are ignored. In the 64-bit
• Privileged operation (selected PSW-key-mask bit addressing mode, the true length is in bit positions
is zero in the problem state) 0-63 of the register.
Programming Note: See the programming notes for The contents of the general registers just described
the MOVE WITH SOURCE KEY instruction. are shown in Figure 10-28 on page 10-59.
The first and second operands are of the same obtained as if the operands were processed one byte
length, called the effective length. The effective at a time and each result byte were stored immedi-
length is equal to the true length or 256, whichever is ately after the necessary operand byte was fetched.
less. Access exceptions for the first and second oper- The storage-operand-consistency rules are the same
ands are recognized only for that portion of the oper- as for the MOVE (MVC) instruction.
and within the effective length. When the effective
length is zero, no access exceptions are recognized As part of the execution of the instruction, the value
for the first and second operands, and no movement of the true length is used to set the condition code. If
takes place. the true length is 256 or less, including zero, the true
length and effective length are equal, and condition
Each storage operand is processed left to right. code 0 is set. If the true length is greater than 256,
When the storage operands overlap, the result is
set.
1. MOVE WITH KEY can be used in a loop to move
Special Conditions a variable number of bytes of any length, as fol-
lows:
In the problem state, the operation is performed only
if the source access key is valid, that is, if the corre- LOOP MVCK D1(R1,B1),D2(B2),R3
sponding PSW-key-mask bit in control register 3 is BC 8,END
one. Otherwise, a privileged-operation exception is AHI B1,256
recognized. In the supervisor state, any value for the AHI B2,256
source access key is valid. AHI R1,-256
B LOOP
END [Any instruction]
The priority of the recognition of exceptions and con-
dition codes is shown in Figure 10-29 on page 10-60.
The above program is for execution in the 24-bit
or 31-bit addressing mode. In the 64-bit address-
Resulting Condition Code:
ing mode, AGHI instructions should be substi-
tuted for the AHI instructions.
0 True length less than or equal to 256
1 -- 2. The performance of MOVE WITH KEY on most
2 -- models may be significantly slower than that of
3 True length greater than 256 the MOVE (MVC) and MOVE LONG instructions.
Therefore, MOVE WITH KEY should not be used
Program Exceptions: if the keys of the source and the target are the
same.
• Access (fetch, operand 2; store, operand 1)
• Privileged operation (selected PSW-key-mask bit
is zero in the problem state) MOVE WITH OPTIONAL
SPECIFICATIONS
1.-6. Exceptions with the same priority as the priority MVCOS D1(B1),D2(B2),R3 [SSF]
of program-interruption conditions for the general
case. 'C8' R3 '0' B1 D1 B2 D2
0 8 12 16 20 32 36 47
7.A Access exceptions for second and third
instruction halfwords.
The first operand is replaced by the second operand.
8. Privileged-operation exception due to selected Bits in general register 0 determine the address-
PSW-key-mask bit being zero in the problem space-control modes and protection keys that are
state. used to access the first and second operands.
9. Completion due to length zero.
The addresses of the first and second operands are
10. Access exceptions for operands. virtual.
Figure 10-29. Priority of Execution: MOVE WITH KEY
Bits 32-47 of general register 0 contain the operand-
access control for the first operand (OAC1), and bits
48-63 of general register 0 contain the operand-
access control for the second operand (OAC2). The
operand-access control has the following format.
Key / / / / AS / / / / K A
0 4 8 10 14 15
Specified-Address-Space Control (AS): Bit posi- Bits 0-31 of general register 0 are ignored. Bits 4-7
tions 8-9 contain the address-space control that is and 10-14 of both operand-access controls (that is,
used to access the operand when the specified- bits 36-39, 42-45, 52-55, and 58-61 of general regis-
address-space-control validity bit (A) is one; other- ter 0) are reserved and should contain zeros; other-
wise, the specified-address-space control is ignored. wise, the program may not operate compatibly in the
The meaning of bits 8-9 is identical to that of the future.
address-space control in bits 16-17 of the PSW.
General register R3 contains an unsigned binary inte-
Specified-Access-Key Validity Bit (K): Bit 14 ger called the true length. In the 24-bit or 31-bit
controls whether the PSW key or the specified- addressing mode, the true length is in bit positions
access key is used to access the operand. When the 32-63 of the register, and the contents of bit positions
K bit is zero, the PSW key is used. When the K bit is 0-31 of the register are ignored. In the 64-bit
one, the specified-access key is used. addressing mode, the true length is in bit positions 0-
63 of the register.
Specified-Address-Space-Control Validity Bit
(A): Bit 15 controls whether the address-space The contents of the general registers just described
control in the current PSW or the address-space con- are shown in Figure 10-30.
trol in the specified-ASC is used to access the oper-
The first and second operands are the same length, No test is made for destructive overlap, and the
called the effective length. The effective length is results in the first-operand location are unpredictable
equal to the true length or 4,096, whichever is less. when destructive overlap exists. Operands are said
Access exceptions for the first and second operands to overlap destructively when the first-operand real
are recognized only for that portion of the operand location is used as a source after data has been
within the effective length. When the effective length moved into it.
is zero, no access exceptions are recognized for the
first and second operands, and no movement takes Operands do not overlap destructively if the leftmost
place. byte of the first operand does not coincide with any of
the second-operand bytes participating in the opera-
As part of the execution of the instruction, the value tion other than the leftmost byte of the second oper-
of the true length is used to set the condition code. If and. When an operand wraps around from location
24 31 64
the true length is 4,096 or less, including zero, then 2 - 1 (or 2 - 1 or 2 - 1) to location 0, operand
24
the true length and effective length are equal, and bytes in locations up to and including 2 - 1 (or
31 64
condition code 0 is set. If the true length is greater 2 - 1 or 2 - 1) are considered to be to the left of
than 4,096, then the effective length is 4,096, and bytes in locations from 0 up.
condition code 3 is set.
location 224 - 1 to location 0; in the 31-bit addressing specified-access-key control, bit 62 of general
mode, wraparound is from location 231 - 1 to location register 0, is one; and the specified-access key,
0; and, in the 64-bit addressing mode, wraparound is bits 48-51 of the register, designates a PKM bit
from location 264 - 1 to location 0. position that contains zero.
• DAT is off. – The PSW key, bits 8-11 of the PSW, desig-
nates a PKM bit position that contains zero.
• The address-space control in OAC1 designates
the home-space mode, the address-space-con- In the supervisor state, any value for the implied- or
trol validity bit in OAC1 is one, and the current specified-access key is valid.
PSW is in the problem state (that is, bits 40-41 of
general register 0 are 11 binary, bit 47 of the reg- The priority of the recognition of exceptions and con-
ister is one, and bit 15 of the current PSW is dition codes is shown in Figure 10-31.
one).
GR0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / L
0 56 63
GR1 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Key / / / /
0 56 60 63
L specifies the number of bytes to the right of the first Each of the operands is processed left to right.
byte of each operand. Therefore, the length in bytes When the operands overlap destructively in real stor-
of each operand is 1-256, corresponding to a length age, the results in the first-operand location are
code in L of 0-255. unpredictable. Except for this unpredictability in the
case of destructive overlap, the storage-operand-
The fetch accesses to the second-operand location consistency rules are the same as for the MOVE
are performed by using the key specified in general (MVC) instruction.
register 1, and the store accesses to the first-oper-
and location are performed by using the PSW key.
treated as zero.
In the problem state, the operation is performed only
if the access key specified in general register 1 is LTR 4,4
valid, that is, if the corresponding PSW-key-mask bit BC 12,END
in control register 3 is one. Otherwise, a privileged- AHI 4,-256
operation exception is recognized. In the supervisor BC 12,LAST
state, any value for the specified access key is valid. LA 0,255
LOOP MVCSK 0(2),0(3)
LA 2,256(2)
Condition Code: The code remains unchanged.
LA 3,256(3)
AHI 4,-256
Program Exceptions: BC 2,LOOP
LAST LA 0,255(4)
• Access (fetch, operand 2; store, operand 1) MVCSK 0(2),0(3)
• Privileged operation (selected PSW-key-mask bit END [Any instruction]
is zero in the problem state)
2. MOVE WITH SOURCE KEY and MOVE WITH Bits 32-63 of general register R2 are a 32-bit
DESTINATION KEY should be used only when unsigned binary integer called the expanded-stor-
movement is between storage areas having dif- age-block number. This number designates the 4K-
ferent keys. The performance of these instruc- byte block of expanded storage which is to be trans-
tions on most models may be significantly slower ferred. If the expanded-storage-block number desig-
than that of the MOVE (MVC) instruction. nates an inaccessible block in expanded storage,
condition code 3 is set.
3. MOVE WITH SOURCE KEY or MOVE WITH
DESTINATION KEY can be used in a loop to The contents of general register R1 are a real
move a variable number of bytes as shown in the address which designates a 4K-byte block in main
following example. In the example, the specified storage. In the 24-bit-addressing mode, bits 40-51
access key, the first-operand address, the sec- designate the block, and bits 0-39 are ignored. In the
ond-operand address, and the length of each 31-bit-addressing mode, bits 33-51 designate the
operand are assumed to be in general registers block, and bits 0-32 are ignored. In the 64-bit-
1-4, respectively, at the beginning of the exam- addressing mode, bits 0-51 designate the block. In all
ple. The length of each operand is treated as a modes, bits 52-63 of the address are ignored.
PAGE OUT
tion is performed before the operation begins and
again after the operation is completed. PGOUT R1,R2 [RRE]
If the page-in operation encounters an expanded- A page-out operation is performed which transfers a
storage data error, condition code 1 is set. For an 4K-byte block from the real-storage location desig-
expanded-storage data-error condition, the contents nated by general register R1 to the expanded-storage
of the entire 4K-byte block in real storage is unpre- block designated by general register R2.
dictable, but this condition does not result in the gen-
eration of invalid checking-block codes in real Bits 32-63 of general register R2 are a 32-bit
storage. unsigned binary integer called the expanded-stor-
age-block number. This number designates the 4K-
If the expanded-storage block is not available, that is, byte block of expanded storage which is to be
the block is not provided or is not currently in the con- replaced. If the expanded-storage-block number des-
figuration, then condition code 3 is set, and no other ignates an inaccessible block in expanded storage,
action is taken. condition code 3 is set.
Operation of PAGE IN in a Multiple-CPU Configu- The contents of general register R1 are a real
ration address which designates a 4K-byte block in main
storage. In the 24-bit-addressing mode, bits 40-51
The accesses to main storage and to expanded stor- designate the block, and bits 0-39 are ignored. In the
age by PAGE IN are not necessarily single-access 31-bit-addressing mode, bits 33-51 designate the
references and are not necessarily performed in a block, and bits 0-32 is ignored. In the 64-bit-address-
left-to-right direction, as observed by other CPUs and ing mode, bits 0-51 designate the block. In all modes,
by channel programs. bits 52-63 of the address are ignored.
See also the description under PAGE OUT. Because it is a real address, the address designating
the main-storage block is not subject to dynamic
Resulting Condition Code: address translation. PAGE OUT is not subject to key-
controlled protection.
0 Page-in operation completed
1 Expanded-storage data error A serialization and checkpoint-synchronization func-
2 -- tion is performed before the operation begins and
3 Expanded-storage block not available again after the operation is completed.
Program Exceptions: Depending on the model, after the data has been
written to the expanded-storage block, a read-back-
• Addressing (block designated by general register check operation may be performed to determine
R1) whether the data was written correctly. If the read-
• Operation (if the expanded-storage facility is not back-check operation determines that the data has
installed) been written correctly, condition code 0 is set. If the
• Privileged operation read-back-check operation encounters an expanded-
• Protection (block designated by general register storage data error, condition code 1 is set.
R1; low-address protection)
Most models do not perform the read-back-check
operation, and, after the page-out operation is com-
pleted, condition code 0 is set.
— Not applicable
In the access-register mode, access register 1 speci- The parameter block used for the function has the fol-
fies the address space containing the parameter lowing format:
block.
0
As observed by other CPUs and channel programs, Status Word
8
reference to the parameter block may be multiple- 0 63
access references, accesses to these storage loca-
tions are not necessarily block-concurrent, and the Figure 10-35. Parameter Block for PCKMO-Query
sequence of these accesses or references is unde-
fined. A 128-bit status word is stored in the parameter
block. Bits 0-127 of this field correspond to function
codes 0-127, respectively, of the PCKMO instruction.
PCKMO-Query (Function Code 0)
When a bit is one, the corresponding function is
The locations of the operands and addresses used
installed; otherwise, the function is not installed.
by the instruction are as shown in Figure 10-34 on
page 10-67.
0 Cryptographic Key (K) The parameter block used for the function has the fol-
8 DEA Wrapping-Key lowing format:
Verification Pattern
24 (WKdVP) 0
Cryptographic Key
0 63 8
(K)
16
Figure 10-36. Parameter Block for PCKMO-Encrypt-DEA-
Key 24 DEA Wrapping-Key
Verification Pattern
The 8-byte cryptographic key, K, in byte offsets 0-7 of 40 (WKdVP)
the parameter block is encrypted using the DEA 0 63
wrapping key. (See the section “Protection of Crypto-
Figure 10-38. Parameter Block for PCKMO-Encrypt-TDEA-
graphic Key” on page 7-339 for the encryption algo-
192-Key
rithm.) The result is placed back in byte offsets 0-7 of
the parameter block. The contents of the DEA wrap-
The 24-byte cryptographic key, K, in byte offsets 0-23
ping-key verification-pattern register are placed in
of the parameter block is encrypted using the DEA
byte offsets 8-31 of the parameter block.
wrapping key. (See the section “Protection of Crypto-
graphic Key” on page 7-339 for the encryption algo-
PCKMO-Encrypt-TDEA-128-Key rithm.) The result is placed back in byte offsets 0-23
(Function Code 2) of the parameter block. The contents of the DEA
The locations of the operands and addresses used wrapping-key verification-pattern register are placed
by the instruction are as shown in Figure 10-34 on in byte offsets 24-47 of the parameter block.
page 10-67.
PCKMO-Encrypt-AES-128-Key (Function
The parameter block used for the function has the fol-
Code 18)
lowing format:
The locations of the operands and addresses used
by the instruction are as shown in Figure 10-34 on
0 Cryptographic
page 10-67.
8 Key (K)
16 DEA Wrapping-Key The parameter block used for the function has the fol-
Verification Pattern lowing format:
32 (WKdVP)
0 63 0 Cryptographic
8 Key (K)
Figure 10-37. Parameter Block for PCKMO-Encrypt-TDEA-
128-Key 16
AES Wrapping-Key
Verification Pattern
The 16-byte cryptographic key, K, in byte offsets 0-15 (WKaVP)
of the parameter block is encrypted using the DEA 40
wrapping key. (See the section “Protection of Crypto- 0 63
graphic Key” on page 7-339 for the encryption algo-
rithm.) The result is placed back in byte offsets 0-15 Figure 10-39. Parameter Block for PCKMO-Encrypt-AES-
of the parameter block. The contents of the DEA 128-Key
The 24-byte cryptographic key, K, in byte offsets 0-23 1. Bit 56 of general register 0 is not zero.
of the parameter block is encrypted using the AES 2. Bits 57-63 of general register 0 specify an unas-
wrapping key. (See the section “Protection of Crypto- signed or uninstalled function code.
graphic Key” on page 7-339 for the encryption algo-
rithm.) The result is placed back in byte offsets 0-23 Condition Code: The code remains unchanged.
of the parameter block. The contents of the AES
wrapping-key verification-pattern register are placed Program Exceptions:
in byte offsets 24-55 of the parameter block.
• Access (fetch, parameter block; store, parameter
PCKMO-Encrypt-AES-256-Key (Function block)
Code 20) • Operation (if the message-security-assist-exten-
The locations of the operands and addresses used sion-3 facility is not installed)
by the instruction are as shown in Figure 10-34 on • Privileged operation
page 10-67. • Specification
Explanation:
When the frame-size code is 0, the specified frame- • When an interruption occurs (other than one that
management functions are performed for the 4K-byte follows termination), the second-operand
frame specified by the second operand. General reg- address in general register R2 is updated by the
ister R2 is unmodified in this case. number of 4K-byte blocks processed, so the
instruction, when reexecuted, resumes at the
When the frame-size code is 1, the specified frame- point of interruption.
management functions are performed for one or
more 4K-byte blocks within the 1M-byte frame, begin- • When the instruction completes without interrup-
ning with the block specified by the second-operand tion, the second-operand address in general reg-
address, and continuing to the right with each suc- ister R2 is updated to the next 1M-byte boundary.
cessive block up to the next 1M-byte boundary. In this
case, PERFORM FRAME MANAGEMENT FUNC- When the frame-size code is 1, the following also
TION is interruptible, and processing is as follows: applies:
• In the 24-bit addressing mode, bit positions 32- 39 of general register R2 are set to zeros.
general register R2 is set to zero. key operation is performed first when both of the
respective controls are one. When both the clear-
• In either the 24-bit or 31-bit addressing mode, frame and set-key controls are one, and either the
bits 0-31 of general register R2 are unchanged. MR or MC bit is also one, and the clear operation is
performed first, the storage key that is compared with
When the clear-frame control is one, references to bits 56-62 of general register R1 in the set-key opera-
main storage within the second operand are not nec- tion is the key following the clear operation (that is,
essarily single-access references and are not neces- both the R and C bits will have been set to one by the
sarily performed in a left-to-right direction as clear operation). Provided that there is no other
observed by other CPUs and by channel programs. access to the storage by other CPUs or the channel
The clear operation is not subject to key-controlled subsystem, the final results of the instruction reflect
protection; however low-address protection applies the specified key value, including the specified R and
regardless of whether the frame-size code desig- C values when MR and MC are zero.
nates a 4 K-byte or 1 M-byte frame (that is, regard-
less of whether the second-operand address is real Special Conditions
or absolute, respectively).
A specification exception is recognized and the oper-
When the storage-key control is one, the operation ation is suppressed for any of the following condi-
for each 4K-byte block is similar to that described in tions:
“SET STORAGE KEY EXTENDED” on page 10-121,
except that when the keys for multiple blocks are set, • Bits 32-45, 55, or 63 of general register R1 are
the condition code and the contents of general regis- not zero.
ter R1 are unchanged.
• When the nonquiescing key-setting facility is not
A serialization and checkpoint-synchronization func- installed, bit 52 of general register R1 is not zero.
tion is performed before the operation begins and
again after the operation is completed, except that • The frame-size code specifies a reserved value.
when the seven bits of all storage keys to be set are
the same as bits 56-62 of general register R1, or Condition Code: The code remains unchanged.
when the MR and MC bits allow all the storage keys
to remain unchanged, it is unpredictable whether the Program Exceptions:
serialization and checkpoint-synchronization func-
tions are performed after the operation completes. • Access (store, low-address-protection only, oper-
See “SET STORAGE KEY EXTENDED” on and 2, when the clear-frame control is one)
page 10-121 for details on the cases where setting of • Addressing (operand 2)
the key may be bypassed. • Operation (enhanced-DAT facility not installed)
• Privileged operation
When the set-key control is one, and either (a) the • Specification
nonquiescing key-setting facility is not installed, or
(b) the facility is installed but the nonquiescing con- Programming Note: When PFMF is issued with the
trol (NQ) is zero, a quiescing operation is performed. set-key control set to one, the program must ensure
When the set-key control is one, the nonquiescing that no channel subsystem is simultaneously altering
key-setting facility is installed, and the NQ control is the storage designated by general register R2. The
one, a quiescing operation is not necessarily per- program also must ensure that no other CPU or
formed. See “Storage-Key Accesses” on page 5-91 channel subsystem is accessing the storage desig-
for a discussion the effects of quiescing on key-set- nated by general register R2 when the nonquiescing
ting instructions, and see “Quiescing” on page 5-102 (NQ) control is one. Otherwise, unpredictable results
for details on the quiescing operation. may be observed by the other CPUs and channel
subsystem, including the alteration of the block des-
ignated by general register R2.
Figure 10-43. General Register Assignment for PERFORM TIMING FACILITY FUNCTION
machine level, this value is the Tv-Tp epoch differ- Figure 10-48. Parameter Block for PTFF-QPT (Query
ence (Dv). Physical Clock)
PTFF-QSI (Query Steering Information) The 64-bit physical-clock value returned (pb.Tr) is the
current value of the physical clock. Zeros are stored
The parameter block used for the function has the fol- for the rightmost bit positions that are not provided by
lowing format: the physical clock. When the clock is running, two
executions of PTFF-QPT, either on the same or dif-
Hex Dec ferent CPUs, do not necessarily return different val-
00 0 Physical Clock (0:31) ues of the clock.
pb.Tu
04 4 Physical Clock (32:63)
08 8 Old Episode Start Time (0:31) PTFF-ATO (Adjust TOD Offset)
pb.old.s
0C 12 Old Episode Start Time (32:63)
10 16 Old Episode Base Offset (0:31) The parameter block used for the function has the fol-
pb.old.b
14 20 Old Episode Base Offset (32:63) lowing format:
18 24 Old Episode Fine-Steering Rate pb.old.f
1C 28 Old Episode Gross-Steering Rate pb.old.g Hex Dec
20 32 New Episode Start Time (0:31) 00 0 TOD Offset Adjustment (0:31)
pb.new.s pb.a
24 36 New Episode Start Time (32:63) 04 4 TOD Offset Adjustment (32:63)
28 40 New Episode Base Offset (0:31) 0 31
pb.new.b
2C 44 New Episode Base Offset (32:63)
Figure 10-49. Parameter Block for PTFF-ATO (Adjust TOD
30 48 New Episode Fine-Steering Rate pb.new.f
Offset)
34 52 New Episode Gross-Steering
Rate pb.new.g
0 31
The 64-bit value (pb.a) from the parameter block,
treated as an unsigned-binary value, is added to the
Figure 10-47. Parameter Block for PTFF-QSI (Query base offset of the next episode. A carry if any, out of
Steering Information) bit position 0 is ignored in this addition. The effect is
not immediate, but is scheduled to coincide with the
The 64-bit physical-clock value returned (pb.Tu) is next TOD-offset-update event.
the value of the physical clock at the most recent
TOD-offset-update event. The remaining fields are If the next episode has already been scheduled, and
the values of the old-episode and new-episode regis- has not yet become active, then the sum of pb.a and
ters. new.b replaces new.b and no other action is taken.
computed using the current steering parameters. new episode is scheduled, the new-episode fine-
steering and gross-steering rates are the same as
The steering rate is not changed by this function, if a the current values.
new episode is scheduled, the new-episode fine-
steering and gross-steering rates are the same as When issued at the logical-partition or virtual-
the current values. machine level, the function may be simulated by the
hypervisor and operates on the TOD epoch differ-
Execution of the adjust-TOD-offset function is inter- ence for the current level of CPU execution (Dp or Dv,
locked such that the entire contents of the TOD-offset respectively); no new episode is scheduled and the
register appear to be updated concurrently and change takes effect immediately.
simultaneously as observed by all CPUs in the con-
figuration. However, accesses to the logical TOD Execution of the set-TOD-offset function is inter-
clocks (basic-machine TOD clock, logical-partition locked such that the entire contents of the TOD-offset
TOD clock, and virtual-machine TOD clock) by CPUs register appear to be updated concurrently and
in the configuration are not artificially delayed; thus, simultaneously as observed by all CPUs in the con-
addition of a large unsigned adjustment value may figuration. However, accesses to the logical TOD
have the effect of a negative change and may cause clocks (basic-machine TOD clock, logical-partition
the logical TOD clocks to appear to step backwards. TOD clock, and virtual-machine TOD clock) by CPUs
in the configuration are not artificially delayed; thus,
PTFF-STO (Set TOD Offset) replacement of the TOD offset by a smaller value
may cause the logical TOD clocks to appear to step
The parameter block used for the function has the fol- backwards.
lowing format:
PTFF-SFS (Set Fine-Steering Rate)
Hex Dec
00 0 New TOD Offset (0:31) The parameter block used for the function has the fol-
pb.d
04 4 New TOD Offset (32:63) lowing format:
0 31
Figure 10-50. Parameter Block for PTFF-STO (Set TOD Hex Dec
Offset) 00 0 New Fine-Steering Rate pb.f
0 31
The 64-bit value (pb.d) from the parameter block Figure 10-51. Parameter Block for PTFF-SFS (Set Fine-
replaces the TOD offset. Steering Rate)
When issued at the basic-machine level, the effect is The 32-bit value (pb.f) from the parameter block
not immediate, but is scheduled to coincide with the becomes the fine-steering rate for the next episode.
next TOD-offset-update event. The effect is not immediate, but is scheduled to coin-
cide with the next TOD-offset-update event.
If the next episode has already been scheduled, and
has not yet become active, then pb.d replaces new.b If the next episode has already been scheduled, and
and no other action is taken. has not yet become active, then pb.f replaces new.f
and no other action is taken.
If the next episode has not been scheduled (that is,
the new-episode registers are the current episode), If the next episode has not been scheduled (that is,
then the new-episode registers are saved in the old- the new-episode registers are the current episode),
episode registers and a new episode is scheduled then the new-episode registers are saved in the old-
(thus, making the old-episode registers the current episode registers and a new episode is scheduled
episode). The new-episode start time (new.s) is set (thus, making the old-episode registers the current
to the value the physical clock will have at the next episode). The new-episode start time (new.s) is set
TOD-offset-update event and the new-episode base to the value the physical clock will have at the next
offset (new.b) is set to the value of pb.d. TOD-offset-update event and the new-episode base
offset (new.b) is set to the value the TOD-offset will
PTFF-SGS (Set Gross-Steering Rate) The priority of execution for the PTFF instruction is
shown in Figure 10-53.
The parameter block used for the function has the fol-
lowing format: A privileged operation exception is recognized if a
PTFF control function is issued in the problem state.
Hex Dec
00 0 New Gross-Steering Rate pb.g A specification exception is recognized and no other
0 31 action is taken if any of the following occurs:
Figure 10-52. Parameter Block for PTFF-SGS (Set Gross-
Steering Rate) 1. Bit 56 of general register 0 is not zero.
The 32-bit value (pb.g) from the parameter block 2. Bits 57-63 of general register 0 specify an unas-
becomes the gross-steering rate for the next episode. signed or uninstalled function code.
The effect is not immediate, but is scheduled to coin-
cide with the next TOD-offset-update event. Resulting Condition Code:
If the next episode has already been scheduled, and 0 Requested function performed
has not yet become active, then pb.g replaces new.g 1 --
and no other action is taken. 2 --
3 Requested function not available
If the next episode has not been scheduled (that is,
the new-episode registers are the current episode), Program Exceptions:
then the new-episode registers are saved in the old-
episode registers and a new episode is scheduled • Access (fetch, parameter block for control func-
(thus, making the old-episode registers the current tions; store, parameter block for query functions)
episode). The new-episode start time (new.s) is set • Operation (if the PERFORM TIMING FACILITY
to the value the physical clock will have at the next FUNCTION instruction is not installed)
TOD-offset-update event and the new-episode base • Privileged operation (attempt to execute a PTFF
offset (new.b) is set to the value the TOD-offset will control function in the problem state)
have at that same instant, computed using the cur- • Specification
rent steering parameters. The new-episode gross-
Programming Notes: These equations hold only for the time between
two TOD-offset-update events. The information
1. The status bits returned by the PTFF-QAF func- from PTFF-QSI can be used to extend this rela-
tion indicate the PTFF functions which are tionship for the entire time span of two episodes,
installed and available for a program running in beginning with the old-episode start time
supervisor state at the basic-machine level. (pb.old.s) through the new episode and continu-
Since all installed PTFF query functions are ing on to that instant in the future when a subse-
available in both the problem state and supervi- quent episode takes effect.
sor state at all levels of CPU execution, these
status bits can be used directly by any program 5. For PTFF-QTO (Query TOD Offset) and PTFF-
to determine which PTFF query functions are QSI (Query Steering Information), the 64-bit
available. PTFF control functions are never avail- physical-clock value returned (pb.Tu) is the value
able to a program running in problem state. Con- of the physical clock at the most recent TOD-off-
dition code 3 is set when a particular PTFF set-update event. This is the current value of the
control function is issued and the function is physical clock, but with zeroes in positions to the
installed but is not available in that state or at that right of the bit position incremented concurrently
level of CPU execution. Thus, the status bits for with each TOD-offset-update event. The program
PTFF control functions indicate whether it is safe can use this value to determine the time span
to issue a particular PTFF control function with- over which the various offsets returned by Query
out the danger of a specification exception. TOD Offset can be used without any error. For
Query Steering Information, pb.Tu can be used
2. The physical time (pb.Tu) returned in the param- to determine whether the machine is operating in
eter block for PTFF-QTO and PTFF-QSI is the the old or new episode. When pb.new.s [ pb.Tu,
current value of the physical clock, but with the machine is operating in the new episode, and
zeroes in positions to the right of the bit position none of the information returned by the query
incremented concurrently with each TOD-offset- has changed since the most recent TOD-offset-
update event. This value is not necessarily update event. When pb.new.s > Pb.Tr, the
unique. The same value may be returned if the machine is operating in the old episode, a new
PTFF instruction is issued multiple times on the episode has been scheduled and has not yet
taken effect. The program should avoid any
dependency on the new episode values returned
Leap
Year Month Day Sec. TOD Clock (Hex) NTP Timestamp (Hex)
1900 1 1 0000 0000 0000 0000 0000 0000 0000 0000
1972 1 1 8126 D60E 4600 0000 876C E580 0000 0000
1972 7 1 1 820B A981 1E24 0000 885C D680 0000 0000
1973 1 1 2 82F3 00AE E248 0000 894F 6A80 0000 0000
1974 1 1 3 84BD E971 146C 0000 8B30 9E00 0000 0000
1975 1 1 4 8688 D233 4690 0000 8D11 D180 0000 0000
1976 1 1 5 8853 BAF5 78B4 0000 8EF3 0500 0000 0000
1977 1 1 6 8A1F E595 20D8 0000 90D5 8A00 0000 0000
1978 1 1 7 8BEA CE57 52FC 0000 92B6 BD80 0000 0000
1979 1 1 8 8DB5 B719 8520 0000 9497 F100 0000 0000
1980 1 1 9 8F80 9FDB B744 0000 9679 2480 0000 0000
1981 7 1 10 9230 5C0F CD68 0000 994A 4900 0000 0000
1982 7 1 11 93FB 44D1 FF8C 0000 9B2B 7C80 0000 0000
1983 7 1 12 95C6 2D94 31B0 0000 9D0C B000 0000 0000
1985 7 1 13 995D 40F5 17D4 0000 A0D0 6880 0000 0000
1988 1 1 14 9DDA 69A5 57F8 0000 A585 6380 0000 0000
1990 1 1 15 A171 7D06 3E1C 0000 A949 1C00 0000 0000
1991 1 1 16 A33C 65C8 7040 0000 AB2A 4F80 0000 0000
1992 7 1 17 A5EC 21FC 8664 0000 ADFB 7400 0000 0000
1993 7 1 18 A7B7 0ABE B888 0000 AFDC A780 0000 0000
1994 7 1 19 A981 F380 EAAC 0000 B1BD DB00 0000 0000
1996 1 1 20 AC34 336F ECD0 0000 B581 9380 0000 0000
1997 7 1 21 AEE3 EFA4 02F4 0000 B674 2780 0000 0000
1999 1 1 22 B196 2F93 0518 0000 BA36 8E80 0000 0000
2000 1 1 22 B361 1854 4318 0000 BC17 C200 0000 0000
2001 1 1 22 B52D 42F2 F718 0000 BDFA 4700 0000 0000
2002 1 1 22 B6F8 2BB4 3518 0000 BFDB 7A80 0000 0000
2003 1 1 22 B8C3 1475 7318 0000 C1BC AE00 0000 0000
2004 1 1 22 BA8D FD36 B118 0000 C39D E180 0000 0000
2005 1 1 22 BC5A 27D5 6518 0000 C580 6680 0000 0000
2006 1 1 23 BE25 1097 973C 0000 C761 9A00 0000 0000
Figure 10-55. TOD Clock and NTP Timestamps
'B9A2' / / / / / / / / R1 / / / /
Reserved
0 16 24 28 31
0 31
Reserved RC FC
32 48 56 63
PROGRAM CALL
TION specifies function-code 2 that completes
FC Meaning with condition code 1.
0 Request horizontal polarization.
• Subsystem reset is performed.
1 Request vertical polarization.
2 Check topology-change status. Special Conditions
Undefined function codes in the range 0-255 are A specification exception is recognized for either of
reserved for future extensions. the following conditions:
Upon completion, if condition code 2 is set, a reason • Bit positions 0-55 of general register R1 are not
code is stored in bit positions 48-55 of general regis- zeros.
ter R1. • An undefined function code is specified.
Bits 16-23 and 28-31 of the instruction are ignored. Resulting Condition Code: When the function
code is 0 or 1, the condition code is set as follows:
Operation of Function Codes 0 and 1
When no exceptional conditions are detected, a pro- 0 Topology-change initiated
cess is initiated to place all CPUs in the configuration 1 --
into the polarization specified by the function code, 2 Request rejected
and condition code 0 is set. Completion of the pro- 3 --
cess is asynchronous with respect to execution of the
instruction and may or may not be completed when When the function code is 2, the condition code is set
execution of the instruction completes. as follows:
Execution completes with condition code 2, and the 0 Topology-change-report not pending
reason code is set, for any of the following reasons: 1 Topology-change report pending
2 --
RC Reason 3 --
0 No reason specified.
Program Exceptions:
1 The configuration is already polarized as specified
by the function code.
• Operation (configuration-topology facility is not
2 A topology change is already in process installed)
• Privileged operation
Operation of Function Code 2: • Specification
The topology-change-report-pending condition is
checked. When a topology-change-report is not Programming Note: Further information on configu-
pending, condition code 0 is set. When a topology- ration topology may be found in “SYSIB 15.1.2 -
change report is pending, condition code 1 is set. 15.1.6 (Configuration Topology)” on page 10-142.
authorization key mask in the ETE is nonzero or bit 129 of the ETE is one, stacking PROGRAM CALL
when the CPU is in the supervisor state. sets bits 31 and 32 of the PSW to one. Thus, stack-
ing PROGRAM CALL can set the 24-bit, 31-bit, or
When the PC-type bit, bit 128 of the ETE, is zero, an 64-bit addressing mode.
operation called basic PROGRAM CALL is per-
formed. When the PC-type bit is one, an operation When the resulting addressing mode is the 24-bit or
called stacking PROGRAM CALL is performed. 31-bit mode, both basic and stacking PROGRAM
CALL place bits 33-62 of the entry instruction
Basic PROGRAM CALL, in the 24-bit or 31-bit address in the ETE, which are bits 33-62 of the ETE,
addressing mode, loads the basic-addressing-mode with 33 leftmost and one rightmost zeros appended,
bit, bits 33-62 of the updated instruction address, and in bit positions 64-127 of the PSW as the new
the problem-state bit from the PSW into bit positions instruction address, and they place the entry-prob-
32-63 of general register 14, and it leaves bits 0-31 of lem-state bit, bit 63 of the ETE, in bit position 15 of
this register unchanged. In the 64-bit addressing the PSW as the new problem-state bit. Bits 32-63 of
mode, bits 0-62 of the updated instruction address the entry parameter in the ETE are placed in bit posi-
and the problem-state bit are placed in bit positions tions 32-63 of general register 4, and bits 0-31 of this
0-63 of general register 14. In any addressing mode, register remain unchanged.
the PSW-key mask and PASN are placed in bit posi-
tions 32-63 of general register 3, and bits 0-31 of this When the resulting addressing mode is the 64-bit
register remain unchanged. mode, both basic and stacking PROGRAM CALL
place bits 0-62 of the entry instruction address, bits
Stacking PROGRAM CALL places the entire PSW 0-62 of the ETE, with one rightmost zero appended,
contents, except with an unpredictable PER mask, in bit positions 64-127 of the PSW, and they place bit
and also the PSW-key mask, PASN, SASN, and EAX 63 of the ETE in bit position 15 of the PSW. Bits 0-63
in a linkage-stack program-call state entry that it of the entry parameter in the ETE are placed in gen-
forms. A called-space identification, an indication of eral register 4.
whether the resulting addressing mode is the 64-bit
mode, the numeric part of the program-call number, Basic PROGRAM CALL ORs the entry key mask
and the contents of general registers 0-15 and from the ETE into the PSW-key mask in control regis-
access registers 0-15 also are placed in the state ter 3. Stacking PROGRAM CALL does the same, or it
entry. If the ASN-and-LX-reuse facility is installed and replaces the PSW-key mask with the entry key mask,
enabled, the PASTEIN and SASTEIN also are placed as determined by the PSW-key-mask control in the
in the state entry. ETE.
For basic PROGRAM CALL, the extended-address- Stacking PROGRAM CALL optionally replaces the
ing-mode bit, bit 31 of the PSW, must have the same PSW key in the PSW and the EAX in control register
value as the entry-extended-addressing-mode bit, bit 8 from the ETE, and it sets the address-space-con-
129 of the ETE; otherwise, a special-operation trol bits in the PSW, as determined by control bits in
exception is recognized. Basic PROGRAM CALL the ETE.
does not change bit 31 of the PSW and, therefore,
does not switch between a basic addressing mode The ETE causes a space-switching operation to
(the 24-bit or 31-bit mode) and the extended occur if it contains a nonzero ASN. When the ETE
addressing mode (the 64-bit mode). In the 24-bit or contains a zero ASN, the operation is called PRO-
31-bit addressing mode, basic PROGRAM CALL GRAM CALL to current primary (PC-cp); when the
sets the basic-addressing-mode bit, bit 32 of the ETE contains a nonzero ASN, the operation is called
PSW, with the value of the entry-basic-addressing- PROGRAM CALL with space switching (PC-ss).
mode bit, bit 32 of the ETE, and, thus, it may switch When space switching is specified, the new PASN is
between the 24-bit and 31-bit addressing modes. In loaded into control register 4 from the ETE, and a
the 64-bit addressing mode, bit 32 of the PSW new primary-ASTE origin (PASTEO) is loaded into
remains unchanged. control register 5, also from the ETE. From the
PASTE, a new primary ASCE (PASCE) and AX are
Stacking PROGRAM CALL, when bit 129 of the ETE loaded into control registers 1 and 4, respectively. If
is zero, sets bit 31 of the PSW to zero and sets bit 32 ASN-and-LX reuse is enabled, a new primary ASTE
PROGRAM CALL
register 4, also from the PASTE. entry index. The size and format of the linkage first
index depend on whether the PC number is 20 bits or
In both PC-cp and PC-ss, the SASN and secondary 32 bits, which in turn depends on whether bit 44 of
ASCE (SASCE) are set equal to the original PASN the second-operand address is zero or one, respec-
and PASCE, respectively, and, if ASN-and-LX reuse tively. In these cases, the second-operand address
is enabled, the secondary ASTE instance number has the following formats:
(SASTEIN) in control register 3 is set equal to the
original PASTEIN. However, the space-switching Second-Operand Address when ASN-and-LX Reuse Is
stacking PROGRAM CALL operation may instead set Enabled and Bit 44 Is Zero
the SASN and SASCE equal to the new PASN and
PASCE, respectively, and, if ASN-and-LX reuse is 0 31
enabled, set the SASTEIN equal to the new
LX
PASTEIN, as determined by a control bit in the ETE.
LFX
In a PC-ss to the base space of the dispatchable unit
0 LFX2 LSX EX
when the dispatchable unit is subspace active, bits
32 44 45 51 56 63
0-55 and 58-63 of the new PASCE are replaced by
the same bits of the ASCE in the ASTE for the sub- Second-Operand Address when ASN-and-LX Reuse Is
space in which the dispatchable unit last had control. Enabled and Bit 44 Is One
This occurs before the possible setting of the SASCE
equal to the PASCE. 0 31
LX
PROGRAM CALL PC-Number Translation
LFX
The second-operand address is not used to address
data; instead, the rightmost 20 or 32 bits of the LFX1 1 LFX2 LSX EX
address are used as a PC number divided into two 32 44 45 51 56 63
PROGRAM CALL
PROGRAM CALL is specified.
The following operations are performed when stack-
Bit 31 of the current PSW (the extended-addressing- ing PROGRAM CALL is specified.
mode bit) must equal bit 129 (G) of the ETE; other-
wise, a special-operation exception is recognized. The stacking process is performed to form a linkage-
stack program-call state entry and place the following
In the 24-bit or 31-bit addressing mode, bits 97-126 information in the state entry: current PSW (with an
of the PSW (bits 33-62 of the updated instruction unpredictable PER mask), PSW-key mask, PASN,
address) are placed in bit positions 33-62 of general SASN, EAX, called-space identification, an indication
register 14, bit 32 of the PSW (the basic-addressing- of whether the resulting addressing mode is the
mode bit) is placed in bit position 32 of the register, 64-bit mode, numeric part of the program-call num-
and bit 15 of the PSW (the problem-state bit) is ber, contents of general registers 0-15, and contents
placed in bit position 63 of the register. Bits 0-31 of of access registers 0-15, and, if ASN-and-LX reuse is
the register remain unchanged. enabled, PASTEIN and SASTEIN. This is described
in “Stacking Process” on page 5-80. The entry-type
In the 64-bit addressing mode, bits 64-126 of the code in the state entry is 0001101 binary.
PSW (bits 0-62 of the updated instruction address)
are placed in bit positions 0-62 of general register 14, When bit 129 of the ETE (G) is zero, bit 31 of the
and bit 15 of the PSW (the problem-state bit) is PSW (the extended-addressing-mode bit) is set to
placed in bit position 63 of the register. zero, and bit 32 of the ETE (A) is placed in bit posi-
tion 32 of the PSW (the basic-addressing-mode bit).
In the 24-bit or 31-bit addressing mode, bits 32 and (The addressing mode is set to the 24-bit mode if bit
33-62 of the ETE (A and the EIA), with a zero 32 is zero or to the 31-bit mode if bit 32 is one.) When
appended on the right of bits 33-62, are placed in bit 129 of the ETE is one, bits 31 and 32 of the PSW
PSW bit positions 32 and 97-127, respectively (the are set to one. (The 64-bit addressing mode is set.)
basic-addressing-mode bit and bits 33-63 of the
instruction address). In the 64-bit addressing mode, When the resulting addressing mode is the 24-bit or
bits 0-62 of the ETE, with a zero appended on the 31-bit mode, bits 33-62 of the ETE (the EIA), with 33
right, are placed in PSW bit positions 64-127 (the leftmost and one rightmost zeros appended, are
instruction address), and PSW bit 32 remains placed in PSW bit positions 64-127 (the instruction
unchanged. In any addressing mode, bit 63 of the address). When the resulting addressing mode is the
ETE (P) is placed in PSW bit position 15 (the prob- 64-bit mode, bits 0-62 of the ETE (the EIA), with one
lem-state bit). rightmost zero appended, are placed in PSW bit
positions 64-127.
The PSW-key mask, bits 32-47 of control register 3,
is placed in bit positions 32-47 of general register 3, Bit 63 of the ETE (P) is placed in PSW bit position 15
and the current PASN, bits 48-63 of control register (the problem-state bit).
4, is placed in bit positions 48-63 of general register
3. Bits 0-31 of general register 3 remain unchanged. When bit 131 of the ETE (K) is zero, bits 8-11 of the
PSW (the PSW key) remain unchanged. When bit
Bits 96-111 of the ETE (the EKM) are ORed with the 131 of the ETE is one, bits 136-139 of the ETE (the
PSW-key mask, bits 32-47 of control register 3, and EK) replace the PSW key in the PSW.
the result replaces the PSW-key mask in control reg-
ister 3. When bit 132 of the ETE (M) is zero, bits 96-111 of
the ETE (the EKM) are ORed with the PSW-key
In the 24-bit or 31-bit addressing mode, bits 224-255 mask, bits 32-47 of control register 3, and the result
of the ETE (bits 32-63 of the entry parameter) are replaces the PSW-key mask in control register 3.
loaded into bit positions 32-63 of general register 4, When bit 132 of the ETE is one, bits 96-111 of the
and bits 0-31 of the register remain unchanged. In ETE replace the PSW-key mask in control register 3.
the 64-bit addressing mode, bits 192-255 of the ETE
(the entry parameter), are loaded into bit positions When bit 133 of the ETE (E) is zero, the EAX, bits
0-63 of general register 4. 32-47 of control register 8, remains unchanged.
When bit 133 of the ETE is one, bits 144-159 of the
When the resulting addressing mode is the 24-bit or Bits 161-185 of the ETE, with six zeros appended on
31-bit mode, bits 224-255 of the ETE (bits 32-63 of the right, are used as the real address of the ASTE
the entry parameter) are loaded into bit positions designated by the new PASN. An ASX-translation
32-63 of general register 4, and bits 0-31 of this reg- exception is recognized if bit 0 of the ASTE is one.
ister remain unchanged. When the resulting address-
ing mode is the 64-bit mode, bits 192-255 of the ETE Bits 64-127 of the ASTE (the ASCE) are placed in
(the entry parameter), are loaded into bit positions control register 1 as the new PASCE.
0-63 of general register 4.
Bits 32-47 of the ASTE (the AX) are placed in bit
Key-controlled protection does not apply to refer- positions 32-47 of control register 4 as the new
ences to the linkage stack, but low-address and DAT authorization index.
protection do apply.
If ASN-and-LX reuse is enabled, bits 352-383 of the
PROGRAM CALL to Current Primary (PC-cp) ASTE (the ASTEIN) are placed in bit positions 0-31
of control register 4 as the new PASTEIN.
If bits 80-95 of the ETE (the ASN), are zeros, PRO-
GRAM CALL to current primary (PC-cp) is specified, Bits 33-57 of the ASTE address are placed in bit
and the execution of the instruction is completed after positions 33-57 of control register 5 as the new pri-
the operations described in “PROGRAM CALL PC- mary-ASTE origin, and zeros are placed in bit posi-
Number Translation” and either “Basic PROGRAM tions 32 and 58-63. Bits 0-31 of the register remain
CALL” or “Stacking PROGRAM CALL” have been unchanged.
performed and the following operations have been
performed. In basic PROGRAM CALL, or in stacking PROGRAM
CALL when bit 135 of the ETE (S) is zero, the PASN
The current PASN, bits 48-63 of control register 4, is existing before the PASN is replaced from the ETE is
placed in bit positions 48-63 of control register 3 to placed in bit positions 48-63 of control register 3 to
become the current SASN. become the current SASN, and the PASCE existing
before the PASCE is replaced from the ASTE is
The current PASCE in control register 1 is placed in placed in control register 7 to become the current
control register 7 to become the current SASCE. SASCE. If ASN-and-LX reuse is enabled, the
PASTEIN existing before the PASTEIN is replaced
If ASN-and-LX reuse is enabled, the current from the ASTE is placed in bit positions 0-31 of con-
PASTEIN, bits 0-31 of control register 4, is placed in trol register 3 to become the current SASTEIN. (The
bit positions 0-31 of control register 3 to become the SASN and SASCE are set equal to the old PASN and
current SASTEIN. PASCE, respectively, and, if ASN-and-LX reuse is
enabled, the SASTEIN is set equal to the old
The basic PC-cp operation is depicted in parts 1-3 of PASTEIN.)
Figure 10-58 on page 10-90. The stacking PC-cp
operation is depicted in parts 1, 4, and 5 of the figure. In stacking PROGRAM CALL when bit 135 of the
ETE (S) is one, the SASN is replaced by the PASN
PROGRAM CALL with Space Switching (PC-ss) after the PASN is replaced from the ETE, and the
SASCE is replaced by the PASCE after the PASCE is
If the ASN in the ETE is nonzero, PROGRAM CALL replaced from the ASTE. If ASN-and-LX reuse is
with space switching (PC-ss) is specified, and the enabled, the SASTEIN is replaced by the PASTEIN
execution of the instruction is completed after the after the PASTEIN is replaced from the ASTE. (The
PROGRAM CALL
and PASCE, respectively, and, if ASN-and-LX reuse LSTESN in the linkage-second-table entry is non-
is enabled, the SASTEIN is set equal to the new zero, that LSTESN must be equal to the LSTESN
PASTEIN.) specified in bit positions 0-31 of general register 15;
otherwise, an LSTE-sequence exception is recog-
The description in this paragraph applies to use of nized.
the subspace-group facility. After the new PASCE
has been placed in control register 1 and the new pri- A stack-full or stack-specification exception may be
mary-ASTE origin has been placed in control register recognized during the stacking process.
5, if (1) the subspace-group-control bit, bit 54, in the
PASCE is one, (2) the dispatchable unit is subspace When, for PC-ss, the primary space-switch-event-
active, and (3) the primary-ASTE origin designates control bit, bit 57 of control register 1, is one either
the ASTE for the base space of the dispatchable unit, before or after the execution of the instruction, a
then bits 0-55 and 58-63 of the PASCE are replaced space-switch-event program interruption occurs after
by the same bits of the ASCE in the ASTE for the the operation is completed. A space-switch-event
subspace in which the dispatchable unit last had con- program interruption also occurs after the completion
trol. This replacement occurs before a replacement of a PC-ss operation if a PER event is reported.
of the SASCE in control register 7 by the PASCE.
Further details are in “Subspace-Replacement Oper- The operation is suppressed on all addressing and
ations” on page 5-65. protection exceptions.
The PC-ss operation is depicted in parts 1 and 4-6 of The priority of recognition of program exceptions for
Figure 10-58 on page 10-90. the instruction is shown in Figure 10-57 on
page 10-88.
PROGRAM CALL Serialization
Condition Code: The code remains unchanged.
For both the PC-cp and PC-ss operations, a serial-
ization and checkpoint-synchronization function is Program Exceptions:
performed before the operation begins and again
after the operation is completed. However, it is unpre- • Access (fetch or store, except for key-controlled
dictable whether or not a store into a trace-table entry protection, linkage-stack entry)
or linkage-stack entry from which a subsequent • Addressing (linkage-table or linkage-first-table
instruction is fetched will be observed by the CPU designation in primary ASN-second-table entry;
that performed the store. linkage-table entry; linkage-first-table entry; link-
age-second-table entry, entry-table entry; ASN-
Special Conditions second-table entry, PC-ss only)
• ASX translation (PC-ss only)
The basic PROGRAM CALL operation can be per- • EX translation
formed successfully only when (1) the CPU is in the • LFX translation
primary-space mode at the beginning of the opera- • LSTE sequence
tion, (2) the subsystem-linkage control, bit 0 of the • LSX translation
linkage-table designation or linkage-first-table desig- • LX translation
nation in the current primary ASN-second-table entry, • PC-translation specification
is one, and (3) the extended-addressing-mode bit, bit • Privileged operation (AND of AKM and PSW-key
31 of the current PSW, equals the entry-extended- mask is zero in the problem state)
addressing-mode bit, bit 129 of the entry-table entry. • Space-switch event (PC-ss only)
Stacking PROGRAM CALL can be performed suc- • Special operation
cessfully only when the CPU is in the primary-space • Stack full (stacking PC only)
mode or access-register mode at the beginning of • Stack specification (stacking PC only)
the operation and the subsystem-linkage control is • Subspace replacement (PC-ss only)
one. In addition, PC-ss can be performed success- • Trace
fully only when the ASN-translation control, bit 44 of
control register 14, is one. If any of these rules is vio- Programming Note: The effective address from
lated, a special-operation exception is recognized. which a PC number is derived is subject to the
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B Special-operation exception due to DAT being off or the CPU being in secondary-space mode or home-
space mode.
8.B.1 Addressing exception for access to linkage-table designation or linkage-first-table designation in primary
ASN-second-table entry.
Note: The LFX-translation, LSX-translation, and LSTE-sequence exceptions can be recognized only if ASN-
and-LX reuse is enabled, and the LX-translation exception cannot be recognized in that case.
8.B.5 LX-translation or LFX-translation exception due to I bit (bit 0) in linkage-table or linkage-first-table entry,
respectively, being one.
8.B.7 LSX-translation exception due to I bit (bit 0) in linkage-second-table entry being one.
8.B.8 LSTE-sequence exception due to LSTE sequence number in linkage-second-table entry being nonzero and
not equal to bits 0-31 of general register 15.
8.B.11 Special-operation exception due to the CPU being in access-register mode or extended-addressing-mode
bit, bit 31 of PSW, not being equal to entry-extended-addressing-mode bit, bit 129 of entry-table entry (basic
PC only).
8.B.12 PC-translation-specification exception due to invalid combination (bits 33-39 not zeros when resulting
addressing mode is 24 bit) in entry-table entry.
8.B.13 Privileged-operation exception due to zero result from ANDing PSW-key mask and AKM in the problem
state.
8.B.14 Special-operation exception due to ASN-translation control, bit 44 of control register 14, being zero (PC-ss
only).
8.B.16 ASX-translation exception due to I bit (bit 0) in ASN-second- table entry being one (PC-ss only).
Note: Subspace-replacement exceptions, which are not shown in detail in this figure, can occur with any
priority after 8.B.16 and before 9.
Note: Exceptions 8.B.18-8.B.23 can occur only if there is not enough remaining free space in the current
linkage-stack section.
8.B.18 Stack-specification exception due to remaining-free-space value in current linkage-stack entry not being a
multiple of 8.
8.B.19 Access exceptions (fetch) for second word of the trailer entry of the current section. The entry is presumed to
be a trailer entry; its entry-type field is not examined (stacking PC only).
8.B.20 Stack-full exception due to forward-section validity bit in the trailer entry being zero (stacking PC only).
8.B.21 Access exceptions (fetch) for entry descriptor of the header entry of the next section (stacking PC only). This
entry is presumed to be a header entry; its entry-type field is not examined.
8.B.22 Stack-specification exception due to not enough remaining free space in the next section (stacking PC only).
8.B.23 Access exceptions (store) for second word of the header entry of the next section. If there is no exception,
the header is now called the current entry.
8.B.24 Access exceptions (store) for entry descriptor of the current entry and for the new state entry (stacking PC
only).
Entry-Table Entry
/
A EIA P AKM ASN EKM T G ASTE Address EP 32-63
/
Shown again below T=0
=0 ? Special-Op.
(with 33 zeros on left) Exception
No
PSW
after
GR4
P E A IA 0-62 0 32-63 EP 32-63
after
E=0
From above
AKM ASN EKM
Privileged-Op.
AND Exception if Zero in
Problem State
OR
PC-cp PC-ss
Instruction Operations
Complete on ASTE
(see part 5)
GR3
32-63 PKM PASN
after
PSW
before
GR14 CR7
32-63 A IA 33-62 P after SASCE
after
Figure 10-58. Execution of PROGRAM CALL (Part 1 of 5).
Entry-Table Entry
/
EIA P AKM ASN EKM T G ASTE Address EP
/
Shown again below T=0
=1 ? Special-Op.
No Exception
PSW
after
GR4
P E A IA 0-62 0 after EP
E=1 A=1
From above
AKM ASN EKM
Privileged-Op.
AND Exception if Zero in
Problem State
OR
PC-cp PC-ss
Instruction Operations
Complete on ASTE
(see part 5)
GR3
32-63 PKM PASN
after
PSW
before
P E A IA 0-62 0 CR1 PASCE
before
E=1 A=1
Stacking PC-cp and PC-ss from 24-Bit or 31-Bit Addressing Mode to 64-Bit Addressing Mode
Entry-Table Entry
/ /
EIA P AKM ASN EKM T G K M E C S EK EEAX ASTE Adr. EP
/ /
Shown again below T=1
G=1
K=1
1 1
PSW
after /
/ / GR4
Key P 0 C E A IA 0-62 0 after EP
/ / /
E=1
From above
AKM ASN EKM CR8
32-63 EAX
after
Privileged-Op. CR8
AND 32-63 EAX
Exception if Zero in before
Problem State
LS
CR3 CR4
before SASTEIN* PKM SASN before PASTEIN* AX PASN
LS LS LS LS
LS
M=1
PC-cp, or ASN
*** PC-ss and =0
OR S=0 ** Yes ? No
PC-cp, or
M=0 PC-ss and
S=0 **
PC-cp PC-ss
CR3 Instruction Operations
after SASTEIN* PKM SASN Complete on ASTE
(see part 5)
PSW
before
CR1 PASCE
before
LS
PC-cp, or
PC-ss and
S=0 **
*: Operations on the ASTE instance number performed if ASN-and-LX-reuse enabled
**: If PC=ss and S-1, SASN is replaced by new PASN, SASCE is replaced by new PASCE,
and, if ASN-and-LX reuse is enabled, SASTEIN is replaced by new PASTEIN CR7 SASCE
after
***: Resulting PKM selected from output of OR operation (M=0) or EKM (M=1)
Entry-Table Entry
/ /
A EIA P AKM ASN EKM T G K M E C S EK EEAX ASTE Adr. EP 32-63
/ /
Shown again below T=1
G=0
(with 33 zeros on left)
Privileged-Op. CR8
AND 32-63 EAX
Exception if Zero in before
Problem State
LS
CR3 CR4
before SASTEIN* PKM SASN before PASTEIN* AX PASN
LS LS LS LS
LS
M=1
PC-cp, or ASN
PC-ss and =0
*** S=0 ** Yes ? No
OR PC-cp, or
M=0 PC-ss and
S=0 **
PC-cp PC-ss
CR3 Instruction Operations
after SASTEIN* PKM SASN Complete on ASTE
(see part 5)
PSW
before
CR1 PASCE
before
LS
PC-cp, or
PC-ss and
S=0 **
*: Operations on the ASTE instance number performed if ASN-and-LX-reuse enabled
**: If PC=ss and S-1, SASN is replaced by new PASN, SASCE is replaced by new PASCE,
and, if ASN-and-LX reuse is enabled, SASTEIN is replaced by new PASTEIN CR7 SASCE
after
***: Resulting PKM selected from output of OR operation (M=0) or EKM (M=1)
ASN-Second-Table Entry
/ /
R I ATO B AX ATL C R
A A ASCE ASTEIN**** **
/ /
0 000000
CR5
32-63 PASTEO
after
R: Address is real
*: First word and A of ETE are bits 0-32 of EIA if resulting addressing mode is the 64-bit mode.
**: ASTE is 64 bytes; selected fields and the last 16 bytes are not shown.
***: Bits 0-55 and 58-63 of PASCE may be replaced from a subspace ASCE
****: Operations on the ASTE instance number performed if ASN-and-LX-reuse enabled
Figure 10-58. Execution of PROGRAM CALL (Part 5 of 5).
PROGRAM RETURN
address in control register 15 is replaced by the described in “ASN Translation” on page 3-26. The
address of the next preceding state or header entry. exceptions associated with ASN translation are col-
This also is described in “Unstacking Process”. lectively called ASN-translation exceptions. These
exceptions and their priority are described in
When the state entry is a program-call state entry, it Chapter 6, “Interruptions.”
causes a space-switching operation to occur if it con-
tains a PASN that is not equal to the current PASN. If ASN-and-LX reuse is enabled, the PASTEIN saved
When the state entry contains a PASN that is equal in bytes 180-183 of the state entry must equal the
to the current PASN, the operation is called PRO- ASTEIN in bit positions 352-383 of the located ASTE;
GRAM RETURN to current primary (PR-cp); when otherwise, an ASTE-instance exception is recog-
the state entry contains a PASN that is not equal to nized.
the current PASN, the operation is called PROGRAM
RETURN with space switching (PR-ss). PASN trans- Bits 64-127 of the ASTE are placed in control register
lation occurs in PR-ss. SASN translation and authori- 1 as the new PASCE.
zation may occur in either PR-cp or PR-ss. The terms
PR-cp and PR-ss do not apply when the state entry Bits 32-47 of the ASTE are placed in bit positions
is a branch state entry. 32-47 of control register 4 as the new AX. The PASN
and PASTEIN in control register 4 remain as restored
When the ASN-and-LX-reuse facility is installed and from the state entry.
enabled and PASN or SASN translation occurs, the
PASTEIN or SASTEIN, respectively, saved in the Bits 33-57 of the ASTE address are placed in bit
state entry is compared to the ASTEIN in the located positions 33-57 of control register 5 as the new pri-
ASTE. mary-ASTE origin, and zeros are placed in bit posi-
tions 32 and 58-63. Bits 0-31 of this register remain
Key-controlled protection does not apply to accesses unchanged.
to the linkage stack, but low-address and DAT protec-
tion do apply. The description in this paragraph applies to use of
the subspace-group facility when PASN translation
The sections “PASN Translation,” “SASN Translation,” has occurred. If (1) the subspace-group-control bit,
“SASN Authorization,” and “PROGRAM RETURN bit 54, in the new PASCE is one, (2) the dispatchable
Serialization” apply only when the unstacked state unit is subspace active, and (3) the new primary-
entry is a program-call state entry. The functions ASTE origin designates the ASTE for the base space
described in those sections are not performed when of the dispatchable unit, then bits 0-55 and 58-63 of
the state entry is a branch state entry. the new PASCE in control register 1 are replaced by
the same bits of the ASCE in the ASTE for the sub-
The actions involving the PASTEIN and SASTEIN space in which the dispatchable unit last had control.
occur only when ASN-and-LX reuse is enabled by This replacement occurs, in the case when the new
the ASN-and-LX reuse control in control register 0. SASN is equal to the new PASN, before the SASCE
is set equal to the PASCE. Further details are in
PASN Translation “Subspace-Replacement Operations” on page 5-65.
If the new PASN is equal to the old PASN in bit posi- SASN Translation
tions 48-63 of control register 4, PASN translation is
not performed, the PASTEIN in control register 4 If the new SASN is equal to the new PASN, the
remain as restored from the state entry, and the SASCE in control register 7 is set equal to the new
PASCE in control register 1 and primary-ASTE origin PASCE in control register 1. The SASTEIN, PKM,
(PASTEO) in control register 5 are not changed. In and SASN in control register 3 remain as restored
this case, there is not a test of whether the new from the state entry. In this case, there is not a test of
PASTEIN is equal to the old PASTEIN. whether the new SASTEIN is equal to the new
PASTEIN.
If the new PASN is not equal to the old PASN, the
new PASN replaces the PASN in bit positions 48-63 If the new SASN is not equal to the new PASN, the
of control register 4 and is translated to locate a new SASN is translated to locate a 64-byte ASTE.
in bytes 176-179 of the state entry must equal the when the ASN-translation control, bit 44 of control
ASTEIN in bit positions 352-383 of the located ASTE; register 14, is one. If either of these rules is violated,
otherwise, an ASTE-instance exception is recog- a special-operation exception is recognized.
nized.
A stack-empty, stack-operation, stack-specification,
Bits 64-127 of the ASTE are placed in control register or stack-type exception may be recognized during
7 as the new SASCE. the unstacking process.
Control register 3 remains as restored from the state If ASN-and-LX reuse is enabled, the restored
entry. PASTEIN must equal the ASTEIN in the located
ASTE if PASN translation is performed, and the
SASN Authorization restored SASTEIN must equal the ASTEIN in the
located ASTE if SASN translation is performed; oth-
If the new SASN is not equal to the new PASN, the erwise, an ASTE-instance exception is recognized.
authority-table origin (ATO) from the ASTE for the
new SASN is used as the base for a third table When, for PR-ss, the primary space-switch-event
lookup. The new authorization index, bits 32-47 of control, bit 57 of control register 1, is one either
control register 4, is used, after it has been checked before or after the execution of the instruction, a
against the authority-table length, as the index to space-switch-event program interruption occurs after
locate the entry in the authority table. The authority- the operation is completed. A space-switch-event
table lookup is described in “ASN Authorization” on program interruption also occurs after the completion
page 3-31. of a PR-ss operation if a PER event is reported.
The description in this paragraph applies to use of The PSW which is to be loaded by the instruction is
the subspace-group facility when SASN translation not checked for validity before it is loaded. However,
and authorization have occurred. If (1) the subspace- after loading, a specification exception is recognized,
group-control bit, bit 54, in the new SASCE is one, and a program interruption occurs, if any of bits 0,
(2) the dispatchable unit is subspace active, and 2-4, 12, 24-30, and 33-63 of the PSW is a one, if bits
(3) the ASTE origin obtained by SASN translation 31 and 32 are zero and one, respectively, and bits
designates the ASTE for the base space of the dis- 64-96 are not all zeros, if bits 31 and 32 are both zero
patchable unit, then bits 0-55 and 58-63 are replaced and bits 64-103 are not all zeros, or if bits 31 and 32
by the same bits of the ASCE of the ASCE in the are one and zero, respectively. In these cases, the
ASTE for the subspace in which the dispatchable unit operation is completed, and the resulting instruction-
last had control. Further details are in “Subspace- length code is 0. The specification exception, which
Replacement Operations” on page 5-65. in this case is listed as a program exception in this
instruction, is described in “Early Exception Recogni-
PROGRAM RETURN Serialization tion” on page 6-8. It may be considered as occurring
early in the process of preparing to execute the fol-
When the unstacked state entry is a program-call lowing instruction.
state entry, a serialization and checkpoint-synchroni-
zation function is performed before the operation If a space-switch event is indicated and the PSW that
begins and again after the operation is completed. was loaded by the instruction is invalid because of a
However, it is unpredictable whether or not a store reason described in the preceding paragraph, it is
into a trace-table entry or linkage-stack entry from unpredictable whether the resulting instruction-length
which a subsequent instruction is fetched will be code is 0 or 1, or 0 or 2 if EXECUTE was used, or 0
observed by the CPU that performed the store. or 3 if EXECUTE RELATIVE LONG was used.
7. Special-operation exception due to DAT being off or the CPU being in secondary-space mode or home-
space mode.
8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry.
8.B.2 Stack-type exception due to current entry not being a state entry or header entry.
Note: Exceptions 8.B.3-8.B.7 can occur only if the current entry is a header entry.
8.B.3 Stack-operation exception due to unstack-suppression bit in the header entry being one.
8.B.4 Access exceptions (fetch) for second word of the header entry.
8.B.5 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero.
8.B.6 Access exceptions (fetch) for entry descriptor of preceding entry, which is the entry designated by the
backward stack-entry address in the current (header) entry.
8.B.8 Stack-type exception due to preceding entry not being a state entry.
8.B.9 Stack-operation exception due to unstack-suppression bit being one in the state entry.
8.B.10 Access exceptions (fetch) for the state entry, and access exceptions (store) for entry descriptor of the entry
preceding the state entry.
Note: Exceptions 8.B.11-8.B.15 and the event 9 can occur only if the state entry is a program-call state
entry.
8.B.11 Special-operation exception due to the ASN-translation control, bit 44 of control register 14, being zero (if
PASN or SASN translation occurs).
8.B.13 ASTE-instance exception due to new PASTEIN not being equal to ASTEIN in ASN-second-table entry
located by PASN translation (if ASN-and-LX reuse enabled).
Note: Subspace-replacement exceptions for replacement of bits in the PASCE, which are not shown in detail
in this figure, can occur with any priority after 8.B.13 and before 9.
8.B.15 ASTE-instance exception due to new SASTEIN not being equal to ASTEIN in ASN-second-table entry
located by SASN translation (if ASN-and-LX reuse enabled).
Note: Subspace-replacement exceptions for replacement of bits in the SASCE, which are not shown in
detail in this figure, can occur with any priority after 8.B.15 and before 9.
8.B.16 Secondary-authority exception due to authority-table entry being outside table (if SASN translation occurs).
8.B.17 Addressing exception for access to authority-table entry (if SASN translation occurs).
8.B.18 Secondary-authority exception due to S bit in authority-table entry being zero (if SASN translation occurs).
10. Specification exception due to any PSW error of the type that causes an immediate interruption.
• Special operation
• Specification Note: In this instruction definition, the name “PRO-
• Stack empty GRAM TRANSFER (WITH INSTANCE)” refers to the
• Stack operation PROGRAM TRANSFER instruction and the PRO-
• Stack specification GRAM TRANSFER WITH INSTANCE instruction.
• Stack type
• Subspace replacement (if PASN or SASN trans- Bits 32-63 of general register R1 are used as the new
lation occurs) values for the PSW-key mask, the PASN, and the
• Trace SASN. Bits 32-63 or 0-63 of general register R2,
depending on the current addressing mode, are used
Programming Note: Because PROGRAM CALL as the new values for the problem-state bit, basic-
cannot be executed successfully in the secondary- addressing-mode bit, and instruction address in the
space or home-space mode, PROGRAM RETURN is current PSW. In the PROGRAM TRANSFER WITH
not intended to load a PSW specifying one of these INSTANCE operation, bits 0-31 of general register R1
translation modes. PROGRAM RETURN, unlike SET are an ASTEIN and are compared against the new
ADDRESS SPACE CONTROL and SET ADDRESS value of the PASTEIN if the PASN is changed. In the
SPACE CONTROL FAST, does not recognize a PROGRAM TRANSFER operation, bits 0-31 of gen-
space-switch event because of loading a PSW that eral register R1 are ignored.
specifies the home-space mode.
The format of general registers R1 and R2 are shown
in Figure 10-60.
In any of the PT-cp, PTI-cp, PT-ss, and PTI-ss opera- Bits 48-57 of general register R1 are a 10-bit AFX
tions, the ASN specified by bits 48-63 of general reg- that is used to select an entry from the ASN first
ister R1 replaces the SASN in control register 3, and table. Bits 58-63 are a six-bit ASX that is used to
the SASCE in control register 7 is replaced by the select an entry from the ASN second table. The ASN
final contents of control register 1. table-lookup process is described in “ASN Transla-
tion” on page 3-26. The exceptions associated with
In the PROGRAM TRANSFER operation, if the ASN- ASN translation are collectively called “ASN-transla-
and-LX-reuse facility is installed and is enabled by a tion exceptions.” These exceptions and their priority
one value of the ASN-and-LX-reuse control, bit 44 of are described in Chapter 6, “Interruptions.”
control register 0, the SASTEIN in control register 3
is replaced by the final value of the PASTEIN in con- In PT-ss if the ASN-and-LX-reuse facility is installed
trol register 4. This replacement occurs in the PRO- and is enabled by a one value of the ASN-and-LX-
GRAM TRANSFER WITH INSTANCE operation reuse control, bit 44 of control register 0, the reus-
regardless of the value of the ASN-and-LX-reuse able-ASN bit, bit 63, in the located ASN-second-table
control. entry (ASTE) must be zero; otherwise, a special-
operation exception is recognized. In PTI-ss, regard-
PROGRAM TRANSFER (WITH INSTANCE) to Cur- less of the ASN-and-LX-reuse control, the controlled-
rent Primary (PT-cp or PTI-cp) ASN bit, bit 62, in the ASTE must be zero if the CPU
is in the problem state at the beginning of the opera-
tion; otherwise, a special-operation exception is rec-
and-LX-reuse control and the reusable-ASN bit, the begins and again after the operation is completed.
ASTEIN in bit positions 0-31 of general register R1 However, it is unpredictable whether or not a store
must equal the ASTEIN in bit positions 352-383 of into a trace-table entry from which a subsequent
the ASTE; otherwise, an ASTE-instance exception is instruction is fetched will be observed by the CPU
recognized. that performed the store.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B.1 Operation exception (PTI only, if the ASN-and-LX-reuse facility is not installed).
7.B.2 Special-operation exception due to DAT being off or the CPU being in secondary-space mode, access-
register mode, or home-space mode.
8.B.1 Addressing exception for access to linkage-table designation or linkage-first-table designation in primary
ASN-second-table entry.
8.B.3 Privileged-operation exception due to attempt to set the supervisor state when in the problem state.
8.B.4 Specification exception due to invalid combination (bit 32 is zero and bits 33-39 not zeros) in general register
R2 in 24-bit or 31-bit addressing mode.
8.B.5 Special-operation exception due to the ASN-translation control, bit 44 of control register 14, being zero (PT-
ss or PTI-ss only).
8.B.7 Special-operation exception due to ASN-and-LX reuse enabled and reusable-ASN bit in ASN-second-table
entry being one (PT-ss only).
8.B.8 Special-operation exception due to controlled-ASN bit in ASN-second-table entry being one and CPU being
in problem state at the beginning of the operation (PTI-ss only).
8.B.9 ASTE-instance exception due to ASTEIN in general register R1 not being equal to ASTEIN in ASN-second-
table entry (PTI-ss only).
Note: Subspace-replacement exceptions, which are not shown in detail in this figure, can occur with any
priority after 8.B.9 and before 9.
8.B.10 Primary-authority exception due to authority-table entry being outside table (PT-ss and PTI-ss only).
8.B.11 Addressing exception for access to authority-table entry (PT-ss and PTI-ss only).
8.B.12 Primary-authority exception due to P bit in authority-table entry being zero (PT-ss and PTI-ss only).
PROGRAM TRANSFER
Instruction
'B228' / / / / R1 R2
In 24-Bit or
31-Bit Mode
R1 R2
32-63 PKM ASN A IA 33-62 P
32-63
PSW
after (with 33 zeros on left)
/ / /
P E A IA 0-62 0
CR3 / / /
32-63 PKM SASN E=0
before
AND
In 64-Bit Mode
R2 IA 0-62 P
CR3 SASTEIN PKM SASN
after
PSW
after
/ / /
P E A IA 0-62 0
CR4 / / /
before PASTEIN AX PASN E=1 A=1
PT-cp PT-ss
Instruction (see part 2) CR7 SASCE
Complete after
PT-ss
CR14 R1
T AFTO 32-63 PKM ASN
32-63
(x4096)
AFX ASX
(x4) (x64)
+
ASN First Table
R I ASTO
(x64)
+
Special-operation exception if ASN-and-LX
ASN-Second-Table reuse enabled and RA is one.
/ /
R I ATO B AX ATL C R
A A ASCE ASTEIN*** *
/ /
(x4)
CR4
32-63 AX PASN CR4
before after PASTEIN*** AX PASN
(x1/4)
+
CR1
after PASCE
R P S **
0 000000
CR7 CR5
after SASCE 32-63 PASTEO
** after
Primary-authority exception if P bit is zero or table length exceeded
R: Address is real
*: ASTE is 64 bytes; selected fields and the last 16 bytes are not shown.
**: Bits 0-55 and 58-63 of PASCE and SASCE may be replaced from a subspace ASCE
***: Operations on the ASTE instance number performed if ASN-and-LX-reuse enabled
PROGRAM TRANSFER
WITH INSTANCE Instruction
'B99E' / / / / R1 R2
In 24-Bit or
31-Bit Mode
R1 ASTEIN PKM ASN R2 A IA 33-62 P
32-63
PSW
after (with 33 zeros on left)
/ / /
P E A IA 0-62 0
CR3 / / /
32-63 PKM SASN E=0
before
AND
In 64-Bit Mode
R2 IA 0-62 P
CR3 SASTEIN PKM SASN
after
PSW
after
/ / /
P E A IA 0-62 0
CR4 / / /
before PASTEIN AX PASN E=1 A=1
(PTI-cp only)
CR1
before PASCE
R1.ASN
= PASN
Yes No
? (PTI-cp only)
PTI-cp PTI-ss
Instruction (see part 2) CR7 SASCE
Complete after
PTI-ss
AFX ASX
(x4) (x64)
+
ASN First Table
=? ASTE-
R I ASTO No instance
exception
(x64)
Special-operation exception if CA
+ is one and CPU in problem state
ASN-Second-Table at beginning of operation
/ /
R I ATO B AX ATL C R
A A ASCE ASTEIN*** *
/ /
(x4)
CR4
32-63 AX PASN CR4
before after PASTEIN AX PASN
(x1/4)
+
R: Address is real
*: ASTE is 64 bytes; selected fields and the last 16 bytes are not shown.
**: Bits 0-55 and 58-63 of PASCE and SASCE may be replaced from a subspace ASCE
'B20D' //////////////// The remaining bits of the storage key, including the
0 16 31 change bit, are not affected.
The translation-lookaside buffer (TLB) of this CPU is The condition code is set to reflect the state of the
cleared of entries. No change is made to the con- reference and change bits before the reference bit is
tents of addressable storage or registers. set to zero.
The TLB appears cleared of its original contents Resulting Condition Code:
beginning with the fetching of the next sequential
instruction. The operation is not signaled to any other 0 Reference bit zero; change bit zero
CPU. 1 Reference bit zero; change bit one
2 Reference bit one; change bit zero
A serialization function is performed. 3 Reference bit one; change bit one
MULTIPLE
RP D2(B2) [S]
RRBM R1,R2 [RRE] 'B277' B2 D2
0 16 20 31
'B9AE' / / / / / / / / R1 R2
0 16 24 28 31
Certain contents of the current PSW and of access
register and general register B2 are replaced from
Beginning with the block designated by the address
three or four corresponding fields in the second oper-
in general register R2, the reference bits in the stor-
and. The size of the PSW field in the second oper-
age keys of the 64 consecutive 4 K-byte blocks are
and, the size or number of general-register fields in
inspected and reset. For each of the 64 blocks, the
the second operand, and the offsets of the fields in
reference bit is placed in an ascending bit position of
the second operand are specified in a parameter list
general register R1, beginning with bit position 0 of
that immediately follows the instruction in the instruc-
the register. Subsequent to the inspection of each
tion address space.
reference bit, the reference bit in the storage key is
reset to zero.
The instruction address space is the address space
from which instructions are fetched. It is composed of
General register R2 designates the first of 64 blocks
real addresses if DAT is off.
in absolute storage on a 64-block (256 K-byte)
boundary. In the 24-bit addressing mode, bits 40-45
The first 64 bits of the parameter list have the follow-
of the register, with six binary zeros appended on the
ing format:
right, designate the first block, and bits 0-39 and
46-63 of the register are ignored. In the 31-bit
addressing mode, bits 33-45 of the register, with six 0 0 0 0 0 0 0 0 0 0 0 0 0 PRD Offset of PSW Field
0 13 14 15 16 31
binary zeros appended on the right, designate the
first block, and bits 0-32 and 46-63 of the register are Offset of AR Field Offset of GR Field 1
ignored. In the 64-bit addressing mode, bits 0-45 of 32 48 63
the register, with six binary zeros appended on the
right, designate the first block, and bits 46-63 of the When bits 14 (R) and 15 (D) of the parameter list are
register are ignored. both one, the list is an additional 16 bits in length, as
follows:
Because it is an absolute address, the address des-
ignating the first storage block is not subject to
Offset of GR Field 2
dynamic address translation. The references to the
64 79
storage keys are not subject to protection exceptions.
The remaining bits of the storage keys are not Bit 13 of the parameter list (P) specifies the size of
affected. the PSW field in the second operand. The field is
eight bytes if bit 13 is zero or 16 bytes if bit 13 is one.
Condition Code: The code remains unchanged.
Bits 14 and 15 of the parameter list (R and D) provide
Program Exceptions: specifications about one or two general-register
fields in the second operand, as follows:
• Addressing (address specified by general regis-
ter R2) • When bit 14 is zero, then bit 15 is ignored, the
• Operation (reset-reference-bits-multiple facility general-register field 1 in the second operand is
not installed) four bytes, from which bits 32-63 of general reg-
• Privileged operation ister B2 will be replaced, there is not a general-
register field 2 in the second operand, and bits
0-31 of general register B2 will remain
unchanged.
RESUME PROGRAM
general-register field 1 is eight bytes, from which responding fields in the PSW field in the second
bits 0-63 of general register B2 will be replaced, operand. The PSW fields that are replaced are as fol-
and there is not a general-register field 2. lows:
• When bits 14 and 15 are both one, then the gen- PSW Bits Field Name
eral-register fields 1 and 2 are both four bytes,
16 and 17 Address-space control (AS)
bits 32-63 of general register B2 will be replaced
from field 1, and bits 0-31 of the register will be 18 and 19 Condition code (CC)
replaced from field 2. (The letter “D” stands for 20-23 Program mask
disjoint.) 31 Extended addressing mode (EA)
32 Basic addressing mode (BA)
Bits 16-31 of the parameter list are an unsigned 64-127 Instruction address
binary integer that is the offset in bytes from the
beginning of the second operand to a field that has
The remaining fields in the PSW field in the second
the format of an eight-byte or 16-byte PSW, depend-
operand are ignored. Specifically, there is no test for
ing on bit 13, and from which fields in the current
whether bit 12 is one in an eight-byte PSW or zero in
PSW will be replaced. Bits 32-47 similarly are an off-
a 16-byte PSW. There is also no test for whether bit
set to a four-byte field from which the contents of
31 is zero in an eight-byte PSW.
access register B2 will be replaced. Bits 48-63 simi-
larly are an offset to a four-byte or eight-byte field,
Unassigned fields in the PSW may be assigned in
depending on bits 14 and 15, from which bits 32-63
the future and may then be among those restored by
or 0-63, respectively, of general register B2 will be
RESUME PROGRAM. Therefore, these fields in the
replaced. If bits 64-79 of the parameter list exist, they
PSW field in the second operand should contain
similarly are an offset to a four-byte field from which
zeros; otherwise, the program may not operate com-
bits 0-31 of general register B2 will be replaced.
patibly in the future.
Bits 0-12 of the parameter list must be zeros; other-
When PSW bits 64-127 are replaced from an eight-
wise, a specification exception is recognized.
byte PSW field in the second operand, they are
replaced with bits 33-63 of the field, with 33 zeros
An eight-byte second-operand PSW field has the
appended on the left.
ESA/390 PSW format, as follows:
The fields in the second operand are fetched before
I E Prog.
0R000T Key 1 M W P AS CC 00000000 the contents of access register B2 and general regis-
OX Mask
ter B2 are changed.
0 1 2 5 6 7 8 12 13 14 15 16 18 20 24 31
operation is to set the home-space mode; otherwise, one; (2) the home space-switch-event control, bit 57
a privileged-operation exception is recognized. When of the home ASCE in control register 13, is one; or
DAT is off, the values of bits 16 and 17 of the PSW (3) a PER event is to be indicated.
field in the second operand are not tested.
The operation is suppressed on all addressing and
When the CPU is in the home-space mode either protection exceptions.
before or after the operation, but not both before and
after the operation, a space-switch-event program The priority of recognition of program exceptions for
interruption occurs after the operation is completed if the instruction is shown in Figure 10-64 on
any of the following is true: (1) the primary space- page 10-110.
switch-event control, bit 57 of the primary address-
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
8.B.2 Specification exception due to bits 0-12 of parameter list not being all zeros.
8.B.3 Access exceptions for bits 64-79 of parameter list, if these bits exist.
8.B.5 Privileged-operation exception due to attempt to set the home-space mode when in the problem state.
8.B.6 Specification exception due to invalid values in bit positions 31, 32, and 64-127 of PSW in second operand.
9. Space-switch event.
Resulting Condition Code: The code is set as applicable when RESUME PROGRAM is the tar-
specified by the new condition code loaded. get of an execute-type instruction since the exe-
cute-type instruction may be refetched in order to
Program Exceptions: generate, from its second operand, the address
of the parameter list used by RESUME PRO-
• Access (fetch, parameter list and operand 2) GRAM. If the execute-type instruction is
• Privileged operation (attempt to set the home- refetched, there is not necessarily a test for
space mode when in the problem state) whether storage still contains either the execute-
• Space-switch event type instruction or the RESUME PROGRAM
• Specification instruction.
• Trace
2. The storage-operand references for RESUME
Programming Notes: PROGRAM may be multiple-access references.
(See “Storage-Operand Consistency” on
1. As described in “Instruction Fetching” on page 5-95.)
page 5-89, the bytes of an instruction may be
fetched piecemeal, and the instruction may be SET ADDRESS SPACE CONTROL
fetched multiple times for a single execution.
Therefore, the results are unpredictable when SAC D2(B2) [S]
instructions are fetched for execution from stor-
age that is being changed by another CPU or a 'B219' B2 D2
channel program. This warning is particularly 0 16 20 31
SACF D2(B2) [S] When the CPU is in the home-space mode either
'B279' B2 D2 before or after the operation, but not both before and
0 16 20 31 after the operation, a space-switch-event program
interruption occurs after the operation is completed if
any of the following is true: (1) the primary space-
Bits 52-55 of the second-operand address are used switch-event control, bit 57 of the primary address-
as a code to set the address-space-control bits in the space-control element (ASCE) in control register 1, is
PSW. The second-operand address is not used to one; (2) the home space-switch-event control, bit 57
address data; instead, bits 52-55 form the code. Bits of the home ASCE in control register 13, is one; or
0-51 and 56-63 of the second-operand address are (3) a PER event is to be indicated.
ignored. Bits 52 and 53 of the second-operand
address must be zeros; otherwise, a specification The priority of recognition of program exceptions for
exception is recognized. the instructions is shown in Figure 10-65 on
page 10-111.
The following figure summarizes the operation of
SET ADDRESS SPACE CONTROL and SET Condition Code: The code remains unchanged.
ADDRESS SPACE CONTROL FAST:
Program Exceptions:
Second-Operand Address
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / • Privileged operation (attempt to set the home-
0 31 space mode in the problem state)
/ / / / / / / / / / / / / / / / / / / / Code / / / / / / / / • Space-switch event
32 52 56 63
• Special operation
• Specification
Result in PSW
Code Name of Mode Bits 16 and 17 1.-6. Exceptions with the same priority as the priority
of program-interruption conditions for the general
0000 Primary space 00
case.
0001 Secondary space 10
0010 Access register 01 7.A Access exceptions for second instruction
0011 Home space 11 halfword.
All others Invalid
7.B Special-operation exception due to DAT being
off.
The CPU must be in the supervisor state when the
operation is to set the home-space mode; otherwise, 7.C Special-operation exception due to the
a privileged-operation exception is recognized. secondary-space control, bit 37 of control
register 0, being zero. May be omitted for SET
For SET ADDRESS SPACE CONTROL, a serializa- ADDRESS SPACE CONTROL FAST.
tion and checkpoint-synchronization function is per-
8. Privileged-operation exception due to attempt to
formed before the operation begins and again after set home-space mode when in problem state.
the operation is completed. This function is not per-
formed for SET ADDRESS SPACE CONTROL FAST. 9. Specification exception due to non-zero value in
bit positions 52 and 53 of second-operand
Special Conditions address.
stopped state.
1. SET ADDRESS SPACE CONTROL and SET
ADDRESS SPACE CONTROL FAST are defined The doubleword operand replaces the contents of
in such a way that the mode to be set can be the clock, as determined by the resolution of the
placed directly in the displacement field of the clock. Only those bits of the operand are set in the
instruction or can be specified from the same bit clock that correspond to the bit positions which are
positions of a general register as those in which updated by the clock; the contents of the remaining
the mode is saved by INSERT ADDRESS rightmost bit positions of the operand are ignored
SPACE CONTROL. and are not preserved in the clock. In some models,
starting at or to the right of bit position 52, the right-
2. SET ADDRESS SPACE CONTROL FAST may most bits of the second operand are ignored, and the
provide better performance than SET ADDRESS corresponding positions of the clock which are imple-
SPACE CONTROL, depending on the model. mented are set to zeros. Zeros are also placed in
3. Because SET ADDRESS SPACE CONTROL positions to the right of bit position 63 of the clock.
FAST does not perform the serialization function,
it does not cause copies of prefetched instruc- After the clock value is set, the clock enters the
tions to be discarded. To ensure predictable stopped state. The clock leaves the stopped state to
results after SET ADDRESS SPACE CONTROL enter the set state and resume incrementing under
FAST is used to switch to or from the home- control of the TOD-clock-sync control, bit 34 of con-
space mode, the program must cause prefetched trol register 0, of the CPU which most recently
instructions to be discarded before an instruction caused the clock to enter the stopped state. When
is executed in a location that does not contain the the bit is zero, the clock enters the set state at the
same instruction in both the primary and home completion of the instruction. When the bit is one, the
address spaces. The operations that cause clock remains in the stopped state until the bit is set
prefetched instructions to be discarded are to zero or until another CPU executes a SET CLOCK
described in “Instruction Fetching” on page 5-89. instruction affecting the clock. If an external time ref-
erence (ETR) is installed, a signal from the ETR may
4. If a program stores into the instruction stream at be used to set the set state from the stopped state.
a location following a subsequent SET Whenthe system is not in the interpretive-execution
ADDRESS SPACE CONTROL FAST instruction, mode, and an external time reference (ETR) is not
and the SET ADDRESS SPACE CONTROL attached to the configuration, the TOD-clock-sync
FAST instruction changes the translation mode control is treated as being zero, regardless of its
either from or to either the access-register mode actual value; in this case, the clock enters the set
or the home-space mode, a copy of a prefetched state and resumes incrementing upon completion of
instruction may be executed instead of the value the instruction.
that was stored. To avoid this situation, either
SET ADDRESS SPACE CONTROL must be The value of the clock is changed and the clock is
used instead of SET ADDRESS SPACE CON- placed in the stopped state only if the manual TOD-
TROL FAST or some other means must be used clock control of any CPU in the configuration is set to
to cause prefetched instructions to be discarded the enable-set position or the TOD-clock-control-
after the conceptual store occurs. override control, bit 42 of control register 14, is one. If
the TOD-clock control of all CPUs is set to the secure
position and the TOD-clock-control-override control is
SET CLOCK zero, the value and state of the clock are not
changed. Whether the clock is set or remains
SCK D2(B2) [S] unchanged is distinguished by condition codes 0 and
'B204' B2 D2 1, respectively.
0 16 20 31
When the clock is not operational, the value and
state of the clock are not changed, regardless of the
The current value of the TOD clock is replaced by the settings of the TOD-clock control and the TOD-clock-
contents of the doubleword designated by the sec- control-override control, and condition code 3 is set.
2. To ensure predictable operation of the CPU timer Condition Code: The code remains unchanged.
after the TOD clock enters the set state, SET
CPU TIMER should be issued on all CPUs in the Program Exceptions:
configuration.
• Access (fetch, operand 2)
3. To ensure predictable operation of clock-compar- • Privileged operation
ator interruptions after the TOD clock enters the • Specification
set state, one of the following instructions should
be issued on each CPU in the configuration: SET
CLOCK COMPARATOR (SCKC), STORE SET CLOCK PROGRAMMABLE
CLOCK (STCK), or STORE CLOCK EXTENDED FIELD
(STCKE). (Execution of STCKF does not neces-
sarily include the interlocks required for this spe- SCKPF [E]
cial situation.)
'0107'
4. SET CLOCK is provided for compatibility pur- 0 15
Special Conditions
Programming Note: The values in the TOD pro- After the second operand is fetched, the value is
grammable registers of a configuration should be the tested for validity before it is used to replace the con-
same and should be unique within a multiple-configu- tents of the prefix register. Bits 1-18 of the operand
ration system. with 13 zeros appended on the right and 33 zeros
appended on the left are used as an absolute
address of the 8K-byte new prefix area in storage.
SET CPU TIMER This address is treated as a 64-bit address regard-
less of the addressing mode specified by the current
SPT D2(B2) [S] PSW. The two 4K-byte blocks within the new prefix
'B208' B2 D2 area are accessed; if either is not available in the
0 16 20 31 configuration, an addressing exception is recognized,
and the operation is suppressed. The accesses to
the blocks are not subject to protection; however, the
The current value of the CPU timer is replaced by the accesses may cause the reference bits for the blocks
contents of the doubleword designated by the sec- to be set to ones.
ond-operand address.
If the operation is completed, the new prefix is used
Only those bits of the operand are set in the CPU for any interruptions following the execution of the
timer that correspond to the bit positions to be instruction and for the execution of subsequent
updated; the contents of the remaining rightmost bit instructions. The contents of bit positions 0 and
positions of the operand are ignored and are not pre- 19-31 of the second operand are ignored.
served in the CPU timer.
The ART-lookaside buffer (ALB) and translation-
Special Conditions lookaside buffer (TLB) are cleared of entries. The
ALB and TLB appear cleared of their original con-
The operand must be designated on a doubleword tents, beginning with the fetching of the next sequen-
boundary; otherwise, a specification exception is rec- tial instruction.
ognized.
A serialization function is performed before or after
The operation is suppressed on all addressing and the second operand is fetched and again after the
protection exceptions. operation is completed.
Condition Code: The code remains unchanged. Special Conditions
Program Exceptions: The second operand must be designated on a word
boundary; otherwise, a specification exception is rec-
• Access (fetch, operand 2) ognized.
• Privileged operation
• Specification The operation is suppressed on all addressing and
protection exceptions.
SET PREFIX
Condition Code: The code remains unchanged.
SPX D2(B2) [S]
Program Exceptions:
'B210' B2 D2
0 16 20 31 • Access (fetch, operand 2)
• Addressing (new prefix area)
The four-bit PSW key, bits 8-11 of the current PSW, is SET SECONDARY ASN
replaced by bits 56-59 of the second-operand
address. SSAR R1 [RRE]
'B225' / / / / / / / / R1 / / / /
The second-operand address is not used to address
0 16 24 28 31
data; instead, bits 56-59 of the address form the new
PSW key. Bits 0-55 and 60-63 of the second-operand
address are ignored.
SET SECONDARY ASN WITH
Special Conditions INSTANCE
In the problem state, the execution of the instruction SSAIR R1 [RRE]
is subject to control by the PSW-key mask in control
'B99F' / / / / / / / / R1 / / / /
register 3. When the bit in the PSW-key mask corre-
0 16 24 28 31
sponding to the PSW-key value to be set is one, the
instruction is executed successfully. When the
selected bit in the PSW-key mask is zero, a privi- Note: In this instruction definition, the name “SET
leged-operation exception is recognized. In the SECONDARY ASN (WITH INSTANCE)” refers to the
supervisor state, any value for the PSW key is valid. SET SECONDARY ASN instruction and the SET
SECONDARY ASN WITH INSTANCE instruction.
Condition Code: The code remains unchanged.
The ASN specified in bit positions 48-63 of general
Program Exceptions: register R1 replaces the secondary ASN in control
register 3, and the address-space-control element
• Privileged operation (selected PSW-key-mask bit corresponding to that ASN replaces the SASCE in
is zero in the problem state) control register 7.
SSAIR-ss operations are depicted in Figure 10-68 on ASTEIN in bit positions 0-31 of general register R1
page 10-120. must equal the ASTEIN in bit positions 352-383 of
the ASTE; otherwise, an ASTE-instance exception is
SET SECONDARY ASN (WITH INSTANCE) to Cur- recognized.
rent Primary (SSAR-cp or SSAIR-cp)
The ASN-second-table entry (ASTE) obtained as a
In the SSAR-cp or SSAIR-cp operation, the new ASN result of the second lookup contains the address-
is equal to the PASN. The new ASN replaces the space-control element and the authority-table origin
SASN, bits 48-63 of control register 3; the PASCE in and length associated with the ASN.
control register 1 replaces the SASCE in control reg-
ister 7. The authority-table origin from the ASTE is used as a
base for a third table lookup. The current authoriza-
In SSAR-cp, if the ASN-and-LX-reuse facility is tion index, bits 32-47 of control register 4, is used,
installed and is enabled by a one value of the ASN- after it has been checked against the authority-table
and-LX-reuse control, bit 44 of control register 0, the length, as the index to locate the entry in the author-
SASTEIN in bit positions 0-31 of control register 3 is ity table. The authority-table lookup is described in
replaced by the PASTEIN in bit positions 0-31 of con- “ASN Authorization” on page 3-31.
trol register 4. This replacement occurs in SSAIR-cp
regardless of the value of the ASN-and-LX-reuse The new ASN, bits 48-63 of general register R1,
control. In SSAIR-cp, there is not a test of whether replaces the SASN, bits 48-63 of control register 3.
the current PASTEIN equals the ASTEIN in bit posi- The address-space-control element in the ASTE
tions 0-31 of general register R1; the ASTEIN is replaces the SASCE in control register 7. In SSAR-ss
ignored. The operation is completed. if ASN-and-LX reuse is enabled, and in SSAIR-ss
regardless of that enablement, the ASTEIN in the
SET SECONDARY ASN (WITH INSTANCE) with ASTE replaces the SASTEIN in bit positions 0-31 of
Space Switching (SSAR-ss or SSAIR-ss) control register 3.
In the SSAR-ss or SSAIR-ss operation, the new ASN The description in this paragraph applies to use of
is not equal to the PASN, and the new ASN is trans- the subspace-group facility. After the new SASCE
lated by means of a two-level table lookup. Bits 0-9 of has been placed in control register 7, if (1) the sub-
the new ASN (bits 48-57 of the register) are a 10-bit space-group-control bit, bit 54, in the SASCE is one,
AFX which is used to select an entry from the ASN (2) the dispatchable unit is subspace active, and
first table. Bits 10-15 of the new ASN (bits 58-63 of (3) the ASTE obtained by ASN translation is the
the register) are a six-bit ASX which is used to select ASTE for the base space of the dispatchable unit,
an entry from the ASN second table. The two-level then bits 0-55 and 58-63 of the SASCE are replaced
lookup is described in “ASN Translation” on by the same bits of the ASCE in the ASTE for the
page 3-26. The exceptions associated with ASN subspace in which the dispatchable unit last had con-
translation are collectively called “ASN-translation trol. Further details are in “Subspace-Replacement
exceptions.” These exceptions and their priority are Operations” on page 5-65.
described in Chapter 6, “Interruptions.”
SET SECONDARY ASN (WITH INSTANCE) Serial-
In SSAR-ss, if the ASN-and-LX-reuse facility is ization
installed and is enabled by the ASN-and-LX-reuse
control in control register 0, the reusable-ASN bit, bit For any of the SSAR-cp, SSAIR-cp, SSAR-ss, and
63, in the located ASN-second-table entry (ASTE) SSAIR-ss operations, a serialization and checkpoint-
must be zero; otherwise, a special-operation excep- synchronization function is performed before the
tion is recognized. In SSAIR-ss, regardless of the operation begins and again after the operation is
ASN-and-LX-reuse control, the controlled-ASN bit, completed. However, it is unpredictable whether or
bit 62, in the ASTE must be zero in the problem state; not a store into a trace-table entry from which a sub-
otherwise, a special-operation exception is recog- sequent instruction is fetched will be observed by the
nized. Also in SSAIR-ss, and regardless of the ASN- CPU that performed the store.
1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.
7.B.1 Operation exception (SSAIR only, if the ASN-and-LX-reuse facility is not installed).
7.B.2 Special-operation exception due to DAT being off, or the ASN-translation control, bit 44 of control register 14,
being zero.
8.B.2 Special-operation exception due to ASN-and-LX reuse enabled and reusable-ASN bit in ASN-second-table
entry being one (SSAR-ss only).
8.B.3 Special-operation exception due to controlled-ASN bit in ASN-second-table entry being one in the problem
state (SSAIR-ss only).
8.B.4 ASTE-instance exception due to ASTEIN in general register R1 not being equal to ASTEIN in ASN-second-
table entry (SSAIR-ss only).
Note: Subspace-replacement exceptions, which are not shown in detail in this figure, can occur with any
priority after 8.B.4.
8.B.5 Secondary-authority exception due to authority-table entry being outside table (SSAR-ss and SSAIR-ss
only).
8.B.6 Addressing exception for access to authority-table entry (SSAR-ss and SSAIR-ss only).
8.B.7 Secondary-authority exception due to S bit in authority-table entry being zero (SSAR-ss and SSAIR-ss only).
R1
+ ASN
32-63
ASN First Table
(Accessed for SSAR-ss only)
ASN
AFX ASX
(x64)
=?
Yes No
SSAR-cp SSAR-ss
+ Special-operation exception if
ASN-Second-Table ASN-and-LX reuse enabled and
(Accessed for SSAR-ss only) RA is one (SSAR-ss only)
/ /
R I ATO B AX ATL C R
A A ASCE ASTEIN *
/ /
(x4)
(x1/4)
+
(SSAR-cp (SSAR-ss
(SSAR-cp (SSAR-ss only and only and
only) only) ASN-and-LX ASN-and-LX
R P S reuse enabled) reuse enabled)
CR7 CR3
after SASCE after SASTEIN PKM SASN
**
Secondary-authority exception if S bit is zero
or if table length exceeded (SSAR-ss only)
R: Address is real
*: ASTE is 64 bytes; selected fields and the last 16 bytes are not shown.
**: For SSAR-ss only, bits 0-55 and 58-63 of SASCE may be replaced from a subspace ASCE
Figure 10-67. Execution of SET SECONDARY ASN
+ R1 ASTEIN ASN
ASN First Table
(Accessed for SSAIR-ss only)
ASN
AFX ASX
/ /
R I ATO B AX ATL C R
A A ASCE ASTEIN *
/ /
(x4)
(x1/4)
+
R: Address is real
*: ASTE is 64 bytes; selected fields and the last 16 bytes are not shown.
**: For SSAIR-ss only, bits 0-55 and 58-63 of SASCE may be replaced from a subspace ASCE
Figure 10-68. Execution of SET SECONDARY ASN WITH INSTANCE
The bits of the M3 field are defined as follows: If an invalid checking-block code (CBC) is
detected when fetching the storage key, then
• Nonquiescing Control (NQ): The NQ bit, bit 0 (a) the entire storage key for the 4K-byte
of the M3 field, controls whether a quiescing block is replaced by bits 56-62 of general
operation is performed, as described below. register R1, (b) the contents of bit positions
48-55 of general register R1 are unpredict-
able, and (c) the instruction completes by
setting condition code 3.
bit of the storage key for the designated 4K- general register R1, the reference bit for the
byte block are compared with the corre- key is unpredictable, and the instruction
sponding fields in bits 56-60 of general regis- completes by setting condition code 2. It is
ter R1. If the respective fields are not equal, unpredictable whether condition code 1 or 2
the entire storage key for the 4K-byte block is is set.
replaced by bits from general register R1,
and the instruction completes by setting con- When the enhanced-DAT facility is not installed, or
dition code 1. when the facility is installed but the multiple-block
control is zero, general register R2 contains a real
When the access-control and fetch-protec- address. When the enhanced-DAT facility is installed
tion bits in the storage key are equal to the and the multiple-block control is one, general register
respective bits in general register R1, pro- R2 contains an absolute address.
cessing continues as described below.
In the 24-bit addressing mode, bits 40-51 of general
c. When both the MR and MC bits are one, the register R2 designate a 4K-byte block in real or abso-
instruction completes by setting condition lute storage, and bits 0-39 and 52-63 of the register
code 0. The storage key remains unchanged are ignored. In the 31-bit addressing mode, bits
in this case. 33-51 of general register R2 designate a 4K-byte
block in real or absolute storage, and bits 0-32 and
d. When the MR bit is zero and the MC bit is 52-63 of the register are ignored. In the 64-bit
one, then the reference bit of the storage key addressing mode, bits 0-51 of general register R2
for the designated 4K-byte block is compared designate a 4K-byte block in real or absolute storage,
with bit 61 of general register R1. If the bits and bits 52-63 of the register are ignored.
are equal, the instruction completes by set-
ting condition code 0. The storage key Because it is a real or absolute address, the address
remains unchanged in this case. designating the storage block is not subject to
dynamic address translation. The reference to the
If the bits are not equal, then either (a) the storage key is not subject to a protection exception.
entire storage key for the designated 4K-byte
block is replaced by the bits in general regis- The new seven-bit storage-key value, or selected bits
ter R1, and the instruction completes by set- thereof, is obtained from bit positions 56-62 of gen-
ting condition code 1; or (b) the reference bit eral register R1. The contents of bit positions 0-55
for the storage key is replaced by bit 61 of and 63 of the register are ignored. When the condi-
general register R1, the change bit for the key tional-SSKE facility is installed, and either or both the
is unpredictable, and the instruction com- MR and MC bits are one, bit position 63 should con-
pletes by setting condition code 2. It is tain a zero; otherwise, the program may not operate
unpredictable whether condition code 1 or 2 compatibly in the future.
is set.
A serialization and checkpoint-synchronization func-
e. When the MC bit is zero and the MR bit is tion is performed before the operation begins and
one, then the change bit of the storage key again after the operation is completed, except that
for the designated 4K-byte block is compared when the conditional-SSKE facility is installed and
with bit 62 of general register R1. If the bits the resulting condition code is 0, it is unpredictable
are equal, the instruction completes by set- whether a serialization and checkpoint-synchroniza-
ting condition code 0. The storage key tion function is performed after the operation com-
remains unchanged in this case, except that pletes.
the reference bit is unpredictable.
When the nonquiescing key-setting facility is not
If the bits are not equal, then either (a) the installed, or when the facility is installed and the non-
entire storage key for the designated 4K-byte quiescing control (NQ) is zero, the following applies:
block is replaced by the bits in general regis-
ter R1, and the instruction completes by set- • A quiescing operation is performed.
ting condition code 1; or (b) the change bit
• When an interruption occurs (other than one that • Addressing (address specified by general regis-
follows termination), the leftmost bits of general ter R2)
register R2 comprising the 4K-byte block address • Privileged operation
have been updated so the instruction, when
reexecuted, resumes at the point of interruption. Programming Notes:
If either or both the MR or MC bits are one, the
condition code is unpredictable; otherwise, the 1. The M3 field of the instruction is considered to be
condition code is unchanged. optional, as indicated by the field being con-
tained within brackets [] in the assembler syntax.
• When the instruction completes without interrup-
When the M3 field is not specified, the assembler
tion, the leftmost bits of general register R2 com-
places zeros in that field of the instruction.
prising the 4K-byte block address have been
updated to the next 1M-byte boundary. If either 2. When setting multiple storage keys within the
or both the MR or MC bits are one, condition same 1M-byte block to the same value, use of
code 3 is set; otherwise, the condition code is the multiple-block control (MB, bit 3 of the M3
unchanged. field) may yield better performance than execut-
ing separate SSKE instructions for each 4K-byte
In either of the above two cases, the following block in the megabyte.
applies:
3. If the program does not rely on the setting of the
reference bit, it may set the MR bit of the M3 field
tional-SSKE facility is installed. Similarly, if the ered as caused by execution of this instruction or as
program does not rely on the setting of the occurring early in the process of preparing to execute
change bit, it may set the MC bit of the M3 field to the subsequent instruction.
one, regardless of whether or not the conditional-
SSKE facility is installed. In these cases, the pro- The operation is suppressed on all addressing and
gram cannot rely on the condition code or the key protection exceptions.
value returned in general register R1. Conversely,
if the program depends on accurate setting of the Condition Code: The code remains unchanged.
reference or change bit, then the MR and MC
bits should be set to zero, such that reference Program Exceptions:
and change bit recording are properly main-
tained when the conditional-SSKE facility is • Access (fetch, operand 2)
installed. • Privileged operation
• Special operation
4. When SSKE is issued, the program must ensure • Specification
that no channel subsystem is simultaneously
altering the storage designated by general regis-
ter R2. The program also must ensure that no SIGNAL PROCESSOR
other CPU or channel subsystem is accessing
the storage designated by general register R2 SIGP R1,R3,D2(B2) [RS-a]
when the nonquiescing (NQ) control is one. Oth-
'AE' R1 R3 B2 D2
erwise, unpredictable results may be observed
0 8 12 16 20 31
by the other CPUs and channel subsystem,
including the alteration of the block designated
by general register R2. An eight-bit order code and, if called for, a 32-bit
parameter are transmitted to the CPU designated by
the CPU address contained in the third operand. The
SET SYSTEM MASK result is indicated by the condition code and may be
detailed by status assembled in bit positions 32-63 of
SSM D2(B2) [S] the first-operand location.
'80' / / / / / / / / B2 D2
0 8 16 20 31
The second-operand address is not used to address
data; instead, bits 56-63 of the address contain the
eight-bit order code. Bits 0-55 of the second-operand
Bits 0-7 of the current PSW are replaced by the byte address are ignored. The order code specifies the
at the location designated by the second-operand function to be performed by the addressed CPU.
address. The assignment and definition of order codes appear
in “CPU Signaling and Response” on page 4-58.
Special Conditions
The 16-bit binary number contained in bit positions
When the SSM-suppression-control bit, bit 33 of con- 48-63 of general register R3 forms the CPU address.
trol register 0, is one and the CPU is in the supervisor Bits 0-47 of the register are ignored. When the speci-
state, a special-operation exception is recognized. fied order is the set-architecture order, the CPU
address is ignored; all other CPUs in the configura-
The value to be loaded into the PSW is not checked tion are considered to be addressed.
for validity before loading. However, immediately after
loading, a specification exception is recognized, and The general register containing the 32-bit parameter
a program interruption occurs, if the contents of bit in bit positions 32-63 is R1 or R1+1, whichever is the
positions 0 and 2-4 of the PSW are not all zeros. In odd-numbered register. It depends on the order code
this case, the instruction is completed, and the whether a parameter is provided and for what pur-
instruction-length code is set to 2. The specification pose it is used.
exception, which is listed as a program exception for
this instruction, is described in “Early Exception Rec-
SIGNAL PROCESSOR
mats: it is not provided in the installation, it is not in the con-
figuration, it is in any of certain customer-engineer
General register designated by R1: test modes, or its power is off), condition code 3 is
set.
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
0 31 Resulting Condition Code:
Status
0 Order code accepted
32 63
1 Status stored
2 Busy
General register designated by R1 or R1 + 1, which- 3 Not operational
ever is the odd-numbered register:
Program Exceptions:
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
0 31 • Privileged operation
Parameter
32 63
Programming Notes:
gency-signal or external-call order, followed by control registers are stored in successive words
execution of the PURGE TLB instruction on the beginning at the second-operand address, and bits
addressed CPU, than by use of the set-prefix 0-31 of the registers are ignored. For STORE CON-
order. TROL (STCTG), bits 0-63 of the control registers are
stored in successive doublewords beginning at the
second-operand address.
STORE CLOCK COMPARATOR
The storage area where the contents of the control
STCKC D2(B2) [S] registers are placed starts at the location designated
'B207' B2 D2 by the second-operand address and continues
0 16 20 31 through as many storage words, for STCTL, or dou-
blewords, for STCTG, as the number of control regis-
ters specified. The contents of the control registers
The current value of the clock comparator is stored at are stored in ascending order of their register num-
the doubleword location designated by the second- bers, starting with control register R1 and continuing
operand address.
up to and including control register R3, with control
register 0 following control register 15. The contents
Zeros are provided for the rightmost bit positions of
of the control registers remain unchanged.
the clock comparator that are not compared with the
TOD clock.
The displacement for STCTL is treated as a 12-bit
unsigned binary integer. The displacement for
Special Conditions
STCTG is treated as a 20-bit signed binary integer.
The operand must be designated on a doubleword
Special Conditions
boundary; otherwise, a specification exception is rec-
ognized.
The second operand must be designated on a word
boundary for STCTL or on a doubleword boundary
Condition Code: The code remains unchanged.
for STCTG; otherwise, a specification exception is
recognized.
Program Exceptions:
Condition Code: The code remains unchanged.
• Access (store, operand 2)
• Privileged operation
Program Exceptions:
• Specification
• Access (store, operand 2)
STORE CONTROL • Privileged operation
• Specification
STCTL R1,R3,D2(B2) [RS-a]
'B6' R1 R3 B2 D2 STORE CPU ADDRESS
0 8 12 16 20 31
STAP D2(B2) [S]
STCTG R1,R3,D2(B2) [RSY-a] 'B212' B2 D2
0 16 20 31
'EB' R1 R3 B2 DL2 DH2 '25'
0 8 12 16 20 32 40 47
STORE CPU ID
of the CPU. Bit positions 0-7 and 49-63 contain
The operand must be designated on a halfword zeros.
boundary; otherwise, a specification exception is rec-
ognized. Special Conditions
Condition Code: The code remains unchanged. The operand must be designated on a doubleword
boundary; otherwise, a specification exception is rec-
Program Exceptions: ognized.
mat:
Program Exceptions:
• “Annnnn” in the basic mode, or
• LPnnnn” in the LPAR (logically-partitioned) • Access (store, operand 2)
mode, when the format bit is zero, or • Privileged operation
• PPnnnn” in the LPAR mode, when the format • Specification
bit is one.
6. The format bit is always stored as a zero in the The second-operand address is ignored but should
basic mode. be zero to permit possible future extensions.
7. Model z800 and z900 machines always store the
format bit as a zero. Key-controlled and low-address protection do not
apply.
8. When STORE CPU ID is executed in a virtual
machine, the VM operating system replaces bits Condition Code: The code remains unchanged.
0-7 of the information stored with FF hex.
Program Exceptions:
Special Conditions
The contents of bit positions 33-50 of the prefix regis-
The operand must be designated on a doubleword ter are stored in bit positions 1-18 of the word loca-
boundary; otherwise, a specification exception is rec- tion designated by the second-operand address, and
ognized. zeros are stored in bit positions 0 and 19-31 of the
word.
Special Conditions
STORE REAL ADDRESS
The first operand must be designated on a double-
STRAG D1(B1),D2(B2) [SSE] word boundary; otherwise, a specification exception
'E502' B1 D1 B2 D2 is recognized.
0 16 20 32 36 47
The operation is suppressed on all addressing
exceptions.
The 64-bit real address corresponding to the second-
operand virtual address is stored in the doubleword Condition Code: The code remains unchanged.
at the location designated by the first-operand
address. Program Exceptions:
The virtual address specified by the B2 and D2 fields • Access (fetch, operand 2, except for an address-
is translated by means of the dynamic-address-trans- ing or protection exception for the designated
lation facility, regardless of whether DAT is on or off. location; store, operand 1)
• Privileged operation
DAT is performed by using an address-space-control • Specification
element that depends on the current value of the
address-space-control bits, bits 16 and 17 of the Programming Note: STORE REAL ADDRESS is
PSW, as shown in the following table: contrasted to LOAD REAL ADDRESS as follows:
PSW
• In the 24-bit or 31-bit addressing mode, LOAD
Bits 16 Address-Space-Control Element
REAL ADDRESS (LRA) loads bits 33-63 of the
and 17 Used by DAT
real address if bits 0-32 of the address are all
00 Contents of control register 1 zeros or recognizes a special-operation excep-
10 Contents of control register 7 tion if bits 0-32 are not all zeros. LRA in the 64-bit
01 The address-space-control element addressing mode, and LOAD REAL ADDRESS
obtained by applying the access-register- (LRAG) in any addressing mode, loads bits 0-63
translation (ART) process to the access of the real address. STORE REAL ADDRESS
register designated by the B2 field stores bits 0-63 of the real address in any
11 Contents of control register 13 addressing mode.
– Ignored.
Figure 10-69. Valid Function-Code, Selector-1, and
Selector-2 Combinations for STORE SYSTEM
INFORMATION
20
selector-2 combination is invalid (is other than as
Sequence Code
shown in Figure 10-69), or if it is valid but the
requested information is not available because the
specified level does not implement or does not fully 24 Plant of Manufacture
implement the instruction or because a necessary 25
part of the level is uninstalled or not initialized, and
Model
provided that an exception is not recognized (see
“Special Conditions”), the condition code is set to 3.
When the function code is nonzero, the combination 29
is valid, the requested information is available, and Model-Permanent-Capacity Identifier
there is no exception, the requested information is
stored in a system-information block (SYSIB) at the
second-operand address. 33
Model-Temporary-Capacity Identifier
Some or all of the SYSIB may be fetched before it is
stored.
37 Model-Capacity Rating
SYSIB 1.1.1 has the following format: Word 0, Byte 0: Byte 0 of word 0 contains the fol-
lowing bit definitions:
SYSIB 1.1.1
0 P Reserved T IBM CCR CAI
Bit Meaning
1 0 When bit 0 of byte 0 (P) is one, the type-percent-
Reserved
age bytes, located in words 40-41, are valid.
When P is zero, the bytes are stored as zeros,
8
but have no meaning.
Manufacturer
1-6 Bits 1-6 of byte 0 are reserved and stored as
zeros.
12 Type
13 7 Bit 7 of byte 0 (T), when one, indicates that the
Reserved condition represented by the CCR and CAI fields
is relatively transient.
Capacity-Change Reason (CCR): When the CAI Primary CPUs and all secondary-type CPUs are sim-
byte is nonzero, the content of byte 2 of word 0 is an ilarly affected.
8-bit unsigned integer whose value indicates one of
the following reasons which is associated with the The model-capacity rating is not affected. A change
present values contained in SYSIB 1.1.1. in the CAI may also reflect a change in CPU-capabil-
ity fields of SYSIB 1.2.2.
CCR Capacity-Change Reason
Manufacturer: Words 8-11 contain the 16-charac-
0 Machine is running at nominal capacity. ter (0-9 or uppercase A-Z) EBCDIC name of the
1 The capacity change is due solely to the set- manufacturer of the configuration. The name is left
ting of a manual control, such as intentional justified with trailing blanks if necessary.
power-save.
Type: Word 12 contains the four-character (0-9)
2 The capacity change is due to a machine- EBCDIC type number of the configuration. (This is
exception condition, such as detection of called the machine-type number in the definition of
overheating. STORE CPU ID.)
3 The capacity change is due to a non-excep- Model-Capacity Identifier (C): Words 16-19 con-
tion machine condition, such as concurrent tain the 16-character (0-9 or uppercase A-Z)
service. EBCDIC model-capacity identifier of the configura-
4 The capacity change is due to an exception tion. The model-capacity identifier is left justified with
condition external to the machine, such as trailing blanks if necessary.
detection of supplied power or cooling falling
outside required tolerances. Sequence Code: Words 20-23 contain the
16-character (0-9 or uppercase A-Z) EBCDIC
5-255 Reserved. sequence code of the configuration. The sequence
code is right justified with leading EBCDIC zeros if
When the CAI byte is zero, the CCR field is unde- necessary.
fined, and stored as zero.
Plant of Manufacture: Word 24 contains the four-
When multiple capacity-change reasons exist, CCR character (0-9 or uppercase A-Z) EBCDIC code that
is set according to the following priority: identifies the plant of manufacture for the configura-
tion. The code is left justified with trailing blanks if
1a. Machine-exception condition, CCR=2. necessary.
1b. External-exception condition, CCR=4. Model: When word 25 is not binary zeros, words
25-28 contain the 16-character (0-9 or uppercase A-
2. Non-exception machine condition, CCR=3. Z) EBCDIC model identification of the configuration.
The model identification is left justified with trailing
3. Manual control, CCR=1. blanks if necessary. (This is called the model number
in programming note 4 on page 10-127 of STORE
Capacity-Adjustment Indication (CAI): Byte 3 of CPU ID.) When word 25 is binary zeros, the contents
word 0, when nonzero, is an 8-bit unsigned integer of words 16-19 represent both the model-capacity
whose value is in the range 1-100 and represents the identifier and the model.
aggregate position of model-dependent controls.
Temporary capacity changes that affect machine per- Model-Permanent-Capacity Identifier (P): When
formance (for example, those due to Capacity non-zero, words 29-32 contain the 16-character (0-9
Backup, CBU, On/Off Capacity on Demand, OOCoD, or uppercase A-Z) EBCDIC model-permanent-
and Capacity Planned Event, CPE) are not included. capacity identifier of the configuration. The identifier
When zero, the indication is not reported. When in is left justified with trailing blanks if necessary.
the range 1-99, some amount of reduction is indi-
non-zero, words 33-36 contain the 16-character (0-9 formal description of the algorithm used to generate
or uppercase A-Z) EBCDIC model-temporary-capac- this integer. The NPR value equals the PR value
ity identifier of the configuration. The identifier is left when the CAI byte contains a value of 100. When the
justified with trailing blanks if necessary. CAI byte is less than 100, the PR value is less than
the NPR value.
Model-Capacity Rating (CR): When non-zero, word
37 contains a 32-bit unsigned integer whose value is Nominal Model-Temporary-Capacity Rating
associated with the model capacity as identified by (NTR): When non-zero, word 44 contains a 32-bit
the model-capacity identifier. There is no formal unsigned integer whose value is associated with the
description of the algorithm used to generate this nominal model-temporary capacity as identified by
integer. the model-temporary-capacity identifier. There is no
formal description of the algorithm used to generate
Model-Permanent-Capacity Rating (PR): When this integer. The NTR value equals the TR value
non-zero, word 38 contains a 32-bit unsigned integer when the CAI byte contains a value of 100. When the
whose value is associated with the model-permanent CAI byte is less than 100, the TR value is less than
capacity as identified by the model-permanent- the NTR value.
capacity identifier. There is no formal description of
the algorithm used to generate this integer. Programming Notes:
Model-Temporary-Capacity Rating (TR): When 1. The fields of the SYSIB 1.1.1 are similar to those
non-zero, word 39 contains a 32-bit unsigned integer of the node descriptor described in the publica-
whose value is associated with the model-temporary tion Common I/O-Device Commands and Self
capacity as identified by the model-temporary-capac- Description, SA22-7204. However, the contents
ity identifier. There is no formal description of the of the SYSIB fields may not be identical to the
algorithm used to generate this integer. contents of the corresponding node-descriptor
fields because the SYSIB fields:
Type N Pctg. Each of the byte fields in words 40-41
that is designated as a type-N percentage contains • Allow more characters.
an 8-bit unsigned binary integer whose value is in the • Are more flexible regarding the type of char-
range 0-100 and represents a percentage. When acters allowed.
non-zero, the percentage may be used to affect the
use and allowed utilization of the secondary-CPUs • Provide information that is justified differently
whose CPU type corresponds to the particular byte. within the field.
When a byte in this range contains a value of zero,
use rules of the corresponding secondary-CPU type • May not use the same method to determine
are not overridden. The reserved bytes in word 41 the contents of fields such as the sequence-
are reserved for the potential addition of new second- code field.
ary CPU types. 2. The model field in a node descriptor corresponds
to the content of the STSI model field and not the
Nominal Model-Capacity Rating (NCR): When STSI model-capacity-identifier field.
non-zero, word 42 contains a 32-bit unsigned integer
whose value is associated with the nominal model 3. The model field specifies the model of the
capacity as identified by the model-capacity identifier. machine (i.e., the physical model); the model-
There is no formal description of the algorithm used capacity identifier field specifies a token that may
to generate this integer. The NCR value equals the be used to locate a statement of capacity or per-
CR value when the CAI byte contains a value of 100. formance in the System Library publication for
When the CAI byte is less than 100, the CR value is the model.
less than the NCR value.
4. Each of the three model-capacity-identifier fields
Nominal Model-Permanent-Capacity Rating specifies a token that may be used to locate a
(NPR): When non-zero, word 43 contains a 32-bit statement of capacity or performance in the Sys-
unsigned integer whose value is associated with the tem Library publication for the model.
nominal model-permanent capacity as identified by
CPU Capability: Word 8 specifies the capability of Multiprocessing CPU-Capability Adjustment Fac-
one of the CPUs in the configuration. tors: Beginning with bytes 0 and 1 of word 11, the
SYSIB contains a series of contiguous two-byte
If bits 0-8 of word 8 are zero, the word contains a fields, each containing a 16-bit unsigned binary inte-
32-bit unsigned binary integer (I) in the range ger used to form an adjustment factor (fraction) for
1 [ I < 223. If bits 0-8 of word 8 are nonzero, the word the value contained in the CPU-capability field. Such
contains a 32-bit binary floating point short-format a fraction is developed by using the value (V) of the
number instead of an unsigned binary integer. first two-byte field according to one of the following
methods:
Regardless of encoding, the value represents the
capability of one of the CPUs in the configuration, • If V is in the range 0 < V [ 100, a denominator of
and a lower value indicates a proportionally higher 100 is indicated which produces a fraction of
CPU capability. Beyond that, there is no formal V/100.
description of the algorithm used to generate this
value. The value is used as an indication of the capa- • If V is in the range 100 < V [ 255, a denominator
bility of the CPU relative to the capability of other of 255 is indicated which produces a fraction of
CPU models. V/255.
configured state. Each successive adjustment-factor tor fields correspond to configurations with increasing
field corresponds to a configuration with a number of numbers of CPUs in the configured state. The first
CPUs in the configured state that is one more than alternate-adjustment-factor field corresponds to a
that for the preceding field. configuration with two CPUs in the configured state.
Each successive alternate-adjustment-factor field
Alternate CPU Capability: When the format field corresponds to a configuration with a number of
has a value of one, if bits 0-8 of word N are zero, the CPUs in the configured state that is one more than
word contains a 32-bit unsigned binary integer (I) in that for the preceding field.
the range 0[I<223 that specifies the announced capa-
bility of one of the CPUs in the configuration. If bits SYSIB 2.2.1 (Logical-Partition CPU)
0-8 of word N are nonzero, the word contains a 32-bit
binary floating point short-format number instead of a SYSIB 2.2.1 has the following format:
32-bit unsigned binary integer.
SYSIB 2.2.1
Regardless of encoding, a lower value indicates a 0
proportionally higher CPU capacity. Beyond that,
Reserved
there is no formal description of the algorithm used to
generate this value. The value is used as an indica-
tion of the announced capability of the CPU relative 20
to the announced capability of other CPU models. Sequence Code
• If V is in the range 0 < V [ 100, a denominator of Sequence Code: Words 20-23 contain the
100 is indicated which produces a fraction of 16-character (0-9 or uppercase A-Z) EBCDIC
V/100. sequence code of the configuration. The code is right
justified with leading EBCDIC zeros if necessary.
• If V is in the range 100 < V [ 255, a denominator
of 255 is indicated which produces a fraction of Plant of Manufacture: Word 24 contains the four-
V/255. character (0-9 or uppercase A-Z) EBCDIC code that
identifies the plant of manufacture for the configura-
• If V is in the range 255 < V [ 65,535, a denomi- tion. The code is left justified with trailing blanks if
nator of 65,536 is indicated which produces a necessary.
fraction of V/65,536.
Logical-CPU ID: Bytes 0 and 1 of word 25 contain
Thus, the fraction represented by each two-byte field a 16-bit unsigned binary integer that can be used in
is then developed by dividing the contents of a two- conjunction with the logical-CPU address to distin-
byte field by the indicated denominator. guish the logical CPU from the other logical CPUs
provided by the same LPAR hypervisor.
The number of alternate-adjustment-factor fields is
one less than the number of CPUs specified in the
8 LPAR Number Reserved LCPUC 1 Shared: When one, bit 1 indicates that one or
9 Total LCPU Count Configured LCPU Count more of the logical CPUs for this level-2 configu-
ration are provided using level-1 CPUs that can
10 Standby LCPU Count Reserved LCPU Count
be used to provide logical CPUs for other level-2
11 configurations. The number of logical CPUs that
Logical-Partition Name
12 are provided using shared level-1 CPUs is speci-
13 Logical-Partition CAF fied by the shared-LCPU-count value in bytes 2
and 3 of word 18.
14
Model-Dependent Data
15 When zero, bit 1 indicates that none of the logical
16 CPUs for this level-2 configuration are provided
Reserved using shared level-1 CPUs.
17
18 Dedicated LCPU Count Shared LCPU Count 2 Utilization Limit: When one, bit 2 indicates that
the amount of use of the level-1 CPUs that are
19
used to provide the logical CPUs for this level-2
Reserved configuration is limited.
1023
0 16 24 31
When zero, bit 2 indicates that the amount of use
of the level-1 CPUs that are used to provide the
logical CPUs for this level-2 configuration is
Reserved: The contents of words 0-7, byte 2 of unlimited.
word 8, words 16-17, and words 19-63 are reserved
and are stored as zeros. The contents of words 3-7 Reserved.
64-1023 are reserved and may be stored as zeros or
may remain unchanged.
contain a 16-bit unsigned binary integer that speci- word 18 contain a 16-bit unsigned binary integer that
fies the total number of logical CPUs that are pro- specifies the number of configured-state logical
vided for this level-2 configuration. This number CPUs for this level-2 configuration that are provided
includes all of the logical CPUs that are in the config- using dedicated level-1 CPUs. (See the description
ured state, the standby state, or the reserved state. of bit 0 of the logical-CPU-characteristics field.)
Configured Logical-CPU Count: Bytes 2 and 3 of Shared Logical-CPU Count: Bytes 2 and 3 of
word 9 contain a 16-bit unsigned binary integer that word 18 contain a 16-bit unsigned binary integer that
specifies the number of logical CPUs for this level-2 specifies the number of configured-state logical
configuration that are in the configured state. CPUs for this level-2 configuration that are provided
using shared level-1 CPUs. (See the description of
A logical CPU is in the configured state when it is in bit 1 of the logical-CPU-characteristics field.)
the level-2 configuration and is available to be used
to execute programs. SYSIB 3.2.2 (Virtual-Machine CPUs)
Standby Logical-CPU Count: Bytes 0 and 1 of SYSIB 3.2.2 has the following format:
word 10 contain a 16-bit unsigned binary integer that
specifies the number of logical CPUs for this level-2 SYSIB 3.2.2
configuration that are in the standby state. 0
Reserved
A logical CPU is in the standby state when it is in the
level-2 configuration, is not available to be used to
execute programs, and can be made available by 7 Reserved DBCT
issuing instructions to place it in the configured state. 8
Virtual-Machine Description Block
Reserved Logical-CPU Count: Bytes 2 and 3 of
word 10 contain a 16-bit unsigned binary integer that
specifies the number of CPUs for this level-2 configu- 24
ration that are in the reserved state. §
Logical-Partition Name: Words 11-12 contain the Reserved: The contents of words 0-6, bits 0-27 of
8-character EBCDIC name of this level-2 configura- word 7, and words 136-1023 are reserved and are
tion. The name is left justified with trailing blanks if stored as zeros.
necessary.
Description-Block Count (DBCT): Bits 28-31 of
Logical-Partition Capability Adjustment Factor word 7 contain a four-bit unsigned binary integer that
(CAF): Word 13 contains a 32-bit unsigned binary specifies the number (up to eight) of virtual-machine
integer, called an adjustment factor, with a value of description blocks that are stored in the SYSIB
1000 or less. The adjustment factor specifies the beginning at word 8.
amount of the underlying level-1-configuration capa-
bility that is allowed to be used for this level-2 config- Virtual-Machine Description Blocks: Words
uration by the LPAR hypervisor. The fraction of 8-135 contain from one to eight 64-byte virtual-
level-1-configuration capability is determined by machine description blocks, depending on the num-
dividing the CAF value by 1000. ber of nested level-3 configurations, if any, and their
processing characteristics.
ration that are in the reserved state. response is limited. STSI completes with condition
code 3 for the following cases:
A logical CPU is in the reserved state when it is in the
level-3 configuration, is not available to be used to 1. If the maximum-MNest facility is installed and
execute programs, and cannot be made available by selector 2 exceeds the nonzero model-depen-
issuing instructions to place it in the configured state. dent maximum-selector-2 value.
(It may be possible to place the logical CPU in the
standby or configured state through manual actions.) 2. If the maximum-MNest facility is not installed and
selector 2 is not specified as two.
Virtual-Machine Name: Words 3-4 contain the
eight-character EBCDIC name of this level-3 configu- Reserved: The contents of bytes 0-1 of word 0,
ration. The name is left justified with trailing blanks if byte 2 of word 2, and word 3 are reserved and are
necessary. stored as zeros. The contents of words N-1023 are
reserved and may be stored as zeros or may remain
Virtual-Machine Capability Adjustment Factor unchanged.
(CAF): Word 5 contains a 32-bit unsigned binary
integer, called an adjustment factor, with a value of Length: Bytes 2-3 of word 0 contain a 16-bit
1000 or less. The adjustment factor specifies the unsigned binary integer whose value is the count of
amount of the underlying level-1-, level-2-, or bytes of the entire SYSIB 15.1.2. The length of just
level-3-configuration capability that is allowed to be the topology list is determined by subtracting 16 from
used for this level-3 configuration by the virtual- the length value in bytes 2-3 of word 0. N in
machine control program. The fraction of the underly- Figure 10-70 is determined by evaluating the formula
ing capability is determined by dividing the CAF N=Length/4.
value by 1000.
Mag1-6: Word 1 and bytes 0-1 of word 2 constitute
Control-Program Identifier: Words 6-9 contain six one-byte fields where the content of each byte
the 16-character EBCDIC identifier of the virtual- indicates the maximum number of container-type
machine control program that provides this level-3 topology-list entries (TLE) or CPU-type TLEs at the
configuration. This identifier may include qualifiers corresponding nesting level. CPU-type TLEs are
such as version number and release level. The iden- always found only at the Mag1 level. Additionally, the
tifier is left justified with trailing blanks if necessary. Mag1 value also specifies the maximum number of
CPUs that may be represented by a container-type
SYSIB 15.1.2 - 15.1.6 (Configuration Topology) TLE of the Mag2 level. When the value of the nesting
level is greater than one, containing nesting levels
SYSIBs 15.1.2 through 15.1.6 each have the follow- above the Mag1 level are occupied only by container-
ing format: type TLEs. A dynamic change to the topology may
alter the number of TLEs and the number of CPUs at
SYSIB 15.1.2 - 15.1.6 the Mag1 level, but the limits represented by the val-
ues of the Mag1-6 fields do not change within a
0 Reserved Length
model family of machines.
1 Mag6 Mag5 Mag4 Mag3
2 Mag2 Mag1 Reserved MNest The topology is a structured list of entries where an
3 Reserved entry defines one or more CPUs or else is involved
with the nesting structure. The following illustrates
4
the meaning of the magnitude fields:
§ Topology List
N-1
• When all CPUs of the machine are peers and no
N containment organization exists, other than the
§ Reserved
entirety of the central-processing complex itself,
1023
the value of the nesting level is 1, Mag1 is the
0 8 16 24 31
only non-zero magnitude field, and the number of
CPU-type TLEs stored does not exceed the
Mag1 value.
When the maximum-MNest facility is installed, the Sibling TLEs have the same value of nesting level
maximum possible nesting is indicated by other which is equivalent to either the value of the nesting
means and the MNest value in byte 3 of word 2 level minus one of the immediate parent TLE, or the
reflects both the requested selector-2 value and the value of MNest minus one, because the immediate
number of non-zero magnitude values beginning with parent is the topology list rather than a TLE.
the magnitude field at byte 1 of word 2 (Mag1).
Reserved, 0: For a container-type TLE, bytes 1-3
Topology List: Words of Figure 10-70 in the range of word 0 and bytes 0-2 of word 1 are reserved and
4 through N-1 specify a list of one or more topology- stored as zeros. For a CPU-type TLE, bytes 1-3 of
list entries (TLE). Each TLE is an eight-byte or six- word 0 and bits 0-4 of word 1 are reserved and
teen-byte field; thus N is an even number of words, stored as zeros.
and a corollary is that a TLE always starts on a dou-
bleword boundary. Container ID: Byte 3 of word 1 of a container-type
TLE specifies an 8-bit unsigned non-zero binary inte-
Topology-List Entries: The first TLE in the topol- ger whose value is the identifier of the container. The
ogy list begins at a nesting level equal to MNest-1. container ID for a TLE is unique within the same par-
The entire topology list represents the configuration ent container.
of the issuer of the STSI instruction specifying SYSIB
15.1.2; no outermost container TLE entry is used as Dedicated (D): Bit 5 of word 1 of a CPU-type TLE,
it would be redundant with the entire list, and the when one, indicates that the one or more CPUs rep-
entire configuration. Therefore, the highest nesting resented by the TLE are dedicated. When D is zero,
level may have more than a single peer container. the one or more CPUs of the TLE are not dedicated.
TLE specify the polarization value and, when polar- and whose presence is represented by the value of
ization is vertical, the degree of vertical polarization bit position 0 in the CPU mask. A CPU-address origin
also called entitlement (high, medium, low) of the is evenly divisible by 64. The value of a CPU-address
corresponding CPU(s) represented by the TLE. The origin is the same as that stored by the STORE CPU
following values are used: ADDRESS (STAP) instruction when executed on the
CPU represented by bit position 0 in the CPU mask.
PP Meaning
0 The one or more CPUs represented by the TLE are CPU Mask: Words 2-3 of a CPU-type TLE specify
horizontally polarized. a 64-bit mask where each bit position represents a
CPU. The value of the CPU-address origin field plus
1 The one or more CPUs represented by the TLE are
vertically polarized. Entitlement is low. a bit position in the CPU mask equals the CPU
address for the corresponding CPU.
2 The one or more CPUs represented by the TLE are
vertically polarized. Entitlement is medium.
When a CPU mask bit is zero, the corresponding
3 The one or more CPUs represented by the TLE are CPU is not represented by the TLE. The CPU is
vertically polarized. Entitlement is high. either not in the configuration or else must be repre-
sented by another CPU-type TLE.
Polarization is only significant in a logical and virtual
multiprocessing configuration that uses shared host When a CPU mask bit is one, the corresponding
processors and addresses how the resource CPU has the modifier-attribute values specified by
assigned to a configuration is applied across the the TLE, is in the topology of the configuration, and is
CPUs of the configuration. When horizontal polariza- not present in any other TLE of the topology.
tion is in effect, each CPU of a configuration is guar-
anteed approximately the same amount of resource. Thus, for example, if the CPU-address origin is a
When vertical polarization is in effect, CPUs of a con- value of 64, and bit position 15 of the CPU mask is
figuration are classified into three levels of resource one, CPU 79 is in the configuration and has the CPU
entitlement: high, medium, and low. type, polarization, entitlement, and dedication as
specified by the TLE.
Both subsystem reset and successful execution of
the SIGP set-architecture order specifying ESA/390 TLE Ordering: The modifier attributes that apply to
mode place a configuration and all of its CPUs into a CPU-type TLE are CPU type, polarization, entitle-
horizontal polarization. The CPUs immediately ment, and dedication. Polarization and entitlement
affected are those that are in the configured state. (for vertical polarization) are taken as a single
When a CPU in the standby state is configured, it attribute, albeit with four possible values (horizontal,
acquires the current polarization of the configuration vertical-high, vertical-medium, and vertical-low).
and causes a topology change of that configuration
to be recognized. A single CPU TLE is sufficient to represent as many
as 64 CPUs that all have the same modifier-attribute
A dedicated CPU is either horizontally or vertically values.
polarized. When a dedicated CPU is vertically polar-
ized, entitlement is always high. Thus, when D is one, When more than 64 CPUs exist, or the entire range
PP is either 00 binary or 11 binary. of CPU addresses are not covered by a single CPU-
address origin, and the modifier attributes are con-
CPU Type: Byte 1 of word 1 of a CPU-type TLE stant, a separate sibling CPU TLE is stored for each
specifies an 8-bit unsigned binary integer whose CPU-address origin, as necessary, in ascending
value is the CPU type of the one or more CPUs rep- order of CPU-address origin. Each such TLE stored
resented by the TLE. The CPU-type value specifies has at least one CPU represented. The collection of
either a primary-CPU type or any one of the possible one or more such CPU TLEs is called a CPU-TLE
secondary-CPU types. set.
CPU-Address Origin: Bytes 2-3 of word 1 of a When multiple CPU types exist, a separate CPU-TLE
CPU-type TLE specify a 16-bit unsigned binary inte- set is stored for each, in ascending order of CPU
ger whose value is the CPU address of the first CPU type.
When both dedicated and not-dedicated CPUs exist, 9. CPU-TLE set of highest CPU-type value, vertical
a separate CPU-TLE set is stored for each, dedi- medium, not-dedicated
cated appearing before not-dedicated.
10. CPU-TLE set of highest CPU-type value, vertical
All TLEs are ordered assuming a depth-first traversal low, not-dedicated
where the sort order from major to minor is as fol- 11. CPU-TLE set of highest CPU-type value, hori-
lows: zontal, dedicated
The ordering by CPU-address origin and modifier 5. The content of a TLE is defined as follows:
attributes of sibling CPU TLEs within a parent con-
tainer is done according to the following list, which • If a TLE is a container-type TLE, the content
proceeds from highest to lowest. is a list that immediately follows the parent
TLE, comprised of one or more child TLEs,
1. CPU-TLE set of lowest CPU-type value, vertical and each child TLE has a nesting level of
high, dedicated one less than the nesting level of the parent
TLE or topology-list end.
2. CPU-TLE set of lowest CPU-type value, vertical
high, not-dedicated • If a TLE is a CPU-type TLE, the content is
one or more CPUs, as identified by the other
3. CPU-TLE set of lowest CPU-type value, vertical fields of a CPU TLE.
medium, not-dedicated
6. When the first TLE at a nesting level is a CPU
4. CPU-TLE set of lowest CPU-type value, vertical entry, the maximum nesting level 0 has been
low, not-dedicated reached.
resulted in a non-uniform memory access (NUMA) ment of a dedicated CPU is defined to be high.
behavior, sometimes also called “lumpiness”. The
purpose of the SYSIB 15.1.2 and the PERFORM • Medium entitlement guarantees an unspecified
TOPOLOGY FUNCTION (PTF) instruction is to pro- amount of host CPU resource (one or more host
vide additional machine topology awareness to the CPUs) being assigned to a logical/virtual CPU,
program so that certain optimizations can be per- and any remaining capacity of the host CPU is
formed to improve cache-hit ratios and thereby considered to be slack that may be assigned
improve overall performance. elsewhere. The best case for the available slack
would be to assign it as local slack if that is pos-
The amount of host-CPU resource assigned to a sible. A less-beneficial result occurs if that avail-
multiprocessing (MP) guest configuration has gener- able slack is assigned as remote slack. (See
ally been spread evenly across the number of config- “CPU Slack” on page 10-147 for descriptions of
ured guest CPUs. Such an even spread implies that the two slack terms.) It is also the case that the
no particular guest CPU or CPUs are entitled to any resource percentage assigned to a logical CPU
extra host-CPU provisioning than any other, arbi- of medium entitlement is a much softer approxi-
trarily-determined guest CPUs. This condition of the mation as compared to the 100% approximation
guest configuration, affecting all CPUs of the configu- of a high-entitlement setting.
ration, is called horizontal polarization. • Low entitlement guarantees approximately 0% of
a host CPU being assigned to a logical/virtual
Under horizontal polarization, assignment of a host CPU. However, if slack is available, such a logi-
CPU to a guest CPU is approximately the same cal/virtual CPU may still receive some CPU
amount of provisioning for each guest CPU. When resource.
the provisioning is not dedicated, the same host
CPUs provisioning the guest CPUs also may be used A model of nested containers using polarization is
to provision guest CPUs of another guest, or even intended to provide a level of intelligence about the
other guest CPUs of the same guest configuration. machine's nodal structure as it applies to the
When the other guest configuration is a different logi- requesting configuration, so that, generally, clusters
cal partition, a host CPU, when active in each parti- of host CPUs can be assigned to clusters of guest
tion, typically must access main storage more CPUs, thereby improving as much as possible the
because the cache-hit ratio is reduced by having to sharing of storage and the minimizing of different
share the caches across multiple relocation zones. If configurations essentially colliding on the same host
host-CPU provisioning can alter the balance such CPUs.
that some host CPUs are mostly, or even exclusively,
assigned to a given guest configuration, and that Polarization and entitlement indicate the relationship
becomes the normal behavior, then cache-hit ratios of physical CPUs to logical CPUs or logical CPUs to
improve, as does performance. Such an uneven virtual CPUs in a guest configuration, and how the
spread implies that one or more guest CPUs are enti- capacity assigned to the guest configuration is
tled to extra host-CPU provisioning versus other, apportioned across the CPUs that comprise the con-
arbitrarily-determined guest CPUs that are entitled to figuration. Historically, a guest configuration has
less host-CPU provisioning. This condition of the been horizontally polarized. For however many guest
guest configuration, affecting all CPUs of the configu- CPUs were defined to the configuration, the host-
ration, is called vertical polarization. CPU resource assigned was spread evenly across all
of the guest CPUs in an equitable, non-entitled man-
The architecture categorizes vertical polarization into ner. It can be said that the weight of a single logical
three levels of entitlement of provisioning, high, CPU in a logical partition when horizontal polariza-
medium, and low: tion is in effect is approximately equal to the total
configuration weight divided by the number of CPUs.
• High entitlement guarantees approximately However, with the introduction of the 2097 and family
100% of a host CPU being assigned to a logi- models, it becomes imperative to be able to spread
cal/virtual CPU, and the affinity is maintained