FACULTY OF MANUFACTURING AND

MECHATRONICS TECHNOLOGY ENGINEERING

ELECTRONICS IN MECHATRONIC SYSTEM

BHM 4402 SEM 2 19/20

TITLE:
ASSIGNMENT 3: UP/DOWN COUNTER BY USING THREE
PROCESS MODEL

LECTURER:
MR. ZULKIFLI MD YUSOF

NAME ID
NORLIA EMAH ZUBAIDAH BINTI MOHAMAD HA16025
NORUDIN
UP/DOWN COUNTER BY USING THREE (3) PROCESS MODEL

In this assignment, the students are require to implement three (3) process model in
up/down counter. Therefore, we are require to construct the finite state machine based on the
sequence of our identification card number. The identification card number must be converted
into hexadecimal as shown in Figure 1. Then the hexadecimal identification number is convert
into binary code so that it is easier to implement the finite state machine into the VHDL
program.

Based on Figure 2, the state or sequence of the system will change based on the input
of ‘Up’. When ‘Up’ is 1 or high, the state will count up. On the other hand, when ‘Up’ is 0 or
low, the state will count down or move in reverse direction.

960225-13-5052 Decimal

9602A5-13-BCDE Hexadecimal

Figure 1 The conversion of the Identification Card Number

1. Finite State Machine

The finite state machine is as shown below:

Figure 2 Finite State Machine

 2. VHDL Program

The up/down counter is design by using the three (3) process modelling approach. Moore
machines are chosen as counter because the counter’s output only depend on the current state.
The Reset is active low so when the Reset is 0 or low, the system will be force to start from
nine (9) instead of zero (0). This is to ensure that the sequence of the system is similar with the
sequence of the finite state machine.

Below is the VHDL program for the up/down counter by using three (3) process model:
3. RTL Simulation

current_s tate
C9 WideOr12
C6

C0
C2

Clock clk CA

Res et reset C5

Up Up C1

C3 WideOr13
CC

CD
CE

WideOr14
CNT[3..0]

WideOr15

Figure 3 RTL Simulation of the program

 4. Result
Initially the waveform simulates the output in a binary signal or logic signal, which
represented two (2) states of a Boolean value such as 0 and 1. Then the binary outputs are
converted to the hexadecimal output so that we can compare the result easily. This waveform
is compared with the finite state diagram to ensure the sequence of the state is similar and
correct. Below shows the simulation waveform:

Figure 4 Simulation waveform

Based on the waveform, when the input of the ‘Up’ is 0 or low, the sequence of the
identification card number is in reverse or anti-clockwise. The counter become a down counter,
as the state is count in down manner. When the input of the ‘Up’ is 1 or high, the sequence of
the identification card number is in clockwise. The counter become an up counter due to the
state is count in up manner. Therefore, the result of the output will be similar with sequence of
the finite state machine due to the value of the ‘Up’ input.
CONCLUSION

In summary, there are no fix method or way to program a counter based on our finite
state machine. In our previous assignment, we need to construct K-map to obtain the simplified
Boolean equation for the logic gates circuit. Then link the Boolean equation with the T flip-
flops so that we can produce the sequence of the output that is similar to the sequence of the
finite state machine. However, the three (3) process model method is much simpler than the
method that we used in the previous assignment as we are not require to construct the K-map.
We can easily get the same output sequence by assigning the current state and the next state.
Moreover, we can reuse the state memory process for other finite state machines.

REFERENCES

[1] Brock J.LaMeres (2017), Chapter 9 : Behavioral Modeling of Sequential Circuit In

Introduction to Logic CircuitS and Logic Design with VHDL, Page: 313-325.