High-Efficiency Inverter with H6-Type
Configuration for Photovoltaic Non-Isolated AC
Module Applications
Wensong Yu, Jih-Sheng Lai, Hao Qian, and Chris
Hutchens
Bradley Department of Electrical and Computer
Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA, USA
wensong@vt.edu, jslai@vt.edu, hqian@vt.edu,
Hutchens@vt.edu
Abstract—A novel, high-efficiency inverter using MOSFETs for
all active switches is presented for photovoltaic, non-isolated, ac
module applications. The proposed H6-type configuration
features high efficiency over a wide load range, low ground
leakage current, no need for split capacitors, and low output ac-
current distortion. The detailed power stage operating
principles, PWM scheme, and novel bootstrap power supply for
the proposed inverter are described. Experimental results of a
300 W hardware prototype show that not only are MOSFET
body diode reverse-recovery and ground leakage current issues
alleviated in the proposed inverter, but also that 98.3%
maximum efficiency and 98.1% European Union efficiency are
achieved.
I. INTRODUCTION
Photovoltaic (PV) ac modules may become a trend for
future PV systems because of their greater flexibility in
distributed system expansion, easier installation due to their
“plug and play” nature, lower manufacturing cost from
modular and scalable production, and higher system-level
energy harnessing capabilities under shaded or PV
manufacturing mismatch conditions as compared to the single-
or multi- string inverters [1-4]. A number of inverter
topologies for PV ac module applications have been reported
so far with respect to the number of power stages, location of
power-decoupling capacitors, use of transformers, and types
of grid interface [5-15]. Unfortunately, these solutions suffer
from one or more of the following major drawbacks: (1) the
limited-lifetime issue of electrolytic capacitors for power
decoupling [5-9]; (2) limited input voltage range for the
available panels in the market [10-12]; (3) high ground
leakage current when the unipolar pulse-width-modulation
(PWM) scheme is used in a transformer-less PV system [13];
(4) low system efficiency if an additional high-frequency
bidirectional converter is employed [14-16]; and (5) increased
cost and complexity of the circuit if energy in the transformer
leakage inductance is recycled by either an active snubber or
soft-switching circuit [17-19].
Since galvanic insulation in an ac module for PV
application is not required by code, a non-isolated ac module
978-1-4244-4783-1/10/$25.00 ©2010 IEEE 1056
Jianhui Zhang, Gianpaolo Lisi, Ali Djabbari, Greg
Smith, and Tim Hegarty
National Semiconductor Corporation
Santa Clara, CA, USA
Jianhui.Zhang@nsc.com, Gianpaolo.Lisi@nsc.com,
Ali.Djabbari@nsc.com,
Greg.Smith@nsc.com,Tim.Hegarty@nsc.com
combining a non-isolated high step-up converter and a high-
efficiency inverter with H6-type configuration, as shown in
Fig. 1, can be used to solve the above issues. Reference [20]
reported a dc/dc converter with a single active switch –
combining boost, flyback, and charge-pump circuits to
achieve wide input range, high voltage gain, high efficiency,
and low cost simultaneously as a part of a 20-70 V input, 180-
200 V output, and 97.4% peak efficiency PV integrated ac
module. This paper concentrates on the second power stage –
the inverter circuit.
20-70 V 200±20 V Grid
PV non-isolated
high step-up High-efficiency
DC/DC H6-type
converter DC/AC
inverter
Fig. 1 PV ac module application of the H6-type inverter
The simplest inverter using hybrid MOSFETs and IGBTs
with unipolar PWM to achieve high efficiency is shown in
Fig.2. The high side IGBTs serve as line frequency polarity
selection switches and low side MOSFETs operate in high
frequency sinusoidal PWM to control the output voltage or
current. The high efficiency of the hybrid 4-swich inverter can
be achieved over wide load range because the MOSFETs can
avoid the fixed voltage-drop losses and significantly reduce
the turn-off losses without tail current as compared to the case
with IGBTs. However, the hybrid 4-swich inverter with
unipolar PWM is not suitable for non-isolated AC module
application because the high ground leakage current is
generated through the parasitic capacitance of the PV panel
due to high frequency voltage swing at the PV terminals [21,
22]. Reference [23] presented the 5-switch high efficiency
inverter with unipolar PWM, as shown in Fig. 3, to solve the
high ground leakage current issue. The MOSFET S5 and S1 or
S2 operate in SPWM and share half the DC bus voltage, high
frequency voltage swing at the PV terminals is eliminated.
Note that MOSFETs cannot be used as S3 or S4 in the inverter
because of the MOSFET body diode slow reverse-recovery
issue. Moreover, the cost-effective solution using bootstrap
technology with the integrated chips to drive the high-side and that not only are MOSFET body diode reverse-recovery and
mid-side active switches has not been presented. ground leakage current issues alleviated in the proposed
inverter, but also that 98.3% maximum efficiency at about half
of rated output power and 98.1% European Union (EU)
S3 D3 S4 D4 efficiency are achieved.
G3 G4 L1
C1 II. THE PROPOSED INVERTER TOPOLOGY AND
OPERATION ANALYSIS
L2 Fig.4 shows the circuit diagram of the proposed inverter
S1 S2 with H6-type configuration, which is composed of six power
G1 G2 MOSFETs (S1-S6), two freewheeling diodes (D1 and D2), and
two split inductors (L1 and L2) as a low-pass filter. This circuit
is well suited for non-isolated ac module applications thanks
G1 t to the following advantages: (1) high efficiency over a wide
load range by using MOSFETs for all active switches since
G4 t their intrinsic body diodes are naturally inactive; (2) low
ground leakage current because the voltage applied to the
G2 t parasitic ground-loop capacitance contains only low-
frequency components; (3) no need for limited lifetime
G3 t electrolytic capacitors for a split dc link similar to that of the
half-bridge family of inverters with two or three levels; (4)
Fig. 2 Simplest inverter using hybrid MOSFETs and IGBTs with unipolar smaller output inductance as compared to that of the common
PWM to achieve high efficiency. full-bridge inverter with bipolar PWM switching; and (5) low
output ac current distortion because there is no need to have
S5 dead time for the proposed circuit since the same phase-leg
active switches never all turn on during the same PWM cycle.
G5 S3 D3 S4 D4
G3 G4 L1 L1
C1 G1
S1 G2
S2

Grid
L2 VDC
D1 D2
S1 S2
G1 G2 S4 L2
G3 S3 G4

G1 t

G5 S5 G6 S6
G4 t

G2 t Fig. 4 Circuit diagram of the proposed inverter with H6-type configuration.

G3 t Fig. 5 illustrates the PWM scheme for the proposed

G5
Fig. 3 High efficiency 5-switch inverter without high ground leakage current
issue.
In this paper, a novel, high-efficiency inverter using
MOSFETs for all active switches is proposed for photovoltaic,
non-isolated, ac module applications. The presented H6-type
configuration features high efficiency over a wide load range,
low ground leakage current, no need for split capacitors, and
low output ac-current distortion. Detailed power stage
operating principles, PWM scheme, and novel bootstrap
power supply for the proposed inverter are described. To
verify the validity of the circuit and the improved performance
of the proposed inverter, a 300 W hardware prototype –
targeted at PV non-isolated ac module applications – has been
designed, fabricated and tested. Experimental results show
inverter. As shown in Fig. 5 (a), the top device in one leg and
t the bottom device in the other leg are switched simultaneously
in the PWM cycle and the middle device operates as a polarity
selection switch in the grid cycle. As shown in Fig. 5 (b), if
the sinusoidal control voltage vcontrol, which is synchronized
with grid voltage, is higher than the triangular carrier voltage
vcarrier, the gating voltage G1 and G6 are active; otherwise, G1
and G6 are inactive. And if vcontrol is higher than zero, the
gating voltage G4 is active; otherwise, G4 is inactive.
Similarly, the comparison of (-vcontrol) with vcarrier or zero
results in the logical signals to control G2, G5 and G3,
respectively.
Fig.6 shows the four topological stages in one grid cycle
for the proposed inverter. Note that the point N is the dc link
negative terminal, and the point E is the grid negative
terminal. The four operation modes are briefly described as
follows. During the grid positive half cycle, switch S4 remains

1057
on, whereas S1, S6 and D1 commutate at the PWM switching L1
frequency. When S1, S6 and S4 are on and the other switches S1 S2 vL1
G1 G2
and diodes are off, the inductor current is charging, as shown
in Fig. 6 (a). Under the condition that the inductance values of VDC
vG
L1 and L2 are identical, the inductor voltage can be found as D1 D2 vL2
v L1 = v L 2 = 0.5 ⋅ ( vDC − vG ) (1) G3 S3 G4
S4 L2 E

And the grid voltage vG is calculated by

vG = v DC ⋅ M ⋅ sin(ωt ) (2)
G5 S5 G6 S6
N
where vDC is the dc link voltage; M is the modulation index; (a)
and ω is the angular frequency of the grid.
L1
From (1) and (2), the ground potential vEN1 in the charging vL1
S1 S2
interval during positive grid half cycle can be expressed G1 G2

[
vEN1 = 0.5 ⋅ vDC ⋅ 1 − M ⋅ sin(ωt ) ]
(3) VDC
D1 D2
vG
vL2
In the freewheeling interval during the positive grid half
G3 S3 G4
S4 L2 E
cycle shown in Fig. 6 (b), the S1 and S6 simultaneously turn
off and S4 and D1 are on. The voltages of the inductor L1 and
L2 are given as
S5 S6
v L1 = vL 2 = −0.5 ⋅ vG (4) G5 G6
N
(b)
Under the condition that the S1 and S6 share the dc link
voltage when they are simultaneously turned off, the voltage L1
stress of the S6 can be found as S1 S2 vL1
G1 G2

vS 6 = 0.5 ⋅ vDC (5) VDC

vG
D1 D2 vL2

t G3 S3 G4
S4 L2 E
(-vcontrol) vcarrier
vcontrol

G1 S6
G5 S5 G6
& G6 t N
(c)
G4
t
L1
G2
S1 S2 vL1
& G5 t G1 G2
vG
VDC
G3 t D1 D2 vL2

(a) G3 S3 G4
S4 L2 E

G4
G5 S5 G6
S6
N
G1 (d)
& G6
-1 Fig. 6 Topological stages of the proposed inverter: (a) charging interval and
K (b) freewheeling interval during positive grid half cycle, (c) charging
G2
interval and (d) freewheeling interval during negative grid half cycle.
vcontrol & G5

vcarrier
From (2), (4) and (5), the ground potential vEN2 in the
G3 freewheeling interval during positive grid half cycle can be
expressed
[
vEN2 = 0.5 ⋅ vDC ⋅ 1 − M ⋅ sin(ωt ) (6) ]
(b)
Based on the fact that (6) is identical to (3), the PWM
Fig. 5 PWM scheme for the proposed inverter: (a) signals in time domain;
and (b) implemented circuit. switching frequency voltage of the ground potential is
avoided. The operation modes similarly change during the
grid negative half cycle. From Fig. 6 (a)-(d), it can be seen that

1058
the body diodes of the MOSFETs are naturally inactive and transfer energy to the high-side and mid-side switches from a
the high-frequency voltage of the ground potential is avoided single non-isolated power supply Ea. Note that the energy of
during the whole grid cycle. As a result, MOSFETs can be the Ca1 can not be transferred from Ca3 which in the same leg
employed as all the active switches and high ground leakage because the middle device S3 and its body diode are never on
current can be avoided. when S1 operates at high-frequency, such that inter-leg
connections of the bootstrap circuit for the proposed inverter
The output inductance can be calculated based on the are necessary. The novel bootstrap power supply is preferred
design criterion that the maximum magnitude of the peak-to- over isolated auxiliary supply for each gate drive thanks to the
peak current ripple is less than (10~20) % of the rated output compact size and compatibility with integrated chips. It makes
current Irated. The peak-to-peak inductor current ripple can be the proposed inverter more appealing for PV ac module
derived as applications.
Δi pk = ( vDC − vG ) ⋅ D ⋅ TS ( L1 + L2 ) (7)
S1 S2
And the duty cycle D in the proposed inverter is calculated by Ca1
L1 L2 Ca2
D=M ⋅ sin(ωt ) (8) Da1 Da3
VDC Grid
From (2), (7) and (8), the peak-to-peak ripple of the S4
S3
inductor current can be derived as D1 D2
Ca3 Ca4
0.25 ⋅ vDC ⋅ TS Da2 Da4
Δi pk = ⋅ [1 − (1 − 2 M sin ωt )2 ] (9) S5 S6
L1 + L2 Ca5 Ca6
where TS is the PWM switching period. Ea
when
Fig. 7 Circuit diagram of the bootstrap power supply for the proposed
1 − 2 M sin(ωt ) = 0 (10) inverter.

The maximum peak-to-peak ripple of the inductor current in The high-side and middle-side MOSFETs in the same
the whole grid cycle is calculated by phase leg can be driven by one piece of the integrated chip
FAN7385, as shown in Fig. 8.
0.25 ⋅ vDC ⋅ TS
Δi pk ,max = ≤ (10 ~ 20)% ⋅ I rated (11) 12V 12V
L1 + L2
Vdd Vb1 Vdd Vb1
In the proposed inverter, the output inductance then can be G1-in In1 Ho1 G1 G2-in In1 Ho1 G2
calculated as Vs1 S1 Vs1 S2
FAN7385 FAN7385
0.25 ⋅ vDC ⋅ TS Vb2 Vb2
( L1 + L2 ) ≥ (12) G3-in In2 Ho2 G3 G4-in In2 Ho2 G4
(10 ~ 20)% ⋅ I rated Gnd Vs2 S3 Gnd Vs2 S4
In the conventional full-bridge inverter using bipolar PWM
scheme, the output inductance can be calculated as
Fig. 8 High-side and middle-side gate drivers using integrated chips
0.5 ⋅ vDC ⋅ TS FAN7385 for the proposed inverter.
Lout ≥ (13)
(10 ~ 20)% ⋅ I rated IV. EXPERIMENTAL VERIFICATIONS
Thus, the output inductance in the proposed inverter is half A 300 W hardware prototype has been designed,
that of the conventional full-bridge inverter using bipolar fabricated and tested to verify the validity of the proposed
PWM scheme. inverter targeted at PV non-isolated ac module application.
The main devices S1~S6 are 250 V, 42.5 mΩ MOSFETs
III. NOVEL BOOTSTRAP POWER SUPPLY AND INTEGRATED (FDB2710), the freewheeling diodes D1 and D2 are ultrafast
GATE DRIVERS FOR THE PROPOSED INVERTER diodes CMR5U-04 (400 V/5 A), the auxiliary diodes Da1~Da4
Although the proposed inverter has the distinctive are ultrafast diodes MURA160 (600 V/1 A), and the bootstrap
advantages over the conventional full-bridge inverter, there capacitors Ca1~Ca4 are 1 µF, 25 V X7R. A low-pass filter (L1 =
are also some shortcomings associated with this method: two L2= 0.8 mH, Cf = 0.68 µF) is used as the output filter. The
more active switches and their gate drivers and the individual three pieces of dual-channel high-side gate driver integrated
power supplies. A cost-effective solution to power the high- chips FAN7385 with the proposed bootstrap power supply are
side and mid-side gate drives for the proposed inverter using designed to produce the matched gating signals for the six
the bootstrap power supply technique is shown in Fig. 7. Four power MOSFETs. A digital control board with Spartan-3E
small capacitors Ca1-Ca4 and diodes Da1-Da4 are employed to FPGA is used as the sinusoidal output current controller.

1059
Specifications of the inverter are as follows: dc link voltage in Fig. 12. This figure shows that the proposed inverter
VDC = 180-200 V; output power Po = 300 W; output voltage presents high power-factor and low harmonic distortion.
Vo,RMS = 120 V; switching frequency fsw = 30 kHz.
io (5 A/ div)
The experimental gating signals in the grid cycle and in
PWM cycle are shown in Fig. 9(a) and (b), respectively. It can
be seen that the experimental gating signals vG1, vG6 and vG4 vS1 (100V/div)
agree with the analysis results of the PWM scheme and the
proposed bootstrap circuit works well by observing that the vS4 (100V/div)
gate drive voltage level of the middle and top switches are
kept constant during the grid cycle. The gate drive signal vG1
of the top switch in one leg and the vG6 of the bottom switch in
the other leg are matched with each other. vS6 (100V/div)

io (5 A/ div) t (5ms/div)
(a)
vG1 (20V/div) io (5 A/ div)

vG6 (20V/div) vS1 (100 V/div)

vG4 (20V/div)

vS4 (100 V/div)

t (5ms/div)
vS6 (100 V/div)
(a)
t (10 µs/div)
io (5 A/ div)
(b)

vG1 (20 V/div) Fig. 10 Experimental switches voltage waveforms: (a) in the grid cycle and
(b) in the PWM cycle.

vG6 (20 V/div)

vEN (100V/div)
vG4 (20 V/div)

t (5 µs/div)
(b) io (5 A/ div)

Fig. 9 Experimental gating signals: (a) in the grid cycle and (b) in the PWM
cycle.
t (5ms/div)
The experimental switches voltage waveforms under 200
V dc link conditions are shown in Fig. 10. The voltage stress Fig. 11 Experimental waveforms of the ground potential under full-load
conditions.
of the top switch S1 and the middle switch S4 is 200V, which
is the same as the dc link voltage. The voltage stress of the
bottom switch S6 is about half of the dc link voltage, as shown
io (5 A/ div)
in Fig. 10 (a). It can be seen from Fig. 10 (b) that the switches
S1 and S6 almost evenly share the dc link voltage when they
switch off simultaneously.
Fig. 11 shows the experimental waveforms of the ground
potential under full-load conditions. The testing results of the vAC (200 V/div)
ground potential vEN agree with the (6). The high ground
leakage current is avoided by observing that the high-
frequency voltage of the ground potential is less than 10 VRMS
under full-load conditions. t (5 ms/div)
The experimental waveforms of the output current under Fig. 12 Experimental waveforms of the output current under the 120 VRMS ac
the 120 VRMS ac voltage and full-load conditions are described voltage and full-load conditions.

1060
 Fig.13 illustrates the experimental results for efficiency
under different dc link voltages and output loads with the 30
kHz switching frequency and 120 VRMS ac voltage conditions.
The maximum experimental efficiency of the prototype is
98.3% at about half of rated output power and its European
Union efficiency is 98.1%.
99.0%
98.5%
98.0%
97.5%
Vdc=180V
97.0%
Vdc=200V
96.5%
96.0%
95.5%
95.0%
0 50 100 150 200 250 300
Fig. 13 Experimental results of efficiency as a function of the input
voltage and the output power.
V. CONCLUSION
This paper proposes a novel single-phase inverter with H6-
type configuration as a part of a wide input range, high-
efficiency, and long lifetime PV non-isolated 300 W ac
module. Key features of the proposed circuit are as follows:
(1) high efficiency over a wide load range by using MOSFETs
for all active switches since their body diodes are naturally
inactive; (2) low ground leakage current even if no
transformer is used; (3) no need for bulky capacitors for a split
dc link like what three-level inverters do; (4) 50% reduction of
the output inductance as compared to that of the common full-
bridge inverter with bipolar PWM switching; (5) low output
ac current distortion because the PWM dead time for the
proposed circuit is eliminated; and (6) simple bootstrap power
supply and integrated gate drivers for the inverter. A 300 W
hardware prototype has been designed, fabricated and tested.
Experimental results verify the validity of the novel circuit and
show 98.1% European efficiency.
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