5 4 3 2 1

U101-F

R101 0R AG17 T3 R102 0R

VDD18_6583 DVDD18_MD DVDD18_MIPITX VDD18_6583
DVSS18_MIPITX T2
R103 0R AH14
VA_PMU AVDD18_MD
AD16 L7 C104 C105 C106
C101 C102 C103 AVSS18_MD DVDD18_MIPIRX 100nf 100nf 100nf
AE17 AVSS18_MD DVSS18_MIPIRX M6
100nf 100nf 100nf
D AJ12 AVDD18_AP DVDD18_MIPIIO H1 D
AD12 AVSS18_AP DVSS18_MIPIIO K6
AE13 AVSS18_AP
R104 0R AH19 AB28 R105 0R VUSB_PMU
VTCXO_1_PMU AVDD28_DAC AVDD33_USB_P0
AVDD18_USB_P0 AD27
R106 0R AJ11 AB26
VDD18_6583 DVDD18_PLLGP AVSS33_USB_P0
AF29 R107 0R VUSB_PMU
R108 0R AVDD33_USB_P1 R109 0R
VDD18_6583 M16 AVDD18_MEMPLL AVDD18_USB_P1 AC26 VDD18_6583
M15 AVSS18_MEMPLL AVSS33_USB_P1 AE28
C107 C108 C109 C110 C111 C112
100nf 100nf 100nf 100nf 100nf 100nf
MT8388E1_LPDDR2

DVDD18_EMI R111 0R
VDD18_6583

DVDD12_EMI

U101-B
1.8V IO for DDR
1.2V IO for DDR2
C R112 0R C
C5 GND DVDD18_EMI H10 DVDD12_EMI VM_PMU
C8 GND DVDD18_EMI H19
C21 H20 C113 C114 C115 C116
GND DVDD18_EMI 100nf 100nf 100nf 100nf
C24 GND DVDD18_EMI J10
D7 GND DVDD18_EMI J11
D9 GND DVDD18_EMI J17
D11 GND DVDD18_EMI J18
D18 GND DVDD18_EMI J19
D20 GND DVDD18_EMI J20
D22 GND DVDD18_EMI K13
J6 GND DVDD18_EMI K15 LDO requirement
J14 GND DVDD18_EMI K20
K10 GND
K11 R24 R113 0R VEMC_1V8_PMU
GND DVDD18_MC0 R114 0R
K12 GND DVDD33_MC1 U1 VMC_PMU
K16 Y1 R115 0R VDD28_6583
GND DVDD33_MC2 R116 0R
K17 GND DVDD28_BPI AE25 VDD18_6583
K18 GND DVDD28_BSI AG23 Close to MT6588
L24 AJ22 R117 0R VDD18_6583
GND DVDD18_BSI R118 0R
P11 GND DVDD18_NML1 J29 VDD18_6583
P12 GND DVDD28_NML2 Y24
P13 GND DVDD18_NML3 AF1
P14 GND DVDD18_NML4 F1
P15 GND DVDD18_MC12 W8
P16 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126
GND 100nf 1uf 100nf 100nf 100nf 100nf 100nf 100nf 100nf 100nf
R10 GND DVDD N10
R11 GND DVDD N11
R13 GND DVDD N12
R14 GND DVDD N13
R16 GND DVDD N14
R18 GND DVDD N15
R20 GND DVDD N16 DVDD[3]
3
T8 GND DVDD N17
T9 GND DVDD P10
T11 GND DVDD P17
T13 P18 DVDD R119 0R
GND DVDD VCORE_PMU
T14 GND DVDD P19
B T16 P20 C127 C128 C129 C130 C131 C132 C133 C134 C135 B
GND DVDD 100nf 100nf 100nf 100nf 100nf 1uf 10uf 10uf 10uf
T18 GND DVDD R17
T20 GND DVDD R19
U8 GND DVDD T17
U11 GND DVDD T19
U16 GND DVDD U17
U18 GND DVDD U19
V6 U20 R125 R124 0R
GND DVDD n.m
V7 GND DVDD V17 DVDD_GPU[3]
3
V8 V20 1 2
GND DVDD
V11 GND DVDD W20
V16 DVDD_GPU_BB R120 n.m VGPU_PMU
GND
V18 GND DVDD_GPU T10
V19 U9 C136 C137 C138 C139
GND DVDD_GPU 100nf 100nf 1uf 10uf
W11 GND DVDD_GPU U10
W16 GND DVDD_GPU V9 DVDD_DVFS[3]3
W19 GND DVDD_GPU V10
W24 GND
AA6 R12 DVDD_DVFS R121 0R
GND DVDD_DVFS VPROC_PMU
AD20 GND DVDD_DVFS R15
AD24 T12 C140 C141 C142 C143 C144 C145 C146 C147 C148
GND DVDD_DVFS 100nf 100nf 100nf 100nf 100nf 1uf 10uf 10uf 22uF
DVDD_DVFS T15
DVDD_DVFS U12
DVDD_DVFS U13
DVDD_DVFS U14 R122 ¿¿½üIC µ×²¿À-»ØPMIC
U15 R122 0R
DVDD_DVFS GND_DVDD_DVFS[3] 3
3 VPROC_BB[3] AB11 VPROC_FB DVDD_DVFS V12
3 GND_VPROC_BB [3] AD11 GND_VPROC_FB DVDD_DVFS V13
DVDD_DVFS V14
DVDD_DVFS V15
DVDD_DVFS W12 DVDD_SRAM[3]
3
A1 NC DVDD_DVFS W15
A29 NC
AJ1 W13 DVDD_SRAM R123 0R VSRAM_PMU
NC DVDD_SRAM
AJ29 NC DVDD_SRAM W14
C149 C150 C151 C152
100nf 100nf 1uf 10uf
A MT8388E1_LPDDR2 A

Title
01 MT6588 - Power
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 1 of 17

5 4 3 2 1
 5 4 3 2 1

U101-A

VDD18_6583
VBAT
6 TX_IP [6] AF18 UL_I_P1 BPI1_BUS0 AJ24 ASM_VCTRL_A
[7] 7
ED[0:31] U101-D
6 TX_IN [6] AF17 UL_I_N1 BPI1_BUS1 AG26 ASM_VCTRL_B
[7] 7
[5]
6 TX_QP[6] AF19 UL_Q_P1 BPI1_BUS2 AJ27 ASM_VCTRL_C
[7] 7
6 TX_QN [6] AF20 UL_Q_N1 BPI1_BUS3 AH28 ED31 C23 RDQ31 RCS_ F12 ECS0_B[5]5
AF27 WG_GGE_PA_ENABLE
[7] 7 R201 10K,1/20W,5%,0201 R220 ED30 D23 E14 ECS1_B[5]5
BPI1_BUS4 n.m RDQ30 RCS1_
AG13 AG28 0R ED29 C22
AG14
UL_I_P2 BPI1_BUS5
AF26
Active low ED28 A24
RDQ29
E16
UL_I_N2 BPI1_BUS6 SYSRST_B [2,3,15]
15,2,3,9 RDQ28 RWE_
AF14 AJ25 W_PA_B1_EN
[7] 7 ED27 D21 C14
DVDD28_BPI

UL_Q_P2 BPI1_BUS7 U213 RDQ27 RRAS_

AF13 UL_Q_N2 BPI1_BUS8 AG27 W_PA_B2_EN
[7] 7 Delay time is 7.5S ED26 B21 RDQ26 RCAS_ B15
AH26 W_PA_B5_EN
[7] 7 R219 0 1 6 ED25 B22 E13
BPI1_BUS9 1 2 /REST TEST RDQ25 RCKE ECKE[5]5
AJ16 AH24 W_PA_B8_EN
[7] 7 C203 ED24 B24
6 RX_IP [6] DL_I_P1 BPI1_BUS10 RDQ24
Loading AH16 AF24 2 5 100nf ED23 B5 C9 EDQM0[5]5
6 RX_IN [6] DL_I_N1 BPI1_BUS11 GND DSR RDQ23 RDQM0
AH18 AJ28 SDV 08/28 remove RX1/2/3 SW201 ED22 B7 C18 EDQM1[5]5
RX_QP[6]
<10pF66 RX_QN DL_Q_P1 BPI1_BUS12 RDQ22 RDQM1
AH17 AH25 STS-A85SNS C201 3 4 ED21 B8 A8 EDQM2[5]5
[6] DL_Q_N1 BPI1_BUS13 /SR0 VCC RDQ21 RDQM2
AE26 TP201 TP/SMD/0.5MM n.m ED20 D8 A21 EDQM3[5]5
1

BPI1_BUS16 FT7521 RDQ20 RDQM3

AG15 DL_I_P2 BPI1_BUS17 AH27 TP202 TP/SMD/0.5MM ED19 A5 RDQ19
AG16 AE24 TP203 TP/SMD/0.5MM KEYPAD-5.2-1.8-4.0 DVDD12_EMI ED18 C7 F9 EDQS0[5]5
DL_I_N2 BPI1_BUS18 RDQ18 RDQS0
AF15 DL_Q_P2 ED17 D6 RDQ17 RDQS1 E20 EDQS1[5]5
AF16 AF28 VM0
[7] 7 researved for debug?? ED16 C6 E6 D
DL_Q_N2 VM0 RDQ16 RDQS2 EDQS2[5]5
VM1 AH29 VM1
[7] 7 ED15 B17 RDQ15 RDQS3 F23 EDQS3[5]5
ED14 C19 RDQ14 RDQS0_ E9 EDQS0_B[5]5
AE20 BSI1A_CS0
[6] 6 0 R202 C202 ED13 D19 F20 EDQS1_B[5]5
BSI1A_CS0 RDQ13 RDQS1_
AG18 VBIAS BSI1A_CLK AH22 BSI1A_CLK
[6] 6 3 PWRKEY [3,8,15]R221 8.06K 100nF ED12 B20 RDQ12 RDQS2_ F6 EDQS2_B[5]5
AG20 AH21 BSI1A_DATA0
[6] 6
1 2 ED11 C20 E23
7 WG_GGE_PA_VRAMP [7] APC1 BSI1A_DATA0 RDQ11 RDQS3_ EDQS3_B[5]5
TP/SMD/0.5MM TP204 AG19 APC2 BSI1A_DATA1 AE21 BSI1A_DATA1
[6] 6 ED10 A17 RDQ10
6 DCOC_FLAG
[6] AH20 TXBPI1 BSI1A_DATA2 AG22 BSI1A_DATA2
[6] 6 2,5 EVREF[2,5] EVREF ED9 B18 RDQ9 RCLK0 H16 EDCLK[5]5
ED8 A20 RDQ8 RCLK0_ H15 EDCLK_B[5] 5
BSI1B_CS0 AE23 ED7 B9 RDQ7 RCLK1 H12 RCLK1, RCLK1B reserve for
AF21 AF23 C206 C204 ED6 B11 H13
BSI1C_CLK BSI1B_CLK RDQ6 RCLK1_ 2nd DDR3x16
DVDD28_BSI

AH23 AE22 R203 100nf 1uf ED5 A12

BSI1C_DATA BSI1B_DATA 8.06K RDQ5
ED4 C10 RDQ4 NLD15 G25 GPIO_STROBE [8] 8
MT8388E1_LPDDR2
ED3 A9 RDQ3 NLD14 D28 GPIO_SUB_CMRST [8]8
ED2 D10 RDQ2 NLD13 F28 GPIO_SUB_CMPDN [8]8
ED1 C11 RDQ1 NLD12 F25 TP205 TP/SMD/0.5MM
ED0 B12 RDQ0 NLD11 E26 TP206 TP/SMD/0.5MM
NLD10 H25
2,5 EVREF[2,5] H14 VREF NLD9 J28
H18 VREF NLD8 E28 TP219 TP/SMD/0.5MM
NLD7 C29
C15 RBA2 NLD6 G28
C12 RBA1 NLD5 H28
B14 RBA0 NLD4 B28
15 URXD4[15] URXD4 SCL0[2,8]
2,8 D12 RA14 NLD3 G27
TP220 TP221
TP/SMD/0.5MM
TP/SMD/0.5MM
15 UTXD4[15] UTXD4 SDA0[2,8]
2,8 D17 RA13 NLD2 H27
SCL1[2,8]
2,8 B13 RA12 NLD1 G26
EA[0:9]
SDA1[2,8]
2,8 F16 RA11 NLD0 C28
[5]
10 URXD3[10] SCL2[2]2,9 D14 RA10
10 UTXD3[10] SDA2[2]2,9 EA9 F17 RA9 NRNB B29
TP218 SCL3[2,13]
13,2 EA8 F18 RA8 NCLE D27
SDV 8/28 SDA3[2,13]
13,2 EA7 C17 RA7 NALE H26
EA6 E18 RA6 NWEB F29
TP/SMD/0.5MM TP/SMD/0.5MM 9 EA5 C16 J25
TP260 RA5 NREB
14 URXD2[15] EA4 A13 RA4 NCEB0 E29
14 UTXD2[15] EA3 A15 RA3 NCEB1 H29 MODEx : DRVVBUS
EA2 D13 RA2
EA1 E12 RA1 TP_MEMPLL N19 TP217 TP/SMD/0.5MM
15 URTS1 [15] URTS1 EA0 E11 RA0 TN_MEMPLL N18 NAND IF HIF IF
GPIO_SPM [14] 3
15 UCTS1[15] UCTS1 NCEB0 LPCE0/1B
11,15 URXD1[11,15] URXD1 E17 DDR3RSTB REXTDN E15
NCEB1 LPCE0/1B
11,15 UTXD1[11,15] UTXD1 SDV 09/16

1
NCLE LPA0
R204 NALE LPA0
60.4R NREB LRDB
AA29
AA26
AA28

C
W26

W28

W25

W27
AG5
AE9

AH5
AF9

AF5
V24

V25

V29
V28

AJ6
Y27
Y26
Y29
Y25

Y28

D2
C1
B3

A2
B1

NWEB LWRB
F4

U101-C

2
UTXD1
URXD1
UCTS1
URTS1

UTXD2
URXD2
UCTS2
URTS2

UTXD3
URXD3

UTXD4
URXD4

SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3

SPI1_CSN
SPI1_MO
SPI1_MI
SPI1_CLK

PWM1
PWM2
PWM3
PWM4

SDV 08/28
6 CLK1_BB[6] AJ19 CLK26M1 SYSRSTB R29 SYSRST_B [2,3,15]
15,2,3,9
R217 0R AJ14
CLK26M2 VDD28_NML2 VDD28_NML2 VDD28_NML2
EXT_CLK_EN AJ21 TP207 TP/SMD/0.5MM
3,9 RTC32K1V8 [3] P25 RTC32K_CK SRCLKENAI E5 SRCLKENAI [10]10
SRCLKENA P26 SRCLKENA[3,6]
3,6
L25 TESTMODE SRCLKENA2 AF22 SRCLKENA2[3] 3
D24 FSOURCE_P SRCVOLTEN P29 SRCVOLTEN [3,6]3,6
<TESTMODE>
Connect to VIO18 : Enter Test Mode 3 WATCHDOG_B [3] R28 WATCHDOG PWRAP_SPI0_CSN L29 PWRAP_SPI0_CSN [3] 3
Connect to GND : Normal mode PWRAP_SPI0_CLK M29 PWRAP_SPI0_CLK [3] 3
15 MCU_JTCK[15] U24 JTCK PWRAP_SPI0_MI M26 PWRAP_SPI0_MI [3] 3
Close to MT6583 15 MCU_JTDO [15] U28 M28 PWRAP_SPI0_MO [3] 3
<FSOURCE_P> 15 MCU_JTRST_B [15] T25
JTDO
JTRST_B
PWRAP_SPI0_MO
PWRAP_EVENT L28 PWRAP_EVENT [3] 3
SDV 8/17
Connect to VGP6 (2v0) : w/i EFUSE program 15 MCU_JTDI [15] U29 JTDI U101-E
15 MCU_JRTCK [15] U25 JRTCK ADC_CLK K25 ADC_CLK[3] 3
Connect to GND : w/oR205
EFUSE program
5.11K V26 K26
15 MCU_JTMS [15] JTMS ADC_WS ADC_WS[3] 3
ADC_DAT_IN K28 ADC_DAT_IN [3] 3 P8 TCP DPIVSYNC AD1 LCDC_VSYNC[9] [16]
USB_VRT AD28 USB_VRT DAC_CLK M27 DAC_CLK[3] 3 R7 TCN DPIHSYNC AC2 LCDC_HSYNC [9] [16]
VBUS AE27 USB_VBUS DAC_WS L26 DAC_WS[3] 3 R3 TDP0 DPIDE AF4 LCDC_DEN[9] [16]
1 2 AC27 L27 P3 AJ2
12 USB_DP[12] USB_DP_P0 DAC_DAT_OUT DAC_DAT_OUT [3] 3 TDN0 DPICK LCDC_PCLK[9] [16]
R206 12 USB_DM[12] AB27 P4
R / 4.99/ M / 0402 / 1% USB_DM_P0 TDP1
12 USB_ID[12] R26 IDDIG SIM1_SCLK N25 SIM1_SCLK[3] 3 R4 TDN1 DPIR0 AE5 LCDC_RED0[9] [16]
1 2
90 Ohm SIM1_SIO M25 SIM1_SIO [3] 3 R1 TDP2 DPIR1 AG3 LCDC_RED1[9] [16]
TP/SMD/0.5MM TP210 AE29 USB_DP_P1 SIM1_SRST P28 SIM1_SRST [3]3 EINT0 : Gyro-Sensor R2 TDN2 DPIR2 AB2 LCDC_RED2[9] [16]
VDD18_6583 R207 differential
TP/SMD/0.5MM TP211 AD29 M24 SIM2_SCLK[3] 3 13 SARS_TOUT [13]
P7 AD5 LCDC_RED3[9] [16]
R / 1 / M / 0201 / 1% USB_DM_P1 SIM2_SCLK EINT1 : ALS&P sensor TDP3 DPIR3
SIM2_SIO N24 SIM2_SIO [3] 3 P6 TDN3 DPIR4 AF2 LCDC_RED4[9] [16]
3 CHD_DP[3] AB25 N28 SIM2_SRST [3]3
EINT2 : G sensor AD2
CHD_DP_P0 SIM2_SRST DPIR5 LCDC_RED5[9] [16]
3 CHD_DM[3] AA25 CHD_DM_P0 EINT3
PWM1 ::GPIO
PMU M4 RCP DPIR6 AC4 LCDC_RED6[9] [16]
EINT0 T28 EINT_GY [13]13 MT6605 OSC_EN Need to default low EINT4::GPIO
M-Sensor N4 RCN DPIR7 AG2 LCDC_RED7[9] [16]
R208 R209 T27 EINT_A [13]
13 PWM2 L1
EINT1 for MT6605 TESTMODE boot-strap EINT5 RDP0
4.7K 4.7K 10 DAICLK[10] B2 MRG_I2S_PCM_CLK EINT2 T26 EINT_G [13]
13 PWM3 ::GPIO
CTP M1 RDN0 DPIG0 AC1 LCDC_GRN0[9] [16]
10 DAIPCMIN [10] C2 MRG_I2S_PCM_RX EINT3 R27 EINT_PMU [3] 3 EINT6
PWM4 ::GPIO
EINT_MT3332 N3 RDP1 DPIG1 AB5 LCDC_GRN1[9] [16]
10 DAISYNC [10] C3 MRG_I2S_PCM_SYNC EINT4 R25 EINT_M [13]
13 EINT7 : M3 RDN1 DPIG2 AH1 LCDC_GRN2[9] [16]
10 DAIPCMOUT [10] E2 MRG_I2S_PCM_TX EINT5 AE8 EINT_CTP [8]8 SDV 08/28 M2 RDP2 DPIG3 AD3 LCDC_GRN3[9] [16]
E1 AH8 EINT8 : EINT_G2 N2 AD6
10 DAIRST [10] DAI_RSTB EINT6 EINT_MT3332
11 [11] RDN2 DPIG4 LCDC_GRN4[9] [16]
13,2 SCL3[2,13] EINT7 AG8 EINT_G2 [13]13 EINT9
UART1:: EINT_6628_WIFI
Debug P2 RDP3 DPIG5 AA5 LCDC_GRN5[9] [16]
13,2 SDA3[2,13] 10 I2S0_CK[10] AG9 I2S_CLK EINT8 AJ8 EINT8_6628_BGF [10] 10 EINT10: HEADSET P1 RDN3 DPIG6 AH2 LCDC_GRN6[9] [16]
10 I2S0_WS [10] AH9 I2S_WS EINT9 AF8 EINT_6628_WIFI [10]10 UART2: GPIO_BSI2 (2nd Talk) DPIG7 AA2 LCDC_GRN7[9] [16]
AJ9 AD10
EINT14 : MT6620 BGF L4
10 I2S0_DAT_IN [10] EINT_HP [4] 4 8 CMDAT9[8]
SDV 8/20, Changed for lvds bridge TP/SMD/0.5MM TP212 AD8
I2S_DATA_IN
I2S_DATA_OUT
EINT10_AUXIN2
EINT11_AUXIN3 AE10 LCM_LDO_EN[9]
UART3:
EINT18 : MT6628
MT6620 WiFi 8 CMDAT8[8] K4
RCP_A
RCN_A DPIB0 AC3 LCDC_BLUE0[9] [16]
B
VDD18_6583 AF10 [3]
BAT_ID_AUXIN4 EVT 10/28 UART4: Debug 8 CMVREF[8] L3 AC5
EINT16_AUXIN4 RDP0_A DPIB1 LCDC_BLUE1[9] [16]
8 CMHREF[8] K3 RDN0_A DPIB2 AG1 LCDC_BLUE2[9] [16]
LSCE0B AJ3 GNSS_LDO_EN [11] 11 8 CMDAT7[8] K2 RDP1_A DPIB3 AB4 LCDC_BLUE3[9] [16]
TP/SMD/0.5MM TP209 AH11 AUXIN0 LSCE1B AJ5 GPIO_CTP_RST [8] 8 8 CMDAT6[8] L2 RDN1_A DPIB4 Y5 LCDC_BLUE4[9] [16]
AH10 AUXIN1 LSCK AG4 DISP_PWR_EN [9]2 DPIB5 AE2 LCDC_BLUE5[9] [16]
LSDA AH3 MODE4/6 : MD1/2_GPS_SYNC GPIO_6628_GPS_SYNC [10] 10 SDV 08/28 8 CMDAT5[8] J4 RCP_B DPIB6 AD4 LCDC_BLUE6[9] [16]
R210 R211 AF12 AE6 8 CMDAT4[8] H4 AA1
AUX_XP LSA0 POWER_3V3_EN [9] RCN_B DPIB7 LCDC_BLUE7[9] [16]
4.7K 4.7K AE11 AH6 GNSS_HRST [11]11 8 CMDAT1[8] J3
AUX_XM LRSTB RDP0_B
AE12 AUX_YP LPCE0B AH4 LVDS_SHUTDOWN_N [9]4 8 CMDAT0[8] H3 RDN0_B
AG12 AUX_YM
DVDD33_MC2 DVDD33_MC1
LPCE1B AF6 GNSS_FRAME_SYNC [11]
11 8 CMDAT3[8] J2 RDP1_B CMMCLK G3 CMMCLK[8]8
AH7 J1 H2
MSDC2_SDWPI

MSDC1_SDWPI

LPTE GPIO_USB_DRVVBUS [12,14]

12,14 I2C0 : CTP 8 CMDAT2[8] RDN1_B CMRST CMRST [8] 8
MSDC0_RSTB
MSDC3_DAT3
MSDC3_DAT2
MSDC3_DAT1
MSDC3_DAT0

MSDC2_DAT3
MSDC2_DAT2
MSDC2_DAT1
MSDC2_DAT0

MSDC1_DAT3
MSDC1_DAT2
MSDC1_DAT1
MSDC1_DAT0

MSDC0_DAT7
MSDC0_DAT6
MSDC0_DAT5
MSDC0_DAT4
MSDC0_DAT3
MSDC0_DAT2
MSDC0_DAT1
MSDC0_DAT0
MSDC3_CMD

MSDC2_CMD

MSDC1_CMD

MSDC0_CMD

AH12 G4
MSDC3_CLK

MSDC2_CLK

MSDC1_CLK

MSDC0_CLK

2,9 SCL2[2] I2S CMPCLK[8]8

I2C1::MHL
MSDC2_INSI

MSDC1_INSI

REFP CMPCLK
2,9 SDA2[2] AH13 REFN DISP_PWM AE7 BL_PWM[9] 9 Main Camera / Sub Camera CMPDN F2 CMPDN[8] 8
MIPI_VRT R6 G2
TP216 TP/SMD/0.5MM
I2C2 : Main 3D Camera SDV 8/17 VRT CMFLASH GPIO_FSA8049 [4]
Power by CAM_IO C205
VGP2_PMU 1uf
I2C3 : G/M/GYRO/ALS sensor
MT8388E1_LPDDR2
I2C4 (PMIC) : MHL R212 MT8388E1_LPDDR2
D3
D4
B4
A4
C4
D5

W5
W2
Y4
V4
W3
W4
V5
Y3

T5
V2
T4
V1
U2
U5
U6
Y2

D26
B27
A27
A25
D25
B25
C26
B26
C27
A28
E25

1.5K
I2C5 (PMIC) : NFC
EMMC_RST
[5] 5 MSDC0 : eMMC
EMMC_CMD
[5] 5 I2C6 (PMIC) : Charger, T sensor
EMMC_CLK
[5] 5 MSDC1 : T-Card
R213 R214 EMMC_DAT0
[5] 5
4.7K 4.7K Close to MT658310 MC3DA3
[10] EMMC_DAT1
[5] 5
MSDC2 : GPIO_BPI2 (2nd Talk)
@ 3D Camera need to use I2C1/I2C2
10 MC3DA2
[10] EMMC_DAT2
[5] 5 MSDC3 : MT6628 Close to MT6588
10 MC3DA1
[10] EMMC_DAT3
[5] 5
2,8 SCL1[2,8] 10 MC3DA0
[10] EMMC_DAT4
[5] 5
2,8 SDA1[2,8] 10 MC3CLK
[10] EMMC_DAT5
[5] 5
SDV 8/17,R203 change to 1.5k??
10 MC3CMD
[10] EMMC_DAT6
[5] 5
EMMC_DAT7
[5] 5
SDV 08/28

10 GPIO_6628_GPS_LNA_EN [10] MC1INSI [12]12

VDD18_6583
MC1SDWPI
4 SPKL_EN[4] MC1CM[12]
12
MC1CK[12]
12
LCM_ID[9] MC1DA0[12]12
BOARD_ID_1
BOARD_ID_2

4 SPKR_EN[4] MC1DA1[12]12
10 GPIO_6628_PMU_EN [10] MC1DA2[12]12
R215 R216 MC1DA3[12]12
4.7K 4.7K
VDD28_6583

Power by CTP A
R260

R262

2,8 SCL0[2,8]
1

2,8 SDA0[2,8]
n.m

n.m

EVT 10/28
2

2
R263
R261
1

1
n.m
n.m
2

Title
02 Baseband
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 2 of 17

5 4 3 2 1
KEYPAD-5.2-1.8-4.0
 5 4 3 2 1

Charger

OVP: 12V
Symbol LPDDR2/1.2V DDR3U/1.25V DDR3L/1.35V DDR3/1.5V
VM_SEL1 L L H H
VBUS
PCH_LED
VM_SEL2 L H L H NM
U301-A

LED303
Weakly pull high
n.m C1 DRIVER C17 ISINK0 N.M
R301 330K Internal 70K pull R306
low PWM ISINK0
VCDT[3] 3 1.268V
VCDT rating: 2-1L1B/SMD/SSM3K35MFV VDD18_6583 VM_SEL1C2 C18 ISINK1
25V rating TP375 1 n.m 2 VMSEL1 ISINK1
3

R302 VM_SEL2 B2 B18 2 1 VBAT

RUM002N02T2L 1 2 VMSEL2 ISINK2
K A
C301 R309 39K U302
1 KPLED E14 0201, 1/20W
1uf VCDT[3] VCDT W17 CHARGER D15 FLASH
2

VCDT FLASH L301 VLS252010ET-R68N R307 D

CHR_LDO [3] CHR_LDO U16
< MP Test Points > VDRV VDRV K15
AVDD28_CHRLDO
VDRV B13 VPROC_SW VPROC_PMU n.m
VPROC_BB[1]
40mil ISENSE/BSTSNS 4mil ISENSE [14] 14 ISENSE W15 BUCK OUTPUTVPROC B14 L/IND/SMD/2520 C303 1 2 1
ISENSE VPROC C361 4.7uF R303 0R
differential to Rsense BATSNS[14] BATSNS W16 1NF
Indicator LED
R305 14 BATSNS DVDD_DVFS[1] 1
PCH_DET VBAT_SUPPLY TP303 TP / 40mil BAT_ON [3] 3 BAT_ON V16 BATON VPROC_FB E13 VPROC_PMIC_FB
CHR_LDO [3] 3 3,8 PWRKEY [2,3,8,15] TP308 TP / 40mil TREF [3] 3 TREF U15 TREF GND_VPROC_FB F13 GND_VPROC_PMIC_FB 4 mil GND trace with
PCH_DET J16 L302 VLS252010ET-R68N R308
PCH_DET good shielding from baseband (Differential) n.m LED302
3.3K VCORE B11 VCORE_SW VCORE_PMU GND_VPROC_BB [1] 1
C304 C305 B12 L/IND/SMD/2520 C302 1 2
TP309 TP / 40mil VCORE C362 1NF
40mil 1uf N.M 4.7uF R310 0R ISINK0 1 B 4 VBAT
CONTROL SIGNAL
VCORE_FB D14 DVDD[1] 1
GND_DVDD_DVFS[1] 1 Green 1 4
3,8 C4 PCH_LED 2 R 5
KCOL0[3,8,15] TP311 TP / 40mil 2,6 SRCLKENA[2,6] SRCLKEN_PERI Local sense Red 2 5 VBUS
For download A2 L303 VLS252010ET-R68N
3,8 KROW0 [3,8,15] TP306 TP / 40mil 2 SRCLKENA2[2] SRCLKEN_MD2
A4 A15 VM_SW VM_PMU ISINK1 3 G 6 VBAT
2,6 SRCVOLTEN [2,6] SRCVOLTEN VM Blue 3 6
R304 1K G15 A16 L/IND/SMD/2520 C306
3,8 PWRKEY [2,3,8,15] PWRKEY VM C363
GND_SIGNAL T16 1NF 4.7uF
Close to MT6583 15,2,9 SYSRST_B [2,15] G13
PMU_TESTMODE
RESETB VM_FB C15 DVDD12_EMI
2 WATCHDOG_B [2] R311 0R A3 SYSRSTB L304 VLS252010ET-1R0N 19-337/R6GHBHC-A01/2T
GND_SIGNAL C9 FSOURCE
EVT 11/05 VSRAM B10 VSRAM_SW
L/IND/SMD/2520 C307
VSRAM_PMU 4 mil GND trace with
2 PWRAP_SPI0_CLK [2] PMU_FSOURCE high(AVDD18_DIG) A7 good shielding from baseband (Differential)
SPI_CLK
Delete Internal charger 2 PWRAP_SPI0_CSN [2] -> EFUSE program B7 SPI_CSN VSRAM_FB D13 DVDD_SRAM[1] 1 4.7uF
2 PWRAP_SPI0_MO [2] B6 SPI_MOSI (1) VPROC_BB & GND_VPROC_BB
2 PWRAP_SPI0_MI [2] D5 SPI_MISO (2) DVDD_DVFS & GND_DVDD_DVFS (GND @ bypass-cap)
L305 VLS252010ET-2R2M
2 PWRAP_EVENT [2] B8 WRAP_EVENT VPA H2 VPA_SW VPA_PMU
2 EINT_PMU [2] C3 L/IND/SMD/2520 C308
INT C364 D380
VPA_FB D2 1NF
2.2uf VPA_SW VBAT_VPA
TP333 L306 VLS252010ET-2R2M
VBAT TP334 HOMEKEY B3 HOMEKEY VRF18_1 E2 VRF18_1_SW VRF18_PMU D / RB551V-30
L/IND/SMD/2520 C309
RB551V-30(UMD2)
The same net with PWRKEY??? H13 PMU_EN VRF18_FB E3
2.2uf
VBAT INPUT L307 VLS252010ET-2R2M
50mil 50mil R313 0R 30mil A13 F2 VRF18_2_SW VGPU_PMU
VBAT_VPROC VRF18_2 L/IND/SMD/2520 C310
A14 VBAT_VPROC
R314 0R 20mil A11 E4 DVDD_GPU[1] 1
VBAT_VCORE VRF18_2_FB 4.7uf
A12 VBAT_VCORE
R315 0R 20mil A17 L308 VLS252010ET-2R2M
VBAT_VM
MMSZ5231B

VDD18_6583 A18 G2 VIO18_SW R316 0R VDD18_6583

VBAT_VM VIO18 L/IND/SMD/2520 C311
Add Zenar Diode B16 VBAT_VM
EVT 11/05 C312
22uF
R317 0R 20mil A10 VBAT_VSRAM VIO18_FB F4
2.2uf
BATTERY CONNECTOR ADD BAT ID detection circuit
Place on the path
2
D301

R362 R318 0R 30mil VBAT_VPA G1 TP331 TP330 TP332

100K from VBAT to IC R319 0R VBAT_VPA
SOD123 20mil D1 VBAT_VRF18
R320 0R E1 LDO OUTPUT
(Battery connector R321 0R VBAT_VRF18_2
500mW 20mil F1 VBAT_VIO18 VA T17 VA_PMU
1

R361 0R [2]
BAT_ID_AUXIN4 or test point or IO R16 VRF28_1_PMU
R322 0R VRF28_1
Big Battery 1500mA 12mil P18 VBAT_LDOS1 VRF28_2 P17 VRF28_2_PMU
connector) VF : 4.85V~5.36V R323 0R 12mil N18 R15 VTCXO_1_PMU
R324 0R VBAT_LDOS2 VTCXO_1
BAT_NTC [14] 12mil K18 VBAT_LDOS3 VTCXO_2 N15 VTCXO_2_PMU
DF57H-6P-1.2V(21) R325 0R 12mil D18 VBAT_LDOS4 VCAMA P14 VCAMA_PMU
6 40mil VBAT_SUPPLY R326 0R 12mil H17 T14 VAST_PMU
6
5 Between IC and IO port R327 0R 12mil G18
VBAT_LDOS5
VBAT_LDOS6
VAST
VIO28 H18 VDD28_6583 C
5 R328 1K
8 4 BAT_ON [3] 3 VUSB L18 VUSB_PMU
8 4
7 3 VMC L17 VMC_PMU
7 3 R329 n.m
2 TREF [3] 3 VMCH L13 VMCH_PMU
2 R330 0R
1 R360 VA_PMU VDD18_6583 12mil T18 AVDD18_LDO VEMC_3V3 K12 VEMC_3V3_PMU
1
1 2 VEMC_1V8 E18 VEMC_1V8_PMU
D384 D381 D382 L15 VGP1_PMU
J301 39K VGP1
PESD5V0S1BL PESD5V0S1BL PESD5V0S1BL VGP2 L16 VGP2_PMU
VGP3 M16 VGP3_PMU
A6 DVDD18_IO VGP4 N16 VGP4_PMU
M1 D16 VGP5_PMUVGP5 :2.8V for touch ic power supply
R331 Rfg DVDD18_IO VGP5
VGP6 F15 VGP6_PMUVGP6 :3.3V for sar sensor power supply
3 FGN[3] AVDD18_DIG B1 DVDD18_DIG VSIM1 G16 VSIM1_PMU
1 2 SDV 8/28 G17
VSIM2 VSIM2_PMU
R / 0.02 / ohm / 0805 / 1%
GAS GAUGE M15 VIBR_PMU
Kelvin connection FGP_IC V17
VIBR
C313 CS_P C314
FGN_IC U17 CS_N Close to MT6320
GND_VREF V14
3 FGN[3] R332 0R FGN_IC C315
C316C317C318C319 C320C321C322 C323C324C325C326C327C328C329C330 1uf C331 1uf
R333 0R FGP_IC FGN_IC/FGP_IC 4mil V15 C332
2.2uf
4.7uf 4.7uf 4.7uf 4.7uf 2.2uf 2.2uf 2.2uf 1uf 1uf 1uf 1uf 1uf 1uf 1uf 100nf100nf VREF 1uf VRTC
differential to Rfg
2 CHD_DP[2] V18 CHG_DP
BC 1.1
SDV 8/28
AVDD33_RTC V2
VIBR_PMU
CHD_DM[2] U18
VIBRATOR
2 CHG_DM
R332, R333 close to Rfg (R331) XIN W1 32K_IN R356
XOUT V1 32K_OUT X301
E10 U2 C333
R331 1000mA
Small Battery close to j301 F10
GND_VPROC RTC_XOSC32_ENB
U3 R334
GND_VPROC RTC_GPIO RTC32K2V8 [10,11]
10,11 1uf 0R
J10 GND_VPROC RTC_32K1V8 A9 RTC32K1V8 [2] 2,9 2 OUT IN 1 0R
K10 GND_VPROC
F9 TP327
G9
GND_VCORE
GND_VCORE GND_LDO L10
VRTC C334 C335 15mil TP / 2X1.2
Bypass GND to PMIC GND first J9 GND_VCORE GND_LDO A1 22pF Q13FC1350000400 22pF
and connect to system GND K9 GND_VCORE GND_LDO L11 TP328

2
E11 L8 R335 N.M D383
GND_VM GND_LDO R336 0
F11 GND_VM GND_LDO L9 TP312 TP313
J11 M10 C336
GND_VM GND_LDO TP/SMD/0.5MM
TP/SMD/0.5MM
K11 GND_VM GND_IO E6 TP / 2X1.2
F8 M6 1uf 1SS400TE61

1
J6
GND_VSRAM
GND_VPA
GND_IO
GND_DIG F6 Close to MT6320
K8 GND_VPA GND_DRV E15
H8 GND_VRF18 GND_LDO M11
H7 GND_VRF18_2 GND_LDO M8
H5
J8
GND_VIO18
GND_VIO18
GND_LDO
GND_LDO
GND_LDO
GND_LDO
M9
P11
T8
V6
W18 R337 N.M DCXO_32K
[6] 6
TBD
GND_LDO
R338 N.M
MT6320E1

< 32K - Less> B

1. MT6320 XOUT connect to MT6167 32KHz output
VDD18_6583 2. MT6320 XIN connect to GND

U301-C
Audio
U301-B Digital R339
4.7K
R340
4.7K
VBAT R341 0R

C337 2.2uf
W4 VBAT_SPK SPK_N W2 AU_SPK1N[4] 4

U4 GND_SPK SPK_P W3 AU_SPK1P[4] 4

TP372 TP373 U1 K5
Symbol Application Vout (V) Iout (mA)
KCOL0[3,8,15] KP_COL0 3,8 SCL_0 SCL4[3]3
R2 K4 SDA4[3]3 3 SCL4[3] TP314 TP/SMD/0.5MM
T1
KP_COL1 SDA_0 TP315 TP/SMD/0.5MM R342 0R W10 R11C338 1uf VPROC CPU 0.7~1.4 (DC/DC+PTP) 2000
KP_COL2 3 SDA4[3] VBAT VBAT_AUD AVDD28_AUD
T2 KP_COL3 SCL_1 K6 SCL5 AVSS28_AUD T11 VCORE MDSYS/Infra 0.7~1.4 (DC/DC) 1200
R4 L6 SDA5 TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM W12
KP_COL4 SDA_1 TP318 TP319 TP320 AVSS28_AUD
N5 KP_COL5 2 ADC_DAT_IN [2] B9 ADC_DAT VM VM 1.2/1.35/1.5 1100
P4 L4 SCL6[3,13,14]
13,14,3 2 ADC_CLK[2] D7 P8 R343 0R VDD18_6583
KP_COL6 SCL_2 ADC_CK AVDD18_AUD
14 GPIO_CHG_EN [14] P5 KP_COL7 SDA_2 L5 SDA6[3,13,14]
13,14,3 2 ADC_WS[2] F7 ADC_WS AVSS18_AUD R8 VSRAM Memory 0.7~1.4 (DC/DC+PTP) 600
SDV 8/18 2 DAC_DAT_OUT [2] C6 DAC_DAT Buck
VDD18_6583
2 DAC_CLK[2] D6 DAC_CK VPA 3GPA 0.5~3.4 (50mV/step) 600
2 DAC_WS[2] C7 V5 AVSS12N_AUD C339 2.2uf
DAC_WS AVSS12N_AUD
3,8 KROW0 [3,8,15] N2 KP_ROW0 VRF18 1st RF 1.825 300
KROW1 [8] N1 KP_ROW1
14 EINT_CHG_STAT [14] R1 KP_ROW2 MICBIAS0 V13 AU_MICBIAS0 DC couple VRF18_2 450
R3 R344 R345 MICBIAS1 W13 W9
AU_FLYP
TP371 KP_ROW3 4.7K 4.7K AU_MICBIAS1 AU_FLYP
T3 KP_ROW4 2nd RF 1.825
M4 C340 C341
M5
KP_ROW5 1uf U9
AU_FLYN 1uf
Close to MT6320 VIO18 IO
GPUApp.
OD 1.8
1.05~1.25 (500mV/step) 600
KP_ROW6 AU_FLYN
P2 KP_ROW7 4 AU_VIN0_P [4] R12 AU_VIN0_P VA ABB 1.8/2.5 60
TP325 TP / 30mil SCL5 4 AU_VIN0_N [4] T12
TP326 TP / 30mil AU_VIN0_N
SDA5 4 AU_VIN1_P [4] V12 AU_VIN1_P ACCDET U13 ACCDET[4] 4 VA28 Audio Block 2.8 40
VSIM1_PMU J1 DVDD_VSIMLS1 4 AU_VIN1_N [4] V11 AU_VIN1_N
2 SIM1_SCLK[2] D8 SIM1_AP_SCLK SIMLS1_SCLK J3 SIM1_CLK[12]12 4 AU_VIN2_P [4] U12 AU_VIN2_P VRF28_1 MDSYS 2.85 200
2 SIM1_SIO [2] M3 SIM1_AP_SIO SIMLS1_SIO L3 SIM1_DATA [12]12 4 AU_VIN2_N [4] U11 AU_VIN2_N HSN U8 AU_HSN [4]
2 SIM1_SRST [2] B4 SIM1_AP_SRST SIMLS1_SRST J2 SIM1_RST [12]
12 Close to Switching charger modify to one DMIC HSP T9 AU_HSP[4] VRF28_2 General 1.8/2.85 200
VDD18_6583
VSIM2_PMU H1 DVDD_VSIMLS2 R368 HPR T7 AU_HPR AU_HPR [4] 4 Analog VTCXO_1 MDSYS 2.8 40
2 SIM2_SCLK[2] E7 SIM2_AP_SCLK SIMLS2_SCLK K2 SIM2_CLK[12]12 [4]
AUDIO_GND_IN 1 2 V7 AU_REFN HPL V8 AU_HPL AU_HPL[4] 4
2 SIM2_SIO [2] M2 L2 SIM2_DATA [12]12
LDO
B5
SIM2_AP_SIO SIMLS2_SIO
L1
0R VTCXO_2 MDSYS 1.8/2.8 40
2 SIM2_SRST [2] SIM2_AP_SRST SIMLS2_SRST SIM2_RST [12]
12
10 AU_FMINL [10] W7 AU_FMINL VCAMA VCAMA 1.5/1.8/2.5/2.8 200
R346 R347 10 AU_FMINR [10] W6 R10 CLK4_AUDIO[6] 6
4.7K 4.7K AU_FMINR CLK_26M
1R / 49.9 / K /20201

1R / 49.9 / K /20201

MT6320E1 VIO28 2.8 400

MT6320E1
VAST LVDS bridge 0.9/1.0/1.1/1.2 300
R348

R349

13,14,3 SCL6[3,13,14] VUSB 3.3 200

13,14,3 SDA6[3,13,14]
Digital VMC T-Card 1.8/3.3 200
LDO
VMCH T-Card 3.0/3.3 800
VEMC_3V3 eMMC (Core) 3.0/3.3 800
A
VEMC_1V8 eMMC 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VGP1 VCAMD 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 400
VGP2 VCAM_IO 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VGP3 VCAM_AF 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VGP4 CTP/CMMB 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VGP5 CTP/CMMB 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VGP6 CTP/CMMB 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VSIM1 VSIM1 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
VSIM2 VSIM2 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
Vibrator VIBR Vibrator 1.2/1.3/1.5/1.8/2.5/2.8/3.0/3.3 200
Title
RTC VRTC RTC Block 2.8
03 MT6320
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 3 of 17

5 4 3 2 1
 5 4 3 2 1

L402 VBAT

BLM18PG181SN1D
C440 C487
33pf 4.7uf

Speaker
A2

U404
EVT 11/05
C403
VDD

6.8nf R461 0R A1
AU_HPL[3,4] IN+ L403
C402 C1 C3 L404 SPKL_N
6.8nf IN- OUT- BLM18PG181SN1D
[3,4]
AUDIO_GND_IN SPKL_P
BLM18PG181SN1D
OUT+ A3
R402 0R 2 C2
SPKL_EN[2] CTRL
C404 C405
PGND

AGND

B2 VREF 33pf 33pf

D R421 C406 (1) iPhone : L-R-G-M D
100K 1uf
(2) °ê¼Ð : L-R-M-G (V)
B3

B1

YDA145 VDD18_6583

CON401
close to IC close to connector
value???
R1411
470K 2
6

Earphone Audio L410

2 EINT_HP [2]
L412
R404 47K
5
R405 33R
3 AU_HPR [3,4] BLM18BD252SN1D BLM18BD252SN1D
L411 L413
R406 33R 4
3,4 AU_HPL[3,4]
BLM18BD252SN1D L414
BLM18BD252SN1D
HP_MIC POLE3 POLE3_J 3
BLM18BD252SN1D POLE42 1 POLE4_J 1
C407 C408 R420 2 n.m 1
33pf 33pf R414 n.m

D411 D412 D413 D414 C461 C460

PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL PESD5V0S1BL n.m n.m R415
EVT 11/05 10K
R409
R410
L401 VBAT 10K
10K

BLM18PG181SN1D
C441 C488
33pf 4.7uf
R411 0R FM_ANT [10] 10

MICBIAS1

Speaker Earphone MICPHONE

A2

U401
EVT 11/05
C409
VDD

6.8nf R460 0R 3 AU_SPK1P[3] 2 1

A1

REC460
3,4 AU_HPR [3,4] IN+

2
R412 N.M L405
C410 L406 R419 GND of C435(10uF) and headset

1
C1 IN- OUT- C3 SPKR_N Close to BB Close to MIC
6.8nf BLM18PG181SN1D

L460
[3,4]
AUDIO_GND_IN SPKR_P 1K

n.m
BLM18PG181SN1D should tie together and single L407

n.m
C411 C412

2
A3 D404 FB / BLM15AG601SN1
R403 0R C2
OUT+
AU_VIN1_N1 via to GND plane ESD9L5 0ST5G

2
SPKR_EN[2] 2 CTRL 3,4 AU_VIN1_N [3]

1
C413 C414
PGND

AGND

B2

+
C VREF 3 AU_SPK1N[3] 2 1 100nF 10uf C
33pf 33pf C416
R422 C415 R413 N.M 33pf R416 Close to CON401
100K 1uf 1.5K
B3

B1

1
YDA145 C442 R417 0R FM_RX_N_6628 [10]
100pf C <= 1pF

C418
C417
33pf tie together and single via to GND plane
3,4 AU_VIN1_P [3] HP_MIC Single via to GND plane
100nF R418

3 ACCDET[3]
1K

SDV 0905

VRF28_2_PMU

SDV 0903 change to 25pin

BEAD410
J412 FB / BLM15AG601SN1
U402
1 1
2 2 POLE3 B1 MIC VDD A1
3 3 C1 EN GND/MIC1 A3 POLE3_J
GPIO_FSA8049 [2] 1
R439 R / 1002/ K / 0201
4 4 C2 CEXT GND/MIC2 B3 POLE4_J
1

5 5
6 SPKL_N C452
6
GNDA
GNDA

7 C / 1000 / nF / 0402
2

7
GND

8
8
9 9 SPKL_P close to IC close to connector Receiver
1

10 FSA8049
C3
A2
B2

10 C422 L408
11 11
12 C / 100 / nF / 0402 AU_HSN [3] AU_OUT0_N_OUT Need to check with ME
2

12 BLM15BD121SN1D
13 13 SPKR_N
14 POLE4 REC401
14 C443
15 15 2
16 SPKR_P 100pf 1
16
26 26 17 17
27 18 MICBIAS0 2403 260 00031
B 27 18 L409 XHR150622SW39P37-01 B
19 19 MIC2_P
20 20 MIC2_N AU_HSP[3] AU_OUT0_P_OUT
21 BLM15BD121SN1D
21
22 22
23 23
24 C444 C445 D409 D410
24 33pf 33pf
25 25 PESD5V0S1BL
PESD5V0S1BL

FH26-25S-0.3SHW

together then single via to main GND

Handset Microphone 1 Close to MIC Close to BB
Close to MIC Close to BB

MICBIAS0
Analog MIC
Handset Microphone 2-2
MIC401 Analog MIC
SM0401L-MF421-M02
Close to MIC Close to BB

4 1 C420 1uf
VDD OUTPUT C421 AU_VIN0_P [3] 3 C434 1uf
MIC2_P AU_VIN2_P [3] 3
C401 100pf C436
100nF 100pf
A C423 1uf A
3 GND GND 2 AU_VIN0_N [3] 3
MIC2_N C437 1uf
AU_VIN2_N [3] 3
D406 C424 C425
33pf
PESD5V0S1BL 33pf C438 C439
33pf 33pf

R401
0R

TBD
together then single via to main GND
together then single via to main GND Title
04 audio
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 4 of 17

5 4 3 2 1
5 4 3 2 1

eMMC+LPDDR2
EVT 12/30

D
VDD1 : Core 1
DVDD18_EMI
EA[0:9]
AC12
AC13

AD16

AE15

AF14
AF16
AC5

AD1

[2]
AE2

AF1
AF3

U501
EA0 Y6 H9
DNU
DNU
DNU
DNU
DNU

DNU
DNU
DNU
DNU
DNU
DNU

CA0 VDD1
EA1 W6 CA1 VDD1 J4
EA2 V6 CA2 VDD1 AA4 VDD2 : Core 2 C501 C502
EA3 V5 AB9 DVDD12_EMI 2.2uf 100nf
CA3 VDD1
EA4 V4 CA4
EA5 N5 CA5 VDD2 H8
EA6 M5 CA6 VDD2 K5
EA7 M6 CA7 VDD2 N4
ED[0:31]
[2]
EA8 L6 CA8 VDD2 R10
EA9 L5 CA9 VDD2 Y5
VDD2 AB8
ED0 W11 DQ0
ED1 V11 DQ1 VDDQ J10
ED2 V10 DQ2 VDDQ J13
ED3 V12 DQ3 VDDQ K8
ED4 V9 DQ4 Power VDDQ L12
ED5 U10 DQ5 VDDQ M13
ED6 U11 DQ6 VDDQ P9
ED7 U12 R9 C503 C508 C519 C520 C521 C522
DQ7 VDDQ 2.2uf 2.2uf 100nf 100nf 100nf 100nf
ED8 N12 DQ8 VDDQ T9
ED9 N11 DQ9 VDDQ V13
ED10 N10 DQ10 VDDQ W12
ED11 M9 DQ11 VDDQ Y8
ED12 M12 DQ12 VDDQ AA10
ED13 M10 DQ13 VDDQ AA13
ED14 M11 1. VCC : Core Voltage 2.7v ~ 3.6v
DQ14
ED15 L11 DQ15 VDDCA M4 2. VCCQ : IO Voltage 1.7v~1.95v (low voltage range)
ED16 AB10 DQ16 VDDCA P4
ED17 Y9 DQ17 VDDCA W5 EMMC_VCCQ [5]
ED18 AB11 DQ18
ED19 W8 D11 R502 0R VEMC_3V3_PMU
DQ19 VCC
ED20 Y10 DQ20 VCC E5
ED21 AB12 E11 R503 0R VEMC_1V8_PMU
DQ21 VCCQ
ED22 AA11 DQ22 VDDI D8 VDDI
ED23 W9 DQ23
ED24 L9 DQ24 CLKM E8 CLKMR504 27R EMMC_CLK
[2]
ED25 J11 DQ25 RST F4 EMMC_RST
[2] 2,5
ED26 H12 F8 EMMC_CMD
[2,5] 2,5 C516 C518 C511 C512 C517
DQ26 CMD 100nf 4.7uf 220nF 2.2uf 100nf
ED27 K10 DQ27 eMMC C
ED28 L8 DQ28 DAT7 E7 EMMC_DAT7
[2,5] 2,5
ED29 H11 DQ29 DAT6 D7 EMMC_DAT6
[2,5] 2,5
ED30 K9 DQ30 DAT5 D9 EMMC_DAT5
[2,5] 2,5
ED31 H10 DQ31 DAT4 E9 EMMC_DAT4
[2,5] 2,5
DAT3 D10 EMMC_DAT3
[2,5] 2,5
R505 240 ZQ0 K6 E10 EMMC_DAT2
[2,5] 2,5
R506 240 ZQ0 DAT2
J6 ZQ1 DAT1 E6 EMMC_DAT1
[2,5] 2,5
ZQ1 D6 EMMC_DAT0
[2,5] 2,5 Close to Memory
DAT0
J9 VSSQ CS0# U4 ECS0_B[2]2,5
J12 VSSQ CS1# U5 ECS1_B[2]2,5
K13 VSSQ
L13 VSSQ CKE0 T4 ECKE ECKE[2,5]
2,5
M8 VSSQ CKE1 T5 ECKE ECKE[2,5]
2,5
N13 VSSQ
R8 VSSQ CLK R6 EDCLK EDCLK[2,5]
2,5
U13 VSSQ CLK# P6 EDCLK_B EDCLK_B[2,5]
2,5
V8 VSSQ Reserve for Jitter adjust
W13 VSSQ DQS0 U9 EDQS0[2]2,5
Y13 U8 EDQS0_B[2]2,5 2,5 EDCLK[2,5] R501 n.m
VSSQ DQS0# 1 2
AA9 VSSQ DQS1 N9 EDQS1[2]2,5 2,5 EDCLK_B[2,5]
AA12 VSSQ DQS1# N8 EDQS1_B[2]2,5
DQS2 Y11 EDQS2[2]2,5
L4 VSSCA DQS2# Y12 EDQS2_B[2]2,5
R4 VSSCA DQS3 K11 EDQS3[2]2,5
W4 VSSCA DQS3# K12 EDQS3_B[2]2,5

H4 VSSM DM0 T8 EDQM0[2]2,5

E12 VSSM DM1 P8 EDQM1[2]2,5
J5 VSS LP-DDR2 DM2 W10 EDQM2[2]2,5
J8 VSS DM3 L10 EDQM3[2]2,5
K4 VSS
P5 VSS VREFCA N6 2,5 EVREF[2]2,5
R11 VSS VREFDQ R12
Y4 VSS
AA5 VSS NC F5
AA8 VSS NC F7
F6 VSSQM NC F9
NC G4
A1 DNU NC G5
A3 G6 C514 C515
DNU NC 4.7uf 100nf
A14 DNU NC G7
A16 DNU NC G8
B2 DNU NC G9
B15 H5 B
DNU NC
C1 DNU NC H6
C16 DNU NC R5
D4 DNU NC T6
D5 DNU NC U6
D12 DNU NC AA6
D13 DNU NC AB5
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU

E4 DNU NC AB6
E13
H13
K2
K15
M2
M15
R2
R15
U2
U15
AB4
AB13
AC4

KMKTS000VM-B604

16GB EMMC+1GB LPDDR2, 186 ball FBGA, 12*16*1.4mm ,0.5mm pitch

eMMC
BOM check when
EVB SMT back
2,5 EMMC_CMD
[2,5] R507 n.m EMMC_VCCQ [5]
1 2
2,5 EMMC_DAT0
[2,5] R508 n.m
2,5 EMMC_DAT1
[2,5] R509 1 2 n.m A
2,5 EMMC_DAT2
[2,5] R510 1 2 n.m
2,5 EMMC_DAT3
[2,5] R511 1 2 n.m
2,5 EMMC_DAT4
[2,5] R512 1 2 n.m
2,5 EMMC_DAT5
[2,5] R513 1 2 n.m
2,5 EMMC_DAT6
[2,5] R514 1 2 n.m
2,5 EMMC_DAT7
[2,5] R515 1 2 n.m
1 2

Title
05 Memory (eMMC + x32LPDDR2)
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 5 of 17

5 4 3 2 1
 L602
TRXB1[7]
2

7 2.2nH
C602
n.m C603
Note : Use RX Co-banding
1

3.3nH GSM850 = W_PA_OUT_B5

3G B5 [7] 7
C604 GSM900 = 3G B8
L601 C605 C606
U603
27nH 9.1nH 1.8nH
SAYFH836MCA0F00
GSM1900= 3G B2
9
7
5
4
2

1.5nH
TRXB5[7]7

1
L603 L604 3 6 C607 4.7PF
G
G
G
G
G

L606 TX ANT
C601 RX 8 33nH n.m 1 RX

1
47nH

L605
RX 1 8 RX
6 3 C609
7 TRXB8[7] ANT TX

G
G
G
G
G
C608 8.2nH

L607
n.m

n.m
C610

2
4
5
7
9
4.7PF U602 1.8nH
SAYFH897MHA0F00 1.5nH

2
7 W_PA_OUT_B8 [7]
6

C611
ANT

C / 2 / pF / 0402 G 9
G 7
U605 7 W_PA_OUT_B1 [7]
2 1 G 5 C613
SAFEA1G84FA0F00R14 G 4 C / 3.9 / pF / 0402 no 0 ohm , not easy to debug TX @ RX de-sense
2

C612 L608 G U604

2 W_PA_OUT_B2 [7] 7
4
RX
RX
TX
G

OUT SAYRF1G95HN0F0A 1 2
7 GSM1800[7] 1 4.7nH L609
IN
2

2.7nH 3 n.m
3
1
8

OUT
G

L611 U606
n.m
5

L610 L612 LS33M03

n.m 2 1 C615 6.8pf TRXB2[7]7
3 TX ANT 6
C614

1
4.3nH C616 L613 1
1

C / 2 / pF / 0402 RX
C / 4.3 / pF / 0402

C / 4.3 / pF / 0402

2.7nH 8 RX L614
1 2 C617
n.m

G
G
G
G
G
2

n.m n.m n.m

C618

C620

C619 L615

2
4
5
7
9
n.m
1

2
L616 L617

1 n.m 2 1 n.m 2
2

1 2
C621
C / 3.9 / pF / 0402
GGE_PA_HB_IN
[7] 7

W_PA_B1_IN [7] 7
G1
G2

D1

D9
D5
D4
D3
D2

C9
C8
C7
C6
C4

C1

W_PA_B2_IN [7] 7
K1

H2
H1

E2
E1

E9
E4
E3

B1
A1
F2

F9
F6
F5
F4
F3
J2
MT6167

W_PA_LB_IN [7] 7
LNA_5N
LNA_5P
LNA_4P
LNA_4N
LNA_3N
LNA_3P
LNA_2P
LNA_2N
LNA_1P
LNA_1N

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND

TXO_GND
TX_HB1
TX_HB2

U601

GGE_PA_LB_IN
[7] 7

L1 LNA_D1P TX_HB3 A2
K2 LNA_D1N TX_LB1 B2
TX_LB2 B3
K3 LNA_D2N TXO_GND C3
L3 LNA_D2P C622
470nF
L4 LNA_D3P R602 2K
K4 LNA_D3N RCAL B4
VTXHF VRF18-1[6]
A4
TMEAS A5
DET PDET[7]7
B5
6 VRF18-1[6] VRXHF DET_GND
C623 470nF K5 C5 R603
V28(ESD) VTCXO28-1[6] 6
B6 0R
TXBPI1(DCOC) DCOC_FLAG
[2] 2
D6 C624
6 RX_BBQN[6] RX_BBQN
K6 470nF
6 RX_BBQP[6] RX_BBQP TX_BBQP TX_BBQP[6]
L6 A7
TX_BBQN TX_BBQN [6] R604 close to 3G PA
B7
6 RX_BBIN [6] RX_BBIN TX_BBIP TX_BBIP [6]
K7 A8 R604
6 RX_BBIP[6] RX_BBIP TX_BBIN TX_BBIN [6]
L8 B8 NCP15WF104F03RC
VLF2 B9
VRF18-1[6]
K8 TST1 DCXO_32KEN A10
DCXO_32K A11 C625
470nF
K9 RXD_BBIN
K10 RXD_BBIP GND G3
L618 0R L619 0R GND G4
6 VIO18 [6] RXD_BBQN GND
XTAL2/VAFCOUT

L10 G5
L11 RXD_BBQP GND G6 R633 n.m
XTAL1/REFIN

GND VTCXO28-1[6]
G9
1

BSI_DATA2
BSI_DATA1
BSI_DATA0

C627
GND
VTCXO28
CLK_SEL

C626 1uf H3 R632 0R

VXODIG

XMODE

BSI_CK
BSI_EN

n.m GND H4
ENBB

VIO18_LC
CLK1
CLK2
CLK3
CLK4

VLF1
2

TST2

VIO18 GND
GND
GND
GND
GND
GND
GND
GND

K11 H5
GND H9 Note : EN32k (2012/02/08, Checked PMU POR)
Reserved LC filter EN32k = 0 ==> MT6320 is 32K XO
J10
J11
H11
H10
G10
F11
D11
E10
F10
D10

H8
G8
F8
E8
D8

C10

B11
B10

J9
J8
J7
J6
J5
J4
J3

VIO18_LC R606 0R
VXODIG EN32k = 1(VTCXO28) ==> MT6320 is 32K Less
6 VTCXO28-1[6] 2
R630 1
n.m
2,3 SRCLKENA[2,3]
R608 0R
Note : VXODIG DCXO_32K[3]3

VXODIG = VIO18 ==> (VCTCXO or DCXO) + 32K XO R698 0R SRCVOLTEN [2,3]

2,3
6 VTCXO28-1[6]
VXODIG = VTCXO28 ==> DCXO + 32K Less C628
470nF

Note : Xmode
VIO18_LC R609 0R
XMODE
06/19
2

R610 0R 2
VTCXO_1_PMU VTCXO28-1[6] 6 6 VTCXO28-1[6] R631 n.m 1
R611 0R
Xmode = 0 ==> VCTCXO + 32K XO R612
X601
VRF18_PMU VRF18-1[6] 6
Xmode = 1(VIO18) ==> DCXO + 32K XO n.m 4 GND HOT 3 VRF18-1[6]
VDD18_6583 R613 0R VIO18 [6]
1

6
Xmode = 1(VTCX28) ==> DCXO + 32K Less R614 C629
n.m 470nF
TP601 TP / 30mil
1 HOT GND 2
1 2
2

TP602 TP / 30mil
X / 26MHz / TZ1689A R615
n.m BSI1A_CS0[2] 2
C630
R646, R643pin BSI1A_CLK[2] 2
Non-final SCH,
1

100nf
should overlap BSI1A_DATA0 [2] 2
U607
on pin1/3 2of DCXO
GND VCONTROL 1 BSI1A_DATA1 [2] 2 Don't release to customer!
R616 0R 3 OSCOUT VCC 4 VTCXO28-1[6]
BSI1A_DATA2 [2] 2
internal use only!
C631
1

C632 (NC)TXC 7Q26002005 100nf

R617 0R RX_BBIP[6] n.m TCXO_KT21P-DCU28A-26M
2 RX_IP [2]
R618 0R RX_BBIN [6] R619 0R CLK1_BB[2]
2

2 RX_IN [2]
R620 0R RX_BBQP[6]
2 RX_QP[2]
R621 0R
Remove after verified
2 RX_QN [2] RX_BBQN[6]
10,6 R622 0R
CLK2_WCN[10] CLK4_AUDIO[3]

2 TX_IP [2] R623 0R TX_BBIP [6]

2 TX_IN [2] R624 0R TX_BBIN [6]
2 TX_QP[2] R625 0R TX_BBQP[6] 6 VTCXO28-1[6] R629 n.m
2 TX_QN [2] R626 0R TX_BBQN [6] R660 n.m
C634
n.m
R627 n.m

TCXO_KT21P-DCU28A-26M
n.m
4 3 R661 n.m
VCC OSCOUT

R628 n.m 1 2
VCONTROL GND
U660

FOR WIFI ONLY

Title
06 RF_MT6167_RX
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 6 of 17

 SKY77590 control logic table
VctA VctB VctC TxEn
VBAT R701 0R
C701 BS2 BS1 mode ebable
R702 1K ASM_VCTRL_A
[2] 2,7
6 GGE_PA_HB_IN
[6] R703 0R (TRX1)G_DCS L L H L
1

C702 (TRX2)W_Band8 L H H L
1

C704
18pF
1

R705 22uF R706 1K

n.m

ASM_VCTRL_B
[2] 2,7
2

R704 n.m (TRX3)W_Band1 H L H L

n.m
(TRX4)W_Band5 H H H L
2

[7]
MODE R707 1K ASM_VCTRL_C
[2] 2,7
2

(TRX5)W_Band2 L H L L
[7]
TXEN
(TRX6) NA H L L L
R708 1K WG_GGE_PA_ENABLE
[2] 2,7
EDGETX_L H L H H
6 GGE_PA_LB_IN
[6] C705 56pf R709 0R
EDGETX_H H H H H
8
7
6
5
4
3
2
1
1

GND
GND
GND
GND
GND
GND
GND
GND
1

R711

R710 GMSKTX_L H L L H
n.m

n.m GND
TX_HB_IN
29 GMSKTX_H H H L H
2

9
TX_LB_IN GND
2

10 28 0723 50ohm terminated

2,7 BS2 GND
11 SKY77590 ANT 27
12 BS1
26
VBATT GND
13 25 R712 51R
VCC TRX6
14 24
GND TRX5
VRAMP

15 23
MODE
TXEN

TRX1
TRX2
TRX3

TRX4 [6]
TRXB5 6
22 CON701
TRXB2[6]6 3 4 L621
16
17
18
19
20
21

U701 ANT700
C707 39pf ASM_ANT_1 1 2 ASM_ANT2
1 1 ANT_1.2X2.5
[7]
MODE
5 6 0R
1

[7]
TXEN
EDGE TXM
C708

C709 C711 C712 ANT701

n.m

R713 10K 39nH n.m n.m

2

WG_GGE_PA_VRAMP
[2]
C90-101 1 1 ANT_1.2X2.5
2

D797 ANT702
1

GSM1800[6]
R714 C7066 n.m
1
220pF 1 ANT_1.2X2.5
24K 6 TRXB8[6]
2

6 TRXB1[6]
1

Dual talk
NM

U710
XM0860SH-DL0601 7 W_PA_VCC1[7]
PORT1 2 W_PA_B8_IN [7] W_PA_VCC[7]
2 W_PA_B8_EN[2,7] 1 CTL1
1

PORT2 6
1

2 W_PA_B5_EN[2,7] 5 2 VM1[2,7] C716 C717 C722 W_PA_VCC1[7] 7

CTL2
GND

4 C733 C721 2.2uF/16V/X5R

VM0[2,7]
2

PORT3 W_PA_B5_IN [7] 2 SKY's cmd

82pF/50V/NPO

0.1uF/16V/X7R

2.2uF/16V/X5R
2

0.1uF/16V/X7R

C727
1

C729
3

10
4
3

C764
NC

C720
NC

W_PA_VCC[7] 7 C754
2

VMODE_0
VMODE_1

VCC1
VCC2

C763 82pf 0.1uF

2

C799 C734 C723

R750 0 C725
1

3.6nH 2,7 VM1[2,7] C751 2.2uF

2

6 W_PA_LB_IN [6] W_PA_B5_IN [7] 2 9 VM0[2,7] 0.1uF

2

RF_IN RF_OUT W_PA_OUT_B5 [6] 6 2,7

1 2 1 2 1 2 1 2 1 2 2.2uF
2

56pF/50V/NPO 56pF/50V/NPO 56pF/50V/NPO C724 18pF R717 0R

W_PA_B1_IN [6]
10

6
1

4
3

3G_PA_CPL_OUT_B2
7 [7] 8 U708 6 C730
CPL_IN CPL_OUT n.m
1

R732 SKY77765 C732

VMODE_0
VMODE_1

VCC1
VCC2

n.m R718
NC
2

5 n.m C726
2,7 W_PA_B5_EN[2,7] VEN
GND
GND

2 9
2

RF_IN RF_OUT W_PA_OUT_B1 [6] 6

3.9nH
2

1
7
11

8 U705 6 C728 C731

CPL_IN SKY77761 CPL_OUT 0.5pF
2

n.m
2 W_PA_B1_EN[2] 5 VEN
GND
GND

R731
7
11

n.m
C781

WCDMA PA control logic table 1 2

HB_EN B1_EN B2_EN B5_EN LB_EN W_PA_VCC1[7] 7 SKY's cmd W_PA_VCC1[7]

n.m
7 SKY's cmd
W_Band1 H H L L L W_PA_VCC[7] 7
1

VM1[2,7] C761
W_Band2 H L H L L 2,7
1

C766 C738 C765 C755 W_PA_VCC[7] 7 C737 C752

2,7 VM0[2,7]
1

C756 82pf 82pf 0.1uF

2

W_Band5 L L L H H
1

0.1uF 0.1uF 2.2uF VM1[2,7] C753 C762 2.2uF

2

2,7
2.2uF VM0[2,7]
2

W_Band8 L L L L H 2,7
2.2uF 0.1uF
2

6 W_PA_B2_IN [6] C735 18pF R719 0R

10
4
3

VPA_PMU R720 0 W_PA_VCC[7] 7 C740

10
4
3

VMODE_0
VMODE_1

VCC1
VCC2

R722
VMODE_0
VMODE_1

VCC1
VCC2

W_PA_OUT_B8 [6] 6
C741 n.m C744
C739
1

R721 2.2uf 2 9
n.m 56pf RF_IN RF_OUT W_PA_OUT_B2 [6] 6
7 W_PA_B8_IN [7] 2 9 C742 C743 1.2nH
2

RF_IN RF_OUT n.m n.m

1

VBAT C745
2

1 2
1

R723 51R 8 U707 6

56pf U706 CPL_IN SKY77762 CPL_OUT n.m C746
8 6
2

CPL_IN SKY77768 CPL_OUT n.m

2

VBAT R724 0R W_PA_VCC1[7] 7 2 W_PA_B2_EN[2] 5 VEN

GND
GND

2,7 W_PA_B8_EN[2,7] 5 VEN

GND
GND

7
11
7
11

3G_PA_CPL_OUT [7] 7
3G_PA_CPL_OUT_B2 [7] 7
2

C782
n.m
1

near-IC
R726
R / 26.1 / ohm / 0201 R727
PDET[6] R725 0R 3G_PA_CPL_OUT [7] 7
6 1 2 R 1/ 26.1 / ohm 2/ 0201
1

R728 R729 R730

n.m n.m 34.8R
2

Title
07 RF_TX_ASM
Size Document Number Rev
A0 Altay 0.1

Non-final SCH, internal use only Date: Monday, October 15, 2012 Sheet 7 of 17
 5 4 3 2 1

Power Key Sub Camera

CTP DO NOT put pull-up resistor on PWRKEY AVRC18S05Q015050R AVRC18S05Q015050R
1
2

1
2
SW801
CMPCLK[2] 7 3 C_PCLK SDA1[2] 7 3 SENSOR_SDA
1
2

1
2
NTCCM3-01BB01 2 7 3 2 7 3
2 CMDAT6[2] 8 8 4 4 C_DAT6 2 SCL1[2] 8 8 4 4 SENSOR_SCL
2 CMDAT2[2] 9 9 5 5 C_DAT2 2 CMVREF[2] 9 9 5 5 C_VREF
3 PWRKEY [2,3,15] 2 4 2 CMDAT5[2] 10 10 6 6 C_DAT5 2 CMHREF[2] 10 10 6 6 C_HREF
2 4
5

D802 1 1 3 3 U851 U852

D
5

R803 2V8
C803 PESD5V0S1BL
100nf VCAMA_PMU
R804 0R CTP_SCL Power On Sequence
2 SCL0[2] CON811 0R R807
R805 0R CTP_SDA recommend supplied at same time,if not,
2 SDA0[2]
R806 0R VDDI>VDD C804 C805
2 EINT_CTP [2] CTP_INT_N 1 1 Power Off2.8V(ON)
Sequence> VDD 1.2(ON) > CHIP_ENABLE(L?H) ?>MCLK(ON) > VGP3_PMU 2V8
2 GPIO_CTP_RST [2] R808 0R CTP_RST_N 2 KCOL0_CON RESETB(ON) ? 100nf 2.2uf
2 VDDC:1.8V (OFF) > VDDA(OFF)>VDDI(OFF)
3 3 KROW0_CON 0R
4 4 KROW1_CON AVRC18S05Q015050R AVRC18S05Q015050R J802
1
2

1
2

5 5 AVDD&AFVDD: 2V8 ,MAX 57mA ;

CMDAT3[2] 7 3 C_DAT3 CMDAT9[2] 7 3 C_DAT9 1 30
1
2

1
2

2 7 3 2 7 3 DVDD: 1V2/1V5, MAX48mA; DGND AF_GND

4.1x2.5 2 CMDAT4[2] 8 4 C_DAT4 2 CMMCLK[2] 8 4 SENSOR_MCLK C_DAT8 2 29 C806 C807
8 4 8 4 DOVDD:1V8, MAX 22mA Y8 AVDD 100nf 100nf
2 CMDAT1[2] 9 9 5 5 C_DAT1 2 CMDAT8[2] 9 9 5 5 C_DAT8 C_DAT9 3 Y9 AF-VDD(2_8V) 28
CMDAT0[2] 10 6 C_DAT0 CMDAT7[2] 10 6 C_DAT7 C_DAT2 4 27 C_DAT1
Volume Up
2 10 6 2 10 6 Y2 Y1
C_DAT3 5 Y3 Y0 26 C_DAT0
U853 U854 C_DAT4 6 Y4 PCLK 25 C_PCLK
C_DAT5 7 Y5 DGND 24
Follow A2107 ,need to be confirmed by ME 0R
C_DAT6 8 Y6 XCLK 23 SENSOR_MCLK
R809
08/08 DOVDD 1.8V
3 KCOL0[3,15] KCOL0_CON VGP1_PMU change to 1.5V C_DAT7 9 Y7 DOVDD 22 VGP2_PMU
R817 VGP1_PMU R810 10 21 C_HREF
R818 0R 0R DVDD(1_5V) HREF 0R
3,8 KROW0 [3,15] KROW0_CON 2 CMPDN[2] 11 PWDN VSYNC 20 C_VREF
C808 C8162 CMRST [2] 12 19 SENSOR_SCL C810
2.2uf 100nf RESET SIO-C 100nf
13 NC SIO_D 18 SENSOR_SDA
VGP5_PMU D803 D804 14 17 R811 GPIO_STROBE [2]
2
AGND STROBE 0R
J801 PESD5V0S1BL
PESD5V0S1BL 15 AGND DGND 16
VDD18_6583
Á½Â·¹©µç:AVDD DVDDO,2.8V;Èý·¹©µçAVDD 2.8£¬DVDD£¬DOVDD 1.8V Lenovo A2 front camera module AXK7L30223G
AVDD 1
2 R516 n.m CON801
VDD 1 2 R812 0R
SDA 3 CTP_SDA 2V8 VCAMA_PMU 1 NC
9 GND SCL 4 CTP_SCL 2 AGND
10 GND INT 5 CTP_INT_N SENSOR_SDA 3 SIO_D
RESET 6 CTP_RST_N C811
100nf
C812
2.2uf
C813
100nf
4 AVDD connector need to be confirmed with ME
GND 7 SENSOR_SCL 5 SIO_C
8 EVT 10/27 volume up/down key changed SDV 08/28 GPIO_SUB_CMRST [2] 6
Main Camera
GND 2 RESET
C_VREF 7 VSYNC
R815 n.m
2 GPIO_SUB_CMPDN [2] 8 PWDN P5H02A/HI-542 Address 0X40; C
C_HREF 9
FH34SRJ-8S-0.5SH D801 D805 D806 D807
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL Volume Down 1V8
1V8
VGP4_PMU
VGP2_PMU
R814 0R
R813 0R

C_DAT9
10
11
12
HREF
DVDD
DOVDD
0X41
C814 C815 Y9
08/08 DOVDD change to 1.8V SENSOR_MCLK 13 XCLK
100nf 100nf C_DAT8 14 Y8
15 DGND
R819 0R KROW1_CON C_DAT7 16
3,8 KROW1 [3] Y7
C_PCLK 17 PCLK
C_DAT6 18 Y6
VGP5_PMU for Touch 2.8V, voltage domain for control C_DAT2 19 Y2
D809
PESD5V0S1BL
connector need to be confirmed with ME C_DAT5 20 Y5
signals should be changed to 2.8V C_DAT3 21 Y3
C_DAT4 22 Y4
C_DAT1 23 Y1
C_DAT0 24 Y0
GCBF120186R/HI-704 Address RD 0X60;WR 0X61 HRS DF30FC-24DS-0.4V
DF30FC-24DS-0.4V-CCW

Title
08 CTP, Camera, Sidekey
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 8 of 17

5 4 3 2 1
5 4 3 2 1

SDV 8/28 DC-DC change to RT8025 ,400mA

D

VBAT

VEMC_3V3_PMU R929 n.m LCM_3P3

VDD_3P3 R928 0R U905 VLS252010T-4R7M (4.7uH)

1 5 L902 VDD_3P3
VIN LX L/IND/SMD/LVS252010-2R2
3 EN FB/VOUT 4
C913 C914
10uf 12pF C910 C911 C912
2 10uf 1uf 33pf
GND C916
RT8025 R913 10nf
330K

2 POWER_3V3_EN [2] R920 0R

R921
62K

R940 0R LCM_3P3 R923

100K
R941 0R

R942 0R SDV 8/17 C

U911 C921 C924 C923 C925 C927 C926

2.2uf 10nf 2.2uf 10nf 2.2uf 10nf
VCC H5
R926 n.m VDD18_6583
LVDSVCC F1
VDD18_6583 R905 0R G4 IOVCC1
C4 IOVCC2 PLLVCC B2
C922 LCM_3P3
R910 100nf J2 C939
D0 LCDC_RED0[2] [16]
10K D4 K1 RZL035P01 R983 100nf
CLKSEL D1 LCDC_RED1[2] [16]
K2 Q901 100K
D2 LCDC_RED2[2] [16] VBAT U1502
D3 J3 LCDC_RED3[2] [16] D 1
K3 4 2 R925 0R VDD_LCM 3 7
D4 LCDC_RED4[2] [16] S D VCCA VCCB
LVDS_CLKSET J4 5 n.m
D6 LCDC_RED5[2] [16] D
F2 J1 6 BL_PWM[2,9] 5 8 R927 BL_PWM_CON
GND1 D27 LCDC_RED6[2] [16] D A1 B1
G

A1 K4 R981 J901 SDV 0913 1 n.m 2

GND2 D5 LCDC_RED7[2] [16]
2

C5 100K LCM_LDO_EN[2,9] 4 1 R933 LCM_LDO_EN_CON

ADD LVDS EMI
3

R939 GND3 A2 B2 1 2
F5 GND4
n.m D3 K5 R938 0R 1 VDD_LCM 6 2 C940
GND5 D7 LCDC_GRN0[2] [16] 1 OE GND
G3 K6 2 100nf
GND6 D8 LCDC_GRN1[2] [16] 2
C3 J6 ADD LVDS EMI 3 C935 C936 C937 C938 C960 NTS0102GT
1

GND7 D9 LCDC_GRN2[2] [16] 3

H3 G5 2-1L1B/SMD/SSM3K35MFV 4 33pf 100nf 1uf 10uf n.m
GND8 D12 LCDC_GRN3[2] [16] 4
3

B1 GND9 D13 G6 LCDC_GRN4[2] [16] U921 RUM002N02T2L 5 5

J5 GND10 D14 F6 LCDC_GRN5[2] [16] ICMEF062P900MFR 6 6
R937 0R U305
D10 H4 LCDC_GRN6[2] [16] 2 DISP_PWR_EN [2] 1 7 7 LCM_3P3
H6 LVDS_ACLK 1 3 LVDS_ACLK_CON 8
2

D11 LCDC_GRN7[2] [16] 8

9 9 B

2
LVDS_A0 H2 Y0P LVDS_ACLK# 2 4 LVDS_ACLK#_CON 10 10
LVDS_A0# H1 E5 11 R936
Y0M D15 LCDC_BLUE0[2] [16] 11
5
6

LVDS_A1 G2 D5 R982 12 n.m

Y1P D18 LCDC_BLUE1[2] [16] 12
LVDS_A1# G1 C6 100K 13
Y1M D19 LCDC_BLUE2[2] [16] 13
LVDS_A2 E2 B6 14

1
Y2P D20 LCDC_BLUE3[2] [16] 14
LVDS_A2# E1 Y2M D21 B5 LCDC_BLUE4[2] [16] 15 15
LVDS_A3 C2 Y3P D22 A6 LCDC_BLUE5[2] [16] LVDS_A0 1 3 LVDS_A0_CON 16 16 LCM_LDO_EN_CON
U922
LVDS_A3# C1 Y3M D16 E6 LCDC_BLUE6[2] [16] 17 17
LVDS_ACLK D2 D6 LVDS_A0# ICMEF062P900MFR 2 4 LVDS_A0#_CON 18 R / 0 / 0201
CLKP D17 LCDC_BLUE7[2] [16] 18
LVDS_ACLK# D1 19 LVDS_A0#_CON R932 LCM_LDO_EN[2,9]
CLKM 19
5
6

1 2

2
20 20 LVDS_A0_CON
A5 21 R931
[16] LVDS_SHUTDOWN_N [2]
R943

R902
0R

0R
B3

A2
SHTDN#
D23
D24
D25
A4
B4
A3
LCDC_HSYNC [2] [16]
LCDC_VSYNC[2] [16]
U923
ICMEF062P900MFR
Main LCM 21
22
23
22
23
24
LVDS_A1#_CON
LVDS_A1_CON
n.m

1
[16] LCDC_PCLK[2] CLKIN D26 LCDC_DEN[2] [16] 24
LVDS_A1 1 3 LVDS_A1_CON 25 25 LVDS_A2#_CON
26 26 LVDS_A2_CON lvds clk swaped .EVT
SN75LVDS83BZQLR LVDS_A1# 2 4 LVDS_A1#_CON 27
27
28 28 LVDS_ACLK#_CON
5
6

C907 R914 29 LVDS_ACLK_CON

n.m 100K 29
TP960 TP961 TP962 U924 40 40 30 30
TP/SMD/0.5MM TP/SMD/0.5MM TP/SMD/0.5MM 41 31 LVDS_A3#_CON BL_PWM_CON
ICMEF062P900MFR 41 31
32 32 LVDS_A3_CON
LVDS_A2 1 3 LVDS_A2_CON 33 R924
33
34 34 BL_PWM[2,9] 2
LVDS_A2# 2 4 LVDS_A2#_CON 35 n.m
35 R930
36 36 LCM_ID[2]
5
6

37 1 2 0R
37

2
U925 38 38
2

39 R934
ICMEF062P900MFR 39 A
R960 n.m
LVDS_A3 1 3 LVDS_A3_CON n.m

1
LVDS_A3# 2 4 LVDS_A3#_CON XF3H-3955-31AR
1
5
6

Title
09 LCD
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 9 of 17

5 4 3 2 1
 5 4 3 2 1

MT6628_PMU MT6628_BT/WiFi ANT1001 ANT1002

ANT_1.2X2.5 ANT_1.2X2.5

WIFI/BT/GPS
R1081
Single ANT Ref.

1
1

1
1 2
L / NC / 0402
VBAT_6628 U1002
CON1001
50 Ohm
50 Ohm 6 5 WIFI/BT_RF 1 50 Ohm WIFI_BT_ANT
U1001-A R1002 0R R1080 n.m
50 Ohm 2 1 50 Ohm 6 ANT__RF

2
D1097
(IMAX_450mA)

1
L2 n.m C1002 4 3 3 50 Ohm GPS_RF
AVDD55_MISC GPS_RF

GND
GND
GND
GND
GND
GND
C / NC / 0402 L1002 C90-101

2
n.m
K1 H2 D

2
4
5
7
8
9
C1080 AVSS55_MISC AUX_REF
DGLT36M07_EPCOS

2
4.7uF

C1003 1uf L1 F1 TP1001 TP / 30mil

VREF RF_I_CAL
Optional: L1005 for better ESD performance

C1001 100nf J3 G3 GPIO_6628_PMU_EN

(IMAX_10mA) AVDD25_V2P5NA PMU_EN

L5 H3 R1001
(IMAX_5mA) AVDD28_PLL PMU_DSB 1M
C1005
U1001-B
1uf
G2 AVDD25_V2P5
AVDD25_V2P5 (IMAX_10mA)
(IMAX_5mA)
K5 LDM182G4505EC015 R1003 0R A1
AVSS28_PLL F1001 RF_IOP_WBT

(IMAX_200mA) A3 WFLDO
AVDD33_TX_WBT

4
(IMAX_300mA) AVDD17_CLDO_IN J2 AVDD17_SMPS
K3 C1009

NC

GND

BP
AVDD55_SMPS

1
C1016 1uf
C1010 C1006 C1007 B2 10pF
4.7uF 2.2pF NC AVSS33_PA

DC
L1001

BP

2
I/O
(IMAX_300mA) LXBK L3 LXBK1 2 AVDD17_SMPS AVDD17_SMPS
J4 C1011 WIFI_BT_ANT C1012 18pF

3
AVSS55_SMPS 2.2uH 4.7uF
(IMAX_300mA) AVSS33_PA A2
R1004 0R B1
C1013 10pF RF_ION_WBT

(IMAX_100mA) CLDO K2 MT6628_WiFi/BT

AVDD28_TLDO J1 AVDD28_TLDO buck output current loop keep as short as possible
C1014
1uf C1015 1uf WFLDO WFLDO

L4 CLDO
(IMAX_200mA)
(IMAX_10mA) WFLDO CLDO
AVDD28_TLDO_SW H1 AVDD28_TLDO_SW ANTSEL2 F3 TP1081 TP / 30mil
C1046 D1
C1017 LNA_IN_EXT
1uf ANTSEL1 F4 TP1080 TP / 30mil
1uf
MT6628_E1_WLCSP ANTSEL0 F2 TP1002 TP / 30mil

AVDD16_TRX_WBT

AVDD16_SX_WBT
AVDD16_LF_WBT

AVSS16_LF_WBT
WFLDO
(IMAX_300mA) C3
WFLDO VCO_MON_WBT
buck input current loop (K3 and J4) keep as short as possible

AVSS16_WBT

AVSS16_WBT
AVSS55_SMPS (J4) connect to bypass cap first and to GND C1018
2.2uf

MT6628_E1_WLCSP

D2

E1

D4

E2

C2

B3
C1019

10pF

C1020

10pF

C1021 C1022

1uf 100nf

AVDD17_SMPS AVDD17_SMPS

MT6628_GPIO MT6628_GPS / FM
C1023
AVDD28_TLDO_SW MT3332_GPS_RF [11]11
1 2
WIFI_Host 0 SDIO TCXO/SMD/2.5X2.0/IT2205BE
C / NC / 0201
ANTSEL-2 1 SPI (IO Level) VDD1V8_6628 Murata/XWTS27NSC12018712/26M
10 GPS_26M[11]
C1024 U1003
100nf 2 NC
C1025 NC 5
C1026
4 6 R1006 0R AVDD28_TLDO_SW
00 TCXO (MSDC IO Level) VDD1V8_6628
OUT VCC
SDIO_CMD

U1001-C
SDIO_CLK

3 1 C1028 B
MC3DA0

MC3DA1

MC3DA2

MC3DA3

01 Xtal C1027 C1029 1nf GND GND 100nf

Xtal/OCS GNSS SAW Filter 1uf

1
100nf U1004 C / 2.2 / pF / 0201
10 EXTCK U1005 2 4
ANTSEL-1 (b`0) C1030 C1031 GND VCC C1033
EPCOS LZ97A L1003 L1004

2
11 RESERVERD GPS_RF 1 4 3 6 A7 C1034
IN OUT RF_IN RF_OUT RF_IN_GPS
G
G
G

5.6nH 6.2nH A4 GPS_26M CLK2_WCN

OSC_IN 1 2 CLK2_WCN[6,10]
10,6
GPIO_6628_GPS_LNA_EN
5 ENABLE 1
C8
H7

H6

H5

H4

2
3
5
J7

J5

J6

U1001-E 18pF 18pF GND 33pf

1

C1032 n.m
n.m
SDIO_CLK

SDIO_CMD

SDIO_DAT0

SDIO_DAT1

SDIO_DAT2

SDIO_DAT3

DVDDIO

DVDDIO_SDIO

[NXP]BGU7005
2

BT/COM Host 0 UART MT6628E2 Infineon LNA

UART_RTS 1 SDIO MT6628E2 E10 RTCCLK_O R1007 AVDD28_OSC A5 AVDD28_TLDO
C1048 C1035
R1020 NM AVDD17_SMPS AVDD17_SMPS A6 10pF 100nf
n.m AVDD16_RF_GPS
10,11,3 RTC32K2V8 [3,10,11] F10 RTCCLK AVSS28_OSC B5

D9 R1008 10K
BT/COM Host 0 SDIO MT6628E1 UART_RTS C1047 C1038
VRTC_6628 G9 E9 TP1003 TP / 30mil 100nf 10pF G4 R1009 OSC_EN
ANTSEL-0 1 UART MT6628E1 VCCRTC UART_CTS OSC_EN 1 2

1
C1039 F9 UTXD3 n.m
100nf UART_RXD R1010
G7 E8 URXD3 C7 R / 9.1 K / 0402
AVSSRTC UART_TXD TEST_GPS
B6

2
AVSS16_HF_GPS
CLDO CLDO G5 DVDD I2S_CLK F8 I2S_CLK_6628 C6 AVSS16_LF_GPS AGPS_SYNC B9 GPIO_6628_GPS_SYNC
MT6583 <==> MT6628 Connector E7 I2S_WS_6628
R1011 0R C1040 C1041 I2S_WS
VBAT VBAT_6628 E6 DVDD
100nf 100nf D7 I2S0_DAT_IN MT6628_E1_WLCSP
R1012 0R I2S_DATA_OUT
VRTC VRTC_6628
VDD18_6583 R1013 0R VDD1V8_6628 C9 DVDD
2 DAIRST [2,10] DAIRST PCM_CLK A10 DAICLK

2 EINT8_6628_BGF [2,10] EINT8_6628_BGF PCM_OUT B10 DAIPCMIN

2 EINT_6628_WIFI [2,10] EINT_6628_WIFI
10,11,3 RTC32K2V8 [3,10,11] RTC32K2V8 [3,10,11]10,11,3 G6 DVSS PCM_SYNC D10 DAISYNC
10,6 CLK2_WCN[6,10]
F7 DVSS PCM_IN A9 DAIPCMOUT
2 MC3CLK
[2] R1014 0R SDIO_CLK
FSOURCE_WR

R1015 0R U1001-D
2 MC3CMD
[2] SDIO_CMD C10 DVSS1
BGF_INT_B
WIFI_INT_B

SYSRST_B

2 MC3DA0
[2,10] MC3DA0
2 MC3DA1
[2,10] MC3DA1
XTEST

2 MC3DA2
[2,10] MC3DA2
2 MC3DA3
[2,10] MC3DA3 L1082
TP/SMD/0.5MM AVDD28_FM H9 AVDD28_FM AVDD28_TLDO
TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM
TP1085
TP/SMD/0.5MM
TP/SMD/0.5MM
TP1082 TP1083 TP1084 MT6628_E1_WLCSP H10 BLM15AG221SN1D
B8

H8

K7

L7

G8

SALNA_IN_N_VSS
2 UTXD3[2,10] UTXD3
2 URXD3[2,10] URXD3
J9 C1049 A
AVSS28_FM 100nf
EINT8_6628_BGF

2 DAICLK[2,10] DAICLK
EINT_6628_WIFI

2 DAIPCMOUT [2,10] DAIPCMOUT J10 SANT_P AVSS28_FM J8

2 DAISYNC [2,10] DAISYNC
2 DAIPCMIN [2,10] DAIPCMIN
DAIRST

2 GPIO_6628_GPS_SYNC [2,10] GPIO_6628_GPS_SYNC C1043

2 SRCLKENAI [2] R1016 0R OSC_EN GND close to
2 GPIO_6628_PMU_EN [2,10] GPIO_6628_PMU_EN 4 FM_RX_N_6628 [4] K10 LNA_IN_N_VSS AUROUT K8 AUROUT_6628 AU_FMINR
Audio Jakc
1

2 GPIO_6628_GPS_LNA_EN [2,10] GPIO_6628_GPS_LNA_EN

R1017
R1018 0R n.m 1uf
2 I2S0_CK
[2] I2S_CLK_6628
2 I2S0_WS
[2] R1019 0R I2S_WS_6628
L1006
2

C1044
2 I2S0_DAT_IN
[2,10] I2S0_DAT_IN 4 FM_ANT [4] LANT_P L10 LANT_P
27nH L8 AULOUT_6629 AU_FMINL
AULOUT
3 AU_FMINR [3,10] AU_FMINR L1007
C1045 1uf
3 AU_FMINL [3,10] AU_FMINL 0.1uH
10pF MT6628_E1_WLCSP
Title
10 BT, FM, GPS, WiFi (MT6620)
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 10 of 17

5 4 3 2 1
 5 4 3 2 1

RTC Voltage (2.8V)

R1102

VRTC GNSS_HOST_VRTC
D D
0R
RTC_CLK (2.8V Voltage Swing)
10,3 RTC32K2V8 [3,10,11] RTC32K2V8 [3,10,11] 11

15,2 URXD1[2,15] R1103 0R

GNSS_UART_TX [11]11

15,2 UTXD1[2,15] R1104 0R GNSS_UART_RX [11]11

C1119
MT3332 on-chip LNA 10 GPS_26M[10]
Matching
n.m

L1102 3 1
C1103 GND GND
3.3nH
C1102
1

4 6 R1105 0R GNSS_VTCXO_SW
OUT VCC
NC
2 5
2

C1104 1nf NC NC C1105

10 MT3332_GPS_RF [10] U1102 1uf
Murata/XWTS27NSC12018712/26M
1.2pF

C C1106 C1107 C
GNSS_DCV_1V8

GNSS_DCV_1V8
GPS_RFIN

4.7nF 4.7nF
1.8V / 2.8V IO Voltage Selection

VBAT
3.3V LDO 2.8V IO : R5 = 0 , R6 = NC (IO voltage is VTLDO)
R1101
1.8V IO : R5 = NC , R6 = 0 (IO voltage is SMPS_1V8)
48

49
1

VBAT 1 IN OUT 5 GNSS_VGNSS_MAIN

47
RF_IN

AVDD18_RXFE

T1P

OSC

AVDD18_CM

T1N

MAIN_GND

U1101 HRST_B GNSS_HRST [2] 2

2 GNSS_VGNSS_MAIN R1106 n.m
C1101 GND C1108 0R
XTEST 46
4.7uf 3 4 4.7uf
2 GNSS_LDO_EN [2] EN BYP
IF[2]/EINT0/GIO12 44

U1103 C1109 1uf 9 45

AVDD43_VBAT IF[3]/EINT1/GIO13
2

Torex XC6215B332MR-G 36
C1184 C1110 1ufGNSS_VREF 7
EINT2/GIO14 Reserved for GPS HRST from host,
VREF
NC connect to Host (MT62xx) GPIO pin
1

Connect to Host GPIO Pin

GNSS_VTCXO_SW

GNSS_VTLDO
10

11
AVDD_TCXO_SW

AVDD28_TLDO
MT3332 DVDD11_CORE2

DVDD11_CORE3
24

43
GNSS_CORE_1V1

1 C1113
2
C1111 NC
C1112 8 6
U4 without output high-speed discharge function, then
tdrop-down (2.7V-to-0.5V) > 50ms.
C19 is close to pin11
1uf AVSS43_MISC

QFN-48pins DVDD11_CORE1

DVDD28_IO1 30
2.2uf
GNSS_VTLDO
Please use MTK qualified LDOs, such as Torex XC6215/XC6221. R1107 NC
42 C1114 R1108 0R GNSS_DCV_1V8
DVDD28_IO2
GNSS_DCV_1V8 12 AVDD28_CLDO 100nf
C21 is close to pin13
GNSS_CORE_1V1 13 AVDD11_CLDO
B B
GND 29
C1115
1uf GNSS_VGNSS_MAIN 34
JRCK/GIO10
C1116
SCK1/GIO4/F_SCK/EE_SC_L

JDO/GIO9 39
pin14 connet to C22 GND net first, 4.7uF
RX2/GIO2/F_SI/EE_SDA

then connect to reference GND 16 AVDD43_DCV IF[1]/JDI/GIO8/SYNC 33 GNSS_FRAME_SYNC [2] 2

R1109 NC
SCS1#/GIO5/F_SCS

14 26
TX0/H_SO/I2C_DA

AVSS43_DCV IF_CLK/JCK/GIO6
RX0/H_SI/I2C_CK

RX1/GIO0/H_SCK

LQM2MPN1R0NG0
TX1/GIO1/TXIND

TX2/GIO3/F_SO
AVDD43_RTC

AVDD11_RTC

GNSS_DCV_1V8 GNSS_DCV 15 DCV IF[0]/JMS/GIO7/PPS 40

FORCE_ON

L1101 Reserved for improving GNSS Hot-Start performance.

32K_OUT

R1190 17 38
DCV_FB JRST_/GIO11/H_SCS
XOUT
XIN

C1117 0R
4.7uf
23

22

19

18

21

20

37

35

25

27

28

32

31

41

MT3332/MQFN48/SMD/P0.4/6X6
R1191 MT3332 QFN (48 Pins, 0.4mm pitch)
NC

R1110 R1111
10K
NC
GNSS_VGNSS_MAIN C1118 NC
Reference Frequency Selection
1 2

R1112
0R
GNSS_UART_RX
GNSS_UART_TX

EINT_MT3332

16.368MHZ TCXO : R9 = NC , R10 = NC

26MHZ TCXO : R9 = 10K , R10 = NC
[2]

2
[11]

[11]

26MHZ XTAL : R9 = 10K , R10 = 10K

A A
11
RTC32K2V8
GNSS_HOST_VRTC
[3,10,11]

Connect GNSS_HOST_VRTC to always alive voltage source, and keep the

As EINT to Host
11

11

voltage swing of GNSS_HOST_32K RTC clock same as GNSS_HOST_VRTC.

[11]

Title
Connect to HOST UART (TX/RX) interface 11 GNSS-MT3332
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 11 of 17

5 4 3 2 1

R0402
R0402/SMD
 5 4 3 2 1

SDV 08/25

SIM1 & SmartCard

D1201 D1202
D PESD5V0S1BL
PESD5V0S1BL D1203 D1204 D
PESD5V0S1BL
PESD5V0S1BL
/ 40mil

TP / 40mil

TP / 40mil
TP1210

TPTP1212

TP1213
TP / 40mil

SD CARD
TP1211

10

U1201
G

3 SIM1_CLK[3] R1201 0R 6 1 R1202 0R

CLK I/O SIM1_DATA [3]3

3 SIM1_RST [3] 5 RST VPP 2

VSIM1_PMU 4 VCC GND 3

G
G
G

C1201 VMCH_PMU
7
8
9

100nF
EVT 11/05
SIMF006G5K46-00R
Shielding connect to ground
R1204
0R
U1202
2 MC1DA2[2] R1214 0R 1
DAT2
2
2 MC1DA3[2] R1215 0R 2
CD/DAT3
MC1CM[2] R1216 0R 3
SIM1 & SmartCard
2 CMD
2 4
VDD
2
MC1CK[2] R1217 0R 5
CLK
6
VSS
MC1DA0[2] R1218 0R 7
DAT0
D1212 D1213 MC1DA1[2] R1219 0R 8
DAT1
TP / 40mil

TP / 40mil

TP / 40mil

TP / 40mil
TP1260

TP1261

TP1262

TP1263

PESD5V0S1BL
PESD5V0S1BL D1214 D1215
C PESD5V0S1BL
PESD5V0S1BL 9 C
GND
10

U1203 10
GND
G

3 SIM2_CLK[3] R1206 0R 6 1 R1207 0R

SIM2_DATA [3]3 11
CLK I/O D1
R1220

3 SIM2_RST [3] 5 2 12
RST VPP D2
R1221

VSIM2_PMU 4 VCC GND 3

0R
G
G
G

C1203 TF001-22112A81
7
8
9

0R

100nF

SIMF006G5K46-00R D1206 D1207 D1208 D1209 D1210 D1211 C1202 MC1INSI [2]
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL
PESD5V0S1BL 4.7uf

D1221
PESD5V0S1BL

USB HS IF

B B
TP1202 TP1203
IDPULLUP pin is replaced by 1.2V power source. TP / 40mil
TP / 40mil UB007-24123A52

VLS252010T-4R7M (4.7uH)
L1201
USB OTG Power R1209 0R
5

4
GND
11
2 USB_ID[2] ID GND
L/IND/SMD/LVS252010-2R2 10
U1204 2 USB_DP[2] R1210 GND
1 2 3 DP GND 9
1 SW OUT 5 VBUS R1212 GND 8
2 USB_DM[2] 1 2 2 DM GND 7
R1211 0R 6 4 6
VBAT VCC NC GND
C1204 C1206 1
C1205 100nf 10uf VBUS
2 GND EN 3
10uf
SGM6605-5.0 J1201
16V rating 95 ohm differential TP1201
TP / 40mil
R1213 0R
14,2 GPIO_USB_DRVVBUS [2,14]

VBUS

R1260
100K D1216 D1217 D1218 D1219
D / RB551V-30 PESD5V0F1BL
PESD5V0F1BL
PESD5V0S1BL
RB551V-30(UMD2)

A A

Title
12 SIM, T-FLASH, USB
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 12 of 17

5 4 3 2 1
 5 4 3 2 1
VDD18_6583

R1302
0R

G-Sensor R1303 C1302 C1303

NOTE C: R2054 0 for ADI,NM for KIONIX n.m 100nF 2.2uf
VDD18_6583

ALS & P Sensor EVT 10/26 modified

D R1301 U1302 D
16

15

14

0R
VDD28_6583
RES

NC

VDD

VDD18_6583
1 IOVDD RES 13
C1301 2 12
100nF RES GND
C1306
3 DNG INT 11 EINT_G [2]2 1uf R1306
R1304

4.7K
4 SCL RES 10 CON1311
0R

5 9 R1307 n.m 1
GND RES EINT_G2 [2]
2 1
SDA

RES

2
NC

2 SCL3[2,13]
3 3 SDA3[2,13]
NOTE A: C1304/C1305 22OnF for ST,NM for KIONIX KXTIK-1004 4 4 EINT_A [2]
6

NOTE D: R2055 0 for ADIºÍSTµÄINT2,NM for KIONIX 5 5

R1308 n.m 4.1x2.5

GYRO_SDA

GYRO_SCL R1309 n.m R1310

n.m R1312
0R
SCL3[2,13] R1313 0R NOTE B: R2053 0 for ADI,NM for KIONIX
13,2
SDA3[2,13] R1314 0R
13,2
VDD18_6583

accelerometer,I2C mode:0001111

Gyro Sensor I2C Address: 0x68 (Write:0xD0, Read:0xD1) M-Sensor VDD18_6583

VDD28_6583

C C

C1307 R1315
2.2nf 0R
13,2 SCL3[2,13]
13,2 SDA3[2,13]
R1316
0R
VDD18_6583
25
24
23
22
21
20
19

U1303 YAS532B C1308

A2 C1 10nf
GND
SDA
SCL
CLKOUT
RESV
CPOUT
RESV

IOVDD SDA
B2 SCL VSS B1
R1317 R1318 1 18 C1309
n.m n.m CLKIN GND 470nf
2 NC NC 17 C2 VDD INT A1 EINT_M [2]2
3 NC NC 16
4 NC NC 15 U1304
5 NC NC 14 SDA3[2,13]
13,2
GYRO_SDA 6 13 R1329 0R VDD28_6583
IME_DA VDD
REGOUT
VLOGIC
IME_CL

SCL3[2,13]
13,2
FSYNC

C1319 C1310
AD0

22pf 100nF
INT

MPU-3050
7
8
9
10
11
12

GYRO_SCL QFN30/SMD/MPU-3000
EINT_GY [2] 2
VDD18_6583 R1320 0R

C1311 C1312 Sync to Camera key

10nf 100nF

B
Thermal Sensor A Thermal Sensor B B

need check with ME/ANTENNA

VDD18_6583 VDD18_6583

1 1
ANT1301

ANT_1.2X2.5
SARS Sensor VDD18_6583
R1330
0R
R1331
0R
U1305 U1306

R1325 A1 B1 A1 B1
V+ SDA SDA6[3,13,14]
13,14,3 V+ SDA SDA6[3,13,14]
13,14,3
R1324 4.7K
330R A2 B2 A2 B2
VGP6_PMU GND SCL SCL6[3,13,14]
13,14,3 GND SCL SCL6[3,13,14]
13,14,3
P Sensor R1326
U1307
CAP_SNS_ANT 6 5 VDD_SAR n.m n.m
R1327 0 CX VDDHI
2 SARS_TOUT [2] CAP_SNS_OUT 1 OUT
3 CTRL 0R
CAP_SNS_VREG 4 VREG VSS 2
C1313 IQS128TSR-GP
10pF
C1314 C1315 C1316 C1317
1uf 33pf 33pf 1uf
TP1391
SARS_POUT TP/SMD/0.5MM

reserve function

A A

Title
13 Sensors
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 13 of 17

5 4 3 2 1
 5 4 3 2 1

D
Switching Charger
D

VBUS VBUS_1
R1401 0R

C1460 C1461
1uf 100nf

VBUS_1
L1402
SPM3012T-2R2M
U1401 3230L_2.2UH_SPM3012T-2R2M_2.5A

A1 IN SW C2
A2 IN SW C1
C1410
C C1407 4.7uf B1 100nf C
CAP R1402
B2 CAP CBOOT E1
68m
C1408 2.2uf VDD_CORE_1851 E3 D3
VDD18_6583 CORE SENSP
E2 TRANS SENSN D4
C1409 VDD_CORE_1851R1413 n.m E4 R1404 0R VBAT
100nf 1
R1412 2
0R WEAK
C4 ILIM1 FET D5
R1419 E5
10K R1414 0R BAT
VDD_CORE_1851 B4 ILIM2
R1415 n.m C1402
1 2 10uf
R1416 n.m
12,2 GPIO_USB_DRVVBUS [2,12] B3 OTG
3 EINT_CHG_STAT [3] B5 FLAG NTC C5
13,3 SCL6[3,13] A5 SCL PGND D1
13,3 SDA6[3,13] A4 SDA PGND D2
3

4
7

R1418 0R Q1401
3 GPIO_CHG_EN [3] A3 SPM AGND C3
G

S
S

NCP1851FCT1G
R1420 n.m
3 GPIO_SPM [2] 1 2 R1417
D
D
D
D
D

100K
1
2
5
6
8

NTLUS3A40PZ
B B

VBAT_SUPPLY
R1423 n.m R1424 n.m BAT_NTC [3]
1 2 1 2 Differential

VBAT_SUPPLY R1425 0R ISENSE [3]

VBAT R1426 0R BATSNS[3]

A A

Title
14 Switching Charger
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 14 of 17

5 4 3 2 1
 5 4 3 2 1

D TP1513 TP1514 D
TP / 40mil TP / 40mil

TP/SMD/0.5MM
TP1507
TP1508 TP1509
TP / 40mil
TP / 40mil SH1 SH2 SH3 SH10 SH12 SH13
CON1501
GND 1 GND 1 GND 1 1 1 1
GND GND GND
3,15 PWRKEY [2,3,8] 2 1 GND 2 GND 2 GND 2 2 2 2
R1501 0R GND GND GND
2,3,9 SYSRST_B [2,3] 4 3 GND 3 GND 3 GND 3 3 3 3
GND GND GND
3,15 KCOL0[3,8] 6 5 URXD1 URXD1[2,11] 11,2 GND 4 GND 4 GND 4 4 4 4
GND GND GND
3,15 KROW0 [3,8] 8 7 UTXD1 UTXD1[2,11] 11,2 GND 5 GND 5 GND 5 5 5 5
GND GND GND
10 9 URXD2[2] 2
12 11 UTXD2[2] 2 818000135 818000135 818000135 818000135 818000135 818000135
TP1511 TP1512 14 13 URTS1 URTS1 [2] 2
TP / 40mil TP / 40mil 16 15 UCTS1 UCTS1[2] 2
18 17 MCU_JRTCK MCU_JRTCK [2] 2 SH4 SH5 SH6
C C SH15 SH16 SH17
20 19 MCU_JTDO MCU_JTDO [2] 2
22 21 MCU_JTMS MCU_JTMS [2] 2 GND 1 GND 1 GND 1 1 1 1
GND GND GND
24 23 MCU_JTDI MCU_JTDI [2] 2 GND 2 GND 2 GND 2 2 2 2
GND GND GND
2 URXD4[2] 26 25 MCU_JTRST_B MCU_JTRST_B [2] 2 GND 3 GND 3 GND 3 3 3 3
GND GND GND
2 UTXD4[2] 28 27 MCU_JTCK MCU_JTCK[2] 2 GND 4 GND 4 GND 4 4 4 4
GND GND GND
30 29 GND 5 GND 5 GND 5 5 5 5
GND GND GND
32 31
34 33 818000135 818000135 818000135 818000135 818000135 818000135
36 35
38 37
40 39 TP1501
TP1502
TP1503
TP1504
TP1505
TP1506 SH7 SH8 SH9 SH18 SH11 SH14
TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM
TP/SMD/0.5MM
GND 1 GND 1 GND 1 1 1 1
GND GND GND
2 2 2
41
42
43
44

GND GND GND GND 2 GND 2 GND 2

AXT440124 3 3 3
GND GND GND GND 3 GND 3 GND 3
CON20X2/SMD/M/AXT440124 4 4 4
GND GND GND GND 4 GND 4 GND 4
GND 5 GND 5 GND 5 5 5 5
VDD18_6583 GND GND GND
B TP1510 B
818000135 818000135 818000135 818000135 818000135 818000135

TP/SMD/0.5MM

A A

Title
15 Debug
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 15 of 17

5 4 3 2 1
 5 4 3 2 1

MT6575 11HX4_V1.1 Phone w mDDR

OH
micro SD MCU JTAG
D
MCP 4Gb + D
4Gb mDDR
MSDC1 JTAG APUART1_4 MDUART1_2 EMI, NFI IQ, BSI, BPI

I2C, EINT
Capacitive
Touch Panel

LCM DSI PCM, UART3, I2S

FM_LINE

MSDC1
4-in-1
PWM
Backlight MT6620 Speaker (HPRP)
Driver Class D /
Class AB

Flashlight
Driver
C C

Main Camera Camera IF, I2C

parallel
MT6388
Camera IF, I2C MT6320
Sub Camera
Headset (HPLP, HPRP, MIC3)

MIC1
Charger

BJT

SIM1
B SIM1 Fuel Guage
B

USB micor USB

SIM2
SIM2 Battery

KCOL I2C
KROW EINT

Sidekey

G Sensor
M Sensor
ALS, PS,
Gyro
A A

Title
16 Block Diagram
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 16 of 17

5 4 3 2 1
 5 4 3 2 1

Item Category Description SW Modification

V1.0 initial version
V1.1
page 9:delete U901 U902;add U921-U925;swap LVDS clk pins for lcm connector
page 4:C413 C414 change to 0201 size
page 7:Change RF3236 to SKY77590
page 8:delete SW802 SW803
page 13:add con1311,delete R1305 U1301 C1318,als&p-sensor change to place on fpc
page 3:delete TP381-385
page 12: U1202¸ü¸ÄΪTF001-22112A81£¬ADD R1220 R1221 D1221
D D
page 3: ADD R360 R361
page 3: ADD R260 R261 R262 R263 FOR board ID
page 5: Delete U502
page 3: Delete R351 R355 R354 R352 R353 R350 U303 U304
page 4: add C460 C461 L460 REC460
page 3: add R362
page 4: delete D401 D402 D403 D405,add R460 R461
page 3/4: ADD R368, speaker audio ÊäÈëα²î·ÖÊäÈë
page 3:add C361 C362 C363 C364
pag10 :L1001 ¸ü¸ÄΪLQM2MPN2R2NGOL
pag14 :L1402 ¸ü¸ÄΪSPM3012T-2R2M
pag15 :ADDÆÁ±ÎÕÖ¼Ð×ÓSH10-SH18

pag5:U501 B8 pin ÓëR502Á¬½ÓÔö¼Ónet Ãûemmc_vccq

pag9:ADD C960,R960 /n.m
pag3:R339 R340ÉÏÀ-ÖÁÐÞ¸ÄÖÁVDD18_6583
pag3:add D384
pag3:Delete C342
page12:add sim test point TP1210-1213,TP1260-TP1263
page14:ɾ³ýC1401£¬Ôö¼ÓC1460 1u,C1461nF
page12:R1210 R1212 change to 0ohm/0402

page6:delete C633,add R660 R661

page6:delete C710 L622
page6:delete u608 ,Ôö¼ÓTCXO U660¼°Ïà¹Øµç·

page12:ADD R1260, delete R1205 R1208

page9:ADD TP960 TP961 TP962,Delete J901 pin6 µ½µØÁ¬½Ó

C C

B B

A A

Title
17_Change_Notice
Size Document Number Rev
A0 Altay 0.1

Date: Monday, October 15, 2012 Sheet 17 of 17

5 4 3 2 1