CURRENT CONTROL AND CAPACITOR VOLTAGE BALANCING IN A FIVE-
LEVEL INVERTER FOR DSTATCOM APPLICATION
Mr. K. Jaganath and Mr. Mahesh K. Mishra
Indian Institute of Technology Madras, Chennai.
Abstract—In this paper, a slope based hysteresis
current control technique and capacitor voltage
balancing for a five level neutral clamped inverter in
distribution static compensator (DSTATCOM) are
proposed. As the number of levels in a voltage source
inverter(VSI) increases, average error which is
the difference between the reference current and actual
current also increases, due to the increase in hysteresis
and dead bands. This method reduces the average
error. The slope of the reference current is tracked and
a change in slope marks the transition across the lower
band and upper band. Similarly, with every increase in
the level of the inverter, due to unequal flow of
capacitor current caused by switching logic and
average neutral current, balancing capacitor voltages
become very inherent. In this work, a simple external
balancing circuit consisting of aninverter-chopper
arrangement is employed, to correct capacitor
voltages irrespective of the nature of loads.
Index Terms—Capacitor voltage balancing, DSTATCOM,
Multilevel inverter, Slope based hysteresis current
control.
INTRODUCTION
Distribution STAtic COMpensator (DSTATCOM)
is becoming increasing popular for their reactive
power compensation, load balancing and
harmonic elimination [1]. DSTACOM’s are also
used in voltage regulation and voltage flicker
mitigation [2]. DSTATCOM finds importance
these days as there are rapid load variations
which leads to flow of more reactive power
oscillations. The usage of power electronic loads
introduces non-linearities in currents which
generates quite a high amount of harmonics. For
operation of DSTATCOM, a number of control
algorithms have been presented in literature for
generating the desired reference currents from
voltage source inverter (VSI) based DSTATCOM
for compensation. Among them, hysteresis
current control technique is commonly used due
to its ease in implementation, peak current
limiting capability, fast dynamic response and
independent of system parameters [3]. Major
disadvantages of hysteresis control are wide
variation in switching frequency and increased
switching losses in the inverter switches due to
the former. Optimal width of hysteresis band is
required for limiting the switching frequency and
for reducing the tracking error, which is the
difference between the reference current and
actual current, produced due to tracking. More
the hysteresis bands lesser the switching
frequency and more the tracking error, lesser the
hysteresis band, vice versa.
Multi-level inverters are popularly used in various
applications because of their advantages listed in
[4], [5]. A diode clamped five-level neutral
clamped VSI is used for its advantages
mentioned in [4]. The motive to use multilevel
inverter includes lower switching frequency and
high power applications. The use of hysteresis
control in multilevel inverter based DSTATCOM
is described in [6]. In this work, a slope based
hysteresis current control, for tracking the
reference current has been described. The
objective in here is to minimize the tracking error
Σ(ijref - ijact), j=a,b,c where j represents each
phase in the three phase four wire system. The
slopes of the reference currents are calculated
and the transition from lower band to upper and
vice versa depends on the change in slope
together with the magnitude of error. In this paper
a five-level, three-leg, diode clamped, neutral
point clamped (NPC) inverter topology is
considered. Each leg consists of eight switches
with an anti-parallel diode connected across
every switch and six clamping diodes for
clamping capacitor voltages. The midpoint of the
four identical capacitors Cdc is connected to the
neutral wire of the system. The five levels
achievable using the inverter are Vdc/2, Vdc/4, 0, -
Vdc/4 and –Vdc/2, referred to as states +1, +1/2,
0, -1/2 and -1 respectively. Different
combinations of capacitors are selected for
operation of the inverter switches for achieving
the desired voltage levels. Hence, due to
switching logic and average zero sequence
components there are capacitor voltage
imbalance in multilevel inverters. The capacitor
voltage imbalance in the considered five-level
inverter is balanced by using external balancing
circuits as described in [7], [8]. The organization
of this paper is as follows. Section II describes
the slope based hysteresis current control
technique. Section III focuses on the five-level
diode clamped inverter and balancing capacitor
voltages using external balancing circuits. The
paper is concluded in Section IV.
SLOPE BASED HYSTERESIS CURRENT
CONTROL TECHNIQUE
Hysteresis current control is commonly used in
DSTATCOM applications due to their
aforementioned advantages. The basic two level
hysteresis control requires, the error in each
phase to track between two hysteresis bands +h
and -h as described in [3]. In three-level inverters
an additional dead band (δ) is introduced to
accommodate for the zero state. As the number
of level in a VSI increases, the number of
hysteresis and dead bands has to increase for
accommodating the respective number of
achievable levels from the inverter [6]. Due to
this, the tracking error increases as the number
of voltage level increases. With every increase in
h and δ bands, the increase in average tracking
error can be attributed to, taking more time for
the actual current to transit from one band to the
other. If this transition within bands is made
instantaneous, considerable reduction in tracking
error is obtained. This method focuses on the
instantaneous transition from lower band to the
upper band and/or upper band to lower band on
the basis of the slope of the reference current in
each phase. Before and after the transition basic
hysteresis technique is adopted.
The slope based hysteresis current control
technique uses the same band h and δ as in [3]
to track the reference currents. This is illustrated
in Fig. 1 for a three-level VSI. The same
technique is adopted for multilevel inverter with
corresponding increase in h and δ bands.
Reference current
h (i ref)
δ 0
-1 δ elseif refslope < 0 then
h -1
0
1 Else if refslope < 0 then
Actual current
0
(i act)
Slope>0 Slope<0
Figure 1 Slope based hysteresis current control.
One of the main drawbacks in basic three-level
scheme is the average tracking error between
the reference current and the actual current is
high when compared to a basic two level
scheme. This happens because of the
introduction of zero state by the dead band (δ).
The instantaneous error and the average tracking
error are reduced by the improved three-level
scheme [9]. Here, the δ bands are shifted around
the reference current causing an overlap of the
dead bands. This method is mainly suited only
for a three-level inverter. As the number of levels
increase there are more number of δ and h
bands at different current levels. Shifting of δ
bands becomes more complicated and
cumbersome, hence cannot be incorporated. The
slope based current controller is thus designed in
such a way that is independent on level of
inverter. The dead zone bands are near the
reference waveform and the hysteresis bands
are quite a distance from the reference current as
in the basic scheme.
From basic three-level scheme [3], due to the
switching logic, whenever the slope of the
reference current is positive the actual current
tracks the lower band and when the slope is
negative it tracks the upper band. Instead of
transition from lower band to upper band and
vice-versa due to tracking error magnitude alone,
the results of tracking, the reference current is
improved if the transition in made according to
the slope of reference current. The logic for a
slope based hysteresis current control for a
three-level inverter is given.
error = iref - iact
if refslope > 0 then
if (uprevious = -1 or uprevious = 0) then x = 1
if (error ≤ δ and x = 1) then u = -1
if error ≥ h then u = 1
if error ≤ δ then u = 0
(1)
if (uprevious = 1 or uprevious = 0) then y = 1
if (error ≥ - δ and y = 1) then u = 1
if error ≤ -h then u = -1
if error ≥ - δ then u = 0
The logic represented in (1) clearly shows that,
the transition from one band to other is based on
the slope. Flags ’x’ and ’y’ are set in equation (1)
to avoid repetition in the switching logic. Since
the movement is much faster than the basic
three-level inverter the error between the
reference current and the actual current is
considerably reduced. The slope of the reference
currents are just used to track the exact transition
time, the magnitude of the current to be tracked
will depend on the dead and hysteresis bands.
Here, there is a question as to what maximum
value actual currents should be pushed so as to
ensure perfect tracking. For this, consider the
current is tracking upper band and there is a
change of slope. As mentioned in logic the
current should come down to lower band. From
(1) it can be seen that, the current is pushed only
till δ band. This is because of two reasons as
mentioned below.
ƒ If the actual current is pushed to a region
between h and δ and if there is an
immediate change in slope then there
exists no condition in the logic as in (1) for
proper tracking.
ƒ If the current is pushed till h band, then
the switches are unnecessarily operated
for longer time which is not required.
Due to these constraints the reference currents
are pushed till δ band. By doing so there are two
main advantages.
ƒ When the current is pushed till δ band, if
the slope changes, the logic from (1)
pushes the current back to the upper
band.(It is considered that current initially
tracks the upper band).
ƒ The basic three-level switching logic is
effectively utilized. As the actual current
reaches δ band then, as per equation (1)
there is a zero state i.e. when error ≤ δ
occurrence of +1 and -1 states at the time of
transition. This increases the stress across the
switches and is primarily avoided in the basic
multilevel scheme [6]. The occurrence of such a
switching occurs only when the slope of the
reference current changes and the previous input
is either a +1 or -1. Since there is a slope
change, according to (1) there is again a +1 or -1
depending on which band the current is tracking.
With the proposed switching logic, simulation is
carried out for a three-phase four-wire system
using PSCAD. Compensator is a neutral clamped
five-level VSI consisting of three legs having
twenty four IGBT switches (S1i - S8i) where i = a,
b, c and four identical DC storage capacitors
Cdc1, Cdc2, Cdc3 and Cdc4. A single phase
illustration of a five-level VSI is shown in Fig. 2.
Each IGBT switch has an antiparallel diode
connected across it. The inverter is connected to
the point of common coupling (PCC) through
interfacing inductor Lf and resistance Rf. A
Proportional-Integral (PI) controller maintains the
total voltage across the capacitors
(Vdc1+Vdc2+Vdc3+Vdc4) around the reference value
4Vdcref. The source voltages are assumed to be
balanced and sinusoidal as shown in Fig. 3(a).
The loads draw unbalanced and nonlinear
currents from the source, as illustrated in Fig.
3(b). The compensator reference currents (ifa; ifb;
ifc) are extracted using the instantaneous
symmetrical component theory [10] and the
reference current equations are given below.
vsa isa ila
N PCC
n
ifa
S1a
Cdc1 +
vdc1 S2a
- Rf
+
LOAD

S3a Lf
Then u=0. Cdc2
-
vdc2
i0 n S 4a
By increasing the number of h and δ bands, the
same procedure is used for multilevel inverters. ' a
The slope based hysteresis control has also Cdc3 + S5a
vdc3
been simulated on a five-level inverter using - S 6a
PSCAD. As the current level of δ and h bands is +
decreased a better tracking is achieved. This Cdc4 vdc4
- S7a
would in turn increase the switching frequency.
S 8a
Hence, a compromise is arrived between the
achievable frequency and the position of the
respective bands. The problem such as band Figure 2 Single phase five-level diode clamped
violation and finite sampling instants introduces inverter.
higher switching components. One of the primary
limitations of this method is the simultaneous
 * vsa + γ ( vsb − v sc ) ⎫ 350 vsa vsb vsc 13 ila ilb
i fa = ila − isa = ila − ( Plavg + Ploss )⎪ ilc

Voltage (V)

C urrent (A)
∆
⎪
* v sb + γ ( v sc − v sa ) ⎪ 0 0
i fb = ilb − isb = ilb − ( Plavg + Ploss ) ⎬ (2)
∆ ⎪
* v sc + γ ( v sa − v sb ) ⎪ -350 -13
= ilc − isc = ilc − ( Plavg + Ploss )
i fc
⎪ 0 10 Time (ms) 20 0 10 Time (ms) 20
∆ ⎭
(a) (b)
2
Where, ∆= ∑ v sj and γ = tan φ / 3 , φ being the 5 i* ifb*
j = a ,b ,c fa

C urrent(A)
desired power factor angle. For a unity power
factor (UPF) operation, γ =0. The term Plavg, 0
ifc*
which represents the average or mean power of
the load is obtained through a moving average -5
filter (MAF). The losses of the inverter, denoted 0 10 Time (ms) 20
as Ploss are generated using a PI controller. 10 (c) (d)
isa isb isc

C urrrent (A)
0
TABLE I
Simulation Parameters
230 V (L-N rms), 50 -10
0 10 Time (ms) 20
Supply voltages Hz
DC link voltage (2Vdcref) 1200 V Figure 3 (a) Balanced three-phase supply
voltages (b) Unbalanced and nonlinear load
DC capacitors (Cdc) 2200 µF each
currents (c) Compensator reference currents (d)
Compensated source currents.
Interface inductor (Lf, Rf) 20 mH, 1 Ω CAPACITOR VOLTAGE BALANCING IN FIVE-
Hysteresis band (±h) ±0.5 A LEVEL DIODE CLAMPED INVERTER
Dead zone (±δ) ±0.35 A A. Five-Level Diode Clamped Inverter
PI controller gains Kp = 5, Ki = 0.5 Multilevel inverters are growing increasingly due
Full Bridge Rectifier to their advantages mentioned in [5]. There are
Load 168 + j 16 Ω there different topologies in multilevel inverters.
Three pulse rectifier They are diode clamped, flying capacitor and
load 90 + j 48 Ω cascaded H-bridge multilevel inverters [5]. Owing
to advantages of diode clamped multilevel
Za = 39 + j 13 Ω inverter as mentioned in [4], a five-level diode
Unbalanced R-L Loads Zb = 61 + j 19 Ω clamped VSI is used. There are five different
voltage levels namely Vdc/2, Vdc/4, 0, -Vdc/2 and –
Zc = 130 + j 32 Ω Vdc/4, referred to as states +1, +1/2, 0, -1/2 and -
1 respectively. They are obtained by controlling
Parameters chosen for simulation are listed in the respective switches in each leg. A tabular
Table. I. The compensated source currents and column representing the possible switching
filter currents are in Fig. 3(c) and Fig. 3(d). combinations is given below. A schematic
diagram of a single phase five-level diode
clamped inverter is shown in Fig. 2.

TABLE II
Switching Logic For a Single Leg Diode Clamped
Five-Level Inverter
Switch Status Vin
 S1i S2i S3i S4i S5i S6i S7i S8i Fig. 5 is faster and more accurate for
ON ON ON ON OFF OFF OFF OFF 1
compensating voltage imbalance for passive
loads.
OFF ON ON ON ON OFF OFF OFF 1/2
OFF OFF ON ON ON ON OFF OFF 0
OFF OFF OFF ON ON ON ON OFF - 1/2

Voltage (V)
OFF OFF OFF OFF ON ON ON ON -1 Vdc1

B. Capacitor Voltage Balancing Vdc4

Capacitor voltage balancing becomes more
significant as the number of voltage level Vdc3 Vdc2
increases, due to reasons like unequal flow of
capacitor current and average zero sequence
currents. In a two level inverter, capacitor voltage
balancing is not required when the neutral Time (s)
current Io does not have an average component. (a)
Though, capacitor voltage balancing becomes
essential when neutral current have an average
value. But, in the case of a multilevel inverter due
to unequal flow of currents caused due to inverter Voltage (V)
switches, causes imbalance in capacitor voltages V total
even when average neutral current is zero. A
simple external balancer circuit as explained in
[7] is used for correcting capacitor voltages.
Fig. 2 shows a single phase diagram of
DSTATCOM used for compensating an
unbalanced RL load. DSATCOM tracks the Time (s)
reference currents using slope based hysteresis (b)
current control technique as explained above and
the switches are operated according to switching Figure 4 (a) Uncompensated capacitor voltages
logic shown in Table. II. The average current for unbalanced RL load (b)Total capacitor
flowing through the neutral is zero, though there voltages for unbalanced RL load.
are zero sequence components. Therefore, Chopper
ideally, there should not be capacitor voltage
imbalance since, the sum of reactive power
across the three phases are zero. But, due to Dp Sch1 i Cdc1
switching combinations as seen from Table II, ch1

there are unequal flows of current in the Rch Lch

capacitors. The top two capacitors C1 and C2 are Dp Sch2 Cdc2 Five Level Filter
used for obtaining +1 state but only C2 is used for Diode Currents
Clampled
+1/2 state. The same procedure can be put forth Dp Sch3 ifa, ifb, ifc
Multilevel
for -1 and -1/2 for the bottom capacitors. Due to ich2 Cdc3
Inverter
this unequal flow of charges, the capacitor Rch Lch
voltages diverge. The capacitor voltages are Dp Sch4 Cdc4
shown in Fig. 4(a) for an unbalanced RL load. It
can be seen from Fig. 4(b) that the total voltage
across the capacitors is maintained constant by a
PI controller.
Figure 5 Inverter chopper circuit for five-level
Balancing capacitor voltages in multilevel VSI are
diode clamped inverter for passive loads.
tried for a long time. There are many theories in
literature [11],[12] explaining different methods
For controlling the switches carrier based Pulse
for balancing capacitor voltages. However, these
Width Modulated (PWM) method is employed as
techniques provide slow and less efficient
suggested in [13]. In this method charges from
operation. External balancing circuit as shown in
the overcharged capacitors are transferred to an
inductor (Lch) by controlling switches Sch1 and
Sch4. After a certain interval of time, the
corresponding switches are turned off such that
the charges from inductor are transferred back to
the other capacitors through the free wheeling
diodes Dch2 and Dch3 as shown in Fig. 5. The
capacitor voltages and the average capacitor
current i.e. Icap_avg flowing across each capacitor
are measured. For balancing the capacitor
voltages a triangular carrier waveform with
certain amplitude and frequency (fs) is chosen.
The amplitude of the carrier wave depends on
the drift in capacitor voltage that can be tolerated.
The frequency of the waveform depends on the
average capacitor current and duty cycle (D) of
the switches.
During the steady state operation of the chopper
it is assumed that the chopper voltages are
nearly equal to their reference value. Therefore,
the rate of rise of chopper current in the inductor
is same as the rate of fall of the inductor current
where the current freewheels through the diodes.
In order to prevent the increase in the
accumulation of inductor charge, the choppers
are operated in discontinuous conduction mode.
This mode of operation is achieved by fixing the
duty cycle (D) of the choppers strictly lesser than
0.5. The average capacitor current (Icap-avg) is
given by.
Icap-avg = (1/2)(Ipeak)(ton + toff )/2 (3)
Where, Ipeak, ton and toff are the peak chopper
current, on and off time of the choppers
respectively. Ts is the time period of the switches.
The maximum limit up to which discontinuous
current can flow through the inductor for proper
operation is when duty cycle D = 0.5. Simplifying
the above equation.
Icap-avg=Ipeak = D ; D = ton=Ts; (4)
Ts = ton + toff + trest
Where, D is the duty cycle and trest is the time
during which no choppers nor freewheeling
diodes conduct. The above equation shows that
D is directly proportional to the average current
and inversely proportional to the peak of the
chopper current. The value of Ipeak should be
decided based on the peak current ratings of the
chopper and inductor present. Based on the peak
current, the value of D is obtained. Ipeak is given
by the equation
Ipeak = (Vdcref/Lch) * ton (5)
Where, Vdcref is the reference value of the DC
capacitor voltages and Lch is the inductance in
the inverter chopper circuit. Using the equations
(3), (4) and (5) the switching frequency of the
triangular carrier waveform is obtained.
fs =(Vdcref * D)/(Lch * Ipeak) (6)
This value of fs decides the switching frequency
of carrier triangular wave. This frequency is
dependant on duty cycle of operation. The
triangular carrier wave and the voltage error,
which is the difference between the actual
capacitor voltage and reference capacitor
voltage, are compared such that pulses as
shown in Fig. 6 are obtained. The obtained
pulses are given to either of the switches Sch1 and
Sch4 for capacitor voltage balancing.
For discontinuous operation, we have set the
duty cycle less than 0.5, the above value of fs for
D < 0.5 guarantees discontinuous operation. The
duty cycle is varied depending on the chopper
inductor peak current capability. It is noted that
as Ipeak increases for a system, the value of D
decreases. But D from (6) is directly proportional
to the frequency of the triangular carrier wave.
Therefore, as D decreases, frequency fs also
decreases and the error increases as the time of
operation of the switches decreases. A trade off
is thus essential. Heuristically, a good trade off
for duty cycle is between 0.3 and 0.5. From,
equation (6) the corresponding value of
frequency for a chosen duty cycle is obtained.
The compensated capacitor voltages for the
simulation parameters in Table. I are shown in
Fig. 7(a). It is also seen the chopper current
flowing in inverter chopper circuit is
discontinuous as shown in Fig. 7(b).
V carrier
error signal
t
S7 , S8
ton toff+trest t
Ts
Figure 6. Switches pulses to inverter chopper
circuit.
 the inner loop on the average capacitor current
Icap-avg. The simulation results for DSTATCOM
compensating DC loads using the proposed logic
are shown in Fig. 9(a), Fig. 9(b). The external
Voltage (V)

inverter chopper circuit corrects the capacitor

Vdc1 Vdc2 Vdc3 Vdc4
voltages as seen from Fig. 9(b).

Chopper

Dp Sch1 i Cdc1
Time (s) Dp Sch5
ch1

(a) Rch Lch

Dp Sch2 Cdc2 Five Level Filter
Rch Lch Diode Currents
ichT Clampled ifa, ifb, ifc
Dp Sch3 Multilevel
ich2 Cdc3
Inverter
Dp Sch6 Rch Lch
Current (A)

Dp Sch4 Cdc4

I ch2 Figure 8. Inverter chopper circuit for five-level

I ch1 diode clamped inverter for DC loads.

Time (s)
Vdc3
(b)
Voltage (V)

Vdc4
Figure 7. (a) Compensated capacitor voltages for
unbalanced RL load (b) Discontinuous inverter
chopper currents.
DC loads are responsible for non-zero average Vdc1
zero sequence currents. In such cases, unequal
flow of capacitor current due to switching logic Vdc2
combined with average neutral current flowing
into neutral clamped point causes capacitor
voltage imbalance. An example of DC load is a
Time (s)
(a)
three phase half wave rectifier where, there is a
positive average neutral current. Therefore, from
Fig. 2 the bottom two capacitor voltages Vdc3, Vdc4
increases while the top two capacitor voltages
Vdc1, Vdc2 decreases. Also, the rate of increase in
Voltage (V)

voltage Vdc3 is greater than that of voltage Vdc4. V

Similarly, Vdc2 falls steeper than Vdc1. Therefore, V Vdc3 Vdc1 dc2
dc4
two loops are required. The outer loop helps in
balancing the top pair Cdc1, Cdc2 and bottom pair
Cdc3, Cdc4 capacitors, while the inner loop
balances individual capacitors. The schematic of
such an external balancing circuit is shown in
Fig. 8. The same technique as explained above
is used for operation of such loads. The switching
pulse for the outer loop is decided by the average
Time (s)
(b)
neutral current Ioavg and the switching pulses to
Figure 9. (a) Uncompensated capacitor voltages
for unbalanced RL and DC load (b) compensated
capacitor voltages for unbalanced RL and DC
load.
CONCLUSION
In this paper, a slope based hysteresis current
control technique and capacitor voltage
balancing for five-level neutral clamped voltage
source inverter are described. A new method for
tracking the reference currents based on their
slope has been discussed. The objective in here
is to reduce the average tracking error. With
Multi-level inverters the stress across the
switches are reduced and the switches are
operated at a lesser switching frequency for any
given load. A major disadvantage of using such
multilevel inverters is capacitor voltage
imbalance. It is seen that due to switching
combinations and average neutral current
capacitor voltage tends to diverge. External
balancing circuit is used for balancing capacitor
voltages at the expense of additional switching
devices and additional losses. A heuristic value
of duty cycle is also obtained for ensuring
discontinuous current in the inverter chopper
current.
REFERENCES
[1] H. Akagi, Y. Kanazawa, and A. Nabae,
Instantaneous reactive power compensators
comprising switching devices without energy
storage components,” IEEE Trans. on Ind.
Appln., vol. 20, no. 3, 1984.
[2] T. Larsson, C. Poumarede, A. Syst, and S.
Vasteras, “STATCOM, an efficient means for
flicker mitigation,” in IEEE Power Engineering
Society 1999 Winter Meeting, vol. 2.
[3] G. Bode and D. Holmes, “Implementation of
three level hysteresis current control for asingle
phase voltage source inverter,” in 2000 IEEE
31st Annual Power Elec. Specialists Conference,
2000. PESC 00, vol. 1, 2000.
[4] J. Lai and F. Peng, “Multilevel converters-a
new breed of power converters,” IEEE Trans. on
Industry Appln., vol. 32, no. 3, pp. 509–517,
1996.
[5] J. Rodriguez, J. Lai, and F. Peng, “Multilevel
inverters: a survey of topologies, controls, and
applications,” IEEE Trans. on Ind. Electronics,
vol. 49, no. 4, pp. 724–738, 2002.
[6] A. Ghosh, A. Joshi, and R. Gupta, “Cascaded
multilevel control of DSTATCOM using multiband
hysteresis modulation,” 2009.
[7] M. Mishra, A. Joshi, and A. Ghosh, “A new
closed loop control scheme for capacitor voltage
equalisationin shunt compensator using neutral
current injection,” in IEEE Power Engg. Society
Winter Meeting, 2001, vol. 1.
[8] M. K. Mishra, A. Joshi, and A. Ghosh, “Control
schemes for equalization of capacitor voltages in
a neutral clamped shunt compensator,”Power
Engineering Review, IEEE, vol. 22, no. 12, pp. 64
–64, dec. 2002.
[9] S. Srikanthan, M. Mishra, and R. Rao,
“Improved hysteresis current control of three-
level inverter for distribution static compensator
application,”Power Electronics, IET, vol. 2, no. 5,
pp. 517 –526, sept. 2009.
[10] A. Ghosh and A. Joshi, “A new approach to
load balancing and power factor correction
inpower distribution system,” IEEE Trans. on
Power Delivery, vol. 15, no. 1, pp. 417–422,
2000.
[11] H. Akagi and T. Hatada, “Voltage balancing
control for a three-level diode-clamped converter
in a medium-voltage transformerless hybrid
active filter,” IEEE Trans. on Power Electronics,
vol. 24, no. 3, p. 571, 2009.
[12] M. Marchesoni, M. Mazzucchelli, and P.
Tenca, “About the DC-link capacitors voltage
balance in multi-point clampedconverters,” in Ind.
Electronics Society, 1998. IECON’98.
Proceedings of the 24th Annual Conf. of the
IEEE, vol. 1.
[13] S. Srikanthan, M. Mishra, B. Kumar, and K.
Bhaskar, “Capacitor Voltage Balancing in Neutral
Clamped Inverters for DSTATCOM Application,”
in Power Engineering, Energy and Electrical
Drives, 2009. POWERENG ’09., 18-20 March
2009.