The Core i7 Family

Eric Day

In late 2008 Intel released the first of it's current line of processors, the Core i7. The Core i7
line under the code name at the time of Bloomfield sported many changes such as the memory
interface, architecture, and socket. It is a 64Bit x86-64 multicore processor. This processor line is
intended for high-end users and supports hyper threading. The chip speed ranges from 1.6Ghz to
3.3Ghz.
Moving from the Core microarchitecture, the Core i7 uses the Nehalem microarchitecture. The
Nehalem microarchitecture has typically 2 to 6 cores on one chip. This is a big difference from the
Core 2 lines. Although they had multiple cores, it was one core per die. With Nehalem, they are able
to fit the cores onto one die. The quad-core implementation achieves this with 731M transistors. To fit
all of them intel decided to increase the physical dimensions of each die. Another big difference is that
all the cores share a L3 cache. They allocate about 2MB per core, but all cores have access. The Core
2 lines, with the exception of a few, had no L3 cache, and instead sported bigger L1 and L2 caches.

Each core is equipped with two L1 caches. One for instructions and the other for data. As well
each core has its own L2 cache. It seems that when Intel was working on the Core 2 lines, which had a
shared L2 and no L3, when they went to quad core they realized that a shared L2 was not going to cut
it. A shared L2 is fine for 2 cores, but when you increase it to 4 the risk of one core wiping part of the
cache that another core still needs became to great. To solve this, they decided that it was best to
provide each core with its own L1 and L2 cache and a shared L3.

But to make it effective the size of the L1 and L2 caches are very small. 32K for each L1, and
256K for the L2. The bigger L3 cache then contains everything in each of the private caches. As well
it contains 4 bits to tell which core the data is being used in. This way if one core is seeking a certain
block of memory, it can easily tell if the data is already present and being used, and by which core, or if
needs to be fetched from main memory.
This is where another difference from previous lines, Intel removed the front side bus for a
more direct approach. Instead of a memory controller located on the motherboard, commonly referred
to as the north bridge, it has a on board memory controller and is connected directly to the IO
controller. This allows more direct access from the CPU to other devices. One reason for this is that in
multi-core processors memory access time is based on physical distance. Therefore eliminating the
northbridge and placing the controller on the chip itself there is less distance for data to travel from
RAM to the processor. This chip also boasts 3 separate paths for memory access, each at 1.33 GT/s.
An interesting side note is that this line is only compatible with DDR3 memory.
The Core i7 also brings back Intel's Hyper-threading technology. In the most basic sense hyper-
threading turns one pyhical processing core into 2 logical processors. It works by duplicating the
logical components of the processor. The physical execution devices, such as the ALU are not
duplicated. This means that two threads can run on the same processor at the same time, using the
unused portions of the execution core. With a the Core i7-970, whom has 6 cores, means that we could
potentially execute 12 instructions at once.
This of course can serve potentially dangerous, as if any of the instructions share data. This
could cause some applications to run slower due to the processor waiting for resources to free up. But
if the operating system and software running is properly programmed and optimized for hyper-threaded
hardware, these hazards can be avoided.
The Nehalem microarchitecture has a 20 to 24 stage pipeline. At the start is the instruction
fetch stages.

The instruction fetch stages fetch the next instruction. This next instruction is calculated right
there as the branch detection stage is incorporated into the fetch. If there is a branch the return address
is stored in a return stack buffer. Each thread has its own RSB to eliminate overflows that could
possibly occur. Each fetch will grab 16 Bytes of instructions. From there 6 instructions can be sent to
the decode stage.
These processors have 4 decoders. 1 for complex instructions, and 3 for simple x86
instructions. Once decoded it can be passed to the execution portion.
The Nehalem uses an out-of-order execution design. This is mainly so that SMT(simultaneous
multi threading) can properly occur. With an out-of-order engine, some instructions can finish before
others that may have begun exection earlier. From there the instructions are placed into the Re-Order
Buffer. This way code be executed out of order has a place to be rearranged back into proper execution
order.
Then the results are stored back into the L2 cache.

On the following page is the entire pipeline structure connected together.

 Remember that this processor family use hyper-threading. So there are one of these structures
for each thread (up to 12). So we could theoretically have 12 separate programs running in their own
pipeline structure at once.
This processor family is at the fore front of modern day processors. This technology will take us
into a new era of processing power and will hopefully take the same increase in performance that
previous lines have seen.
Sources:

1.http://www.intel.com/products/processor/corei7/index.htm

2.http://en.wikipedia.org/wiki/Intel_Core_i7

3.http://en.wikipedia.org/wiki/Nehalem_(microarchitecture)

4.http://en.wikipedia.org/wiki/Core_(microarchitecture)

5.http://en.wikipedia.org/wiki/Intel_QuickPath_Interconnect

6.http://en.wikipedia.org/wiki/Hyper-threading

7.http://www.firingsquad.com/hardware/intel_core_i7_nehalem_performance_preview/

8.http://www.bit-tech.net/hardware/cpus/2008/11/03/intel-core-i7-nehalem-architecture-dive/5

9.http://www.cs.uaf.edu/2009/fall/cs441/proj1/russell/index.html

10.http://www.realworldtech.com/page.cfm?ArticleID=RWT040208182719

11.http://arstechnica.com/hardware/reviews/2008/11/nehalem-launch-review.ars/13